TWI354239B - Decoding system unit - Google Patents

Description

1354239 ' Nine, invention description:

V TECHNICAL FIELD OF THE INVENTION The present invention relates to data processing systems, and more particularly to programmable graphics processing systems and methods.

t I . [Previous technical standards] - Computer graphics are a technique for generating images, images or other graphics or images Φ image information using a computer. Currently, many graphics systems are implemented through the use of interfaces, such as Microsoft's Direct3D interface, OpenGL, etc. - which can be used for multimedia hardware on computers running specific operating systems (eg Microsoft's Windows systems) (eg: Graphics accelerators or graphics processing units (GPUs) provide control. Image or image generation is generally referred to as rendering, and the details of the above operations are mainly implemented by graphics accelerators. In the three-dimensional (3D) computer graphics, the geometry of the object surface (or volume) in the scene is converted into pixels (image elements) and stored in the frame buffer. And then displayed on the display device. Each _ object or group of objects has specific visual properties related to the appearance of the surface (eg - material, reflection coefficient, shape, texture, etc.), which can be defined Rendering context of objects or groups of objects ° Computer graphics to increase consumer perception of games and other multimedia The controllability and features of the body products, the generation of more realistic images and the improvement of processing speed and energy consumption. Many standards have been developed to utilize fewer bits.

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 5 1354239; number to produce better quality images. One of these standards, the H.264 standard (also the tenth part of the motion picture experts group (MPEG) _4) is the high compression digital video coding (codec) standard. Compared to MPEG-2 encoders, h.264 compatible codecs use only almost one-thirds of the number of bits to encode video and maintain similar video products. The 264.264 specification provides two types of (entr〇py) coding processes, including c〇ntext_adaptive binary arithmetic coding (CAB AC) and content-adaptive variable-length coding (context-adaptive). Variable length coding, CAVLC). In order to meet these continuous changes, many different pure software or pure hardware solutions have been proposed. However, known techniques result in higher inventory, immediate elimination techniques, and lack of flexibility in design. SUMMARY OF THE INVENTION The present invention discloses a decoding system and method for a multi-execution sequential parallel computing core for a graphics processing unit. The present invention provides a system comprising a software programmable core processing unit having a variable length decoding unit for performing a shader, the shader selectively performing a video stream decoding step to output a decoding Data, wherein the video stream is based on content adaptive binary arithmetic coding (CABAC), content adaptive variable length coding (CAVLC), EXP-Golomb, dynamic expert group (MPEG-2), and VC-1 standard. And the above decoding steps are performed using a combination of software and hardware. The present invention provides another system including a graphics processing unit coupled to a host processor and a memory, the graphics processing unit including a graphics

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 6 has factory software programmable core processing unit, including - or multiple implementations J 7L 'above - one execution unit including execution unit The data path is hard, 'which includes - variable length decoding unit, the above variable length decoding unit performs -m above, the shader adapts to the binary arithmetic horse according to the content, and the inner valley adapts to the variable length coding, EXp_G〇1〇mb The MpEG_2 and VC-1 standards are selectively implemented - decoding of the stream encoding to provide a decoded tribute output. The above and other objects, features and advantages of the present invention will become more < Many embodiments of decoding systems and methods are disclosed (wherein the above systems and methods will be collectively referred to as decoding systems). In one embodiment, the decoding system is embedded in one or more of the execution units of the graphics processing unh (GPU) programmable, multithreaded, and parallel computing cores. Use a combination of software or hardware to implement the decoding function. That is, video decoding is done in the context of programming of the graphics processing unit and the hardware implementation in the data path of the graphics processing unit. For example, in one embodiment, the decoding algorithm or method is performed by a shader having an extended instruction set (eg, a vertex shader), an execution unit data path of the graphics processing unit, and Automatic management of bit stream buffers

Client's Docket No.: S3U06-0013-TW IT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 is implemented with additional hardware. Compared to existing systems, existing systems are solutions that deal with pure hardware or pure software, and therefore encounter some of the problems mentioned in the prior art. In the decoding system described herein, an encoding action using information decoding of complex entropy coding can be implemented. The decoding system can be decoded according to the CABAC and CAVLC of the well-known international telecommunication union telecommunication standardization sector &gt; ITU-T H.264 standard, or according to MPEG-2 and VC. The -1 standard is decoded. Different decoding system embodiments operate in accordance with one of a plurality of modes, wherein each mode corresponds to one of the previously described standards and buffers memory or corresponds to a host processor according to execution of one or more slave graphics processing unit frames The set of instructions received by the memory (eg, the central processing unit (CPU)) (eg, via known mechanisms such as preload or cache failure). The hardware can be reused to provide multiple types of decoding standards (ie, depending on the mode selected). Furthermore, the mode selected will also affect the way in which the content memory is initialized, used, and/or updated. Depending on the mode of decoding of the decoding, the decoding system may use, for example, Exp-Golomb encoding, encoding like Huffman (eg, CAVLV, MPEG-2, and VC-1) and/or arithmetic encoding (eg, CABAC). The entropy decoding method is performed by extending the instruction set corresponding to one or more execution units, and providing an additional hardware that automatically manages the bit stream to perform the content model in CAVLV decoding and CABAC decoding. In one embodiment, the entropy coding table uses different memory tables or other data structures (eg, only

Client's Docket No.: S3U06-0013-TW TT, s Docket No: 0608-A41246twf, doc/NikeyChen 8 1354239 '· ° sells a read only memory (ROM) table). In addition, the 'automatic bit stream buffer has some advantages. For example, once the direct buffer access (DMA) engine of the meta buffer knows the location (address) of the bit stream, it automatically manages the bit. , turbulence without further instructions. Compared with the traditional microprocessor/digital processor (DSP) system, the bit stream represents a large amount of overhead. Furthermore, the erroneous bit stream can be detected and processed by tracking the number of bit φ elements used by the bit stream buffer mechanism. Another advantage of the embodiment of the decoding system of the present invention is that the delay of the instruction is reduced to a minimum. For example, because CABAC decoding is a very continuous action and it is not easy to utilize multiple execution order processing, a forwarding mechanism (e.g., temporary forwarding) is used in different embodiments to reduce the effective dependent delay. Further explanation, many deep-pipeline and multi-execution processor limitations are unable to execute instructions in each cycle of the same execution thread. Some systems may use general forwarding, which uses the operand of the previous result by checking the operand (〇perand) address of the previous result and the instruction operand address' when the two are the same. Traditional...Upper general forwarding requires complex comparisons and multiplexes. In some embodiments of the decoding system, whether using previous calculations (such as stored in internal registers) or "original data" will use different forwarding patterns to encode bits in the instruction. For example, a total of 2 bits and each transport element uses 1 bit. In this way, the overall delay can be reduced to improve the efficiency of the processor pipeline. 1 is a block showing an embodiment of a graphics processing system 100.

Client's Docket No.: S3U06-0013-TW TT's Docket No: 〇608-A41246twf.doc/NikeyChen 1354239 The embodiment in which the decoding system and method are implemented in the graphics processing system. In some embodiments, the graphics processing system 1 can be a computer system. The graphics processor system 100 can include a display device 1〇2 driven by a display interface unit 'DIU 104 104 and a local memory 106 (eg, can include a display buffer, a frame buffer, a texture buffer, Command buffer, etc.). The local memory 106 can also be replaced by a frame buffer or a memory. The local memory 1 〇 6 is connected to the graphics processing unit via one or more memory interface units (MIUs) 11 . In one embodiment, the memory interface unit 〇, the graphics processing unit 114, and the display interface unit 〇4 are all coupled to a bus interface interface unit that is compatible with a peripheral component interconnect express (PCI-E). (bus interface unit, BIU) 118. In an embodiment, bus interface interface unit 118 may use a graphics address remapping table (GART), although other memory mapping mechanisms may be used. Graphics processing unit 114 includes a decoding system 200, which will be described later. In some embodiments, although the decoding system 200 is shown as an element within the graphics processing unit 114, the decoding system 200 can also include one or more additional components or different components of the graphics processing system 100 being displayed. The bus interface unit 118 is coupled to the chip set 122 (e.g., a north bridge wafer set) or a switch. Wafer set 122 includes interface electronic circuitry to enhance signals from central processing unit 126 (also referred to as a host processor) and to separate signals entering and leaving system memory 124 and from input/output (I/O) devices (not shown). signal. Although the PCI-E bus protocol is mentioned,

Client's Docket No.: S3U06-0013-TW TT^ Docket No; 0608-A43246twf.doc/NikeyChen i〇 1354239 may also use other connections and/or between the host processor and graphics processing unit 114 in some embodiments. Communication methods, such as PCI, exclusive high-speed bus, etc. System memory 124 also includes driver software 128 that can be used by central processing unit 126 to transfer instruction sets or commands to a scratchpad within graphics processing unit 114. 1 » In some embodiments, an additional graphics processing unit can be coupled to the elements of Figure 1 via a PCI-E busbar protocol via chipset 122. In one embodiment, graphics processing unit 100 may include all of the elements shown in Figure 1, or fewer elements and/or elements other than those shown in Figure 1. Moreover, in some embodiments, additional components may be utilized, such as a south bridge wafer set coupled to the wafer set 122. Referring to Figure 2, a second diagram is a block diagram showing the processing environment in which an embodiment of the decoding system 200 is implemented. In particular, graphics processing unit 114 includes graphics processor 202. Graphics processor 202 includes a multi-execution unit (EU) and computing core 204 (also known as a software programmable core processing unit). In one embodiment, computing core 204 includes a decoding system 200 (also referred to as a VLD unit) embedded in an execution unit data path (EUDP), wherein the execution unit data path is assigned to one or more executions. unit. The graphics processor 202 also includes an execution unit pool 'EUP' control, a vertex/streaming cache unit 206 (referred to herein as an execution unit set control unit 206), and a fixed function logic unit (eg, including a triangle setting unit) A graphics pipeline 208 of a triangle set-up unit (TSU), a grid-tile generator (STG), etc., which will be described later. meter

Client's Docket No.: S3U06-0013-TW TT5s Docket No:0608-A41246twf.doc/NikeyChen The calculation core 204 includes a set of multiple execution units to meet the computational requirements of the colored tasks of different shaded d, where the shader program includes the geometry and geometry. The shader and/or pixel shader processes the graphics tube (10) color test. In one embodiment, when the shader is executed through the computational core 2 = 4, the description of the function of the system 200, the GPU processor embodiment, will be interspersed. Next, a specific embodiment of the decoding system 200 will be described. The decoding system 200 can be implemented in the form of hardware, software, firmware, or a combination thereof. In the preferred embodiment, the 'decoding system 200 is implemented in a hardware and software manner' which includes any of the following known techniques or a combination of discrete circuits having logic gates and logic functions on data signals, Application specific integrated circuit (ASIC) with programmable combination gate, programmable gate array (PGA), field programmable gate array (FPGA), and state State machine, etc. Referring to Figures 3 and 4, which are block diagrams of selected elements in an embodiment of graphics processor 202, respectively. As previously mentioned, an embodiment of the decoding system 200 can be a colorizer within the graphics processor 202 having an extended instruction set and additional hardware components, an embodiment of the graphics processor 202 and corresponding processing will be described later. Although Figures 3 and 4 do not show all of the components of the graphics process, the components shown in Figures 3 and 4 are sufficient for those skilled in the art to understand the functionality and architecture of the associated graphics processor. Referring to Figure 3, the center of the programmable processing environment is computing core 204, which includes decoding system 200 and can process various instructions. Different types

Client's Docket No.: S3U06-0013-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 12 1354239 The shader program can be executed or mapped to the computational core 204, such as vertex, geometry, pixel shader programs. The computational core 204 of the multi-issue processor can process multiple instructions in a single clock cycle. Referring to FIG. 3, the relevant elements of graphics processor 202 include computing core 204, texture filtering unit 302, pixel packer 304, command stream processor 306, write back unit 308, and texture address generation. The device 310. Figure 3 also includes an execution unit set control unit 206, wherein the execution unit set control unit 206 also includes vertex cache memory and/or stream cache memory. For example, as shown in FIG. 3, texture filtering unit 302 provides texel data to computing core 204 (input A and input B). In some embodiments, the texel data is 512 bit data. Pixel wrapper 304 provides pixel shading input to computing core 204 (input C and input D), which is also a 512-bit data format. In addition, the pixel wrapper 304 requests the execution unit collection control unit 206 for the pixel shading task, and the execution unit collection control unit 206 provides the specified execution unit number and thread number to the pixel wrapper 304. Pixel wrapper 304 and texture filtering unit 302 are known techniques and will therefore not be further described herein. Although the pixel and texel packet shown in FIG. 3 is a 512-bit data packet, the size of the packet can be changed in some embodiments depending on the desired performance characteristics of the graphics processor 202. Command stream processor 306 provides a triangle vertex index to execution unit set control unit 206. In the embodiment of Fig. 3, the index is 256 bits of data. Execution unit set control unit 206 combines from stream cache

Client’s Docket No·: S3U06-0013-TW TT^ Docket No:0608-A41246twf.doc/NikeyChen 1354239 Recall the vertex shader input and transfer the data to compute core 204 (input • E). Execution unit set control unit 206 also combines the geometric shading inputs and passes them to computing core 204 (input F). Execution unit set control unit 206 also controls execution unit input 402 and execution unit output 404 (Fig. 4). In other words, the execution unit set control unit 206 controls each input stream and

» I. Each output flows to computing core 204. After processing, computing core 204 provides pixel shading outputs (output J1 and output J2) to write back unit 308. Pixel shading outputs include color • information such as red/green/blue/transparency (RGBA) information, which is well known to those skilled in the art. The pixel shaded output can be two 512-bit data streams. Other embodiments may use other bit widths.

Similar to the pixel shaded output, the compute core 204 also outputs texture coordinates (output K1 and output K2) including UVRQ information to the texture address generator 310. Texture address generator 310 issues a texture description symbol request to L2 cache memory 408 (input X) of computation core 204, while L2 cache memory 408 (output W) of computation core 204 outputs texture description symbol ® data to Texture address generator 310. Texture address generator 310 and write back. Unit 308 is a known technique and will therefore not be further described herein. Furthermore, although URVQ and RGBA are data shown as 512 bits, this parameter may also vary with different embodiments. In the third embodiment, the bus is divided into two 512-bit channels, each of which holds a four-pixel 128-bit RGBA color value and a 128-bit UVRQ texture coordinate. Graphics pipeline 208 includes graphics processing functions for fixed functions. Respond to commands from the driver software 128, such as drawing a triangle, then the vertex information

Clients Docket No.: S3U06-0013-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 14 1354239 Override the vertex shader logic within core 204 to perform vertex conversion. 'In particular, transform objects from object space into triangles for workspace and/or screen space. The triangle passes through the calculation of the core 204 to the triangle setting unit of the graphics pipeline 208, wherein the graphics pipeline 208 incorporates primitives and also performs known tasks, such as: bounding box generation,

I I culling 'edge: function generation and triangle level rejection. The triangle setting unit transfers the data to the grid and block generation unit having the tile generation function in the graphics pipeline 208. Therefore, the data object is divided into tiles (eg, 8 x 8, 16x16, etc.) and passed to other fixed functional units to perform depth (eg, Z-value) processing, such as high-order Z-values (eg, in a similar process) In the order, the higher order uses fewer bits than the lower order). The Z-value is then passed back to the image-like primed logic element of computing core 204 as a function of the pixel shading function based on the received texture and pipeline data. The calculation core 204 outputs the processed values to the destination unit located within the graphics pipeline 208. The destination unit is used to perform alpha ® testing and template testing before different cache memories need to update internal values. It should be noted that there is also a 512-bit vertex cache memory overflow data transfer between the L2 cache memory 408 of the compute core 204 and the execution unit set control unit 206. In addition, two 512-bit vertex cache memory write data (output M1 and output M2) are output from the calculation core 204 to the execution unit set control unit 206 for further processing. Referring to Figure 4, Figure 4 shows additional components of computing core 204 and associated components. The computing core 204 includes a set of execution units 412. in

Clients Docket No.: S3U06-0013-TW TT5s Docket No:0608-A41246twf.doc/NikeyChen 1354239 - Only example t, execution unit set 41 a 420a-420h (collectively referred to as G or one of the lights) Can be in a clock cycle). The parent one execution unit 420 412 can be = ^ at the peak, although the fourth figure shows eight: two simultaneously processing multiple threads. : It can be understood that it is (marked as foot 7), and the number of embodiments can be increased or decreased by two "the number of early elements is 8' in the row unit (for example, the number of execution units 42 is 7^. At least A pertinent-embodiment, which will be described in the following steps. G) The computing core including the decoding line 2〇4 also includes: memory unit, MXU) 406, slamming the C memory access surface arbiter Decent single through the memory medium 408 from the execution unit set 1, take 5 memory 408. L2 hide memory data (input G) early 12 〇 6 receive vertex cache memory overflow Η) to the execution unit隼8^ for vertex cache memory overflow data (transportation from texture address generation unit 206. In addition w cache memory into X), and received: ^ receive texture description symbol request (output W) to texture The address generator ^ provides texture description symbol data (transport memory interface arbitration n-plane, buffer or local record = body == face-to-face 118 provides a interface such as PCKE busbar to the system. Memory interface arbiter 410 And the bus interface single phantom 18 provides the memory and the interface between the L2 cache memory 408 In some embodiments, Q is quickly taken from the memory 40 requested memory access unit to the memory interface 4〇6 _

Clients Docket No.; S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 16 1354239 Arbiter 410 and bus interface unit 118. The memory access unit 406^ converts the virtual memory address obtained from the L2 cache memory 48 and other blocks into an actual memory address. The memory interface arbiter 410 provides memory access (eg, read/write access), instruction/constant/data/texture to the L2 cache 408. » : fetch, direct memory access (eg Load/store), index of scratch access, scratchpad overflow, and vertex cache memory overflow. The computing core 204 further includes an execution unit input 402 and an execution unit • output 404 and is used to provide input to the execution unit set 412 and receive output from the execution unit set 412, respectively. Execution unit input 402 and execution unit output 404 may be crossbars or other; bus bars, or other known input and output architectures. Execution unit input 402 receives vertex shading input (input E) and geometric shading input (input F)&apos; from execution unit set control unit 206 and provides information to execution unit set 412 for processing by each execution unit 420. In addition, execution unit input 402 receives pixel shading inputs (input C and input D) and texel packets (input A and input B) and passes the packets to execution unit set 412 for processing by each execution unit 420. . Again, execution unit input 402 receives information from L2 cache 408 (L2 read) and provides this information to execution unit set 412 when needed. In the embodiment of Figure 4, the execution unit output 404 is assigned an even output 404a and an odd output 404b. Similar to execution unit input 402, execution unit output 404 can be a crossbar, busbar, or other known

Client's Docket No.: S3U06-0013-TW TT's Docket N〇: 0608-A41246twf.doc/NikeyChen 1354239 Architecture. The execution unit even output 404a processes the outputs of the even execution units 420a, 420c, 420e, and 420g, and the execution unit odd output 404b processes the outputs of the odd execution units 420b, 420d, 420f, and 420h. Execution unit even output 404a and execution unit odd output 404b collectively receive outputs from execution unit set 412, such as UVRQ and RGBA. These ones

» The I output can be passed back to the L2 cache: the memory 408, or from the computation core 204: via the output J1 and the output J2 to the writeback unit 308, or via the output Κ1 and output Κ2 to the texture address Generator 310. The execution unit flow of execution unit set 412 typically includes a plurality of levels including: depicting a content level, a thread or task level, and an instruction or execution level. At any point in time, each execution unit 420 can authorize two rendered content, wherein the content is identified by using a one-bit flag or other mechanism. The content information is delivered from the execution unit collection control unit 206 before the task belonging to this content starts. Content level information can include shader types, number of input/output registers, instruction start addresses, output maps, vertex identifiers, and constants in individual constant buffers. Each execution unit 420 of the execution unit set 412 can simultaneously store multiple tasks or threads (e.g., 32 threads in some embodiments). In one embodiment, each thread fetches instructions based on a program counter. Execution unit set control unit 206 may serve as a general schedule for tasks and assign appropriate threads within execution unit 420 using data-driven methods (e.g., vertices, pixels, and geometry packets within the input). For example, execution unit set control unit 206 assigns a thread to an empty thread within each execution unit 420 of execution unit set 412.

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 18 1354239 (slot). When the thread is started, the data provided by the vertex cache memory, other components, or modules (depending on the shader type) will be placed in the general scratchpad buffer. Typically, graphics processor 202 uses programmable vertex, geometry, and pixel buffers. Do not treat these components as having different designs and instruction sets

• The individual fixed functional units of I implement the functions or operations of these elements: ' Instead, these operations are performed by a collection of execution units 420a, 420b ... 420n having a uniform instruction set. Except for execution unit 420a (which includes decoding system 200, thus having additional functionality), each execution unit 420 is identically designed and used for programming operations. In an embodiment, each execution unit 420 can perform multiple thread operations simultaneously. When the vertex shader, geometry shader, and pixel shader produce different coloring tasks, these coloring tasks are passed to the individual execution unit 420 for execution. In an embodiment using vertex shaders, decoding system 200 can be implemented with partial modifications and/or differences from other execution units 420. For example, the difference between an execution unit (e.g., execution unit 420a) that includes decoding system 200 and other execution units (e.g., execution unit 42A) is that execution unit 420a uses a decoding system 200. The other execution units differ from the execution unit 420a in the arrangement of the decoding system 200 in one or more corresponding internal buffers. The data of decoding system 200 is received from memory access unit 406 via connection 413 and execution unit input 402. When individual tasks are generated, execution unit set control unit 206 will assign these tasks to threads that are available in different execution units 420. When the task is completed, the execution unit set control unit 206 further manages the relevant execution

Client's Docket No.; S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 19 1354239 Release of the thread. In this regard, execution unit set control unit 206 refers to the tasks of the vertex shader, geometry shader, and pixel shader to the different execution units 420, and records related tasks and threads. Specifically, the execution unit set control unit 206 maintains the threads of all execution units 420 and the resource table (not shown) of the memory. Execution unit

The II collection control unit 206 will clearly know which thread is assigned to the task and use, which thread will be released when the thread ends, and how many registers register memory register (register file memory register). In use, and how much free space is available for each execution unit. Thus, when assigning a task to an execution unit (eg, execution unit 420a), execution unit set control unit 206 will flag the thread as busy; and subtract all available shared register file memories from each thread. The number of scratchpad footprints occupied. The footprint is set or determined by the state of the vertex shader, geometry shader, and pixel shader. Furthermore, each shader state can have a different footprint size. For example, the vertex shader thread can require 10 shared scratchpads. The file scratchpad can only require 5 shared scratchpad files. The scratchpad. When the thread completes its assigned work, the execution unit 420 executing the thread signals the execution unit set control unit 206. Next, execution unit set control unit 206 updates the resource table to indicate that the execution is unused and adds back the total number of thread shared scratch file space back to the available space. When all threads are busy green or all of the shared scratchpad file memory is allocated (or the remaining scratchpad space)

Client's Docket No.: S3U06-0013-TW TT, s Docket No: 0608-A41246twf.doc/NikeyChen 20 1354239 Too small to accommodate additional threads), execution unit 420 is considered full, and execution unit The collection control unit 2〇6 will not assign any additional or new threads to the execution unit. There is also a thread controller inside each execution unit 420 to be responsible for the official or standard threads for use (e.g., in progress). In this regard, in at least one embodiment, when the vertex shader is performing the functions of the decoding system 200, the execution unit set control unit 〇6 can avoid which shader and pixel shader are executed at the same time. Figure 5A shows an execution unit 42A having the aforementioned graphics processor 202 and computing core 204, which includes an execution unit data path 512 of the embedded decoding system 2 (8). Specifically, FIG. 5A is a block diagram of the execution unit 42A. In one embodiment, the execution unit 42A includes an instruction cache controller 504, a thread controller 506 coupled to the instruction cache controller 5〇4, and a buffer 508 (eg, a constant buffer) The common register file (CRF) 51, the interface to the thread controller 506 and the buffer 508 and the shared register file 51〇 EU data path (EUDP) 512, execution unit data control first in first out (FIFO) 514, 5 predicate register file (PRF) 516, scalar register file , SRF) 518, data output controller 520, and thread task interface 524. As previously described, execution unit 420 攸 execution unit input 402 receives input and provides output to execution unit output 404. The thread controller 506 provides a control function of the execution unit 420a, which

Client's Docket No.: S3U06-00I3-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 21 丄The functions of each thread and the judgment function, for example, how to perform 512 200 j ^ !:! ΐΓ usually includes performing different calculations The function, and package two fT ^ 乂 and integer computing logic unit (anthmetlc loglc her, ALU), private logic function and other logic circuits. The data output controller 520 jiang p — L 1 unit outputs some elements of the marriage::,: body: moved to the vertex cache memory minus the execution, the write back unit collection control unit moves - transmits the "task end" The execution unit (4) path knowledge task has been completed. The data is rotated (four) 520 ’ and the output controller is not written from the memory. The output tribute item of the _ position==== specified by the content is sent to the execution unit output 4B 04. The light task interface 524 sends the task identifier of the execution unit gamma to the execution unit #四(四) unit. The task identifier passes through the pure cell set control unit 206 to assign a new task to one (e.g., execution unit 420a). In an embodiment, the buffer 508 can be divided into 16 blocks, wherein each block has 16 slots, and each slot has 128-bit horizontal vector constants. The shader uses operands and indexes to store Take the constant buffer slot. For example, the index may be a temporary register including a 32-bit unsigned integer or a constant near the "bit" without a sign. The instruction cache memory controller 5〇4 is to the thread controller 5 〇6

Client's Docket No.: S3U06-0013-TW TTys Docket No: 0608-A41246twf.doc/NikeyChen 22 Interface Block. When the thread controller memory extraction can be performed, the coloring crying stomach exists (for example, from the command ^ ^ ^ ^ ^ # ^ ^ ;'' ^ ^ ^ ft ^^1504 (hit/miss). For example, 1 U 仃 仃 / 未 未 未 未 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四When it is taken, the miss occurs. When the life of the memory _ _ unit input 402 request, ^ 守 'If there is no request to execute the consent, the hidden controller 5 〇 4 can take the memory only one read and write bee 5. The instruction of the fast is 1 =: 'If a miss occurs, when there is a replacement block in the cache memory _ and there is empty foIT::::%-;------- 5. ""_Remembered body has = medium: Let the block have 2 bits away from the "When the middle mother inserts a W 4 blocks. Each effect, load, or _^ kind" ' Screening is no factory Uf= Before the data, the block state; and the L2 data H block becomes "loaded", and the block becomes "valid" after loading. ::Execution: The unit data path 512 can be used for the predicate file 516 42〇Γ= U input technique as the entry data and execution unit:: face. In the embodiment, the execution unit input 4〇2 contains a = first in first out buffer to buffer incoming data. Execution unit input 4〇2 can also transfer data to the command cache memory controller 5〇4 instruction cache

Docket 1354239 memory and constant buffer 508. Execution unit input 402 also maintains the coloring content. The execution unit output 404 serves as an interface for sending data from the execution unit 420a to the execution unit set control unit 206, the L2 cache memory 408, and the write back unit 308. In an embodiment, execution unit output 404 includes

1 I : A 4-item FIFO buffer for receiving the request for arbitration and buffering the data of the execution unit set control unit 206. Execution unit output 404 includes a variety of functions including arbitration instruction cache memory read requests, resource output write requests, and execution unit data path read/write requests. The shared register file 510 is used to store input, output, and temporary storage; In one embodiment, the shared scratchpad file 510 includes eight 'banks' having one of 128x128-bit scratchpad files read and write and one read/write. The read-and-write write is used by the execution unit data path 512 for the initial read and write accesses performed by the instruction. Memory banks 0, 2, 4, and 6 are shared by even threads, while banks 1, ® 3, 5, and 7 are shared by odd threads. The thread controller 506 compares the instructions of the different threads and confirms that the memory of the shared scratchpad file does not have a read or write memory conflict. A read/write buffer is used by the execution unit input 402 and the data output controller 520 to load the initial thread input data and write the final thread output to the execution unit set control unit data buffer and the L2 cache memory. 408 or other modules. Execution unit input 402 and execution unit output 404 share a single read/write input/output port, and in an embodiment

Client's Docket No.: S3U06-0013-TW TT5s Docket No: 0608-A41246twf.doc/NikeyChen 24 1354239, write ratio readout has a higher priority. The 512-bit input data enters four different banks to avoid collisions when loading data into the shared scratchpad file 510. The 2-bit channel index, data, and 512-bit aligned base address are transmitted to specify the starting memory of the input data. For example, when the start channel index is 1, the assumption

' I Threading the reference memory offset (offset) is 0, then the first 128 bits from the least significant bit: the least significant bit (LSB) are loaded into the next 128 bits of the memory bank. Loaded into memory 2...etc, and the last 128 bits are loaded into memory bank 0. It is worth noting that the two least significant bits of the thread ID are used to generate the memory offset to randomly rank the starting memory locations of each thread. The shared scratchpad file register index and the thread ID can be used to create a unique logical address that allows the tag to compare the data written and read by the shared scratchpad file 510. For example, the address can be arranged in 128 bits, which is the width of the shared scratch file archive. By combining the 8-bit shared scratchpad file register index and the 5-bit thread ID, a 13-bit address can be created to generate a unique address. Each 1024-bit line has a label, and each bit line has two 512-bit items (characters). Each character is stored in four banks, and the two least significant bits of the shared scratchpad file index are added to the current library's memory offset to establish a bank selection. The tag comparison method allows the different scratchpads to use the shared scratchpad file 510 to effectively utilize the memory, because the execution unit set control unit 206 records the memory usage of the shared scratchpad file 510.

Client's Docket No.: S3U06-0013-TW TT’s Docket No: 0608-A41246twf.doc/NikeyChen = Guaranteed for the new task of the execution unit before scheduling

For the *日召古\Q small to check = = all of the shared register file register is the first to go into the ^ slot index. After the thread controller = =, the file is read by 51*. When the thread execution ends the output data 4 rounds out the controller does not read from the shared register slot 5K) implementation::: The embodiment of the hand 420 includes the data path data path 512 of the decoding system 200, The 5B system displays the execution unit register. The routing path 512 includes the temporary calculation logic unit 5 two: two 28, the inward 'pre-point early 532, the vector integer device-like unit H 536, the multiplexer 538, the temporary storage; variable length production': And decoding system 200. The decoding system 200 includes - or more, a variable length decoding (VLD) unit 530, a second wide decoding, or a plurality of streams. For example, the 'single-variable-length decoding unit can decode the single-streaming, and the two variable-length decoding units 530 (shown by the dotted line*, which are not shown for simplicity) can simultaneously decode the two streams. For purposes of illustration, the following description will only utilize the operation of the decoding system 2 of a single variable length decoding unit 530, and the principles that can be understood can be derived to more than one variable length gamma unit. As shown, execution unit data path 512 includes some parallel data paths corresponding to variable length decoding unit 530, vector floating point unit 532, vector integer calculation logic unit 534, and special purpose unit 536, the root of which

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 26 1354239 ^The received command performs the corresponding operation. The register slot 526 receives 2 (not labeled SRCUSRC2). In the embodiment towel, the register = can correspond to the shared temporary storage 11 broadcast 510 shown in the figure, the temporary storage "case 516, and / or the scalar register slot 51 is worthy of note: In some cases, additional operands may be used. Operation (gongyueshan Lu line 542 provides each unit 53 (M36 receives the medium of the operation signal: dlUm) ° The current signal line 544 is drained to the multiplexer 528 The transfer code is pre-valued for each unit 53G·536 to complete the integer value of the small integer value. The decoder (not shown) provides the operand, operation (function), number= and current signal. The end of the (can include the writeback phase) 538 4 selects the rounded result of the selected data path and provides the output to the scratchpad slot 54. The output register configuration 540 includes the target component 'its It can be the same as the scratchpad file 526 or a different register: component. It is worth noting that in the embodiment, when the source and the target register contain the same component, the bits provided by the instruction have a total of Make ^ source and target selection to multiplex data to/from the appropriate register Execution unit 420a can be regarded as a multi-stage pipeline (for example, having four computational logic units) and operating in four execution phases. It is necessary to implement a delay to allow execution of the decoding thread. The stream buffer has a downward overflow (underfl〇w), waits for the memory, waits for the bit stream to be loaded into the FIFO buffer, and the anti-initial register (explained later), and / Or when the processing time has exceeded the sreg limit of time, the delay can be added during the execution phase. As mentioned above, in some embodiments, the decoding system 2〇〇At also uses a single

Client's Docket No:: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 An execution unit 420a decodes two bit streams simultaneously. For example, according to an extended instruction set, the decoding system can use two data paths (eg, add another variable length decoding unit 530) to simultaneously decode two streams, but can decode more or less at a time. Streaming (so more or fewer data paths are used). Decoding system 200 when multiple streams are required

Some embodiments of I are not limited to simultaneous decoding. Moreover, in some embodiments, single variable length decoding unit 530 can perform multiple simultaneous decoding of the stream. In an embodiment, when the decoding system 200 uses two data paths, the two threads can run simultaneously. For example, in an embodiment of two stream decoding, the number of threads is limited to two, wherein a first thread (eg, thread 0) is assigned to the first bank of decoding system 200 (ie, variable length decoding unit 530) And assign a second thread (e.g., thread 1) to the second memory of decoding system 200 (e.g., the variable length decoding unit shown by the dashed line in Figure 5B). In some embodiments, two or more threads can operate in a single memory bank. In some embodiments, although display decoding system 200 is embedded within execution unit data path 512, it may also include other components, such as logic circuitry within execution unit set control unit 206. In the following description, variable length decoding unit 530 and decoding system 200 are used interchangeably, and it is understood that decoding system 200 can include one or more variable length decoding units 530. The structure located under the decoding system 200 will be described, and the individual decoding system modes are described below. In particular, in one embodiment, the following instructions presented by driver software 128 may set different modes. Further described as follows:

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 Let INIT_CTX (set decoding system 200 to CABAC processing mode), instruction INIT_CAVLC (set decoding system 200 to CAVLC processing mode), command INIT_MPEG2 (Setting the decoding system 200 to the MPEG-2 processing mode), and the instruction INIT_VC1 (setting the decoding system 200 to the YC-1/WMV9 processing mode). In some embodiments, additional initialization may be provided via the instruction » I_NIT_AVS, which may initialize an audio video standard (AVS) bitstream encoding. For the EXP-Golomb system, the EXP-Golomb coded symbols are used under CABAC and CAVLC coding. Thus the iNIT_CTX and the INIT-CAVLC are commanded to download the bitstream of the EXP-Golomb system. There is no need to initialize the EXP-Golomb system. For example, for a symbol to be encoded, the computed coding flag received in the bitstream (eg, the bit set at the slice header level) will display the symbols as EXP-Golomb, CABAC, and CAVLC. coding. When using EXP-Golomb encoding, 'execute the appropriate EXP_Golomb encoding instructions as set forth below. Although these modes affect the implementation of the encoding engine, they also affect the initial, use, and update methods of the suffix, and the steps are described later. Referring to the Brother 5C diagram, the Brother 5C diagram displays a functional block diagram of the variable length decoding unit 530 for performing any of the complex decoding techniques in accordance with the selected mode. The k-length decoding unit 530 includes a variable length decoding logic circuit 550' in which the variable length decoding logic circuit 55 is coupled to the sreg stream buffer/DMA engine 562 (also referred to herein as a DMA engine module). Bitstream buffer management and proximity context memory (NCM) 564 (also known as content)

Clienfs Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 29 丄 j:) 4z:) y memory). The variable length decoding cover-km, 疋 530 also includes one or more registers 566' which are included for storage from the burgeoning 木 木 仃 ( ( ( ("CONTR〇l for example using 来自 σ from the execution unit The control signal of the decoded state is selected to select the module 彳t + ^ 00 犋.' of the variable length decoding logic circuit 550 and the register of the decoding material for the selection of the given mode, and the operation "also, upper" ^ (for example, SRC1" and factory SRC2"), and forwarding registers (such as "F1 丄1U and 1 F2"). The SREG Stream Buffer/DMA Bow Engine 562 includes a station female. . , dry bREG temporary state 562a and bit stream

Buffering benefit 562b will be further explained later. In one embodiment, the variable length sarcasm logic circuit 550 includes the set (also referred to as a logic circuit) shown in FIG. 5C. Variable length decoding logic 55 includes hardware including a register and/or a Boolean or computational logic 'for asserting instructions and (d) selecting the selected bank to decode. Further, the variable length decoding logic circuit 55 includes reading a neighboring content memory module (read-NCM) 568, an inspection string (iNpSTR) module 570, a reading module 572, and a computing preamble (CL0). Module 574, before calculation

Guide 0 (0:1^) module 576,]\/^0 module 578, from (: module 58〇, CAVLC module 582, and coupled to the calculation of the leading 〇 (CLZ) module 576 Exp - Golomb module 584. The Computational Leading (CLZ) module 576 and the CLO module 574 include instructions for decoding MPEG-2 and VC-1 bitstreams. About the Exp-Golomb module 584 The Exp-Golomb symbol is encoded by some leading zeros following the 1 followed by some bits that are specific to the zero number. The differential leading 〇 (CLZ) module 576 measures the number of leading zeros, then moves these The bit is incremented by 1 to record the number of leading zeros.

The Exp-Golomb module 584 reads the number of trailing bits.

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen % Ming 4239 and perform calculations according to the Exp-Golomb mode to determine the value. The contiguous content memory module 568 includes a logical memory I corresponding to the generated address to request the memory read transfer, and the fixed bit number is read from the adjacent content memory 564 and the round The data heart register is stored. The adjacent content t-memory command is the data from the content memory (6) = 32 bits and is returned to the target register of the 420a via the multiplexer. CABAC and cavlc encoding do not use adjacent (four) capacitive memory instructions, but (iv) other variable length decoding, in other words (for example: H, MPEG_4 Asp (DivX)), can enable content memory 564 to maintain variable length decoding The table is to take the adjacent content memory module to read the value in the variable length stone table. The reading module 572 includes a logic circuit to read the sreg temporary crying, and is secreted from the SREG register. The most significant bit (the second job tblt, MSB) part captures the specific number of bits, zero extension (coffee, and puts the value into the scratchpad. Therefore, the read module 572 package = circuit read row read Operation, which reads and locates the number of elements and removes it from the sacred: 562a to return the value of the unsigned value to the target temporary. The check string module 570 &amp; SREG register 562a reads the fixed bit The number of elements, but no bits are removed from the SREG register 562a (for example, the position of the indicator is not changed), and the value of the unsigned value is returned to the target register. Each module 568-584 is connected to the multiplex. Instructor training, in which multiplexer training chooses according to their respective orders - mode. Output is provided to the target register for further processing. ⑽ module also provides an output to the tear multiplexer 586, which corresponds to a command, choosing module

The output of Client's Docket No.: S3U06-0013-TW TT, s Docket No: 0608-A41246twf.doc/NikeyChen 31 1354239 569-582 is provided to SREG register 562a as a round-in. The tribute from the forwarding, control, and computational savings benefits 566 is provided to the CABAC module 580 and the CAVLC module 582 during individual identical operations. By means of the receive control signal (labeled as EXP_GOLOMB_〇p in Figure 5C), the Exp_G〇1〇mb module is similar.

The Exp-Golomb module 584 receives input from a compute leading 〇 (CLZ) module 576 and provides a turn-out to multiplexer 586. The content memory 564 can be used by the CABAC module 58A and the CAVLC module 582. For all modes except the CABAC and CAVLC modes, the read command reads n bits from the SREG register 562a and returns the read value to the execution unit 42A via the multiplexer 586. Target scratchpad. For modes other than CABAC and CAVLC modes, inner valley memory 564 is used to maintain the upper and left content values, which are automatic delta sells as part of the decoding process. These elements, as well as other elements of variable length decoding unit 530, will be further described in conjunction with different modes for the latter two values. In some embodiments, variable length decoding logic may include less than (or more than) all of Display modules and / or multiplexers. The general function of the variable length decoding unit 53A will be described, and the operation of the variable fragrance decoding unit 530 configured in different modes will further explain the CABAC decoding, and then some embodiments of the decoding system will be explained. Usually, the H.264 standard CABAC decoding program can

Client's Docket No.: S3U06-0013-TW TT s Docket No: 0608-A41246twf.doc/NikeyChen 32 1354239 Description is to include an encoded bit stream that parses the first-syntax component, initializes a segment's content variable, and a -gram component The decoding engine, as well as the bmarization. Next, each binary value (bin) is decoded. The program includes obtaining a decoding of the content module and the binary values of the syntax components, and obtaining a meaningful word (c〇dew〇rd) alignment. Further step-by-step interpretation 'decoding I system 2 (10) decodes the syntax components, where each syntax component can represent quantization coefficients, motion vectors, and/or prediction matrices, or other related macroblocks (macr〇bl〇ck Parameter to represent the image or video specific field (fiel (〇 or frame (5)

7L per factory syntax can contain consecutive - or multiple binary symbols - carry value ' and the parent - binary symbols will be decoded into g' code system 200 according to the probability of occurrence of the input binary symbol control round out solution Some symbols (called primary symbols) provide a more efficient way of making money than their CABAC encoders. Red: 4 students' smaller bits/symbols to encode. The coder continues to::: 2 frequency statistics, and appropriately adjust the coding run 2 to enter the negative material type. The binary symbol with higher probability is called ^ = probable symbol ' MPS), while he, % &quot; this character 唬 (m〇st ◦east P - SymboI, LPS), : two is low The sex symbol combines 'each content model with a comparable, content model number value corresponding to the low likelihood symbol. ι and local likelihood symbols In order to decode each binary symbol, the solution is to receive a corresponding range, offset, and content, 〇 or 果. Content model is root

Client's Docket No.: S3U06-0013-TW TT^ Docket No:0608-A41246twf.doc/NikeyChen 33 1354239 According to the symbol type and the adjacent space (such as the current macro block or the adjacent macro area that belonged to the previous decoding) The content determined by the block) is selected from a plurality of possible content models. The content identification symbol can be determined by the content model and used to obtain a high probability symbol value and the current state of the decoding engine used to decode the program. Range represents an interval, each time

I I will reduce the range once by binary decoding. : The interval is divided into two sub-ranges, which correspond to high probability symbol values and low probability symbol values, respectively. The low probability symbol sub-range can be calculated by multiplying the range and the low probability symbol likelihood specified by the known content model. The high likelihood symbol subrange can be calculated by subtracting the low likelihood symbol subrange from the range. The offset is the criterion for determining the binary value of the decoding, and is usually initialized by taking the first 9 bits from the encoded bit stream. For known binary symbol decoding and content models, when the offset is less than the high likelihood symbol subrange, the binary value is a high probability symbol value, and the range used for the next decoding is set to a high probability symbol. range. Conversely, the binary value is determined by the low probability symbol, the inverse of the high probability symbol value is included in the associated content model, and the next range is set to the low likelihood symbol subrange. The result of the decoding process is a continuous decoded binary value that is evaluated to determine if the sequence conforms to a meaningful word. The relationship between the operation of the decoding system 200 and the CABAC decoding is summarized. The following description proposes various elements of the decoding system 200 in the content of the CABAC decoding program, and various variations in accordance with practical applications can be considered. Those skilled in the art will recognize that many of the terms used below are from the H.264 specification and will not be described again for brevity unless it is helpful to understand

Client's Docket No.: S3U06-0013-TW XT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 No, program and / or components, will be done again - step description. And the picture to the 6f picture shows the decoding system and related components =. Block diagram. As shown in the figure, the 'decoding system has a single C-ABAC Γ30 (in the first to fourth (fourth), which can be used interchangeably with the decoding system 200), so in the second embodiment: the amount =: Decode a single bit stream. The same principle: the decoding principle of d ^ 1 unit can be applied to "2()(), which can be simultaneously solved =: (for example, two) (four). In short, the second graph shows the block diagram of the deciphering component, and the The whistle shows the functional block diagram from the other component. The wth and 苐6E® display the solution 6D of the content memory function _ shows the block diagram used in the demonstration mechanism of the solution stone macroblock. The following description is for the content of the _set block decoding, but the principle proposed by the present invention can be used to decode (4) various blocks. Referring to FIG. 6A, the variable length decoding unit 53 〇 &amp; includes the cabac logic module 580 and Memory phantom, group 65. In the embodiment, the cabac logic module 580 includes three modules, which are a binary module 620, a get content (GCTX) module 622, and a binary. A computational decoding (BARD) engine 624. The binary computation decoding engine 624 further includes a state index (pStateldx) register 602, a high probability symbol value (valMPS) register 6〇4, and a code length range (c〇dlRange). Memory 6〇6, and code length offset register (codlOffset) 608. Variable length decoding Element 530a further comprises a memory module 650, which includes a content memory 564 (also referred to as a giant set adjacent block content (mbNeighCtx) memory array or memory contents

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 35 1354239 Example), local register 612, overall register 614, and SREG stream buffer/DMA engine 562 ( Also known as the DMA engine module, which will be further explained in Figure 6C), there are also scratchpads not shown. In one embodiment, the content memory 564 includes an array structure as shown in Figure 6C, as will be further explained hereinafter. The memory module 650 also includes a binary string

* I (:binstring) register 616. The interface of the variable length decoding unit 530a and the execution unit 420a includes a target (DST) bus 628, two source buses SRC1 632 and SRC2 630, a shared and thread information bus 634, and a delay/reset bus 636. The data on the target bus 628 can be transferred to the video processing unit internal or external to the graphics processing unit 114, either directly or indirectly (e.g., via intermediate cache, scratchpad, buffer, or memory). The data on the target bus 628 can be one of a number of different formats, including the Microsoft DX format or other formats. These data may include coefficients, macro block parameters, motion information, and/or IPCM sampling or other data. The variable length decoding unit 530a also includes a memory interface having an address bus 638 and a data bus 640. By obtaining the address from the address bus 638, the memory interface can access the bit stream data for accessing the data received by the data bus 640. In an embodiment, the data on data bus 640 may include unencoded video streams including various signal parameters as well as other data and formats. In some embodiments, a load-store operation can be used to access the bitstream data. Before starting to explain the different elements of the variable length decoding unit 530a, the overall operation of the execution unit 420a regarding CABAC decoding will be briefly explained.

Client's Docket No.: S3UO6-O0I3-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 1354239 Normally, according to the type of slice, the driver software 128 (Fig. 1) prepares and carries the CABAC shader to the execution unit. 42Ga. The CABAC shader uses a standard set of samples, plus a binary instruction, a fetch content instruction, and a binary calculation decode instruction to decode the bit stream. Because the table of contents used by the variable length decoding unit 5 3 0 a can be changed with the type of the segment, each of which is to be carried. In the embodiment - before the other instructions are issued, the first instruction executed by cabac coloring includes the INIT_ctx instruction and the INIT_ADE instruction. These two instructions cause the CABAC unit to start decoding the CABAC bit stream and load the bit stream from the indicator that automatically arranges the stream decoding to the first in first out buffer, which will be described later. Regarding the parsing bit, the data stream is converged from the memory interface and then buffered by the SREG stream buffer/DMA engine 562. Bitstream decoding is provided from the fragment data parsing stage. That is, a bit stream (e.g., a NAL bit stream) includes one or more pictures that will be cut into picture headers and a number of fragments. Fragments are usually associated with successive macroblocks. In an embodiment, the external program (i.e., external to the variable length solution unit 530a) parses the NAL bit stream 'decodes the fragment header and transmits an indicator pointing to the location of the fragment material (e.g., at the beginning of the segment). The hardware (plus software) can parse the H264 bit stream from the graph. However, in the embodiment, CABAC coding only occurs in the segment data and macroblock stages. Typically, the driver software 128 processes the bitstream from the fragment data stage, since this is the application and the AP (^: the function of the dance. The pointer to the location of the fragment data) also contains the first byte of the fragment data (eg : RBSPbyeAddress) and indicate that the bit stream starts or the header position (example

Client's Docket No.: S3U06-0013-TW TT*s Docket No:0608-A41246twf.doc/NikeyChen 1354239 For example: sREGptr) bite dream, _ ^ _ field shift indicator (eg one or more bits) . Tian + ★ moxibustion interpretation '. In some embodiments, the host processor (eg, the central processing unit 126 of the 1st to 1st, 1st, 1st, 1st) can be utilized to process the external port P program to provide picture stage combat, resolution, and fragment header decoding. . In some embodiments, the programming feature ' can be decoded in any stage due to the decoding system Λ / 〇〇. ’

5丨敬乡考g 5C diagram and the sixth diagram, SREG stream buffer/DMA engine 562帛 to respectively connect the busbar S6321 and the busbar SRC1 value of the busbar 630 and the scale SRC2 value, and corresponding to the forwarding Store and t-stock food materials. The SRBG Stream Buffer/DMA Engine 562 includes an internal bit stream buffer 562b, which in one embodiment can be a 32-bit το register in BigEndmn format and eight 128-bit (8 χ 128) registers. The initialization command of the escape mode is issued via the driver software to initially set the s RE G stream buffer/DMA bow engine 562. Once initialized, the internal buffer 562b of the SRE(} string buffer/DMA engine 562 is automatically managed. SREG = stream buffer/DMA engine 562 is used to preserve the position of the parsing bit. In a particular example, SREG φ Stream Buffer / DMA Bow | Engine 562 uses two registers, a fast 32-bit flip-flop with a slower 512 or 1 〇 24-bit memory. The bit stream uses bits. SREG The buffer S62a operates in bits, and the bit stream buffer 562b operates in a byte group, which saves power. Typically, the instructions operate in the SREG register 562a and use a few bits (e.g., 1-3). Bit) When the SREG register 562a uses more than -byte data, the data (in bytes) will be transferred from the bitstream buffer 562b to the SREG register 562a, and then the buffer indicator will Less

Client's Docket No.: S3U06-0013-TW TT,s Docket No:0608-A41246twf.doc/NikeyChen 38 1354239 The number of bytes transmitted. When the DMA of the SREG stream buffer/DMA engine 562 detects the use of 256 bits or more, 256 bits are extracted from the tracing body to refill the bit stream buffer 562t^, thus, The length decoding unit 530a implements a simple circular buffer (256 bit segments X 4) to record the bit hellen buffer 562b and provide padding. In one such embodiment, a single: a buffer can be used, but a circular buffer is required to calculate more complex indicators to keep up with the speed of the memory. An internal instruction to internal buffer 562b can be reached using an initialization instruction, referred to as an INIT-BSTR instruction. In one embodiment, the INIT_BSTR instruction and other instructions described later are issued by the driver software i&amp; Knowing the byte address and bit offset of the bitstream location, the INIT_BSTR instruction loads the data into the internal bitstream buffer 562b and begins the hypervisor. An instruction for the following format will be issued for each call processing fragment data: INIT_BSTR offset, RBSPbyteAddress An INIT_BSTR instruction is issued to load data into the internal buffer 562b of the SREG Stream Buffer/DMA Engine 562. The SRC2 register provides a byte address (RBSPbyteAddress) and the SRC1 register provides a bit offset. Thus, the following general instruction formats are available: INIT-BSTR SRC2, SRC1, where SRC1 and SRC2 in this instruction and other values corresponding to internal register 566 are not limited to these registers. In one embodiment, a 256-bit array of memory fetches is used to access bit stream data,

Client's Docket No.: S3U06-0013-TW TT^ Docket No:0608-A41246twf.doc/NikeyChen 39 1354239 It writes to the buffer register and transfers the 32-bit SREG of the bRhCj stream buffer/DMA engine 562 The memory 562a. In the embodiment, the data in the bitstream buffer pass is arranged in a byte group at the beginning of the operation of the other f for these registers or buffers. By using the platoon command, the _ of the (4) is called the τ instruction. The ABST instruction arranges the bit stream buffer 562b _ data, where the 'arranged bits (for example, padding bits) will be lost in the decoding program. abandoned.

When the SR-EG register 562a uses the data, the internal buffer job fills the data. In other words, the internal buffer 562b of the SREG stream buffer/dma engine 562 acts as a circular buffer modulo 3 (m〇dui〇) to input the 32-bit temporary of the SREG stream buffer/DMa engine 562. State 562a. The CABAC module 580, along with the read module 572, can use the read command to read data from the SREG register 562a. For example, in the H.264 specification, some symbols are fixed length codes, and the value is obtained by executing these specific bit number READ instructions, and zeros to the size of the scratchpad. The format of the READ instruction is as follows: READDST, SRC1, where DST corresponds to the output or target register. In an embodiment, the SRC1 register contains an integer value n that is not signed. The n-bit is read from the SREG register 562a by the READ instruction. When 256-bit data is used from the 32-bit temporary storage state 562a (eg, decoding one or more syntax components), the extraction operation is automatically started to obtain another 256-bit material for writing to the internal buffer 562b. Register, then enter the SREG register

Client’s Docket No·: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 40 1354239 562a is used. In some embodiments, CABAC is used if the data corresponding to a symbol decoded SREG register 562a has been used for a predetermined number of bits or bytes and the internal buffer 562b has not received any further data. Module 580 can perform a delay via delay/reset bus 636 to execute its I » his thread (eg, a thread independent of the CABAC decoder), such as a vertex shader operation. The DMA engine using the SREG Stream Buffer/DMA Engine 562 can reduce all of the buffers needed to compensate for memory delays (e.g., in some graphics processing units, there will be more than three hundred cycles). When a bit stream is used, it can be requested to flow into another bit stream tribute. If the bitstream lean is too low and the bitstream buffer 562b is at risk of a downflow (eg, a known number of cycles, letting the signal flow from the variable length decoding unit 530a to the processor pipeline), passable The delay signal is sent to the processor pipeline to suspend operation until the waiting data arrives at the bit stream buffer 562b. In addition, the SREG Stream Buffer/DMA Engine 562 originally had the ability to handle error bitstreams. For example, due to a bit stream error, it may not be detected at the end of the segment. This detection error can result in a complete decoding error and the use of bits in subsequent patterns or fragments. The SREG Stream Buffer/DMA Engine 562 records the number of bits used. When the number of bits used is greater than the preset limit (which can be changed for each segment), the handler is terminated and an exception signal is sent to the processor (for example, the host processor). The processor then performs the encoding to attempt to reply from the error. Please refer to Figure 6A and Figure 6B for further description of variable length

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 41 1354239 Decode the function of 53〇a, especially the decoding engine (for example: BARD engine or module 624) and content Initialization of variables. The content status and binary calculation decoding module 624 is initialized at the beginning of the segment and before the grammatical component of the first-large block is deciphered. In one embodiment, the driver 128 issues an INIT-CTX instruction and an INIT-ADE instruction to initiate initialization. The INIT_CTX instruction initiates the CABAC decoding mode and initializes one or more table of contents (eg, remote storage or on-wafer memory, such as ROM). The INIT-CTX instruction can be executed according to the following instruction formats: 丽T_CTX SRC2, SRC1 For the INIT-CTX instruction, the operand SRC1 can have one or more of the following H.264 macroblocks depending on the bit position. The values of the parameters: cabac_init_idc, mbPerLine, constrained_intra_pred flag, NAL_unit_type(NUT), and MbaffFlag. It should be noted that constrained_intra-pred_flag, NAL_unit_type(NUT), and MbaffFlag correspond to known H.264 macroblock parameters. Further, according to the bit position, the operand SRC2 has the following values: SliceQPY and mbAddrCurr. In an embodiment, it is further explained that the execution of the INIT-CTX instruction (i.e., the initialization of the CABAC table of contents) requires a cabac_init_idc and a sliceQPY (e.g., quantization) parameter. However, to initialize the entire CABAC engine requires three instructions, the INIT_BTSR instruction, the INIT_CTX instruction, and the INIT_ADE instruction, so the available bits in 'SRC1 and SRC2 (for example: all 64-bit or 32-bit each) can pass the other for

Client's Docket No.: S3U06-0013-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 1354239 Parameters of CABAC proximity content. Therefore, the two source registers SRC1 and SRC2 664 can contain the following values: SRC1[15:0] = cabac_init_idc SRC1[23:16] = mbPerLine SRC 1 [24] = constrained_intra_pred_flag » One I I — :SRC1 [27:25 ] = NAL_unit_type (N; UT) SRC1[28] = MbaffFlag SRC1[31:29]=Undefined SRC2[15:0] = SliceQPY SRC2[31:16] = mbAddrCurr

The value of SliceQPY is used to initialize the state machine (not shown) within bit stream buffer 562b. While various known pattern and segment parameters have been discussed above, some additional parameters regarding variable length decoding unit 530a are provided. In an embodiment, cabac_init_idc is defined for segments that are not encoded as I-picture and switched I-picture (SI). In other words, cabac_init_idc can only be defined for P, SP, and B segments, and 'cabac_init_idc' is the default when I and SI segments are received. For example, when about 460 inner valleys (such as I and SI fragments) are initialized, 'cabac init idc can be set to 3 (because the value of cabac_init_idc can only be 0~2 according to the H.264 specification) 2 bits to indicate that the fragment is I or SI. The variable length decoding unit 530a may also use the iNIT_CTX instruction to initialize the local register 612 and the macroblock neighboring content memory 564 array.

Client's Docket No.: S3U06O013-TW TT5s Docket No: 0608-A41246twf.doc/NikeyChen 43 1354239 Column structure or component 'includes temporary benefits associated with temporary neighboring macroblocks. Referring to Figure 6C, in one embodiment the 'macroblock' adjacent content memory 564 is located above the figure. In an embodiment, the macroblocks of the macroblocks adjacent to the content memory 564 are arranged adjacent to the content memory as memory, and the arrays are configured to store data about the rows of the macroblocks. As shown, 1: macroblock neighboring content memory 564 includes array elements mbNeighCtx[0, 1, i-1, i, i+1, ... 119] (labeled 601), each element is used Stores one of the 120 macroblocks into one column (for example, 1080p for 1080p corresponding to HDTV). Currently 11^]\^811(^乂€;1111^111; the register 603 is used to store the currently decoded macroblock, and the mbNeighCtxLeft register 605 is used to store the previously decoded neighbor (left) macro In addition, the indicators 607a, 607b, and 607c (indicated by arrows in FIG. 6C) point to the registers 603, 605 and the array element 601. In order to decode the current macroblock, the decoded data is stored in mbNeighCtxCurrent. 603. Knowing the content nature of CABAC decoding, the current macroblock is decoded according to the information collected when the macroblock was decoded last time, that is, the left macroblock is stored in the left mbNeighCtxLeft register 605. And pointed by the indicator 6〇7b, and the upper macro block is stored in the array element [i] and pointed to by the indicator 607c. Continue to explain the initialization instruction, the INIT_CTX instruction is used to initialize the current macro block (such as a macro) The blocks are adjacent to the upper and left indicators 607c and 6〇7b of the adjacent macroblocks. For example, the left indicator 607b may be set to 〇 and the upper indicator 607c may be set to 1. In addition, the INIT_CTX instruction Update register 614 overall.

Client's Docket No.: S3U06-0013-TW TTss Docket No; 0608-A41246twf.doc/NikeyChen 44 1354239 Regarding the initialization of the table of contents, the variable length decoding unit 530a establishes one or more content tables, also called the INIT_CTX command. For CTX-TABLE. In one embodiment, the CTX-TABLE may be a 4x460x 16-bit table (8 bits for m, another 8 bits for η, with a positive or negative value) or other data structure.

The I state index register 602 and the high probability symbol value register 604 hold the pStateldx value and the VaiMPS value. The INIT_ADE instruction initiates a binary computation decoding module 624, also known as a decoding engine. In one embodiment, the INIT-ADE command is invoked after the INIT-BTSR instruction is completed. After executing the iNIT_ADE instruction, the variable length decoding unit 530a creates two registers, which are a code length range (codlRange) register 606 and a code length offset (codlOffset) register 608, with the following instructions or Values: codlRange = 0x01 FE and codlOffset = ZeroExtend (READ(#9), #16) As such, in one embodiment, these variables can be 9-bit values. Regarding the codlOffset instruction, the 9-bit element is read from the bit stream buffer 562b and the zero extension (ZeroExtend) is stored in the 16-bit code length offset register 608. Some embodiments may also use other values. The binary calculation decoding module 624 uses the values stored in the registers 6〇6 and 608 to determine whether to output 0 or 1' and these values will be updated after a carry decoding. In addition to the initialization code length range register 606 and the code length offset register 608, the INIT_ADE instruction operation also initializes the binary string register.

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 45 1354239 616. In one embodiment, the binary string register 6i6 can be a ternary register that receives the bits from the binary computation decoding module. Other sizes of registers can be used in some embodiments. When the macro block is coded into I_PCM data, the binary counts the stone, and the group 624 is also initialized. It is known that the Ι-PCM data contains the pixel code = the model H.264 specification, which does not Will: conversion or predictive model application: as before: according to the data. For example, LPCM can be used for non-destructive (1〇ssles :: use. 〃,, rain 吟

The architecture and instructions related to parsing the bit stream and initializing various decoding systems, and the following are described above. The following describes the information and content of the binary imitation ', the system 70 model, and the decoding according to the model and content. More, = order. In general, the variable length decoding unit 530a is configured to obtain all possible binarizations of the syntax element 'SE', which is at least sufficient to obtain the model by the knife progression module 620 and the BIND instruction. The variable length decoding unit 530a further obtains the content of the known § _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In effect, the GCTX/BARD instruction is called, and a bit is rounded out to the binary string register 616 until it finds that the meaningful word with the known syntax component = constitutes a loop. In one embodiment, each time the binary value is decoded: a corresponding decoded bit is provided to the binary string register 616, and the _ carry string register is read back to the content module 622 until a match is found . The decoding system architecture using a single variable length decoding unit 5 3 〇 a is explained in more detail while referring to FIGS. 6A and 6B, via the driver software ‘”128

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0 (508-A41246twf.doc/NikeyChi 46 1354239, issued BIND instruction to enable the binary module 620. In the embodiment, the BIND instruction has the following Format: BIND DST, #Imml6, SRC1, where 'DST corresponds to $target register 652, and #Imml6 corresponds to 16-bit current value, and SRC 1 corresponds to input register SRC 1. Input of BmD instruction operation contains syntax The component (including the 16-bit current value Imm) and the content block type (ctxB1〇ckCat). The syntax component can contain any of the syntax components of the H.264 specification (for example: MBTypelni, MBSkipFlagB, IntraChromaPredMode, etc.) The BIND phase causes the driver software 128 to read the syntax components from the form (or other data structure) stored in the memory (eg, on-wafer memory or remote memory) and obtain the syntax component index (SEIdx). The syntax component index is used to access other forms or data structures to obtain the macroblock parameters as described below. In an embodiment, the target register 652 contains 32 bits. The memory has the following format: bit 0-8 ( ctxIdxOffset), bit 16-18 (maxBinldxCtx), bit 21-23 (ctxBlockCat), bit 24-29 (ctxIdxBlockCatOffset), and bit 31 (bypass Flag) These values (eg, ctxIdxOffset, maxBinldxCtx, etc.) are passed to the fetch content module 622 as a content model. In this embodiment, any undefined reserved bit may be 0. According to the syntax component index and The result of the pairing of the content block type, ctxIdxBlockOffset can be obtained via a form or other data structure stored in the remote or on-chip memory.

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 47 1354239 A description of a non-limiting embodiment of the form content:

codeNum (k) Coded_block_pattem Intra-4x4 Inter 0 47 0 1 31 16 2 15 1 1 3 0 . 2 4 23 4 5 27 8 6 29 32 7 30 3 8 7 5 9 11 10 10 13 12 11 14 15 12 39 47 13 43 7 14 45 11 15 46 13 16 16 14 17 3 6 18 5 9 19 10 31 20 12 35 21 19 37 22 21 42 23 26 44 24 28 33 25 35 34 26 37 36 27 42 40 28 44 39 29 1 43 30 2 45 31 4 46 32 8 17 33 17 18 34 18 20 35 20 24

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 48 1354239 --------_ 36 24 19 37 ------ 6 21 38 ---- 9 26 39 22 — 28 40 25 23 41 32 27 42 33 29 43 14 30 44 36 22 45 40 25 46 --------- 38 38 47 --------- 41 41 Upon receiving the undefined content block type, the variable length decoding unit 53A may treat the undefined parameter as 〇 such that ctxIdxB1〇ck〇ffset is considered to have a value of 0. The call BIND command also causes the reset signal (Rst_Signal) to be output from the binary module 620 to the binary calculation decoding module 624, as explained below. To illustrate the various inputs and outputs of the binary module 620, the operation of the binary module 62A in accordance with at least one embodiment is presented herein. Calling the binary module 620, the binary module 62 retrieves the syntax components and, via the software, knows the known index of the component (SEIdx). Using the syntax component index, the binary module 620 looks up the form to obtain the corresponding values for maxBinldxCtx, ctxIdxOffset, and bypassFlag. This lookup value is temporarily stored in the predefined bit configuration of the target register 652. In addition, using the syntax component index and the content block type, the binary module 620 performs a second form lookup (e.g., remote memory or on-wafer memory) to obtain a ctxIdxBlockOffset value. Second time

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 The lookup value is also temporarily stored in the target register 652. Therefore, the determined value will be used to establish the target register 652 as a 32-bit value output target. For some grammatical components, additional information (syntax components and content, except for the block type) can be used to initiate the H.264 decoding operation. For example, for macroblock parameters like SigCoeffflag and lastSigCoeffFlag, the value stored in the array element maxBinIdxCtx[1] of the macroblock adjacent to the content memory 564 and the input content block type value are used to determine the macro. The block is the field code or the frame code. In some embodiments, even with different syntax components, the same number of grammatical components are used for these flags and then identified using mb_field_dec ding a flag (mbNeighCtx[l] field). In addition to the above-described functions relating to a carry module 620, it is noted that in FIG. 6B, the binary module 620 can incorporate the binary index register 654, the multiplexer unit 656, and/or the forwarding register F1, and F2. As for the binary index register 654 and the multiplexer unit, the multiplexer unit provides an output SRC1 (e.g., the value in the scratchpad SRC1) to the fetch content module 622 based on the different inputs. With respect to the forward register shown as F1, when the bind (or GCTX) instruction produces a result, the result can be written to the target register (e.g., target register 052 and/or forwarding register F1). The forwarding flag in the known command can indicate whether an instruction and the corresponding module (e.g., the content module 622 or the binary decoder module 624) use the forwarding register and F2. The symbol representing the forwarding scratchpad includes F! (ie using the forwarding source)

Client's Docket No.: S3U06-0013-TW TT's Docket No; 0608-A41246twf.doc/NikeyChen 50 &amp; the value 'in one embodiment may be represented by bit 26 in the instruction) to (ie using forwarding source 2 The value, in one embodiment, may be as indicated by instruction ^ 70 27). The data of the acquired content module 622 and the binary-resolved module 624' can be forwarded to individual inputs, and the description has been made to describe the binary module 620 to: and related programs, here will be How the acquired content module 622 obtains the known type of content and the binary index in terms of the GCTX instruction. Briefly, the input to get content module 2 contains maxBinidxCtx, binldx, and CtxIdxOffset, as described below. The get content module 622 uses the CtxIdxOffset and binldx values to calculate the value of Ctxldx (which is an output, representing an exemplary format of the content index instruction as follows: GCTX DST, SRC2, SRC1, where SRC1 corresponds to the output by the multiplexer unit 656 The value is stored in register SRC1, and SRC2 corresponds to the value output by target register 652 and stored in register SRC2, and DST corresponds to the target temporary device. In one embodiment, each register It has the following values: SRCl[7:0]=binIdx; when the current syntax component contains eight codedBlockPattern, the value of SRC1 (from the multiplexer unit 'and as input to the content module 622) can be a binary cable The value of the register 654. ', SRC1 [15:8] can be levelListldx (when calculating sigC〇effpia), lastSigCoeffFlag or mbPartldx (when counting the first #雨码块图

Client’s Docket No.: S3U06-0013-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 1354239 Ref_Idx or binldx). When the syntax component is sigCoeffFlag or lastSigCoeffFlag, multiplexer unit 656 can be used to transmit levelListldx. SRC 1 [16] may contain the iCbCr flag, and when the value is 〇, the block is a Cb chrominance block. In addition, 'SRC1 [丨6] may contain the L0/L1 value, and if it is L0, its value is 0. Those skilled in the art can know from the content of the present invention that L0/L1 is a graphic reference list for motion compensation prediction (L). 〇= iist0 · LI = listl ). SRC1 [21:20] = mbPartitionMode SRC2 [8:0] = ctxIdxOffset SRC2 [18:16] = maxBinldxCtx SRC2 [23:31] = ctxBlockCat SRC2 [29:24] = ctxIdxBlockOffset SRC2 [31] = bypassFlag again ' DST This includes getting the output of the content module 622 with the following values: DST [15:00] = ctxldx DST [ 23:16] = binldx DST [ 27:24] = mbPartldx DST [29:28] = mbPartitionMode DST [30] = The L0 acquisition content module 622 can also interact with the forwarding register. Therefore, when using the forwarding register, the instruction can obtain the format of GCTX.F1.F2, and ^F1 and F2 indicate that the forwarding register is used, that is, there are 2 bits in the pointer ^

Client's Docket No.: S3U06-00! 3-丁W TTJs Docket No:0608-A41246twf.doc/NikeyChen 52 1354239 _ WFl and F2) If not obtained - or two forwarding flags, it means that the Mx temporary state is not use. When these bits are set (for example, set to !), the value temporarily transferred to (for internally generated value) is used. Otherwise, the value of the source register is used. Therefore, the forwarding register provides a hint to the compiler about the earliest possible time to issue an instruction. When the command is not made, the "Day Forward" command may encounter a delay that has been read after knowing the writer of the source register. Luke 对 for the GCTX command, when the reset signal (Rst-Signal) is set to day T, the value of SRC1 is 〇. When the operation is established, SRC1 is the value of the Mnidx from the internal content acquisition module 622 plus i, otherwise SRC1 is the binIdx value from the execution unit register. The output of the two 'homing module 62' can be used as the forward SRC2 value for the GCTX command and the bard command. In the following instructions, the BIND instruction will not be issued until the bard instruction is used to forward the scratchpad. Further, the reset signal and the F1 forward signal are combined into a signal (e.g., a 2-bit signal) Φ {F1, reset}' indicating whether the SRC1 value input to the acquired content module 622 includes a binIdx value or a forward value. Another effect of providing a reset signal is to clear and reset the binary string register 616 and reset the binary index register 654 to zero. Continuing with the discussion of the content module 622 and the content information, in one embodiment, the information shown in Tables 2 and 3 below corresponds to the values of the structure neighboring content memory 564 and the mbNeighCtxCurrent register 603, respectively. The mbNeighCtxCurrent register 603 contains the decoded output of the current macroblock. In the last part of the current macro block processing, issue

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 53 1354239 CWRITE command that copies information from the mbNeighCtxCurrent register 603 to a location within the array of adjacent content memory 564. The copied information is then treated as the top neighbor value. Face size (ί· transformj_size_8x8_flag 1 0 mb_fieldjdecode_flag 1 1 mb_skip_flag 1 2 lntra_chroma_pred_mode 2 4:3 mb_type 3 7:5 codedBlockPattemLuma 4 11:8 codedBlockPattemChroma 2 13:12 coded Flag Y 1 14 codedFlagCb 1 15 codedFlagCr 1 16 coded FiagTrans 8 24:17 refldx 8 32:25 predMode 4 36:33

Table 2 Parameter size lion transform_size—8x8” lag 1 0 mb—field—decode—flag 1 1 mb—skip—flag 1 2 lntra_chromajDred_mode 2 4:3 mbQpDeltaGTO 1 88 codedBlockPattemLuma 4 11:8 codedBlockPattemChroma 2 13:12 coded Flag Y 1 14 codedFlagCb 1 15 codedFlagCr 1 16 coded FiagTrans 24 87:64 refldx 16 52:37 predMode 8 60:53 mb_type 3 63:61 Table 3

Client's Docket No.: S3U06-0013-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 54 1354239 In an embodiment, the parameter codedFlagTrans is divided into three parts. For example, the starting 4-bit system has a content block type of 〇 or 1, and the upper 4-bit system has a content block type of 3 or 4. The above 4 bits can be further divided into two parts, the lower 2 bits give iCbCr==0 and the other 2 bits to iCb (^r=l. The parameter predMode (predictive mode) has one of the following three options: predLO = 〇, predLl = 1 and NiPred 2 2. The 6D shows an example of the parameter refidx structure with reference to Table 2 and Table 3. It should be noted that the parameter refldx is related to the index of the reference image list used in image restoration. The above structure can provide optimization of memory and logic circuits. As shown, the computational syntax component structure includes a top column 609 of a macroblock, a macroblock partition 611 (such as the four regions shown), a value of 613, and The storage bit value Gt 〇 (greater than 〇) 615 and the storage bit value GU of each L0/L1 value are greater than υ 617. Usually, the top neighboring macro block 609 needs to be accessed, but the bottom column of the macro block is also Access is required, which is divided into an embodiment of a 4x4 square matrix, resulting in four messages such as 61 for each mbPartition 611, L 〇 / L1 value 613, but not actual values. About L0 values and L1 values The judgment for i or greater than Cui is determined. In an embodiment The decision is obtained by storing Gt〇6l5 and 617 two-element, which is used to calculate the syntax component. 11 Step-by-step simply describes the computational syntax component structure, the two best rows. In the optimization, only keep 2 The bit (although the reference value is 2 is larger), and no more bits are needed for the decoding of the variable length decoding unit illusion to calculate the syntax component. Decode all the values and maintain the execution of the single = memory or memory (Example: L2 cache memory). Second optimization port

Client’s Docket No.: S3U06-00I3-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 55 1354239 Four elements are maintained (eg two at the top and two at the left). The four elements are recycled' and the last value is written in the neighborhood by the CWRITE instruction, which is stored in memory. Thereafter, only 16 bits are maintained in the mbNeighCtxCurrent register 603, and only 8 bits are maintained in the mbNeighCtxLeft register 605 and the top mbNeighCtx element 601 of the array 564. The storage logic uses re-storage because all calculations of the decoded reference value are replaced by Boolean operations with fewer bits. The mb_type includes the following list four.

Mb_type 4'bOOO SI 4'b001 I_4x4 or l_NxN 4'b010 I_16x16 4'b011 l-PCM 4'b100 P_8x8 4,b101 B_8x8 4'b110 B_Direct_16x16 4,b111 Others Table 4 does not show additional temporary storage in Figure 6B It can be used, such as mbPerLine (for example, 8-bit 'no sign'), mb_qp_delta (8-bit, plus sign), and mbAddrCurr (16-bit, current macro block address). For the mbAddrCurr' 1920x1080 array is implemented, although it only requires 13 bits. Some embodiments will use 16 bits to aid in the execution of 16-bit calculations. Values from the previously described scratchpad are also stored in the overall register 614. The values stored in the overall register 614 are copied and stored in the scratchpad to aid in hardware design. In an embodiment, the overall register 614 includes a format

Client's Docket No.: S3U06-0013-TW TT^s Docket No:0608-A41246twf.doc/NikeyChen 56 1354239 The 32-bit scratchpad is included to contain values corresponding to mbPerline, mbAddrCurr, and mb_qp_delta, except for the NUT, MBAFF_FLAG and other values of chroma_format_idc. The different fields within the overall scratchpad 614 can be updated using the INSERT instruction. The exemplary format of the INSERT instruction is described below:

' I INSERT DST, #Imm, SRC1 : In the above INSERT instruction, an embodiment of #Imm includes a 10-bit number, where the data of the first 5-bit width and the position where the above 5-bit designation data is inserted. Input parameters include the following:

Mask = NOT(0xFFFFFFFF«#Imm[4:0])

Data = SRC1 &amp; Mask SDATA = Data«#Imm[9:5] SMask = Mask«#Imm[9:5] The output DST can be expressed as follows: DST - (DST &amp; NOT(sMask)) I SDATA Note Some of the intercept bits (eg, NUT (NAL_UNIT_TYPE), C (constrained-intra_pred_flag)), MBAFF_FLAG, mbPerLine, and mbAddrCurr values may also be written/initialized to the overall scratchpad 614 using the INIT_CTX instruction. In one embodiment, local register 612 includes a 32-bit scratchpad having fields corresponding to b, mb_qp__delta, numDecodAbsLevelEql, and numDecodAbsLevelGtl. These fields can be updated using the INSERT directive. Local register 612 is also initialized such that b = 0, mb_qp_delta = 0, numDecodAbsLevelEql = -1 and

Client’s Docket No. : S3U06-0013-TW TT’s Docket No: 0608-A41246twf.doc/NikeyChen 1354239 numDecodAbsLevelGtl = 0. The instructions used to provide initialization can use the following format: CWRITE SRC1 ' where SRC1 [15:0] = mbAddrCurr. CWRITE SRC1 updates the mbAddrCurr field of the general register 614. After the neighbor: near element structure and a brief description of its decoding, the additional functions provided by the CWRITE instruction will be described.

In CABAC decoding, 'syntax values are expected and are mimicked from their neighboring macroblocks. The different methods are described as follows, which provide an embodiment of the variable length decoding unit 53a that determines the left and upper neighboring macroblocks and how to determine that the macroblocks are actually usable. As described earlier, the decoder uses neighboring values (e.g., from a macroblock or block to the top and to the left). In an embodiment, the binary calculation decoding engine 624 calculates the following equation 'which uses the current number of macroblocks and the number of macroblocks located in one line (mbPerLine) to calculate the address of the upper macroblock and the left side. Is it available with the macro block above? For example, to determine whether a neighboring macroblock (eg, left neighbor) is present (ie, valid), an operation (eg, mbCurrAddr% executable mbPerLine) can be performed to check if the result is 〇. In one embodiment, the following calculations are performed: a =: [mbCurrAddr%mbPerLine) a = mbCurrAddr - mbCurrAddr mbPerLine x mbPerLine

Client's Docket No.: S3U06-0013-TW TTss Docket No:0608-A41246twf.doc/NikeyChen 1354239 Note that mbCuirAddr is related to the location of the macroblock corresponding to the binary symbol to be decoded, and mbPerLine and each It is known that the number of macroblocks in the column is related. The above calculation is performed using a division, a multiplication, and a subtraction. Further describing the decoding mechanism implemented by the binary decoding decoding 620, referring to FIG. 6E, which shows the image to be decoded (16χ8 macroblock and mbPerLine=16). When decoding the 35th macroblock When the mbCuirent flag is 35 and the 36th macroblock has not been fully decoded, it needs to be from the previously decoded upper macroblock (labeled 19) and the left macroblock (labeled 34). Information. Information on the upper macro block can be obtained from mbNeighCtx[i], where i=mbCurrent%mbPerLine. So, for this example, soil =

35% 16 ’ then i=3. After the current macroblock is decoded, the CWRITE instruction can be used to update the mbNeighCtxLeft 605 and mbNeighCtx[i] 601 in the array. For another example, consider the following: mbCurrAddr e [Ο: max MB -1] where maxMB is 8192 and mbPerLine=120. In one embodiment, in addition to being implemented by multiplying (1/mbPerLine), it looks up a table of memory stored on the wafer (e.g., a table of 120 x 11 bits). When mbCurrentAddr is 13 bits, a Ι3χΐ 1 bit multiplier can be used. In one embodiment, the result of the multiplication operation is completed, the upper 13 bits are stored, and the multiplication of 13x7 bits is performed to store the lower 13 bits. At last,

Client's Docket No.: S3U06-0013-TW TT5s Docket No:0608-A41246twf.doc/NikeyChen 59 1354239 Perform a 13-bit subtraction to determine the order of the "a"^ operation will use 2 cycles' and the result will be Stored for use in other operations, and once again when the mbCurrAddr value changes. In some embodiments, a modulo operation will not be performed, instead a colored logic circuit within the execution unit may be used to provide a first mbAddrCurr value aligned to the first line of the slice. For example, the above-described coloring logic circuit can perform the following calculations: mbAddrCurr = absoluteMbAddrCurr - η * mbPerLine. Because some of the HL264 Flexibility Macroblock Ordering (FMO) modes have some very complex neighboring structures, in order to replicate these modes, the left/upper availability can be calculated in the extra shader of the decoding system 200, And loaded into one or more registers of the variable length decoding unit 53A. By leaving the variable length decoding unit 53a, the hardware complexity can be reduced when all η.264 modes are activated for symbol decoding. The CWRITE instruction copies the appropriate block from mbNeighCtxCurrent 603 to mbNeighCtxTop[] 601 and mbNeighCtxLeft[] (for example, the left macro block of array 564). The specific mbNeighCtxTop[] 601 and mbNeighCtxLeft[] data are written depending on whether mBaffFrameFlag (MBAFF) is set and whether the current and previous macro blocks are blocked or frame decoded. When (mbAddrCurr % mbPerLine = = 0) is established, the flag mbNeighCtxLeft 605 is not available (for example, it is initialized to 0). The contents of mbNeighCtx memory 564, local register 612, and overall register 614 can be removed using the CWRITE instruction. For example, the CWRITE command moves the related content of the adjacent content memory 564 to the ith

CUenVs Docket No.; S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 60 1354239 The left and upper blocks of a macroblock (such as mbNeighCtx[i] or the current macroblock), The mbNeighCtxCurrent register 603 is also cleared. As described above, the upper indicator 607c and the left indicator 607b are associated with the adjacent content memory 564. After the CWRITE instruction, the upper index is incremented by 1, and the contents of the current macroblock are moved to the upper t position and the left position within the array. The above mechanism can reduce the number of read/write 埠 in the memory array at the time of read_/write. The contents of the neighboring content store 564, the local register 612, and the overall register 614 can be updated using the INSERT instruction, as previously described. For example, you can use the INSERT instruction (for example: INSERT $mbNeighCtxCurrent_l, #ImmlO, SRC1) to write the current macro block. Subsequent operations do not affect the upper indicator 607c and the left indicator 607b (ie, only write to the current location). The INSERT instruction and the update from the binary computation decoding module 624 are written to the mbNeighCtxCurrent array 601 of the adjacent content memory 564. The left indicator 607b points to the element of the memory 564, which is identical to the adjacent (near mbNeighCtx 601) array element (i.e., mbNeighCtx[i-l]). In view of the above regarding the content and model information, the binary calculation decoding module 624 and the calculation decoding will be discussed below based on the content and model information. The binary calculation decoding module 624 operates under the BARD instruction. The exemplary format of the BARD instruction is described below: BARD DST, SRC2, SRC1

Client's Docket No.: S3U06-0013-TW TTJs Docket No: 0608-A41246twf.doc/NikeyChen ^ 1354239 It provides a binary calculation decoding operation, and a single-bit output. The input parameters are described as follows - the carryover solver causes SRCi = binIdx/ctxIdx to obtain the output of the board, and 622; 〇 KC2 = bypassFlag &gt; The output of the transport module 620 when using the forward register ,—

BARD.F1.F2, which instructs to forward the temporary cry. The 々 々 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒 勒The signal is not cleared until the first call is received. In the middle, the binary calculation decoding module 624 receives the content index I (ctxldx) value and the indicator to the current bit analysis position from the obtained content module 622 ❸ decoding bit stream (bmldx). The binary calculation solver module 624 uses the offset and range values from the code length offset register 6 〇 8 and the code length range temporary 606 to record the current interval state of the decoding engine (offset) 'Offset + range'. The binary computational decoding module 624 uses the content index value to access the table of contents (CTX_TABLE), which in turn is used to access the currently possible state pStateldx and the high likelihood symbol value. Use pStateldx (for example, from a form stored on the remote or on-wafer memory) to renew the low probability symbol sub-range value, the next high probability symbol value, and the next possible low probability symbol.

Client's Docket No.: S3U06-0013-TW TT5s Docket N〇:0608-A41246twf.doc/NikeyChei 62 to 239 according to the high probability symbol value, - the greedy 'binary calculation decoding module' Possibility probability symbol value. Binary meter*: the high of the binary symbol (bit or: carry value, the example module 624 rounds out the binary signal 2 616. Then 'down-one: into the b-bit: 乂:, The carry string reset procedure, for example, from: _word $ γ gate or 回 different content 622 of the feedback 658 ° to the content module: the two sign of the possibility symbol value and the possibility state is written to 彳The purpose is to note that the transfer register F1 is used for forwarding. When used, when the signal is forwarded, the command can be used to temporarily suspend the F2. For example, when the relay is turned from the binary module _ There is no delay, and there is no delay, and in the lower -__/Gc^xH622, the = module 622 is forwarded to the binary 曰 in the = use to 4 cycles. When in the cycle = 624 'will cycle (j +5) Issue the BARD command 曰·' to fill up to 4 N〇p in the slot. In the absence of &quot; the delay bit calculation decoding module 624, there is no delay to forward to the second

If the code module 624 is forwarded to obtain the content module, the U.S. BARD command can be sent from the carry calculation decoding module 624 to θ π in the period (4). If the second binary string is reserved: !=-the carry-in module (four), - push (four) Iraq...

Hlfnt, s D〇cket No.; S3U06-0013-TW TT's Docket No: 〇6〇8-A41246twf.doc/NikeyChen - There is a switch between the carry-in 四(4), then no delay exists. ^ 63 1354239 By retaining the second binary string, BARD iBARD_8 can be allowed to be issued for bypass situations that do not have to endure delays.曰々CAVLC decoding has been described for variable length decoding unit a 'for CABAC decoding'. For the decoding system, the CAVLC embodiment will now be referred to as 'variable length decoding unit 53%, such as帛 from the map

Before describing the CAVLC architecture, (iv) the H.264 CAVLC procedure describing the content in the variable length decoding unit 530b. It is known that the C A V L C program encodes the level (e.g., size) of a macroblock or its location number, and when the level is repeated (e.g., a few cycles) to avoid the need to decode each bit. The bit stream view receives and analyzes the above information, wherein the buffer is filled when the information is used by the decoding engine of the decoded variable length decoding unit 530b. The variable length decoding unit reverses the encoding process and reconstructs the signal by taking a macro block from the pure bit stream and having a running block and running coefficients. Thus, the variable length decoding unit 5 receives the macroblock money from the bit stream buffer, and analyzes that the stream has been separately leveled and the operating coefficient value is given to the level and the temporary storage of the array is operated. For example, the level and the run array read the pixels corresponding to the block 4 of the block in the macro block, then clear the level and run the array for use by the next block. According to the 264.264 standard, the software can use all the macroblocks according to the 4χ4 building block. The general operation of the information, the following is now available on the decoding macro block

Client's Docket No.: S3U06-0013-TW TT5s Docket N〇: 0608-A41246twf.doc/NikeyChen 64 1354239 The different components proposed in CAVLC^_ 530b can be used to meet the requirements of the vertical length. Those who are familiar with this technique can know that; second;: the labels of the different parameters are included in the 6th noon term (for example, unless it is helpful to understand the different two = clean: re-status, The description of one step. The Yifan piece will be re-entered into the 7th frame showing the variable length solution stone unit ^ - block diagram. The 7th frame shows the single-variable length second instance of the variable length The decoding unit 530b is used to make a single stream of 53%, and the same principle can be applied to the table structure with the amount of ": decoding multiple objects such as heart = early = v B CA; LC ' decoding. Although the description is based on the content of block decoding, the principles proposed by the present invention can be applied to various block decodings, and the same portions will not be described in further detail.

The variable length decoding unit is used to analyze the bit stream, initialize the decoding hardware and the scratchpad/memory structure&apos;, and stage_run decoding. The above-described functions of the above-mentioned H.264 standard CAVLC decoding program will be further described. Regarding the bit stream buffer operation, the SREG stream buffer/DMA engine 562 is shared between the CABAC and cavlc operations, so in addition to the difference in operation between the money and the CABAC and CAVLC modes, the The same parts are further described. Both the CABAC and CAVLC decoding embodiments use the same content memory 564, but the fields (e.g., structures) are not the same, which will be described later. So when Ca VLC

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 65 1354239 The inner valley memory 564 operation is similar to the CABAC operation described above, and the same part will not be further described for the sake of brevity. . In addition, the overall register 614 and the local register 612 are also used, and thus the same portions will not be further described. Referring to the figure, the variable length decoding unit 530b includes a hardware module that includes a coefficient register (t〇ken), a coeff-token 710, a level code module (CAVLC_LevelCode) 712, Level module (CAVLC-Level) 714, level module (CAVLC-L0) 716, zero level module (CAVLC-ZL) 718, running module (CAVLC_Run) 720, level array (LevelArray) 722 And run the array (RunArray) 724. The decoding system also includes a SREG stream buffer/DMA engine 562, an overall register 614, a local register 612, and a neighboring content memory 564 as previously described. The interface of the variable length decoding unit 530b and the execution unit 420a includes one or more target buss and corresponding registers (eg, target registers) of the CABAC embodiment as described above, and two source sinks. Arrange with the corresponding scratchpad (SRC1 and SRC2, etc.). Typically, driver software 128 (Fig. 1) prepares and loads the C A VLC shader to execution unit 420a, depending on the type of segment. The CAVLC shader uses a standard instruction set plus an additional instruction set 'including coeff_token, CAVLC_LevelCode, CAVLC_Level, CAVLC L0, CAVLC_ZL, and CAVLC_Run instructions to decode the bit stream. Additional instructions include READ_LRUN and CLR_LRUN instructions for the read and clear operations of the level array 722 and the run array 724. in

Clients Docket No.: S3U06-0013-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 66 1354239 In one embodiment, the first instruction executed by the CAVLC shader includes the iNIT_CTx instruction and the init_ade before issuing other instructions. instruction. These two instructions initialize the variable length decoding unit 53 〇 b to decode the CAVLC bit stream ' and load the bit stream from the index of the automatically arranged string decoding to the FIFO buffer, which will be described later. Therefore 'variable length decoding unit

I 530b can be used to analyze the bit stream, initialize the decoding hardware and scratchpad/memory structure, and stage-run decoding. The above functions of the CAVLC decoding program of the H.264 standard will be further described later. Regarding the instruction to analyze the bit stream, in addition to the READ and INIT-BSTR instructions previously described in the CABAC program, which are commonly used in the CAVLC program, there are two other instructions for analyzing the bit stream access more about the CAVLC program 'ie the INPSTR instruction. (corresponding to the check string module 570) and the INPTRB command (the previous load to the variable length decoding logic 550 in FIG. 5C). The INPSTR instruction and the INPTRB instruction do not need to be limited to CAVLC operations (for example, the above instructions can be used in other programs such as CABAC, VC-1, and MPEG). Use the inPSTR instruction and the INPTRB instruction to test whether a specific pattern (for example, data start or end pattern) appears in a fragment, a macro block, etc., to enable reading of the bit stream without performing Bit stream. In one embodiment, the order of the instructions includes the implementation of INPSTR and INPTRB followed by the rEad instruction. The exemplary format of the INPSTR instruction is described below:

INPSTR DST where 'in one embodiment, the bit stream is checked and passed back to the SrjeG register 562a

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 67 1354239 The most significant 16 bits are in the lower 16 bits of the target scratchpad. The upper 16 bits of the target scratch state contain the sREGbitptr value. Due to this operation, the data is not removed from the SREG register 562a. The INPSTR instruction can be implemented according to the following pseudo-code (Pseudocode): MODULE INPSTR (DST) t OUTPUT [31:0] DST ; DST = {ZE (sREGbitptr) , sREG [msb: msb-15]};

ENDMODULE Another instruction to analyze the bitstream is the INPTRB instruction, which checks the raw byte sequence payload (RBSP) trailing bits (eg, the bitstream arranged in bytes). The dNPTRB instruction provides the bitstream. The reading of the register 562b. The exemplary format of the INPTRB instruction is described below: INPTRB DST. In the INPTRB operation, no bits are removed from the SREG register 562a. When the high significant bit of the SREG register 562a contains, for example, 100, the SHEG register 562a includes the RBSP stop bit, and the remaining bits in the byte are alignment zero bits. The INPTRB instruction can be implemented according to the following exemplary pseudo code: MODULE INPTRB(DST) OUTPUT DST; REG [7:0] P;

Client's Docket No.: S3U06-0013-TW TT^s Docket No:0608-A41246twf.doc/NikeyChen 68 1354239 P = sREG [msb: msb-7]; Sp = sREGbitptr; T [7:0] = (P » Sp) « sp; DST [1] = (T = - 0x80)? 1: 〇· DST[0] = ! (CVLC_BufferBytesRemaining &gt;〇); ENDMODULE Provides a READ instruction for data conditioning in the bit stream buffer 562b .

The extra bit string buffering of the variable length decoding unit 530b will now be described as an operation 'currently describing the initialization of the CAVLC operation', particularly the memory, the scratchpad structure, and the decoding engine (eg, CAVLC module 582). initialization. The general register portion register 612 and the CAVLC module 582 are initialized in the example at the beginning of the segment and before decoding the syntax component corresponding to the first macroblock register structure, and the driver software 128 issues the INIT. The CAVLC instruction η 1 &quot; — M base line #化. The exemplary format of the INIT_CAVLC instruction is described as follows: Bureau Implementation Initial

INIT_CAVLC SRC2, SRC1 where SRC2 includes the number of bytes decoded in the fragment data. Within the internal CVLC_bufferBytesRemaining: 'value write SRC1 [15:0] = mbAddrCurr ; SRC1 [23:16] = mbPerLine ; SRC1 [24] = constrained_intra_predflag ; SRC1 [27:25] = NAL_unit_type (NUT); SRC1 [29: 28] = chroma-format idc (-implement your I__ use fresh Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 69 1354239 should be in 4:2:0 format 1 Chroma—format—idc value, however some embodiments may use other sampling mechanisms; and SRC1 [31:30]=undefined. Regarding the leg t-CAVLC age, the SRC1_value is written to the corresponding bit in the overall register 614. Furthermore, the value in SRC2 is entered into the internal scratchpad set by the INIT instruction (for example: CVLC-bufferByteRemaining register). Use the CVLC_bufferByteRemaining register to restore any error bitstreams, as described earlier. For example, variable length decoding unit 53% (e.g., SREG stream buffer/DMA engine 562) records information that analyzes buffer bits in the bitstream of a known slice. When a bit stream is used, the variable length decoding unit counts and updates the CVLc_bufferByteRemaining value. When the value is below 0, a value below 0 is indicative of a buffer or bit stream error, prompting termination of the process and returning to application control or being controlled by the driver software 128 to handle the restore. The INIT_CAVLC instruction also initializes different storage structures of the variable length decoding unit 53A, including neighboring content memory 564, mbNeighCtxLeft, which is similar in some respects to the previously described CABAC program.

State 605 and mbNeighCtxCurrent register 603. It is known that the content of CAVLC decoding is essentially 'decoding the current macroblock according to the information collected by the CAVLCJTOTC instruction when decoding the macroblock last time, that is, the left macroblock is stored in the left mbNeighCtxLeft register 605 and Pointed by indicator 607b, and the upper macroblock is stored in array element (1)6〇1 and is indicated by

Chent's Docket No.: S3U06-0013-TW s Docket No: 〇6〇8-A41246twf.doc/NikeyChen 1354239 pointed to by 607c. The upper indicator 607c and the left indicator 607b are initialized using the INIT_CAVLC instruction, and the overall register 614 is updated. In order to determine whether a neighboring macroblock (eg, left neighbor) is present (ie, valid), an operation can be performed by the CAVLC_TOTC instruction (eg, mbCurrAddr% mbPerLine), which is similar to the same procedure performed by '1 in the CAB AC embodiment, Therefore, it will not be described. Similar to the described CABAC program, the content of the adjacent content memory 564 can be removed using the CWRITE instruction, while the content of the adjacent content memory 564 can be updated using the INSERT instruction, the local register 612, and the overall register 614, where The INSERT instruction is used for writing to the mbNeighCtxCurrent register 603. The structure of the data maintained in the adjacent content memory 564 can be described as follows: mbNeighCtxCurrent[01:00] : 2?b : mbType mbNeighCtxCurrent[65:02] : 4,b : TC[16] mbNeighCtxCurrent[81:66] : 45b : TCC[cb][4] mbNeighCtxCurrent[97:82] : 45b : TCC[cr][4] When the CWRITE instruction is executed, the mbNeighCtx[] neighbor value is updated, and then the mbNeighCtxCurrent register 603 is initialized. The content memory structure initialized by the variable length decoding unit 530b and the initialization have been described, and how the variable length decoding unit 53B (especially the CAVLC-TOTC instruction) uses the neighbor content information to calculate the total coefficient (TotalCoeff, TC) will be described below. ), which will be used later to determine if the CAVLC table should be used to decode the symbols. In general, the cavLC solution is based on the variable length decoding table described in the H.264 specification (herein =

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 CAVLC Table) The CAVLC table is selected from the contents of the previously decoded symbols to decode each symbol. That is, for each cell symbol, it is a different CAVLC table.帛7B _ shows the basic table structure, which is a two-dimensional array of variable size. An array of tables is provided (each table can be a specific number), and each symbol is a Huffman code. Hoff Shuangqi is stored as a table of the following structure: struct Table{ unsigned head; struct table { unsigned val; unsigned shv; }table[]; }Table[]; The following describes the use of a unique prefix (prefix) The method of comparison (MatchVLC function). Generally, a CAVLC table includes a variable length portion and a fixed length portion. The alignment can be simplified by performing some fixed-size index lookups. In the MatchVLC function, the READ operation can be performed without removing the bit from the SREG register 562a. Therefore, for the bit stream buffer 562b that processes the bit stream, the READ operation is different from the READ instruction described above. In the MatchVLC function described below, some of the bits (fixL) are copied from the bit stream buffer 562b and then looked up in a specified table. Each item in the specified table contains a specific format (for example: value and size in bit type). Use item size

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 for bit stream. FUNCTION MatchVLC(Table, maxldx) INPUT Table; INPUT maxldx;

Idxl = CLZ(sREG);//count number of leading zeros Idxl = (Idxl &gt; maxldx)? maxldx : Idxl; fixL = Table[Idxl].head; SHL(sREG, Idxl+#1); //shift buffer Idxl + 1 bit left Idx2 = (fixL)? 0 : READ(fixL); (val, shv) = Table[Idxl][Idx2]; SHL(sREG, shv); return val;

ENDFUNCTON Figure 7B is a block diagram showing an exemplary two-dimensional array of the above table structure for describing the MatchVLC function in the content of CAVLC decoding. An example when nC == -1 is obtained from Table 9-5 in the H.264 standard, which is described as follows:

Coeff_token TrailingOnes TotalCoeff Head Value Shift 1 1 1 0 33 0 • - oi &quot; ·*· _Iron 练 练 0 , , 3⁄4 0 is · ▼s f&lt; 07 001 2 2 0 66 0 Άο縦猫丛 a 2 ,;[:3⁄4'.魏"w# ,. 1 / -Ά*4 4 ~ : '·. -VT; --ϊϊϊ&gt;· *· , :〇ρρι〇ι3Α: * ^•vOOOjltlO^ ' OOOf 11 Dv h 2 000010 0 4 1 4 1 000011 0 3 3 1 .0000010 3. ^ 1 67 · 1

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 73 1354239 0000011 :. 3 1 ; 00000010 2 4 1 68 1 00000011 1 4 36 1 ::ooooooof: 3:..' ' -:.: read: .· T '·: 100: ' In terms of pseudocode, the above table can be expressed as follows: Table9-5[8] = { 〇, {{33,0}}, - 〇, {{〇,〇}:}, 〇, {{66, 0}}, 2, {{2,2}, {99,2}, {34, 2), {1,2}}, 1, { {4, 1}, {3, 1}}, 1, {{67, 1}, {35, 1}}, 1, {{68, 1}, {36, 1}}, 〇, {{! 〇〇,〇}} }; Using the above table structure, CAVLC decoding can be performed with φ using the MatchVLC function described above. Due to the MatchVLC function, a calculation of leading 0 is performed on the bitstream to access a table of known syntax components. Furthermore, by calculating whether the value of the leading zero is greater than the maximum value of Idx, the MatchVLC function can be started - calculating the leading 〇 operation (for example, in some embodiments, using the computed leading zero module 576 and the reading module 572), and then Returns maxldx (its disposition is 0000000, as shown in the table in Figure 7B). Another advantage of the MatchVLC function and table structure is that multiple instructions are not needed to handle these situations, which are handled by the MatchVLC section below: Idx 1 = CLZ(sREG) The number of gauges, and Idx 1 = (Idx 1 &gt; maxldx)? maxldx :

Client’s Docket No,: S3U06-0013-TW TT s Docket No:0608-A41246twf.doc/NikeyChen 1354239

Idxl. Next, use the following bits of the MatchVLC function to remove the used bits: SHL(sREG, Idxl+#1). Use the following MatchVLC section to read the header of the sub-array: fixL = Table[Idxl].head, and Idx2=(!fixL)? Ο : READ(fixL), which transfers the maximum number of bits To be read indefinitely. Leading 0 can be the same, but the trailing bit is large

* I can be changed. Thus, in one embodiment, a CASEX category description can be implemented (using more memory, but a simpler code structure). Use (val,shv) = Table[Idxl][Idx2] and SHL(sREG,shv) to read the actual value of the table, which also shows how many bits are actually used by the syntax component. These bits are removed from the bitstream and the value of the syntax component is returned to the target scratchpad. The method of VLC matching and the configuration of the table structure have been described, and then reference is made to Figure 7A to describe the CAVLC decoding engine or program (e.g., CAVLC module 582). Once the bit stream is loaded, and the decoding engine, memory structure, and scratchpad are loaded, the coefficient register module 71 is enabled by issuing the CAVLC_TOTC command by the driver software 128. In one embodiment, the 'CACLC_TOTC instruction has the following exemplary format: CAVLC_TOTC DST, S1, where S1 and DST respectively include an input register and an internal output register, having the exemplary format provided below: SRC1 [ 3:0] = blkldx SRC1 [18:16] = bllcCat SRC1 [24] = iCbCr The remaining bits are undefined. The output format is described as follows:

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 75 1354239 DST [31:16] = TrailingOnes DST [15:〇] = TotalCoeff Therefore 'as shown in the figure, the coefficient is modeled Group 71 receives an indication corresponding to mbCuirAddr, mbType, whether a chroma channel is being processed (eg, .lCbCr), and blkldx (eg, a block index because the image can be divided into a number of blocks). The blkIdx is transmitted for a known macroblock accessed from the bitstream buffer: 562b, whether it is an 8x8 pixel block or a 4χ4 pixel block is being processed at a known location. The above information is provided by the driver software 128. The coefficient signature module 710 includes a lookup table. The number of trailing coefficients (TrailingOnes) and the number of non-zero coefficients (TotalCoeff) can be obtained by inputting the lookup table to the coefficient register module 710 according to the foregoing description. TrailingOnes transmits how many 1s are in a column, and Totalc〇eff transmits how many run/level pair coefficients are on the block data extracted from the bitstream. Trailing〇nes and Ding talC〇eff are provided to the CAVLC level module 714 and the zero level module 718, respectively. TrailingOnes is also provided to a level 0 module 716 that corresponds to a first level (eg, a direct current (DC) value) drawn from the bit stream buffer 562b. The level module 714 records the suffix length of the symbol (eg, the number of trailing 1's) and the level module 714 combines the level code (levelc〇de) to calculate the level value (level[Idx]), The level values are then stored in the level array 722 and the run array 724. The level module 714 operates under the CAVLCJLVL instruction and has the following format: CAVLCJLVL DST, S2, S1, where:

Client's Docket No.: S3U06-0013-TW TT*s Docket No:0608-A41246twf.doc/NikeyChen 76 ^54239 : SI = Idx (16-bit); S2 = suffixLength (16-bit); and DST = suffixLength ( 16_bit). , suffixLength transfer codeword (C0 (ie word) large • : small. Input from the driver software 128 provides a large length of the specified suffix • small poor news. In addition, in an embodiment, Because the suffix length value is updated, • DST and S2 can be selected as the same register. It is also noted that forwarding registers (such as maintaining data generated by known modules) can also be used, such as F1. And F2. The instruction is indicated by a forwarding flag within the known instruction and whether the corresponding module uses the forwarding register. Symbol F1 (ie, using the value of forwarding source 1, in one embodiment, the bit 26 in the instruction The indication) and the symbol F2 (i.e., the value of the forwarding source 2 may be indicated by bit 27 in the instruction in one embodiment) may represent a forwarding register. When a forwarding register is used, the CAVLC_LVL instruction may have φ The following exemplary format: CAVLC_LVL.F1.F2 DST, SRC2, SR1 - 'When F1 is not F1 or F2 is set (eg, established), the specified forwarding source is treated as input. In the case of level module 714, forwarding Register F 1 corresponds to the level index (level [Idx]) generated by the level module 714, which is incremented in the increment module and input to the multiplexer 730. Similarly, the forwarding register F2 corresponds to the suffix Length (suffixLength), which is generated by the level module 714 and input to the multiplex

Client's Docket No.: S3U06-0013-TW TT^ Docket No: 0608-A41246twf.doc/NikeyChen 77 1354239 728. The multiplexer 730 and other inputs to the multiplexer 728 include an execution unit register input (labeled EU in Figure 7A), as described below. Another input to the level module 714 is the level code provided by the level code module 712. Combination operation of the level code module 712 and the level module 714

I Decodes the decodable level value (the level is the conversion coefficient value before scaling). The level code module 712 can be enabled by an instruction having the following exemplary format. CAVLC_LC SRC1 , where SRC1 = suffixLength (16 bits). When forwarding register F1 is used, the instruction can be expressed as follows: CAVLC_LVL.F1 SRC1, where if F1 is set, then forwarding SRC1 is treated as an input. As shown in Figure 7A, when F1 is set (e.g., FI = 1), the level code module 712 obtains the forwarded SRC1 value (e.g., the suffix length from the level module 714) as an input, otherwise the input is from Obtained by the execution unit register (for example, F1 = 0). Returning to the level module 714, the suffix length input can be forwarded by the level module 714 via the multiplexer 728 or via the execution unit register multiplexer 728. In addition, the Idx input can also be forwarded by the level module 714 via the multiplexer 730 (and incremented by the incremental module, or in some embodiments, automatically incremented without incrementing the module), or via

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 78 1354239 - The execution unit register is provided by the multiplexer 730. Furthermore, the level module 714 also receives the registration of the level code directly from the level code module 712. In addition to the output to the transfer register, the level module 714 also provides a level index (level[idx]) output to the level array 722. As mentioned in the article, TrailingOnes outputs to the position permit module 716. - Level 0 module 716 is enabled via the following: command:

• CAVLC_LVLO SRC , where SR_C = trailingOnes(coeff_token). The output of the level module 716 includes a level index (LeVel[IdX]) that is provided to the level array 722. The coefficient value is encoded as a sign and a size. Bit 〇 Module - Provides the sign value of the coefficient. The size value from the CAVLC level module 714 and the sign value from the level module 716 are combined and written to the level array 722. Use the level index (level[Idx]) to specify the location to write. In one embodiment, the coefficients are within a φ 4 χ 4 matrix of sub-blocks (blocks 8 χ 8), not in raster order. The array is then converted to a 4x4 matrix. In other words, the 'decoded coefficient level as well as the non- - raster format. From the level-run data, the 4x4 matrix can be reconstructed (but in the orthodontic scan order)' and then rearranged into raster order 4x4. The TotalCoeff output by the 仗 coefficient payment module 710 is supplied to the zero position module 718. The zero level module 718 can be enabled via the following instructions: CAVLC_ZL DST, SRC1 where ' SRC1 = maxNumCoefi (16 bits) and D.ST = ZerosLeft

Client^ Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 79 1354239 (16-bit). maxNumCoeff is given by the H.264 standard and is resent as the original value of the instruction. In other words, maxNumCoeff is set by the software. In some embodiments, maxNumCoeff can be stored in hardware. The transform coefficients are encoded into a (level, run) format that is related to the number of coefficients (levels) of the encoded 吟0. The zero level module 718 provides two outputs, ZerosLeft and Reset (reset =:〇), which are provided to the multi-mode 740 and the multiplexer 742, respectively. The multiplexer 740 also receives the forward register F2 from the run module 720. The multiplexer 742 receives the forwarded registers from the run module 720 that have been incremented (in some embodiments, via an incremental module or otherwise). The run module 720 receives the ZerosLeft and Idx inputs from the multiplexer 740 and the multiplexer 742, respectively, and provides a run index (Run[Idx]) output to the run array 724. As described earlier, since run_length coding is used for further compression' then the coefficients are encoded into a (level, run) format. For example, 'assuming the following values 10 12 12 15 19 1 1 1 〇〇〇〇〇〇1 〇' can be coded as (10,0) (12,1) (15,〇) (19,〇 ) (1,2) (〇,5) (1,〇) (〇,〇). This code word is usually shorter. The index is the corresponding index of the level index. The run module 720 can be enabled via the following instructions: CAVLC_RUN DST, S2, S1 ' where the ZerosLeft value is updated 'DST and S2 can be selected as the same register. Therefore, the demonstration of the CAVLC-RUN instruction does not have a sign value as follows: S1 = Idx(16-bit),

Client's Docket No.: S3U06-0013-TW TT s Docket No:0608-A41246twf.doc/NikeyChen 80 1354239 t S2 - ZerosLeft( 16-bit) &gt; DST = Zerosleft(16-bit) 〇Refer to Figure 7A 'Forwarding The scratchpad is used, and the CAVLC_RUN state is available in the following format:

I • CAVLC.F1.F2 DST,:SRC2, SRC1 _ , where, when F1 is not set or F2 is set, the appropriate forwarding source is considered to be a round. -^ Regarding the two temporary registers, the level array 722 corresponds to the level and the operational array 724 corresponds to the run. In one embodiment, each array comprises 16 elements-to-level array 722, the size of each element comprising a 16-bit value of • sign, and for running array 724, the value is 4 bits. And does not have a sign. The level values and run values are read from level array 722 and run array 724, respectively, using the following instructions. _ READ LRUN ncnr : where 'in the embodiment, the DST includes four 128-bit consecutive new scratchpads (eg, an execution unit temporary or a shared scratchpad). The last two ‘for the variable length decoding unit 53G _ level register and the register 并 register to the destination (four) register. #This run is read and stored: When the scratchpad is stored, the run value is converted to a 16-bit unsigned value: for example, the first two registers maintain 16 16-bit levels Array stores the first coefficient), while the third and fourth register dimensions =

Client's Docket No.: S3U06-0013-TW TT’s Docket No: 〇6〇8-A41246twf.doc/NikeyChen 81 1354239 16 16-bit running values. When there are more than 16 coefficients, it is decoded to the memory. In one embodiment, the values are written in the following order: in the first register, the least significant 16 bits contain the LEVEL[0] value, and the bits 16-31 contain the LEVEL[1] value, etc., up to the bit. 112-127 contains the LEVEL[7] value. Then, for the second register pair, the least significant 16 bits include I LEVEL [8] and the like. The same method is applied to the RUN value. The CLRJLRUN instruction can be used to clear the level array 722 and the registers that run the array 724 in accordance with the following exemplary instruction format. The software (shading program) and hardware operations (e.g., modules) of the variable length decoding unit 530b described above, particularly the CAVLC module 582, can be described using the following pseudo code.

ResiduaLblock_cavlc( coeffLevel, maxNumCoeff) {_ A CLR_LEVEL-RUN coeff_token_ if( TotalCoeff( coeff_token) &gt; 0) { if( TotalCoeff( coeff_token) &gt; 10 &amp;&amp; TrailingOnes( coeff_token) &lt; 3) _suffixLength = 1 _ Else _suffixLength = 0_ CAVLCJevelOQ; _for( I = TrailingOnes(coeffJaken); I &lt; TotalCoeff( txieffjoken), ' i++){ _CAVLC_levelCode(levelCode&gt;suffixLength);_ CAVLC_level(suffixLength, i.levelCode) CAVLC_ZerosLeft(ZerosLeft, maxNumCoeff) for( i = 0; i &lt; TotalCoeff( coeff_token) -1 ; i++) { CAVLC_run(i, ZerosLeft)_ READ_LEVEL_RUN(level, run) run[ TotalCoeff( cx)eff_token) -1 ] = zerosLeft coeffNum = -1_ for( i = TotalCoeff( coeff a token) -1; i &gt;= 0; i-) { coeffNum += run[ i ] +1

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 82 1354239

MPEG decoding has been described above as a decoding system for CABAC decoding (variable length decoding unit 530a via CABAC module): and CAVLC decoding (via variable length decoding unit 530b of module 582), ^ • An MPEG embodiment of the decoding system 200 will be described below, referred to herein as a scalable length decoding unit 530c. The variable length decoding unit 53A is operated in accordance with an operation performed by the = MPEG module 578 (shown in Fig. 5C). Features that are common to the CABAC and CAVLC embodiments (ie, the bitstream buffer and the corresponding instructions) are omitted, except for the following: • The part that needs attention. The INIT instruction sets the variable length decoding unit 53 to 'wander in the MPEG mode, and uses a mixture of READ, NPSTR, INPTRB (explained above) and VLC-MPEG2 instructions to decode the MPEG_2 bit φ stream. The color program program determines which method to use. The MPEG-2 bit stream has a fully deterministic grammar, and the shading code performs a method for decrypting the grammar. - In an embodiment, for MPEG-2 processing, the implementation table is described in Huffman decoding in the MatchVLC_X function'. Therefore, the two instructions are loaded into the MPEG module 578' including the INIT_MPEG2 instruction and the VLC-MPEG2 reference ♦. INIT_MPEG2 refers to the epoch &amp; rumor history variable length decoding unit 530 enters the MPEG2 mode. In this mode, the overall register 614 holds the value when the first coefficient is direct current (DC). in

Client's Docket No.: S3U06-0013-TW TT's Docket N〇: 0608-A41246twf.doc/NikeyChen 83 1354239 There are one or more streams in MPEG-2, which are the same, but depending on whether it is DC or AC Different interpretations. The bit is loaded into the VLD-globalRegister. The InitDC register is used instead of creating another instruction. Note that the scratchpad corresponding to the overall scratchpad 614 (eg, mapped to the overall scratchpad 614 (eg, gl〇balregister[0])) is used in CABAC and CAVLC modes, but because of the different solutions in MPEG2 mode. Translated (and therefore marked different). Therefore, the start value of the macro block (the bit in the VLD-globalRegister.InitDC register) is initialized to 1. When using the MatchVLC-3 function, it is determined whether the bit in the VLD_globalRegister.InitDC register is 1 or 0. If it is 1, the bit is changed to 〇 for decoding by the discrete cosine transform (DCT) $ after the known macro block. The above values are set by the color picker and internal reset. In the entity part, the VLD_globalRegister.InitDC bit is a flag value that conveys whether the decoded DCT symbol is the beginning of the DCT symbol of the known macroblock. The MPEG module 578 decodes using a very specific grammar with symbols, wherein the above symbols use a limited number of Huffman tables. The analysis of the grammar is performed in a colorimeter having a particular symbol value, the + specific symbol value being obtained using a VLC-MPEG2 instruction having a #Imml6 value for a particular Huffman table, which should be used to solve the specific symbol. A brief description of the hardware and software structures used to implement the different tables of the MPEG-2 standard is described below before describing the different elements of the variable length decoding unit 530c. In the MPEG-2 standard (ISO-IEC 13818-2 (1995))

Client's Docket No.: S3U06-0013-TW TT, s Docket No: 0608-A41246twf.doc/NikeyChen 84 1354239, the codes used are defined in the table; B_1 to Table 5, which are provided by the standard Know the form. In a different embodiment of the variable length decoding unit (7), one or more of Tables B-1 through B_15 are implemented in a professional hardware version, such as a logical gate. Depending on the implementation (eg hdtv, HDDVD f) or the hardware arrangement required today, some tables can be implemented in hardware, but other instructions can be used (eg: EXP-GOL-UD, which will be described later) The instruction is executed by the READ command. For example, δ, although the number of logic gates in Table B-2, Table B-3, and Table B-1 is not large, the addition used may require an additional multiplexer stage, which means speed and delay. In some embodiments, the tables _5 to Β_8 are not supported by the hardware because they do not need to support the profile. However, some embodiments may provide such support through different instructions that have minimal impact on performance (e.g., INPSTR, EXP_GOL-UD, and READ instructions). Continuing with reference to known MPEG tables, Table B-1 (Macroblock_address_increment), Table B-10 (motion_code), and Table B-9 (coded_block_pattern) have similar structures. Because of their partial similarity, the above three tables can be implemented using the MatchVLC function executed by the MPEG module 578 and described later. For Table B-9 and Table B-10, the exemplary table structure is represented as follows: struct Table { unsigned head; //The number of bits in the table address struct table { unsigned val:6; //Table B-10 5 bits

Client's Docket No.: S3U06-0013-TW TTss Docket No:0608-A41246twf.doc/NikeyChen ,239 * » unsigned shv:2; //actual bit number}table[]; }Table[]; fresh table Bl The exemplary table structure is expressed as follows: struct Table {

- I unsigned head; //The number of bits in the table address struct table { % unsigned val:5; unsigned shv:3; //the actual number of bits - }tablet]; - }Table[]; • In the following function Only SHL operations can erase data from the sreG register 562a. Unlike the READ instruction of the coloring benefit, the READ function in the MatchVLC function can be used to remove a bit from the SREG register 562a without removing any bits from the SREG register 562b. The following uses the MatchVLC function that implements the table in MPEG-2 to provide the decoding as Hof@. FUNCTION MatchVLC_1{ ' T = READ(2); / job 2 meal SHL(2); CASE(T){ 00: OUTPUT(1); 01: OUTPUT(2); 10:{ Q = READ (1); SHL (1); CASE (Q){ 0 : OUTPUT(O);

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 86 1354239 1: OUTPUT(3); 11 :{ ldx=CLO(sREG);//| 十朝丨导 1

Idx = min(ldx,7); shv = (Idx != 7) ldx+1: Idx; SHL(shv); , OUTPUT(4+ldx); FUNCTION MatchVLC_2{ T = READ(2); /fiber 2

SHL(2); CASE (TK 00: OUTPUT(O); 01 : OUTPUT(1); 10 : OUTPUT(2); 11 :{ ldx=CLO(sREG);/pin toward |

Idx = min(ldx,8); shv = (Idx != 8) ldx+1: Idx; SHL(shv); OUTPUT(3+ldx);

FUNCTION MatchVLC_3{ INIT—MB DC = TRUE; T = CLZ(sREG); SHL(T+1); CASE (T){ 0: IF (DC){ DC = FALSE; Q = READ(1); SHL(1 ); OUTPUT({0,SGN(Q)*1});} ELSE{ Q = READ(1);

IF (!Q) {OUTPUT({63,0}); shv=1} // EOB ELSE {R=READ(1); OUTPUT({0,SGN(R)*1}); shv=2}

Client’s Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 87 1354239 SHL(shv); Q = READ (3);

CASE (QX 1XX: 0UTPUT({1, SGN(Q[1])*1}); shv = 2; 01X: OUTPUT({2, SGN(Q[0])*1}); shv = 3; OOX : OUTPUT({0, SGN(Q[0])*2}); shv = 3; } SHL(shv); Q = READ(2); SHL(2); CASE(Q){ 00: { R= READ(4); CASE(R){ OOOX: OUTPUT({16, SGN(R[0])*1}); 001X : OUTPUT({5, SGN(R[0])*2}); 01 OX : OUTPUT({0, SGN(R[0])*7}); 011X: OUTPUT({2, SGN(R[0])*3}); 100X: OUTPUT({1, SGN(R[0] )*4}); 101X: OUTPUT({15, SGN(R[0])*1}); 110X : OUTPUT({14, SGN(R[0])*1}); 111X : OUTPUT({4 , SGN(R[0])*2}); }

Shv = 4; } 01X: SGN = READ(1); OUTPUT({0, SGN*3}); shv= 1 10X : SGN = READ(1); OUTPUT({4, SGN*1}); shv= 1 11X : SGN = READ(1); OUTPUT({3, SGN*1}); shv= 1 } SHL(shv); 3:{ Q = READ (3); CASE (Q){ OOX : OUTPUT({7, SGN(Q[0])*1}) 01X: OUTPUT({6, SGN(Q[0])*1}) 10X: OUTPUT({1, SGN(Q[0])*2}) 11X: OUTPUT ({5, SGN(Q[0])*1}) } SHL(3);

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 4:{1354239 〇=READ(3);

CASE (QX OOX: OUTPUT({2, SGN(Q[0])*2}); 01X: OUTPUT({9, SGN(Q[0])*1}); 10X: OUTPUT({0, SGN( Q[0])*4}); 11X: OUTPUT({8, SGN(Q[0])*1}); } , SHL(3); . } 5: Q = READ(19); OUTPUT({ Q[18:13], Q[12:0]}); 6:{ Q = READ (4);

CASE(Q){ OOOX : OUTPUT({16, SGN(Q[0])*1}); 001X: OUTPUT({5, SGN(Q[0])*2}); 01 OX: OUTPUT({0 , SGN(Q[0])*7}); 011X: 0UTPUT({2, SGN(Q[0])*3}); 100X: 0UTPUT({1, SGN(Q[0])*4}) 101X : 0UTPUT({15, SGN(Q[0])*1}); 110X : 0UTPUT({14, SGN(Q[0])*1}); 111X: 0UTPUT({4, SGN(Q[ 0])*2}); } SHL(4); } 7,8,9,10,11: JVLC(TableC[T|);

FUNCTION MatchVLC_4{ T = CLZ(sREG); SHL(T+1); CASE (T){ 〇:{ Q = CLO(sREG); R = min(Q,7); shv = (R != 7)R +1 :R; SHL(shv); CASE (R){ 0: S = READ(1); OUTPUT({0, SGN(S)*1}); shv=1; 1 : S = READ(1) ; OUTPUT({0, SGN(S)*2}); shv=1; 2:{

Client’s Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 89 1354239 R = READ(2); SHL(2);

CASE (RK OX: OUTPUT({0, SGN(R[0])*4}); 1X: OUTPUT({0, SGN(R[0])*5}); 3:{ R = READ(3) ; SHL(3); CASE(RH , OOX: OUTPUT({9, SGN(R[OJ)*1}); 01X: 0UTPUT({1, SGN(R[0])*3}); 10X: OUTPUT ({10, SGN(R[0])*1}); 11X: OUTPUT({0, SGN(R[0])*8});

4:{ R=READ(3);

CASE(RX ' OXX: OUTPUT({0, SGN(R[0])*9}); shv=2; 10X: OUTPUT({0, SGN(R[0])*12}); shv= 3; ' 11X: OUTPUT({0, SGN(R[0])*13}); shv = 3; ' } SHL(shv); ' } 5::{ R = READ(2); SHL(2); CASE (R) { OX : 0UTPUT({2, SGN(R[0])*3}); • 1X: 0UTPUT({4, SGN(R[0])*2}); 6 : S = READ(1 ); OUTPUT({0, SGN(S)*14}); shv=1; 7 : S = READ(1); OUTPUT({0, SGN(S)*15}); shv=1; } SHL( Shv); Q = READ(2); SHL(2); CASE (Q){ OX: 0UTPUT({1, SGN(Q[0])*1}); 10: OUTPUT({63,0}); //&lt;EOB&gt; 11 : R = READ(1); SHL(1); OUTPUT(0,SGN(R)*3});

Client's Docket No.: S3U06-0013-TW TT5s Docket No:0608-A41246twf.doc/NikeyChen 90 1354239 Q = READ(2); SHL(2); CASE (QX 00:{ R = READ(4); shv = 4; CASE (R) { 000X: OUTPUT({1, SGN(R[0])*5}); 001X: 0UTPUT({1,1, SGN(R[0])*1}) 01 OX: OUTPUT ({0, SGN(R[0])*11}) 011X: OUTPUT({0; SGN(R[0])*10}) 100X: 0UTPUT({13, SGN(R[0])*1} ) 101X: OUTPUT({12, SGN(R[0])*1}) 110X : OUTPUT({3, SGN(R[0])*2});

111X : OUTPUT({1, SGN(R[0])*4}); 01 : R = READ(1); 0UTPUT({2,SGN(R)*1}); shv=1; 10: R = READ(1); 0UTPUT({1,SGN(R)*2}); shv=1; 11: R = READ(1); 0UTPUT({3,SGN(R)*1}); shv=1; } SHL(shv); } 3:{ Q = READ(3); SHL(3); CASE (Q){ OOX: OUTPUT({0, SGN(Q[0])*7}); 01X: OUTPUT({0, SGN(Q[0])*6});

10X: 0UTPUT({4, SGN(Q[0])*1}); 11X: 0UTPUT({5, SGN(Q[0])*1}); 4:{ Q = READ(3); SHL( 3); CASE (Q){ OOX: 0UTPUT({7, SGN(Q[0])*1}) 01X: 0UTPUT({8, SGN(Q[0])*1}) 10X: 0UTPUT({6 , SGN(Q[0])*1}) 11X: 0UTPUT({2, SGN(Q[0])*2}) 5: Q = READ(19); OUTPUT({Q[18:13], Q [12:0]}); 6:{

Client’s Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 1354239 Q = READ(2); SHL(2);

CASE (QX 00: R = READ(1); OUTPUT({5, SGN(R)*2}); shv=1; 01 : R = READ(1); OUTPUT({14, SGN(R)*1 }); shv=1; 10:{ R = READ(2); shv = 2;

CASE (RK OX: 0UTPUT({2, SGN(R[0])*4}); 1X: 0UTPUT({16, SGN(R[0])*1}); 11 : R = READ(1); 0UTPUT({15, SGN(R)*1}); shv=1; }

SHL(shv); 7,8,9,10,11:JVLCCTableCn); } } It is noted from the MatchVLC function above that the least significant bit that is usually decoded determines the sign of the value, so it can be checked using the SGN function. It is described as follows: FUNCTION SGN(R){ RETURN (R == 1)? -1:1;} It is more noted that for MatchVLC_3 and MatchVLC_4, the tables are common (or at least a superset), so Use the form below to access features. FUNCTION JVLC(Table){ Q =READ(5); SHL(5); {R,L} = Table[Q]; RETURN {R,L}; } to the interface of MatchVLC, or should say MatcliVLC_X (its

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 〇〇 1354239 where X equals 1, 2, etc.) The function is the following command: VLC_MPEG2 DST, #Imml6 , where #Imml6 value is used Select the appropriate table and therefore decode the specific grammatical components. Use #Imml6 as an index to the table (for example: 〇, 1, 2, 3) to access the table from the instruction. #Imm 16 value and corresponding method, language

The II component and the MPEG-2 table are described in Table 5 below. ° #Imm16 Method mmm MPEG-2 VLC Table 0 MatchVLC(B-1,7) Macroblock_address_increment B-1 1 MatchVLC(B-9,8) Coded_block_pattem B-9 2 MatchVLC(B-10,6) Motion_code B-10 3 Match VLC_1 Dct_dc_size_luminance B-12 4 MatchVLC-2 Dct_dc_size_chrominance B-13 5 MatchVLC_3 DCT coefficients (Table 0) B-14 6 MatchVLC-4 DCT coefficients ( Table 1) B-15 Table 5 EXP-GOLOMB decoding has been described for use as CABAC decoding (variable length decoding unit 530a via CABAC module 580), CAVLC decoding (variable length decoding unit 53 via CAVLC module 582) And the decoding system 200 of the mpeg decoding (variable length decoding unit 530c via the MPEG module 578). Next, the EXp_G〇i〇mb embodiment of the decoding system 2〇〇 will be described, which is referred to herein as a variable length decoding unit. 530d. The variable length decoding unit 53〇d operates in accordance with the operation of the EXP-Golomb module 584 (shown in Fig. 5C). The variable length decoding unit 53 〇d uses the same hardware and the same bit stream buffer arrangement as used by the CABAC and CAVLC embodiments. because

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 Thus, features common to the CABAC and CAVLC embodiments are omitted except for the following points requiring attention. Before describing the variable length decoding unit 5 3 〇d, a brief description about EXP-Golomb is proposed. In EXP-Golomb, the data contains the prefix and suffix formats, as shown below:

I codeNum Range 1 0 0 1 x〇1-2 β 〇〇1 Xi x〇3-6 0 0 0 1 χ2 Xi χ〇7-14 - 0 0 0 0 1 Χ3 χ2 Χτ χ〇15-30 000001Χ4Χ3Χ2χιΧ〇31 -62 • Since most of the code words are shorter, compression is obtained. Furthermore, most codewords are unique and easy to decode. In Η.264, there are four EXP-Golomb encoding methods used. There is no sign *-unary, _ sign, and mapping (codewords are mapped to tables). These methods are used to encode the encoded macroblock pattern and truncation. A single instruction is provided in variable length decoding unit 530d to perform decoding of different types of EXP-Golomb codes as shown in Table 6 below. The truncated EXP-Golomb decoding is described below. codeNum = EXP_GOLOMB_UD t = Cl_Z SHL(t+1) val = READ(t) //val without sign codeNum = 2 — 1 + val codeNum = EXP_GOLOMB_CD(kOrder) IZ := CountLeadingZero(sREG); sREG := {( sREG «(lz+1)), bitStreamBufferi〇:lz]};

Client's Docket No.: S3U06-0013-TW TT5s Docket No:0608-A41246twf.doc/NikeyChen 94 1354239 J:=lz+kOrder-1; val := (J &gt;= 0)? ZeroExtend(sREG[0: J ]): 0; sREG := {(sREG «(lz+1)), bitStreamBuffer{0:lz]}; codeNum := (1"(Iz + kOrder)) + (OxFFFFFFF « kOrder) + val; Seval = EXP_GOLOMB_SD tk = EXP_GOLOMB_UD (-\f+])Ceil{-1 Seval= UJ * cbp = EXP_GOLOMB_MD(Type) k = EXP GOLOMB UD I. — cbp = TableCBP[Type][k] Table 6 further explains these instructions, EXP_GOLOMB_UD instruction Decoding a one-ary coded code symbol. The EXP_GOLOMB_SD instruction decodes a coded symbol with a signed one-element code. As shown in Table 6, for the EXP_GOLOMB_SD instruction, when k = 0, there is no difference between positive 0 and negative ,, so the value returned is 0. The E XP_GOLOMB_MD (SRC1) instruction decodes the mapped coded symbols, where SRC1 = Type, which is related to the macroblock parameters and the coded_block_pattern. The value of Type will result in the following coded_block_parameter :

Type = Intra 4x4 Type = 1 — Inter can use a table (for example: on-wafer memory or a table in remote memory) to specify values based on macroblock prediction mode (eg, number of codes, k) Coded_block_parameter ° The EXP-Golomb instruction that decodes the truncated Exp-Golomb symbol is described as follows: EXP GOLOMB TD DST, SRC1 , where 'SRC 1 is the range. In at least one embodiment, performing truncation

Client’s Docket No.: S3U06-0013-TW TT^s Docket No:0608-A41246twf.doc/NikeyChen 95 1354239

When Exp-Golomb is encoded, you need to know the scope first. Next, wearing a short Exp-Golomb encoding can be derived as follows: codeNum = EXP_GOLOMB_TD(range) { else if(range==l) return READ(1)A1; else return EXP GOLOMB UE; I 丨_ _ :} : Therefore, The EXP_GOLOMB_D instruction is provided. It is useful to interpret the difference between the opcode and the driver-issued software instructions. In general, when designing an ISA, there are at least two effects at work: (1) making the instruction decoder simpler and completing in a single pipeline phase (ie fast); and (2) letting the programmer mnemonics (mnemonics) It's simpler. Referring to the operations of the five EXP-Golomb benchmarks, these operations are different from the user's point of view. Furthermore, there are two different formats: all of the EXP-Golomb benchmarks output the same value, but only some of the operations have an input (except for the bitstream contained in the operation), which provides at least one fundamental difference. Traditionally, CPU instructions do not have implicit input, but pass through operations including implicit input. However, the bit stream is not exposed through computation, but is internally managed automatically and initialized using the INIT instruction. From a hardware point of view, all other EXP-GOLOMB-UD operations can be performed using the same core of the same hardware hardware of the EXP-GOLOMB-UD (or at least) and small additions to the core hardware (eg in software) It is similar to the part of CASE/SWITCH). So the compiler/translator can map all operations to a single instruction. Again, these operations are fixed (for example, the operation does not change dynamically). Refer to the pseudonym line in Table 7 below, note ^

Client's Docket No.: S3U06-0013-TW TT*s Docket No:0608-A41246twf.doc/NikeyChen 96 1354239 For the EXP-GOLOMB-UD and ΕΧΡ-GOLOMB-SD operations, SRC1 can be added (or by the core) Ignored), with mechanisms to distinguish these operations. Again, note that no single source instruction packet exists, but can be mapped to a scratchpad-immediate packet. The area between these instructions can be obtained by using the apparent immediate number of different instructions as shown in Table 7.

I don't result in only one major/time: to calculate the code instead of five, which includes a meaningful store. That is, only one secondary opcode is used because the immediate format instruction can be used, and the difference between the different EXP_Golomb instructions can be accomplished by encoding the immediate data block with the appropriate data and specifying Pseudonym. EXP GOLOMB D Dst, #Type, Srcl.lane 'It can be determined via the following list #Type : #Type Pseudonym Instruction 0x0 EXP_GOLOMB_UD Dst EGOLD Dst,0x0,Src1 0x1 EXP_GOLOMB_SD Dst EGOLD Dst, 0x1, Src1 0x2 EXP_GOLOMB_TD Dst,Src1 EGOLD Dst, 0x2, Src1 0x3 EXP_GOLOMB_MD Dst, Src1 EGOLD Dst, 0x3, Src1 0x4 EXP_GOLOMB_CD Dst, Src1 EGOLD Dst, 0x4, Src1 Table 7 further explains Table 7, for #type=Ox〇 or #type=0xl, no Srcl blocking is required and there is no need to specify these instructions to another primary or secondary opcode group, as it can be specified that the dummy Src or Src and Dst can be marked as the same. The EXP-Golomb code symbols are encoded as shown in the following figure (for example including 〇 or multiple boots 0, followed by 1, and then some bits corresponding to the number of boots 0):

Client's Docket No.: S3U06-0013-TW TTJs Docket No:0608-A41246twf.doc/NikeyChen 1354239 1 0 1 x〇0 0 1 X1 X〇0 0 0 1 X2 X1 0 0 0 0 1 Xs X2 0 0 0 0 0 1 X4 Xs codeNum Range 0 1-2 3-6 x〇7-14 X1 X〇15-30 X2 X1 X〇31-62 φ How these bits are interpreted depends on the specific Golomb type (here is based on H Three types of .264 and the fourth type of AVS). Use UD and SD (without sign and sign) to calculate the logical unit to calculate the value. For example, when the bit stream is 0001010, the value of UD is

• (1&lt;&lt;3)-1+2 = 9, and the value of SD is (-l)A10*ceil(9/2) = +5. CD - A similar procedure occurs. However, for MD, the form lookup is performed (for example, when UD encoding, the value is decoded, then this value is used as an index into the table, and the value of 6 bits is returned (stored as 6 bits in the table) • Value, but the return value is from 〇 to the width of the scratchpad)). In one embodiment there are two tables, one for Intra coding and the other for Inter coding. - An example of how the above instruction conversion is used in the content of the EXP-Golomb decoding, which can be displayed by the exemplary pseudo code of the H.264 fragment header portion decoding as follows. sliceHeaderDecode: EXP_GOLOMB_UD firstMBSlice EXP_GOLOMB_UD sliceType EXP_GOLOMB_UD picParameterSetID READ frameNum, Nval

Client’s Docket No.: S3U06-0013-TW TT’s Docket No:0608-A41246twf.doc/NikeyChen 98 1354239 IB_GT frameMbsOnlyFlag, ZERO, $Label1

READ fieldPicFlag, ONE IB_EQ fieldPicFlag, ZERO, $Label1

READ bottomFieldFlag, ONE

Labeh: ISUBI t1, #5, nalUnitType IB_NEQ ZERO, t1, $Label2

EXP_GOLOMB_UD idrPicID ZERO, picOrderCntType, $Label3 picOrderCntLSB, Nvalt p1, ONE, fieldPicFlag nfieidPicFlag, ZERO nfieldPicFlag, ONE t1, picOrderPresentFlag, nfieldPicFlag ONE, t1,$Label4 EXP_GOLOMB_SD deltaPicOrderCntBottom Label4:

Label2: IB_NEQ READ Label3: ICMPI—EQ [p1]MOV [!p1]MOV AND B NEQ to sliceHeaderDecode:

EGOLD firstMBSlice, #0, ZERO EGOLD sliceType, #0, ZERO EGOLD picParameterSetID, #0, ZERO READ frameNum, Nval IB_GT frameMbsOnlyFlag, ZERO, $Label1 READ fieldPicFlag, ONE IB_EQ fieldPicFlag, ZERO, $Labei1 READ bottomFieldFlag, ONE Label 1: ISUBI t1, #5, nalUnitType IB_NEQ ZERO, t1, $Label2 EGOLD idrPicID, #0, ZERO Label2: Old NEQ ZERO, picOrderCntType, $Label3 READ picOrderCntLSB, Nvalt Label3: ICMPI_EQ p1, ONE, fieldPicFlag [p1]MOV nfieldPicFlag, ZERO [!p1]M0V nfieldPicFlag, ONE AND t1, picOrderPresentFlag, nfieldPicFlac B_NEQ ONE, t1,$Label4 EGOLD deltaPicOrderCntBottom, #1, ZERO

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 1354239 VC-1 decoding: Described as CABAC decoding (variable length decoding unit 530a via CABAC module), CAVLC solution Shima (variable 5 degree decoding unit 530b via CAVLC modulo group 582), mpeg decoding (via • MPEG modulo, variable length decoding unit 530c j of address 57:8, and Exp-Go 〇 mb decoding (via EXP The decoding system 200 of the variable length decoding single S 530 d) of the Golomb module 584 will next describe the VC_1 embodiment of the decoding system 200, here referred to as the variable length decoding unit 530e. The ummar length decoding unit 530e It operates according to the calculation of the preamble 1 module 574 and the calculation of the preamble module 576. να! uses Huffman coding and has more tables. Instead of establishing and testing these tables, since the bit rate needs to be lower, the verification cost Higher, the necessary tables are loaded into the adjacent content memory 564. The table format is the same as that used by MPEG-2, and the READ, VLC-CLZ, VLC-CLO, and INPSTR instructions are used to decode the bit stream. The following pseudo code can be executed Fixed form:

//TABLE -1 Picture CBPCY VLC TABLE

VLC_CI_ZDST0,#8 CASE DSTO 0: VALUE = 0; BREAK; &quot;USE MOVL 1:VLC_CLZDST1#5 CASE DST1 1:T = READ(2);

CASET 0: VALUE = 48; BREAK; 1: VALUE = 56; BREAK; 2 : GO20; BREAK; 3: VALUE=1; BREAK;

CASE_END

Clients Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen ]〇〇1354239 2: VALUE = 2; BREAK; 3: VLC_CLO DST2, #5 CASEDST2 0: VALUE = 28;BREAK; 1 : VALUE = 22; BREAK; 2: VALUE = 43; BREAK; 3: VALUE = 30; BREAK; 4: VALUE = 41; BREAK; 5: VALUE = 49; BREAK;

CASE_END 4: T = READ(1); VALUE = (T)? (READ(1) ? 31 : 54): 27; BREAK; 5: VALUE = 6; BREAK; CASE_END 2: VLC_C1_ZDS1 #4 CASE DST1 1: VALUE = 3; BREAK; 2: T = READ(1); VALUE = (T)? 19: 36; BREAK; 3:T = READ(2);

CASET 0: VALUE = 38; BREAK; 1: VALUE = 47; BREAK; 2: VALUE = 59; BREAK; 3: VALUE = 5; BREAK; CASE_END 4: VALUE = 7;

CASE—END 3: T = READ(1); VALUE = (T)? 16 : 8; BREAK; 4: T = READ(1); VALUE = (T) G010 ? : 12; BREAK;

5: VALUE = 20; BREAK; 6: VALUE = 44; BREAK; 7: T = READ(1); VALUE = (T)? 33 : 58; BREAK; //USE SEL?? 8: VALUE = 15; BREAK ;

CASE_END GO10: INPSTR S1, #3 READ_NCM S2, #0, off+S1 »2 VALUE = S2&amp;0x63; Q = (S2 » 6) &amp;0x3; READ SO, Q RETURN; G〇20:

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen 101 1354239 INPSTRS1,#4 READ_NCM S2, #0, off+s1»2 VALUE = S2&amp;0x63; Q = (S2 » 6 &amp;0x3; READ SO, Q RETURN; In some embodiments, a branch instruction can be used instead of a CASE statement. Therefore, MPEG-2-like VC-1 has a grammar that is easy to define. The symbol in the grammar: the number has a specific method (table) that can be executed as a colorizer, as shown by the above code. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a graphics processor system in which different decoding systems (and methods) can be executed; and FIG. 2 is a block diagram showing an exemplary processing environment in which a decoding system can be executed. Different embodiments of the present invention; Figure 3 is a block diagram showing the selection elements of the exemplary processing environment shown in Figure 2; Figure 4 is a block diagram showing the calculation of the exemplary processing environment shown in Figures 2 and 3, where Different embodiments of the decoding system; FIG. 5A is a block diagram showing the selection elements of the execution unit of the computing core in FIG. 4, in which different embodiments of the decoding system can be executed; FIG. 5B is a block diagram showing the data path of the execution unit, Among them

Client's Docket No.: S3U06-0013-TW TTs Docket No: 0608-A41246twf.doc/NikeyChen 102 1354239 Different embodiments of the row decoding system; Figure 5C shows a block diagram of the decoding system embodiment of Figure 5B, which is applicable In the plural coding standard, and the embodiment of the corresponding bit stream buffer is further displayed; FIG. 6A is a block diagram showing the embodiment of the decoding system in FIG. 5C.

» I use: for CABAC decoding; Figure 6B shows a block diagram of the decoding system embodiment of Figure 6A; Figure 6C shows the content memory structure of the decoding system and the block of the associated register embodiment of Figure 6A Figure 6D shows a macroblock partitioning mechanism using the decoding system of Figure 6A; Figure 6E shows a block diagram of the exemplary macroblock decoding mechanism performed by the decoding system of Figure 6A, 7A The figure shows a block diagram of a decoding system embodiment in FIG. 5C for CABAC decoding; and FIG. 7B shows a block diagram of a table structure embodiment used by the decoding system in FIG. 7A. [Description of main component symbols] 100--graphics processor system 102 to display device 104, - display interface unit 106~ local memory 110-'&quot;memory interface unit 114~ graphics processing unit 118--PCI-E bus interface Unit 122~ Chipset 124--System Memory 126~ Central Processing Unit 128-^Drive Software 200~Decoding System

Client's Docket No.: S3U06-0013-TW TT's Docket No: 0608-A41246twf.doc/NikeyChen 103 1354239 202~Graphic Processor 204~Calculation Core 206~Execution Unit Set Control and Vertex/Stream Streaming Unit 208~/Graphics Pipeline 302~ Texture Filtering Unit 304~-Pixel Wrapper 306~ Command Stream Processor 308-/Write Back Unit|310~ Texture Address Generator 402~/Execution Unit Input: 412~ Execution Unit Set 404a^~Execution Unit Output 404b-'^Execution unit odd output 406~/memory access unit 408~L2 cache memory 410-/memory interface arbiter 504~/instruction cache memory controller 506~/thread controller 508 ~ Buffer 510~Shared scratchpad file 512~ Execution unit data path 514~ 'Execution unit data path FIFO 516-' Predicate register file 518~ suffix register file 520~ / data output controller 524 ~ Thread task interface 526- / register file 530 ~ variable length decoding unit 532 ~ / vector floating point unit 534 ~ vector integer calculation logic unit 536 ~ special purpose list 540 ~ register file 562 ~ SREG stream buffer / DMA engine 562a ~ SREG register 562b ~ bit stream buffer 564 ~ adjacent content memory 568 ~ read adjacent memory module 570 ~ Check string module 572~read module

Client's Docket No.: S3U06-0013-TW TT's Docket No:0608-A43246iwf.doc/NikeyChen]Q4 1354239 574~ Computational Boot 1 Module 578~ MPEG Module 582~ CAVLC Module 602~Status Index 606~ Code Length Range 1 612~ Local register: 616~ Binary string register 622~ Get content module 624~ Binary calculation decoding reference 6 2 8~ Target 632- SRC1 634~ Shared and execution 636~delay/heavy Set 640~data 654~binary index 712~•bit level module 716~•level 0 module 720~ run module 724~•run array

576~Compute Boot 0 Module 580~CABAC Module 584~Exp-Golomb Module 604~High Probability Symbol Value 608~Code Length Offset 614~Overall Register 620~Secondary Module 630~SRC2 63 8~address 650~memory module 710~coefficient register module 714~level module 718~zero level module 722~level array

Client’s Docket No.: S3U06-0013-TW TT's Docket No:0608-A41246twf.doc/NikeyChen

Claims (1)

1354239 Case No. 096120728 Revised on July 4, 100. The scope of the patent application: 1. A solution system, comprising: a software programmable core processing unit having a variable length decoding unit for executing a shader, The above shader selectively performs a video stream decoding step to output a decoded data, wherein the video stream is encoded according to at least one of the complex encoding methods, and the decoding is performed. The combination of the software and the hardware, wherein the variable length decoding unit further comprises a direct memory access engine module, including a bit stream buffer and a direct memory access engine, the direct memory The body access engine repeatedly and automatically buffers the predetermined number in the bit stream buffer when a predetermined number of bits are used corresponding to execution of one of the above-described shaders of each segment. a bit number corresponding to the video stream, wherein the variable length decoding unit is further configured to correspond to the bit stream The expected underflow overflow in the buffer is delayed by the direct memory access engine module described above. 2. The decoding system of claim 1, wherein the decoding step is performed in a content programming of a graphics processing unit, and is implemented in a hardware path of the data processing unit of the graphics processing unit and in a bit stream. The buffer is implemented by an additional hardware for automatic management, and the above complex coding method includes content adaptive binary arithmetic coding (CABAC), content adaptive variable length coding (CAVLC), EXP-Golomb, and dynamic expert group. At least two of (MPEG-2) and VC-1. 3. The decoding system according to claim 2, wherein the variable length decoding unit corresponding to S3U06-0013-TW/0608-A41246TWF1 106 1354239 for adapting binary arithmetic decoding further comprises: a binary rendering ( a BIND module for receiving first information including a syntax component and a content block type, and corresponding to one of the above-described shaders executed by the binary imaging module, and The first information of the content model provides a second information corresponding to one or more macro block parameters; a get content (GCTX) module for receiving the second information, and corresponding to The second instruction of the shader executed by the content module provides a binary bit for binary decoding and content identification information, where the content identification information corresponds to a high probability symbol or a low a probability symbol probability; and a binary calculation decoding (BARD) module for receiving the binary, the content identification information, an offset, and a range, and A binary symbol is decoded corresponding to one of the above-described shaders executed by the binary decoding module. 4. The decoding system of claim 3, further comprising an internal memory array for content-based decoding and a corresponding scratchpad, wherein said content memory array comprises a current macro region And a neighboring macroblock unit, wherein the content module is configured to be used according to the fifth instruction of the shader executed by the content module to obtain the content module The Boolean logic operation of the numerical conversion of the volume array is written to the above content memory array. 5. The decoding system of claim 1, wherein the variable length decoding unit further comprises a binary string register for receiving an S3U06-0013-TW/0608-A41246TWF1 107 1354239 / decoding Pass the binary symbol and provide the updated content &lt; with the words FL. 6. As explained in the fifth paragraph of the patent application scope, the carry string register is used to receive the plural of the grammatical component of the grammar component, the machine, and the grammar component. A carry symbol. 7. As described in the first paragraph of the patent application, the liver and the spider, the straight-forward pair is widely used for variable length decoding units adapted to variable length decoding ', . (coeff token) module, -_ ' receives huge block block information with ^, and corresponds to the sixth command (CAVLC_TOTC) of the above-mentioned coloring cry + q &amp; a short tail coefficient (τ ' , 7 ailingOnes ) and a non-zero coefficient (TotalCoeff) information; - level (CAvLC_Level) module, "fun close to the trailing" information and a quasi-code information, and, corresponding to the upper, +, ~ a work Tons of coloring cry one of the seventh instructions (CAVLC_LVL) and provide - suffix length &amp; ^ ― level index ae - D information 'where the above-mentioned level sling bow ULevei [idx]) information is incremental; one quasi code (CAVLC_LevelCode ) will be, and 'to receive the above suffix length information, and, corresponding Providing the above-mentioned level code information to the level module in the eighth instruction (CAVLC_LC) of the coloring ^. A quasi-zero (CAVLC_L0) module 'for receiving the trailing 'i information' and corresponding to the above The shader-ninth instruction (CAVLC_LVLO) provides a second level of information (Levd [IdxH one quasi-array] where the second level index information is incremented; a zero level (CAVLC-ZL) mode a group for receiving the total coefficient information and a maximum value of the coefficient information, and providing a zero residual information corresponding to one of the tenth commands (CAVLC_ZL) of the coloring boundary S3U06-0013-TW/0608-A41246TWF1 108 1354239 1 And a reset value to a first and a second multiplexer; and a running (CAVLC_Run) module for respectively receiving the zero remaining information and the second level from the first and second multiplexers Index information, and corresponding to the eleventh instruction of the above shader (CAVLC_RUN) to provide a run index (Run [Idx]) to a run array. 8. The decoding system as described in claim 7 ,among them The quasi-array and the run array are configured to provide a decoded level value and a decoded run value corresponding to a twelfth instruction (READ_LRUN) of the shader. The decoding system of item 7, wherein the level array and the running array are cleared corresponding to a thirteenth instruction (CLR_LRUN) of one of the shaders. 10. The decoding system of claim 1, wherein the variable length decoding unit is further configured to use the number of bits in an instruction to determine whether to use one of the internal temporary registers. One of the results of the operation, or one of the data in one source of the operand should be used in one of the one or more modules currently operating. 11. The decoding system of claim 1, wherein the direct memory access engine is further configured to track the number of bits used in the bit stream buffer and to correspond to the number of bits. The above bit stream buffer operation is stopped and the conversion control is performed to a host processor. S3 U 06-0013-TW/0608-A41246TWF1 109 1354239. The decoding system according to claim 1, wherein the variable length solution unit corresponding to the MPEG-2 decoding further comprises: The G module is deleted to execute one or more MatcWLC functions to execute a brain G standard table, and each of the above-mentioned or a plurality of hemp wlc functions corresponds to an individual syntax component, and the above table selection is based on one of the above shader instructions. 13. The decoding as described in claim 12, wherein 4 MatchVLC functions are at least partially implemented in hardware - 14. The system described in claim 1 of the scope of the patent application, wherein the library is used for EXP The variable length solution stone unit of the -G〇1〇m_ code further includes: - an EXP_(5) (10)b module for performing a complex EXP-Gobmb operation using the -single-operating code, each - above complex * Exp_G〇i〇mb The use of the individual values of the immediate data block value in the - shader command is distinguished. The decoding system of claim 2, wherein the library is adapted to decode the variable length decoding unit described above. It is used to select ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^