TW200803526A - Decoding of context adaptive variable length codes in computational core of programmable graphics processing unit - Google Patents

Abstract

Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a context-adaptive variable length coding (CAVLC) unit configured to execute a shader, the shader configured to implement CAVLC decoding of a video stream and provide a decoded data output.

Description

200803526 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a data processing system, and more particularly to a programmable graphics processing method and method. [Prior Art] Computer graphics are the art and science of computer-generated images, images or other graphics or images. The current drawing system contains several interfaces, such as Microsoft's Direct3D interface and 0penGL. It can be controlled on a computer running a specific operating system (such as Microsoft's WINDOWS) such as a graphics accelerator or graphics processing unit (g-ics p: ing (or ^, in a two-dimensional (3D) computer surface, forming the surface of the object in the scene (or object) geometry is transformed into pixels (Figure touch iw 1

ΤΤ:Ρυ) and other multi-hardware 'images, images are often referred to as, = painting (deer), the details of such operations are generally added by the graphics 'to be more realistic Image, has developed many standards can be used 200803526

Video quality video, the number of bits in one of the two is one, you can store the same Η · 264 'Quasi-provide two entropy decoding knives another J 疋 内谷 adaptability one carry 异 编码 code ve ry arithmetic c 〇ding, CABAC) and context-adaptive variable length c〇ding (CAVLc), CAVLC is a content adaptive change of Huffman coding, which changes according to the general class of coded data. The probability of each coded symbol, CAVLC uses a run-level code to succinctly express the zero string, using this method to emit some high frequency + A4 coefficients and join the non-zero coefficients of adjacent blocks in CAVLC. The adaptively encodes the second Hadamard conversion of the 4×4 converted DC coefficient at or below the slice layer. The Uranium CAVLC decoding structure can meet some of the consumer's needs, but there are still limitations in design. . SUMMARY OF THE INVENTION The present invention discloses a content adaptive variable length coding (CABAC) decoding system and method (hereinafter simply referred to as a decoding system), which is applied to a graphics processing unit (GPU). In the embodiment, the system includes a 200803526 software programmable core processing unit having a CAVLC unit to execute a shader. The shader can perform CAVLC decoding of the video stream and provide a decoded data output. The method embodiment then includes the steps of loading the shader into a programmable core processing unit having a CAVLC unit, the CAVLC performing the rendering to decode a video stream in CAVLC, and providing a decoded data round. Those skilled in the art will be able to devise other systems, methods, features, and advantages after the following figures and detailed descriptions. All such systems, methods, features and advantages are within the scope of the present invention. The protection of the scope of the patent. [Embodiment] The present invention discloses a plurality of content-adaptive variable length coding (CAVLC) decoding systems and methods (hereinafter generally referred to as a decoding system). In an embodiment, the decoding system is Embedded in a graphics processing unit (GPU) of one or more execution units of a programmable, multi-threaded, parallel computing core, using software to combine hardware to achieve decoding, that is, video % code The content of the pr〇gramming is done in conjunction with the hardware implemented in the data path of the graphics processing unit. For example, the decoding operation or method has an extended instruction set. Color shader (shader coloring)

, the execution unit data path of the graphics processing unit, and the additional hardware used for the automatic management of the bit stream buffer in the CAVLC 200803526 processing environment, unlike the known legacy systems, with pure hardware Or the software-only CAVLC processing method limits the implementation flexibility. For example, a pure digital signal processor (DSP) or microprocessor based implementation does not have hardware for symbol decoding and bit stream management. . - In addition, the automatic bit stream buffer has some advantages, for example, once the bit memory buffer's direct memory aeeess (DMA) engine knows the location (address) of the bit stream, Will automatically manage the bit stream • stream without further instructions, this mechanism is different from the traditional microprocessor system. 'Bit stream management no longer represents a lot of overhead, and then, by recording the used bits The quantity, bit stream buffer mechanism can extract and process the wrong bit stream. Another advantage of the decoding system of the present invention is that it can reduce the instruction delay (10) which y), because CAVLC decoding is a very continuous action, and it is not easy to utilize multiple lights. Therefore, in various embodiments, a transfer mechanism is used to reduce the wait. Delays such as registerforwarding, in-step interpretation, deeper (deeP-pipeline) and multi-threaded processors can't execute instructions in every cycle of 'xiao-execution, some systems make use of General transfer (general f0rwarding), by checking the previous generation of the Yun Zengyuan address and the instruction operation meta-address (if phase (five), then: pre-human generation of transport), this general transfer Complex comparisons and multiplexed actions are required. In some decoding system embodiments, different transfer methods are used, whether using the previous calculation results (such as retained in the internal register) or the source operand data. The bits in the instruction (for example, a total of 2 bits, 8 200803526 each element using i bits) are encoded, in this way, the overall delay can be reduced, and the efficiency of the processor pipeline can be improved. . The decoding system described herein can utilize the known International Telecommunication Union Telecommunication Standardization Sector (ITU-T) H.264 standard, according to the execution of the slave graphics processing unit buffer memory or the host processor. (such as a central processing unit (CPU)) one or more groups of instructions received by the memory (such as known mechanisms such as preloading (prel〇ad) or cache failures, etc.) The decoding system embodiment can perform the operation. The first diagram is a block diagram of an embodiment of a graphics processor system 100 in which a decoding system and method are described. In some embodiments, the graphics processor system 100 can be a computer system, wherein the graphics processor system 100 can include Display interface unit (DIU) 104 driven display device 102 and area memory 16 (which may include display buffer, picture buffer, texture buffer, command buffer, etc.), area memory 106 may be replaced by a face buffer or a storage unit, and the area memory 1〇6 is connected to a graphics processing unit (GPU) 114 through one or more memory interface units (MIUs). In one embodiment, the memory interface unit 110, the graphics processing unit 114, and the display interface unit 104 are connected to a high-speed peripheral component interconnect express (PCI-E) compatible bus interface unit (bus interface). Unit, BIU) 118. In an embodiment, the bus interface unit 118 can use a graphical address redraw table (graphics 200803526 address rem Mapping table, GART) 'Of course other memory drawing mechanisms can also be used. Graphics processing unit 114 includes a decoding system 2, which will be further described later, although in some embodiments graphics processing elements are The decoding system 2 within 114 is grouped into one component, but the decoding system 200 may include more or less of the components of the graphics processor system. Sakai? Wide back

Group) or switch, chipset 122 includes interface circuitry (eg, (10) - plus - to enhance the signal received from central processing unit umt 'CPU) 126 (also known as the main processor), and separate the narrow memory 124 Incoming and outgoing signals and nicknames entering and exiting from the input/output (I/O) device, as mentioned here, Ρα_Ε busbar agreement, but other 1s and/or tongs (4) can be used to process g and qing processing. The unit memory is dedicated to the speed stream, etc.), and the system memory 124 is also packaged with::=128', which can be communicated to the _Fee 114_ scratchpad by the central processing unit. h can be additionally equipped with a (four)-shaped processing unit, which can be removed, added or changed by using the first embodiment to include the first-fourth embodiment of the processing unit 1 . Referring to the second diagram, a decoding system 200 is illustrated as a block diagram illustrating a processing environment in which the graphics processing unit 114 includes a graphics processor 200803526 202 'graphic processor. 202 includes a plurality of execution units (implementation uit, EU) and a computing core 204 (ie, a software programmable core processing unit). In the consistent example, the 'differentiation core 204 includes a data path embedded in the execution unit.

(execution unit data path, EUDP) decoding system 2 (ie, CAVLC unit), the data path is allocated to one or more execution units, and the graphics processing unit 202 also includes execution unit set control and vertex/streaming cache Memory • Unit 206 (hereafter referred to as EU Set Control Unit 206) and with fixed 10 function logic (4) such as the singular triangle setting unit (9) (10) 咏 叩 叩 T 、 、, grid-tile generator (Span4ile generat〇r, STG), etc., drawing pipeline 208, computing core 204 includes a plurality of joint execution units to meet the computational requirements of the colorizer tasks of different shader programs, which may include vertex shaders, geometry shaders, and / / or pixel coloring, so that the drawing pipeline 208 can process the data, the calculation of the color of the core 204 for the month b for most of the functions of the decoding system 2, the embodiment of the graphics processing 202 will be described in detail below, followed by the decoding system 2 〇〇 details. The decoding system may be implemented in the form of hardware, software, firmware, or a combination thereof. In a preferred embodiment, the decoding system 2 may include hardware or software, using known techniques of the y column or a combination thereof, for example. · Discrete logic circuit with logic gate for the function of data letter 1 , wood with oxygen circuit with proper combination of logic gates (applicati〇n 加以 加以 circuit, ) 粒 grained gate array ( Pr〇grammabie gate array, ) is a type of field programmable gate air array (FPGA) and other components. The second diagram and the fourth diagram are selected for the graphics processor to move the embodiment 200803526 to select the box of the 7-piece, such as the description, the solution, the colorizer in the graphics processor 202, and With the addition of the instruction set and other hardware components, the following will implement the embodiment of the processor and the corresponding program, although the third and fourth figures do not describe the _all components used in graphics processing, but it is enough to familiarize themselves with this. The function and architecture of the artist-related graphics processor. Referring to the third figure, the programmable processing core is a computing core 204, which includes a gamma system, and can process various instructions. The computing core 204 can execute or map multiple colorizer programs, such as vertices and geometries. , pixel coloring, etc. 'Multi-thread processing H's computational core, 2〇4 can process multiple instructions in a single clock cycle. In the third figure, the relevant elements of the graphics processor 2〇2 include a computation core 204, a texture filtering unit 3〇2, a pixel packing component 3〇4, a command stream processing state 306, a bypass unit 308, and a texture address generation. The EU set control unit 206 in the third figure also includes a vertex cache memory and/or a stream cache memory. In addition, the texture filter unit 3〇2 of the third graph provides texel data. To computing core 204 (input a and Β), in some embodiments, the texel data is 512-bit data. Pixel packing component 304 provides pixel shader input (PS input, inputs C and D) to computing core 204, the input is also in the 512-bit data format, and in addition, pixel packing component 304 requests pixel shader from EU collective control unit 2〇6 The task, and the ElJ collection control unit 206 will provide the specified execution unit number (EU#) and the thread number (thread #) to the pixel packing component 304, since the pixel packing component 304 and the texture filtering unit 3〇2 are known. The technique is not described here. Although the third figure shows that the pixel and texture 12 200803526 is a 512-bit data packet, it can be changed according to the performance required by the graphics processor 202 according to various embodiments. Command stream processor 306 provides a triangle vertex index to the EU collective control

The unit 206, in the embodiment of the third figure, indexes the data of 256 bits, and the EU set control unit 206 combines the vertex shader inputs received from the stream cache and sends the data to the computing core. 204 (input E); the EU set control unit 206 also combines the geometry shader inputs and sends the data to the compute core 204 (input F); the EU set control unit 206 additionally controls the execution unit inputs (EU inputs) 4〇2 and The execution unit output (EU output) 404 (fourth diagram), in other words, the EU collective control unit 2〇6 controls the respective input streams and output streams of the different core 204. After processing, the computational core 204 provides pixel output: round out J1 and J2) to the writeback unit 3〇8, and the pixel shader output includes color shade, such as red/green/blue, transparency (rgba) information, regarding implementation = in the data structure, the pixel shader output can be two tributary streams along the edge 'other real _ can also use other bit width. In addition to c = shader round out 'calculation core 2 〇 4 will also turn out texture seat 2 (TC 'output K1 and Κ 2) to the texture address including UVRQ information, texture address ^ where the package to ^ ^ mouth X) of the different core 204, and then calculate the core 2〇4 red 2 ^ ^ seeking (Ir, input > service, +, 咕 咕 夬 έ έ έ 408 408 408 408 408 屮 屮 屮 屮 采 采 采 采 采 采 采 述 述(Ding #资料, turn out and turn out the texture because of the texture fairy: generate $ 3,, _ New generator 310, 0 - when 310 and write back to early 308 is known, so the Tingri no longer repeats - Technology,

..., URVQ and rgb A 13 200803526 are 512-bit data, but this parameter can also be changed with different embodiments. In the embodiment of the third figure, the bus is divided into two 512-bit channels. Simultaneously transmit 128-bit RGBA color values of 4 pixels and 128-bit UVRQ texture coordinates. The drawing pipeline 208 includes a fixed function graphics processing function, for example, a command to draw a triangle from the driver software, the vertex information is converted to the vertex by the vertex shader logic in the core 204, and the object will be swapped from the object space. The triangles of the workspace and the screen space, the triangles reach the triangle setting unit of the drawing pipeline 2〇8 through the calculation core 204, and perform known tasks in combination with the primitives, such as generating a bounding box, culling, generating The edge function (in the case of explicit functi: generation) and the triangle level culling (triangle level and then the triangle setting unit and then: the new: to the _ pipeline with the block generation function of the grid and the tile generation unit, therefore, the dragon object is segmented Plots (eg 8x8, 16χ16 #) and pass them to other fixed function units for depth (z-value) processing, such as high-order z-order (the same program uses fewer bits in higher order than lower order) ) cull, then pass the & value back to the pixel shader logic of the computation core 2G4, based on the resulting Line data for pixel shader function, calculate the core, tear the processed value out to the target unit located in the _ pipeline fine, target list = before the cache memory will update the internal value before the detailed test and template test The L2 cache memory 4〇8 of the core computing core 204 and the orphan set control unit 206 have a transmission of 512 vertices of the vertex cache memory of the trajectory of the trajectory of the singularity of the singularity of the singularity of the singularity of the sequel 512-bit vertices cache memory (4) Write people = two to give the collection control unit to move forward - step processing. And milk) ^ See the fourth picture 'which shows the other core components of the computing core, count the nose core 204 includes an execution unit having one or more execution orders = 420a to 420h (hereinafter referred to as execution unit 42A). Each execution unit 420 may be at - time __ processing port _ ^ Therefore, execution unit set 412 is at a peak At the same time, you can handle multiple executions at the same time or several days, although the fourth diagram only draws 8 execution units (EU0~EU7) 'but not face_decrease 8, which can increase or decrease the number in other embodiments. , the towel at least - the recording unit ( The coffee 420a) having - 2〇〇 decoding system, described in detail below. Computational core 2G4 also contains memory access unit (m(10)ry access umt 'deleted) · 'memory access unit is connected by memory interface arbitrator and L2 wire memory. u cache memory is collected from EU The control unit 2〇6 receives the vertex cache memory overflow data (round G) and provides the vertex cache memory overflow data (input η) to the set, the unit 206, and the L2 cache memory The texture address generator 310 receives the texture description symbol request (τ# request, input X), and provides a texture description symbol data (repeated, rounded out W) to the texture address generator 31 in response to receiving the request. . The memory interface arbiter 410 provides a control interface for the area video memory (such as the face buffer or the area memory 106), and the bus interface unit 8 provides a system interface, which can be a pci_E bus, memory 15 200803526 The physical interface arbitration 11410 and the bus interface unit 118 serve as an interface between the memory and the u cache reader 408. In some embodiments, the L2 cache memory is accessed by the memory access unit. The physical interface arbiter 410 and the buffer interface unit 118 are connected, and the memory access unit ^ converts the virtual memory address obtained from the L2 cache memory and other blocks into an actual memory address. * The New Interface 赖11 provides the L2 cache clock ticker #access (such as read, write access), extractable instructions / constant / data into texture, silk memory access (such as load / store) , index temporary access, scratchpad temperature, vertex cache, content overflow, and so on. The computing core 204 also includes an execution unit input (10) round-in) 4〇2 and an execution unit output (10) output) 4〇4 for providing an input of the execution unit set 412 and an output of the receive execution unit set 412, respectively, performing unit input operations and The execution unit output can be a switch or a bus or other known output mechanism. • Execution unit input 402 receives vertex, shader input (input E), and geometry shader input (input from EU set control unit 2〇6), then provides the poor message to the execution unit set, leaving each execution unit to go > In addition, the execution unit inputs 4〇2 to receive pixel shader inputs (input C and D) and texel packets (input A and magic, and transfer these packets to the execution unit aggregation, age execution unit·Qianli Furthermore, the execution unit input 402 receives information (L2 read) from the L2 cache memory 4〇8 and then provides the information to the execution unit set 412 as necessary. The execution unit output 404 of the fourth embodiment Divided into even outputs 4〇4a 16 200803526 and output 404b' execution unit outputs 4〇4 and execution unit inputs may be switched off or busbars, other known architectures, performing single-turn output 404a processing even execution units 42 〇a, 42〇c, 42 plus, 42 such as the output, and the execution unit odd output 4_ processing odd execution unit object 420d 42Gf 4201ι round, in summary, the two execution unit outputs 404a and 404b The rounds of the receive execution unit set 412, such as wRQ and RGBA data 'the rounds can be passed back to the L2 cache memory 4〇8, or from the compute core 204 via the η and 12 outputs to the writeback unit, or via Κ1 and Κ2 are output to the texture address generator.

The light is as follows: ^ 412 execution unit stream usually contains several levels, such as the content level, thread or task level, instruction or execution level, f any time point, each - execution unit 42G may allow two strokes Content, wherein the _-bit flag or other mechanism identifies the content of the content before the task belongs to the output, and the content information is output from the Eu collection control unit 2〇6, and the content level information can be the type of the shader, and the input is temporarily stored. Read quantity, instruction start address, output mapping table, vertex identifier: each constant __ constant, each good 42G in execution unit set 412 can store multiple tasks or threads simultaneously (for example, % ^) In the embodiment, the 'per-execution is extracted according to the program counter'. Wood 5 controls early 70 206 similar to the total task schedule, using data driven _ such as en) method (such as the vertices, pixels, geometric seals within the input signal to send the appropriate thread within the execution unit 420, for example, ie System 206 assigns - a thread to the execution of the execution unit set 412 ^ 200803526 - empty thread position in element 420, when a thread has started execution, vertex cache memory or other components or modules (according to The data entered by the shader type is placed in the shared scratchpad. Typically, the graphics processor 202 uses programmable vertex, geometry, and buffers, and no longer treats these components as distinct fixed functional units with different designs and instruction sets. And each of these components is executed or operated, but the execution unit 42Ga, the singularity, the instruction group, the execution unit gamma (this execution unit contains the gamma system, a function) The design and structure of the execution of the program operation are the same. In one embodiment, each of the two functions: r420 can perform multiple thread operations, and when the vertex shader and geometry are sent to the Execution unit to execute, in 420 = system! ^ 2〇0 can use a vertex shader, and other execution units which are used by the execution unit 42Ga - solution system 2〇0, system:: wide), because The solution is solved by wiring 2: should: the internal buffer 'decoding system yuan 鄕 to obtain the data. Maru 仃 early into the 402 from the memory access list ¥ generated individual ^ 壬 some tasks to different execution units 4: Two:: Assign this EU set control unit 206 to manage the phase _",, Tian Fancheng task, that is, the set control unit ^ = = 'just, the point color's task to the execution unit (four)'s thread And then 18 200803526 相关 related tasks and threads, specifically, the EU set control a single 〇6 with all the execution units of the thread and the resources of the memory are not explained), EU collection control unit The article will know which ^ = give:: a task to use, know which task - the task of the task: to release, know (four) good (four) make health (four) case memory temporarily crying, therefore, if a task has been assigned to a wound , EU collection control unit 2〇6 will hold this 2 = in ' After that, all the shared register slots will be recorded with the shader and the color like «color (4) «1, = vertex mouth two solids can have different body sizes, for example: in the case of: 1G shared registers can be used to require only 5 registers. When the pixel is done - the thread is finished and it is assigned ^ the line 7G 420 will send a signal 仏Μ 行 的 的 集合 集合 控制 控制 控制 控制 控制 控制 挪 挪 Ευ Ευ Ευ Ευ Ευ Ευ Ευ Ευ Ευ 共用Temporary store floor _ number ^= not in between, although all the threads are in the busy green 1 plus back to the available empty memory has been allocated (or use the scratchpad slot to accommodate additional execution) Thread), β] ψ Save °. The work space is too small, can not be every, the unit early element control unit will not move again = new order: yuan 420 is considered full, the fat set each one to implement a new thread to the implementation can be 19 200803526 to manage or It is noted that each thread is in use (or in execution) or available. In this regard, in one embodiment, when the vertex shading is performing the function of the decoding system 200, the set control unit 2〇 6 prevents geometry shaders and pixel shaders from running at the same time.

The fifth diagram illustrates an execution unit 420a having the aforementioned graphics processor 2〇2 and computing core 204 features, which includes an execution unit data path 512 embedded with a decoding system 2〇〇, specifically, a fifth A diagram is a The block diagram of the execution unit 420a, in one embodiment, includes an instruction cache controller 504, a thread controller 506 coupled to the instruction cache controller 5〇4, and a buffer 5〇8 (eg, Constant buffer), common register file (CRF) 51〇, execution order data path (EUdatapath, EUDP) connected to the thread controller ^ and buffer 508 and the shared register file 51〇 512, execution unit data path first in first out (FIF0) 514, _iCate register flle (PRF) 516, scalar register file 'SRF) 518, data The round-out controller 52Q and the thread task interface 524', as previously described, the execution unit receives the round-in's input from the execution unit input 4〇2 to provide an output to the execution order (10). The thread controller 506 provides the control unit 2 of the entire execution unit 4 for each thread and the judgment function 'for example, how to perform the execution ti, and the EUDP 512 includes the decoding _ _, which includes, for example, a floating-point arithmetic calculation logic unit ( Arithmetic logic leg 'ALU), shift logic function and other logic circuits. The data output controller 520 can move the completed data to some information that is executed to perform the processing of the device vertex cache memory and the write back control unit m that are connected 4〇4 early. 'EUSP5i2 transmits "any data rotation controller 520 contains f two 520, telling the task has been completed, the magic project (her y)), and also includes the points, to complete the tasks of the library (such as not selecting tasks from the library part ^ Solid = 埠, the data wheel out of the controller's register location, from the shared temporary ... x 豕 盗 盗 营 营 营 内容 内容 内容 内容 内容 内容 内容 内容 盗 盗 盗 盗 盗 盗 盗 ^ ^ ^ ^ ^ ^ ^ The task interface 524 is rounded out early: 0 round out 404. The other is assigned to the EU set control unit 2. The task of the early sangha completion task control unit 206 has a specific execution... the broken identifier will notify the EU to collect a new task. The execution of the single-line resource can be assigned to each dm', and the constant buffer 508 can be divided into 16 blocks. The block has 16 positions of 128-bit horizontal vector constants, coloring crying elements and - index access-constants. Buffer position can be referenced to contain 32 bits or close to ', number The register is nearly 32-bit 兀 unsigned integers often Jr: the memory controller 504 is the interface block of the thread controller 506, the domain is reduced by _ 提 亍 = 亍 coloring (four), instruction cache The memory controller 50: 3 marks the table (not 1 will be output) 'to hit / miss the test, give a 2 'if the requested instruction is located in the cache of the instruction cache controller 504 in the body Then the table does not hit 'If the command to be requested is extracted from the L2 cache memory 408 or the memory (10), it means no, if it hits, 21 200803526 and at the same time / there is a round from the execution unit 4〇2 The request cache memory controller 504 can agree to the request, because the instruction cache memory H 504 has only one read/write buffer for the instruction cache, and the execution unit 402 has the highest priority. Conversely, if not, and there is a replaceable block in the L2 cache memory 4〇8 and there is room for the twist ^ 'FI= 514, the instruction cache controller 5〇4 can agree Request, in the shell target example, the cache of the instruction cache controller 504 is cached. The body pack has 32 groups, and the parent group has 4 blocks, each block has a 2-bit status signal, which can represent three states, respectively, invalid, loaded, or valid state. 2 Load L2 data in the block. Previously, the block was in the "invalid" state. When waiting for the L2 material, it was in the "loaded" state. When the L2 data was completely loaded, it became "valid". The EUDP path 512 can be used to temporarily store the statement. The file is read and written, and the execution unit input 402 is used as an interface for entering the data and execution unit 42A. In an embodiment, the execution unit input 4〇2 includes an 8 item advanced • first out buffer 11 to buffer incoming data. The execution unit input 4G2 can also transfer the instruction cache memory and constant buffer 508 to the instruction cache memory controller 5〇4, and the execution unit input 402 can also retain the shader content. The executable unit output 404 is used as an interface for outputting data from the execution unit 42A, to the EU collective control unit 2〇6, the u cache memory 4〇8, and the write back unit 308. In an embodiment, The execution unit output tearing includes a 4-item FIFO buffer for receiving the arbitration request, and buffering the data that is rotated out to the EU collective control unit 2〇6, and the execution unit output marriage includes multiple functions, and the arbitration instruction cache can be arbitrated. Memory read request, data round 22 200803526 Write request, eudp read/write request. The shared temporary storage file 510 is used for storing input, output, and temporary storage data. In one embodiment, the shared temporary storage file 510 includes eight 128 X 128-bit temporary storage files of a bank and a first reading. One write and one read/write 埠, one read and write 璋 is used by EUDP 512, for read and write access of instruction execution, even logic shared memory page 2、, 2, 4, 6, and xy thread § Recalling pages 1, 3, 5, 7, the thread controller 506 is paired differently

The command is executed and the memory of the shared scratchpad file is not read or written. The read/write buffer is used by the execution unit input 402 and the data output controller 52 to load the initial thread input data and output the final thread output to the EU collective control unit data buffer and [2 cache memory or The other modules, the execution unit input 402 and the execution unit output 4〇4 share a read/write I/O淳. In the embodiment, the write has higher priority than the read, and the 512-bit input data enters 4 Different memory pages to avoid conflicts when loading data into the file temporary storage file M0. The 2-bit channel index, data and 512 bit aligned base address are used to specify the rounded data. Start the memory page, for example, if you start to trade! , memory page 1 carries the first 128 bits from the least significant bit (LSB), the next 12δ bit is loaded into memory page 2, and so on, assuming the thread reference memory page = compensation is 0, the last _ (3) bits are loaded into the memory page 〇, please note that the two least significant bits of the executive ID - are used to generate a memory page compensation, to randomize the memory of a thread to start the memory page position. 23 200803526,: the scratchpad index and the thread ID can be used to establish - the unique - the logical address of the 'tag with the difficulty of mateeing" North 2 510 read and write data, for example, the address can be arranged 128 bits = === The width of the memory page is the same. By combining the two: the index and the 5-bit thread ID, you can create a unique 13-bit address, one for each 24-bit line. — The line has two 512-bit items (characters), # + shouting, the mother is one hundred and one, and the receiving one is stored in four records.

In the middle, the two least significant bits of the CRF index are added to the current execution, and the § page compensation is established to establish the memory page selection. The tag pairing method allows the shared buffers of different threads to share the shared temporary storage: 55='effective use of memory' fat collection control unit fine record: use the memory file of the temporary file file 51〇 There is enough space for the new task of the execution of the single 420a. Check the current thread of the target CRF index accounted for all CRF register: large〗 Before the thread control 〇 5 〇 6 to start the thread and color holder = =, the input data should be stored in the shared register file 5lQ, After the execution of the field thread is completed, the data output controller 52 reads the output data from the shared register file 510. The embodiment of the execution unit 420 has an EUDP 512' including a decoding system 2 (10). The fifth b diagram illustrates an embodiment of an EUDP 512. The EUDP 512 includes a scratchpad file 526, a multiplexer 528, and a vector floating point (FP). Unit 532, inward integer arithmetic unit (ALU) 534, special purpose unit 536, multiplex 538, register file 54, and decoding system 200, decoding system 2 includes one or more cavlc units 530 , can decode one or more 24 200803526 streams 'for example, a single CAVT abomination - - * LAVLC early 530 can decode a single - stream, two CAVLC units 53 〇 (as shown by the dotted line, but for the sake of simplicity: The connection relationship is not shown. It is possible to decode two streams at the same time, etc., and the following description is only for the operation of the _Calc unit (10)=, the operation of the code system 200, and the principle can be deduced to more than one Cavlc. As shown, EUDP 512 contains the corresponding cavlc

53〇^t^^^ 532^tALU534.^9^^ Some flat poor = path, each unit can perform the corresponding operation according to the received instruction 'scratch register 526 receive operation unit (mark ^ SRC1 and SRC2) 'In one embodiment, the scratchpad file 526 may be a shared register slot case, a description register slot adder, and/or a scalar register file as shown in FIG. 518, please note that in some embodiments, more operand operations (wei) signal lines 542 can be used to provide a means for each of the single '-, 5 匕 536 to receive an alien signal. The current signal line 544 is connected to the multiplexer 528. The current value encoded into the instruction can be transmitted, and the integer operation of the small integer value is performed for each single 530~536, and the instruction decoder (the 兀, 运, 运算 (function) signal, and the current signal, the data path is written The multiplexer 538 at the end of the back phase selects the correct path, then the output, and the result is sent to the scratchpad file 540, and the output buffer file 54 〇^ contains: the target component, which can be the scratchpad file 526 or Other registers, please note that in the embodiment, #源 and target temporary storage 11 contain the same \ $ for the latter Source and target component selection, for multiplexed crying Information from/to the appropriate scratchpad file. 25 200803526 Therefore, the execution unit 420a can be regarded as a multi-stage pipeline (for example, the 4th-order pipeline γ has 4 arithmetic logic units), and the CAVLC decoding operation occurs in 4 accompaniment phases, which requires a delay to allow the CAVLc to decode the executor action. For example, when the bit stream buffer has a downward overflow (underfl〇w), waiting for initialization of the content memory, etc., the touch bit stream carrying the fifq buffer and the sREG register (explained later), And/or the processing time has exceeded the scheduled time, etc., and the delay can be added during the execution phase. In some embodiments, the decoding system 2 uses a single execution unit 42A to decode and decode two bitstreams. For example, according to an extended instruction set, the decoding system can use two data paths (such as adding another A single 兀 530) (4) to decode two streams, of course, can decode more or less streams (then will use more or less data paths), when involving multiple streams, some Some decoding systems 200 do not limit simultaneous decoding: Additionally, in some embodiments, the single-CAVLC unit 53() can perform multiple simultaneous stream decoding. In the implementation of the shot, when the decoding system uses two #料狎, two threads can be turned off, the side is in the two streams, in the two streams, the number of _executors is two, the first - The thread (such as executor) is assigned to the first memory page of the solution system (ie, cavlc unit 530) 'the first thread (such as the thread is assigned to the second memory of the solution system) Page (ie, the virtual, line CAVLC unit of Figure 5B), in some embodiments, 'two threads can run on a single-memory page', although the decoding system shown here is embedded in EUDp 512. , including other components, such as the logic within the W set control unit. * 26 200803526. The execution unit 420 &, £11 〇 512, and (^\^〇 some embodiments of the unit 530 have been described below,蔺Definition of the decoding system for Η.264 CAVLC operation content 'KevLC program code is known as the level (size) of the signal related to the macroblock or part of the giant tile, know how often this level is ( If the number of cycles is repeated (nm, operation), you don’t need to The code 'obtains from the bit stream buffer and parses such information. When the decoding engine of the decoding system 200 uses the information in the buffer, the data is replenished, and the decoding system 2 〇〇 from the bit stream Extracting the huge block information including the level and the operation (mn) coefficient, inverting the encoding process, and then reconstructing the signal. The decoding system 2 buffers the bit stream to obtain the macro block information and parses the stream to Obtain the level and operating coefficient values, temporarily store them in the hierarchical array and operation 卩 (4), and then read out these hierarchical arrays and operations _ (such as the 4 χ 4 block pixels in the blocks in the block), then clear the tier _ and operate the rush The next-health block, according to H.2641, uses software to process each huge block of 4χ4 blocks. Jiang Xianren-Ma Xiaoxu's various meta-systems of the decoding system 200 in the inner valley::: Various deformations of the application For consideration, many of the terms familiar to this artist (such as the name of each parameter) are from the succinct reason, no longer Wei, unless it is helpful to not even nuclear / or components, will be done again - step description Brother to the first Figure c is a block diagram illustrating a decoding system. 200803526 The decoding system 200 depicted therein has a single CAVLC unit 53A (in Figures 6A through 6C, the cavlc unit 530 used may be interchanged with the decoding system 200), Therefore, in an embodiment, the decoding system 2 can decode a single bit stream, and the same principle can be applied to the decoding system 200 having a plurality of CAVLC units, which can simultaneously decode multiple (eg, two) streams. 6A is a selection component of the CAVLC unit 53A, the sixth B diagram illustrates the stream buffer function provided by the CAVLC unit, and the sixth c diagram illustrates the content memory (including the scratchpad) function of the CAVLC unit 530, The sixth D diagram illustrates the form structure of the CAVLC decoding. Although the following description is about giant tile decoding, this principle can be applied to various tile decoding. Referring to FIG. 6A, the CAVLC unit 53 includes a plurality of hardware modules 'coeff-t〇ken module 61〇, a level code (CAVLC-LevelCode) module 612, and a level (CAVLC- Level 614, tier 0 (CAVLC_L0) module 616, zero level (CAVLC-ZL) module 618, operation (CAVLC-Run) module 620, hierarchical array (LevelArmy) 622, and operational array (RunArray) 624 The decoding system also includes a shift register (SREG) stream buffer/direct memory access (DMA) engine 602 (also see Figure 6b, hereinafter referred to as DMA engine module), total register 606. The area register 608, and the macroblock adjacent content (mbNeighCtx) memory 604 in the sixth c picture (in one embodiment, the mbNeighCtx memory includes a 96-bit register, which may be colored as an intrusion The other three 32-bit registers are not circumvented. The interface between the CAVLC unit 530 and the execution unit 420a includes one or 28 200803526 multiple target rows and corresponding (four) registers (such as DST register) ), two source bus and corresponding register (SRC Bu 2), the target bus can be poor The data processing unit is transmitted to the video processing unit inside or outside the graphics processing unit 114, such as via memory, temporary storage, buffer, or memory. The data on the target bus can be Microsoft. DX API format or other format, these data contain coefficients, giant block parameters

- f ' _ information, and / or 1PCM sampling or other information, CAVLC f 530 also includes a memory composed of health bus and f dragon flow row =, after obtaining the address from the address bus, you can In the embodiment, the data on the data bus can include an unencrypted video stream, including various signal parameters and other data and formats, by using the data obtained from the data bus to access the bit stream data. In some embodiments, a load-storage operation can be used to access the bitstream data. Before the description of each component of the CAVLC single it 530, simply say = the entire operation of the execution unit of the CAVLC decoding, usually, according to the slice form, the driver software 128 (first picture) prepares the CAVLC shader And load it into the execution unit 42. The cavlc coloring is combined with the standard instruction set plus coeff"〇ken, · CAVLC-Level, CAVLC L〇, CAVLC-ZL, and -cA. The decoding of the bit stream can be performed. The principle of naming here is that each module will issue an instruction with the same name. In addition, the hierarchical array 622 and the operational array 624 have READ_LEVEL_RUN and CLR_LEVEL RUN related to the read operation and the clear operation. The instructions, in an embodiment, prior to issuing other instructions, the first 29 200803526 instructions executed by the CAVLC shader are ΙΝΙΤ-CAVLC and INIT_ADE instructions, which cause the CAVLC unit 530 to start CAVLC decoding of the one-bit stream, The bit stream is loaded into the FIFO buffer from the stream decoding point. These two instructions will be described later, so the CAVLC unit 530 provides the parsing bit stream, the initialization decoding hardware, and the scratchpad/memory structure. And level-run decoding, the h, 264 CAVAC decoding program function will be explained later, starting with the operation of the bitstream buffer.

Regarding parsing the bit stream, the bit stream is received from the data bus of the memory interface, and then buffered by the SREG stream buffer/DMA engine 618. The slice data parsing stage provides bit it stream decoding, and the bit stream (such as the bit stream) The elementary stream) consists of - or more pictures, which are cut into a trough head (four) (four) and a number of slices. The - slice usually contains a series of giant tiles, in the embodiment - an external program (ie CAVLC cell) 53〇 External) parsing the NAL low stream, decoding the slice play header, and transmitting the indicator pointing to the slice data (such as the beginning of the slice) 'typically, the driver software m processes the residual stream from the slice data' because this is the function provided by the application and the API. , the indicator transfer to the 贫 poor material position also involves the first byte address of the slice data (such as RBSPbyeAddress) and the bit compensation indicator (such as the bit bit or indicating the start of the bit stream or the position of the header such as sREGptr) Multiple bits), the initialization of the meta-flow will be difficult to explain. In some implementations, the main processor (such as the central processing unit 126) processes the external path to provide image decoding and slice header decoding, and In the embodiment, the decoding system 200 performs h.264 bit stream parsing from the picture, and the ca^ decoding operation is performed according to the slice data from the giant tile. In some implementations 30 200803526, the example is because of the CAVLC unit. Program features that can be decoded at any stage. Please refer to FIG. 6B, which is a block diagram of the selection component part of the SREG stream buffer/DMA engine 602 of the CAVLC unit 530 and other elements. The arithmetic unit registers 661 and 663 respectively receive the SRC1 and SRC2 values. And then transferred to the registers 656 and 667, the CAVLC logic circuit 660 is the module and component of the sixth A picture, but does not include the SREg string * buffer state / DMA engine 602, mbNeighCtx memory 604, total register 606, And the area register 608, the SREG stream buffer/DMA engine 618 includes an internal bit stream buffer 6〇2b, which in one embodiment can be a 32-bit register and 8 in the BigEndian format! 2 8 yuan temporary. The initialization command issued by the driver software 128 initially sets the sreq string buffer state/DMA engine 602, and once started, automatically manages the internal buffer 6〇2b of the sreG stream buffer/DMA engine 602, the SREG stream buffer The /DMA engine 602 reserves the location of the bit to be resolved. In one embodiment, the SREG stream buffer/DMA engine 6〇2 uses two registers, a fast 32-bit flip-flop and a slower 512 or 1024-bit memory bit stream. The bit shifting register 6〇2a operates from the bit, and the bit stream buffer 6〇2b operates in a bit group, which saves energy. Usually the shift register 6〇2& operation will make: a few bits (such as 1~3 bits), when the shift register (10) uses more than one bit_data, f material (bit (four) segment The slave stream buffer 6 is transferred to the shift register·a, and then the buffer indicator is subtracted from the number of bytes transferred, when the SREG stream buffer/DMA engine 6〇2 31 200803526 DMA When the engine detects the use of 256 bits or more, it extracts 256 bits from the memory to fill the bit stream buffer 6〇2b, so the CAVLC unit 530 implements a simple circular buffer (256 bits). Fragment X 4), to track and fill the bitstream buffer 6〇2b, in some embodiments a single buffer can be used, but a circular buffer requires more complex index calculations to keep up with the speed of the memory. . Using the initialization command to interact with the internal buffer 602b, referred to as the INIT^BSTR instruction, in one embodiment, the INITjgSTR instruction (which can be issued by the driver software 128) is issued almost simultaneously with the INIT-CAVLC (or ADE) instruction, forming a delay ( Stall), until the bit stream data enters the buffer 602b, once the data reaches the buffer 6〇2b, the program after the delay condition start is released, and if the buffer storage condition is lower than the predetermined threshold, the SREG bit stream buffer The DMA engine of the /DMA engine 602 will continue to extract the bitstream tribute into the buffer 602b. If the byte address and bit compensation of the bit stream location are known, the INIT-BSTR instruction loads the data into the internal bit stream buffer 602b and starts the hypervisor. Each call processing slice data will be issued in the following format. Instruction: INIT_BSTR offset, RBSPbyteAddress This instruction is used to load data into the internal buffer 602b of the SREG Stream Buffer/DMA Engine 602. In one embodiment, the SRC2 Temporary 663 provides a byte address. (RBSPbyteAddress), while the SRC1 temporary state 661 provides bit compensation, so the following general instruction formats can be used: INITJBSTR SRC2.SRC1, 32 200803526

The SRC1 and SRC2 and other signals in the instruction are values corresponding to the internal registers 661 and 663, but are not limited to the registers. In one embodiment, the memory is extracted using 256-bit arrays. The bitstream data is fetched and written to the buffer register and passed to the 32-bit shift register 602a of the SREG stream buffer/DMA engine 602, in one embodiment, in these registers Before the buffer is operated, the data in the bit stream buffer 602b is arranged in a byte group manner. The data arrangement can be implemented by an arrangement instruction, which is also called an ABST instruction, and the ABST instruction arranges the bit stream buffer. The data in the device 6〇2b, in the decoding process, the arrangement of the bits (such as padding bits) will eventually be discarded. When the shift register 602a uses the data, the internal buffer 6〇2b fills the data. In other words, the internal buffer 602b of the SREG stream buffer/DMA engine 6〇2 is similarly modulo 3 (modulo). The circular buffer, input data into the SREG stream buffer / DMA engine 6 〇 2%: meta-register 602a, CAVIX unit 53 〇 (such as CAVLC logic module 嶋) can use the READ instruction from the shift register Read data at 6〇2a. The format of the read command is as follows:

KbAD DST, SRC1, where DST corresponds to the -output or target register. In the embodiment, the srci register 661 contains an integer value n that is not signed, and is obtained by the 峨d instruction ^ shift register N-bit, when shifting from 32-bit temporary storage "02a consumes 256-bit data (such as decoding one or more syntax components)" automatically starts the extraction action to obtain another 256-bit binary material, write it The internal internal buffer __, then enters the shift two 33 200803526 602 for the next cycle. In some embodiments, if the data corresponding to a symbol decoded shifter 602a has been used The predetermined number of bits or bytes, and the two buffers ϋ 6G2b are not connected to any of the materials, the cavlc logic 660 can be delayed to execute other threads (eg = CAVLC decoder independent of the thread) ), such as the vertex shader operation using the SREG stream buffer / DMA engine 6 〇 2 引 引 可以 can reduce the number of buffers required to compensate for memory delay (for example: in some _ processing unit , will go to more than 300 jobs), #用了The bit stream can be requested to flow into the bit stream data that follows, if the bit material is too small, so that the bit _ 6G2b yang overflows (for example, it is known to let the signal flow from the CAVLC unit 53 to the processor). The number of cycles of the pipeline) can pass a delay signal to the processor pipeline, suspend operation, and wait for the data to arrive at the bitstream buffer 602b. In addition, the SREG stream buffer/DMA bow engine 6〇2 originally has a processing error bit. Meta_capability's _ child, the cyber cell flow error, there may be no left-end slice end mark, this side error may cause the decoding to be completely wrong' and use the later pattern or slice bit, sreg stream buffer / DMA engine 6 〇 2 record the number of bits used, if the number of bits used is greater than the preset threshold (can be changed for everything), then end the processing and send the removed signal to the processor (such as The main processor) then processes the code execution attempt to reply from the error. Two instructions for bit stream access are INpSTR and mpTRB instructions, and INPSTR and inpTRB are used to detect whether in slice or giant image 34 200803526 Appear Other pattern (pattern, such as a beginning or end data pattern), without performing the bit stream can start reading the bitstream, in one embodiment, means

The order is INPSTR, INPTRB, and then the READ instruction. The INPSTR instruction contains the following format: INPSTR DST, in one embodiment, the bit stream is viewed and the most south valid 16 bits of the shift register 6〇2& To the lower 16 bits of the target (DST) register, the south 16 bits of the target temporary state contain the sREGbitptr value, and the data is not removed from the shift register 602a as the operation result, and can be instantiated according to the following formula Virtual code execution instruction: MODULE INPSTR (DST)

OUTPUT [31:0] DST DST = {ZE (sREGbitptr), sREG [msb: msb-15]};

ENDMODULE Another instruction related to the bit stream is the inptrb instruction, which looks at the raw byte sequence payload (RBSP) tail bits (such as the byte array data stream), and the INPTRB instruction is used to read The bit stream buffer 602b can be in the following format: INPTRB DST. In the INPRB operation, no bit is shifted out from the shift register 6〇2b, if the most significant bit of the shift register 602b contains 1〇 〇 (unqualified), the RBSP stop bit is included, and the remaining bytes are all zero bits. The town executes the virtual code execution instruction according to the following formula: MODULE INPTRB(DST) 35 200803526 OUTPUT DST; REG [ 7:0] P; P = sREG [msb: msb-7];

Sp = sREGbitptr; T [7:0] = (P » sp) « sp; DST[l]-(T--0x80)? 1: 0;

DST[0] two! (CVLC-BufferBytesRemaining >〇); The ENDMODULE READ instruction is used to arrange the data in the bit stream buffer 602. The bitstream buffer operation of the CAVLC unit 530 has been described, followed by initialization of the CAVLC operation, particularly the initialization memory, the scratchpad structure, and the decoding engine (e.g., CAVLC logic circuit 660) at the beginning of the slice. Initializing the scratchpad structure, the total register 606, the region register 608, and the CAVLC decoding engine before decoding the syntax components corresponding to the first macroblock. In one embodiment, the driver software 128 issues the INIT-CAVLC The instruction performs this initialization. The init_CAVLC instruction can have the following instruction format: INIT—CAVLC SRC2, SRC1 where 'SRC2 contains the number of bits to slice the poor material to be decoded, and this value is written to the internal CVLC-bufferBytesRemaining register: SRC 1 [ 15:0] two mbAddrCurr, SRC1 [23:16] two mbPerLine, SRC 1 [24] two constrained-intrajpredflag, SRC 1 [27:25] two NAL-unit-type (NUT), 36 200803526 SRCl [29:28 ] = dm) ma_formatjdc (in one embodiment, the chroma_format-idc value of 1 corresponds to 4:2: 〇 format, other sampling mechanisms can be used in other embodiments) ' SRC1 [31:20] = not Definition The INIT-CAVLC instruction writes the SRC 1 value to the corresponding block of the total register 6〇6, and uses the INIT instruction to write the SRC2 value to the internal temporary storage (such as CVLC_bufferByteRemaining), and the CVLC_bufferByteRemaining register. In order to recover the error bit stream, for example, when decoding starts, the CAVLC unit 530 (such as the SREG bit stream buffer/DMA engine 602) records the buffer bits in the bit stream for a slice, after the bit stream is used. The CAVLC unit 53 counts and updates the CVLC_bufferByteRemaining value. If the value is lower than 〇, this indicates that the buffered or bit stream has an error, and the processing is quickly terminated, and the application control or driver software 128 control is returned. Carry out recovery. Referring to the sixth C diagram, the INIT-CAVLC instruction may also initialize the storage structures of the CAVLC unit 530, such as the memory 6〇4, the left mbNeighCtx register 684, and the current mbNeighCtx register 686. In one embodiment, mbNeighCtx Memory 61〇's giant map ghosts are in the middle of the valley, and the memory array is arranged to store the data about the giant tile column. Currently, the mbNeighCtx register 686 is used to store the giant tile of the target shovel decoding. The left mbNeighCtx register 684 is used to store the previously decoded (left) giant tile, and in addition, the upper indicator 6 magic left indicator 685, and the current indicator 687 (in the sixth C diagram, arrow), point to mbNeighCtx Memory 6〇4, left mbNeighCtx temporary storage 37 200803526 684, and current mbNeighCtx register 686, when decoding the current giant tile, the decoded data is stored in the current 咖 仏 仏 register 686 ^ known decoding In the nature of the content, according to the CAVLC-TOTC command, the current giant tile is decoded from the information of the former code reading block, that is, the left giant tile is stored in the left mbNeighCtx register 684 and utilizes the left side. Standard directivity 685, and stored in block upward giant array element [i] 681 and 683 using the index for pointing upward.

The INIT-CAVLC instruction is used to initialize the upper and left sides 683 and 685 of the giant tile adjacent to the current giant tile (such as the element of the mbNeighCtx memory array 604). For example, the left indicator 685 can be set to The upper indicator 683 can be set to 1, and the INIT CAVLC instruction also updates the total register 606. In one embodiment, the mbNeighCtx memory 604 includes an array of 12 elements, labeled mbNeighCtx[0], mbNeighCtx[1]... mbNeighCtx[119], and each picture can store up to 12 huge blocks ( Since the HDTV is 1920 x 1080 pixels, other array structures of different sizes can be utilized by those skilled in the art. For example, to determine whether an adjacent giant tile (such as the left giant tile) exists (valid), the CAVLC-TOTC instruction must perform an operation (such as mbCurrAddr%mbPerLine) to check whether the result is 〇, in the embodiment , the following formula: x mbPerLine mbCurrAddr - :{jnbCnrrAddr%mbPerLine) mbCurrAddr mbPerLine 38 200803526 mbCuirAddr represents the current giant tile position corresponding to the binary symbol to be decoded, mbPerLine represents the number of giant tiles in each column, the above calculation used To a division, a multiplication, and a subtraction. % Consider the following formula: mbCurrAddr ε [Ο : max MB -1] • where maxMB is 8192, and mbPerLine = 120, you can use multiply, go to and use the form stored in the memory on the chip (such as 120x11 bit table)杳_ Find it (1/mbPerLine) for division. If mbCurrentAddr is 13: Element 5, use 13 xll multiplier. In one embodiment, the result of the multiplication operation is taken as an integer, and the upper 13 bits are stored for 13x7. The multiplication is different, the lower 13 bits are stored, and the 13-bit subtraction is finally performed to determine "a". The entire operation requires 2 cycles. This result can be stored for other operations, and is calculated whenever mbCurrAddr is changed. once. In some embodiments, the modulus (m〇dul〇) operation is not performed, and the color filter logic circuit φ in the execution unit (e.g., execution unit 420a, 420b, etc.) provides the first mbAddrCurr value, which is located at In the first line of a slice, for example, the shader logic can perform the following calculations: mbAddrCurr - absoluteMbAddrCurr - nx mbPerLine Use the CWRITE command to "move" the contents of the mbNeighCtx memory 604. The format of the CWRITE instruction can be: CWRITE SRC1, where SRC1 [15:0] = mbAddrCurr, the CWRITE instruction is copied from the appropriate field of the current mbNeighCtx register 686 to the upper mbNeighCtx[i] of the mbNeighCtx[] structure 604 and the left side 39 200803526 mbNeighCtx[il], KmbAddrCUrr% mbPerLine = = 0), & side mbNeighCtxLeft 684 is marked as non-existent (eg, initialized to 〇), and the contents of the mbNeighCtx memory 604, the region register 608, and the total register 606 can be "moved" using the CWRITE command. For example, the CWRITE command moves the relevant content of the mbNeigliCtx memory 604 to the left and upper blocks of the i-th macroblock (eg jj^NeighCtxfi) Or the current giant block), and empty the mbNeighCtx register 686, as previously mentioned, the two indicators associated with the mbNeighCtx memory 604 are the left indicator 685 and the upper indicator 683, after the CWRITE instruction, the upper index is increased, While the contents of the giant tile are moved to the upper and left positions of the array 604, the above system can reduce the number of read/write ports of the memory array to one read/write buffer. The contents of the mbNeighCtx memory 604, the local register 608, and the total register 606 can be updated by using the INSERT instruction. The format of the INSERT instruction can be: INSERT DST, #Imm, SRCl. This INSERT instruction, #Imm contains 10 bits. The number, the first 5 bit width and the higher 5 bits of the data specify the location where the data will be inserted. The input parameters have the following format:

Mask = NOT(0xFFFFFFFF«#Imm[4:0])

Data = SRC 1 & Mask SDATA = Data«#Imm[9:5] SMask = Mask«#Imm[9:5] The round-trip DST can be expressed as: 200803526 DST - (DST & NOT(sMask)) I SDATA For example, you can use the INSERT instruction (such as INSERT $mbNeighCtxCurrent_l, #ImmlO, SRC1) to write the current giant tile. This operation will not affect the left indicator 685 and the upper indicator 683 (that is, only write the current position). The INSERT instruction can be written to the current mbNeighCtx 686. The left side indicates that the array element pointed to by 685 is the same as the adjacent (next to the current jj^NeighCtx) array element (ie mbNeighCtx[il]), when issuing the CWRITE instruction 'current mbNeighCtx structure All or some of the content will be copied to the element pointed to by the left indicator 685 and the upper indicator 683, while the upper indicator is increased by 1 (such as the modulus value of each row of giant tiles), at the same time (or after) the copy operation, with a value of 0 Clear the current mbNeighCtx array element. The data structure retained in mbNeighCtx memory 604 is as follows: mbNeighCtxCurrent[01:00] : 2?b : mbType mbNeighCtxCurrent[65:02] : 4'b : TC[16] mbNeighCtxCurrent[81:66] : 45b : TCC[cb ][4] mbNeighCtxCurrent[97:82] : 4'b : TCC[cr][4] When the CWRITE instruction is executed, the mbNeighCtx[] neighbor data is updated and the current mbNeighCtx 686 is initialized.

The content memory structure used by the CAVLC unit 530 has been described. Next, how the CAVLC unit 530 and the CAVLC-TOTC instruction calculate TotalCoeff(TC) using adjacent content information, which is used to determine which CAVLC table to use to decode symbols, is explained. Usually CAVLC solves the problem by using the variable length decoding table of the H.264 specification (hereinafter referred to as CAVLC 200803526 table), which is based on the CAVLC table within the previously decoded symbol, and therefore, each effect (four) decoded

唬 唬 匕 匕 用 用 用 用 用 用 用 用 用 用 用 用 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟= The symbols are Huffman codes, and the Huffman codes are stored in the following form structure.

Struct table { unsigned head; struct table { unsigned val; unsigned shy; }table[]; }Table[]; The following is a method of pairing (MatchVLC function) according to each preamble (prefix c〇ding), usually CAVLC table Divided into variable length part and fixed length part, so the fixed size index search can simplify the pairing'. In the MatchVLC function, the rEAD operation does not shift out the bit stream from the shift register 602a. READ operation and the READ instruction described above (for the bit stream buffer state 602b) is different, the latter is for the bit stream. In the matchVLC function, some bits (fixL) are copied from the bit stream buffer 602b, and then searched in the specified form, each item in the specified form contains a coefficient pair (dublet, such as value and number of bits), this The number of bits can be used to process the bit stream. 42 200803526

V

'FUNCTION MatchVLC(Table, maxldx) < , , INPUT Table;, ^ INPUT paaxldk;, -' '10v;: _|_l Discussion__ Discussion 1 Art Discussion and Dispute Resolution __ i discussion bell spirit: Idxl, CLZ (sREG>; //count number/.of heading zeros '; , work dxr = (Idxl > maxldx) ? maxldx : Idxl; , '' ~ , fixL;- Table[ Idxl].head; , , ' % SHL{sREG, worker dxl+#l // //shift buffer Idxl ten 1 bit left (fixL) 0 : READ(fixL) , 〆' ' , (valr shv) = Table[Idxl] [Idx2]; ' : : — s ' ^ . f ' ? ^ ; SHL(sREG, shv); - Strong; no rose and 丨: 3⁄43⁄4: ______ ______ 围 ^^ ^ ^ return; val; ...〆' _I_S: 议兹钟__ Discussion and translation of 1 clock: Let the collapse of 1 discussion 3 露 _ _ _ _ _ _ _ _ _ _ _ _ _ l_ _ _ _ _ _ _ Discussion on the fog: 1 discussion _ discussion __ cloud ENDFUNCTON ' ' ' < _ii certificate poor money Wei __ miscellaneous: ____ choice _ strong let the sixth D picture is the block diagram of the aforementioned form structure 2D array Figure, used to explain the MatchVLC function in CAVLC decoding content, this example is Table 9_5 of the H.264 specification (nC = two):

Coeff tokeri ' :人〜 ... \ / TtailingOnes $议_接铁__纤;:_谨_ TotalCoefT Head Value :, '. : :: ? Shift ; 1 1 1 0 33 0 ...V,;>; ,, '?r:'vvif f,::',,', ...人', 0: 〇[,广- let the fiber 1^_黎_·纤铁纤__ ' Ί:::', 4 001 2 2 0 66 0 , , 丄 ' ... ^ ·? , %, : 000100 0 ΙΙ^ΒΒΙΙΙΒβ , i 夕., X 鳞发发纤尔尔:,,,,,,,,,,,,,,,,,,,,,,,,,, '卿101 OS/, 〆,... ' y ,::V, Ί, _ _ 纤 遵 遂 遂 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Love art ', 、, 广,...' >>ν; '人' h,? '', ' .f ' , Ά ... 000110 2 \ : W — iiHi 缠 义 ^ ® ® ® ® ® ® ® ® ® ® ® ® ® ® ® ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ν' = ^^βββ画圆_111 面面面面___ '34' _让^^_议震ΐΜϋ_Ι^Λ_^^矿1德,, ' ' ::-Ί 乂;ν·>·: ·;::·:·:::··:, '', ' „ ' 1 000111 :: _iliiiif 颜颜 s ^ f _ 繊 鲡 鲡 鲡 鲡 议 _ _ _ _ & & & & & & & & , ' ^ ? 雠顾纤i^eilii β·^·· ::s collar lin vine green fiber 丨: 丨丨 丨丨 丨丨 矿 矿 矿 矿 矿 矿 丨丨 丨丨 丨丨 丨丨 丨丨 丨丨 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _丨 丨 丨 龄 潘 潘 激 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :, ', ', ': , , f , , 2 , : , upper : '':," ' , ^ , S , Ύ , 〇000010 0 4 1 4 1 000011 0 3 3 1 :;oooooio / :r / iw again, , , '广广':,Κ Ί: :2'^;γ; ; ,~ f , one-'v, ί ' , ν - β^·βι^β Ί,,:〆',: : lieiia^s :d :/w 61 ι . * ΊΛ,... .'-------- Mine Condensation: Condensation Drive: Window Fiber 1 rV-:: o d bribe ι; : / , heart >:UK:,: ' - : into I,? ' Ί , , 〆 , j ν ; , ν 2 , , r Γ , / · ' , : , , , , 3 ' ' , , , - ' ' , : Λ ' 八 , 囊 浅 钂 : : : : :纤ββΙίρΐΙΒ® _ιβ 薄薄1圆_诵面- <':Λ S ' , , '乂-------- βι^β 43 200803526 00000010 2 4 1 68 1 00000011 1 4 36 1 Λ , ο , r, , , ' , -0000000 ;>" 1«面_议111迟___议_to...'ν ' Θ V''v, meaning, ' ^ s , ί οο :' I a; Iron SS rhyme f • Ά Γ:: \ , , , ^ - For virtual code, this table can be expressed as:

TabIe9-5[8] - { ^ 〇,{{33,0}}, • 〇,{{〇,〇}}, 〇,{{66,0}}, 2,{{2,2},{ 99, 2}, {34, 2}, {1, 2}}, 1, {{4, 1}, {3, 1}}, 1, {{67, 1}, {35, 1}}, 1,{{68,1},{36,1}}, 〇, {{1〇〇,〇}} }; The above virtual code can be represented as a 2D form of the sixth D map, using this form structure The MatchVLC function described above can be used for cAVLC decoding. The _ MatchVLC function calculates the number of consecutive leading zeros (CLZ) from the highest bit in the bit stream to access the form corresponding to the known syntax components. In addition, when the CLZ value Greater than macldx, the MatchVLC function initiates a parameterized clear zero operation, and then maxldx replies (in the form of the sixth D diagram, 〇〇〇〇〇〇〇). Another benefit of the MatchVLC function and the form structure is that it does not require multiple instructions for processing, as long as the following MatchVLC fragments are · Idxl = CLZ(sREG); //count 44 200803526 number of leading zeros, and Idxl II (Idxl &gt ; maxldx)? maxldx : Idxl. The used bits are removed using the following MatcliVLC fragments: SHL(sREG, Idxl+#1); //shift buffer Idxl+1 bit left. Subarray headers are read using the following MatchVLC fragments: fixL = Table[Idxl].head, and Idx2 = (!fixL)? 0 : READ(fixL). The number of consecutive turns in the front may be the same, but the size of the tail bits is different. The CA SEX-type state statement can be used in a consistent example (using more memory but a simpler code structure). Use (val,shv) = Table[Idxl][Idx2] and SHL(sREG,shv) to get the real value from the form. You can also know the actual number of bits used by this syntax component, remove these bits from the bit stream, and then Put the syntax component values back into the target scratchpad. The spade has described the bitstream parsing, initializing the decoding engine and memory structure, and the VLC pairing method and form structure. Now returning to the sixth inset to describe the CAVLC decoding engine (such as CAVLC logic circuit 660) and the program, once loaded The stream, the decoding engine, the memory structure, and the scratchpad, the driver software 128 sends CAVLC - and the c command enables (10) ff toe: module 610, the CAVLC-TOTC instruction format can be: CAVLC - TOTC DSI; S1,

S1 and DST are the wheeled register and the internal output register, respectively, with the following format: W SRC1 [3:0]-blkIdx SRC1 [18:16]-blkCat SRC1 [24] - iCbCr 45 200803526 The bit is undefined and the rounding format is as follows: DST [31:16] - TrailingOnes DST[15:0] - TotalCoeff Therefore 'coeff^oken module 610 receives corresponding to mbType (indicates whether the chroma channel is being processed, such as icbcr ), and v blkWx (such as block index, because the graphics may be cut into many blocks) - when accessing a macro block of bit stream buffer 602b, blkldx indicates that the specific position is processed by 8x8 pixel area Block or 4χ4 pixel block, this kind of credit is provided by the driver. The coeff-token module 610 includes a look-up table, which is based on the lookup table of the input coeffjoken module. TrailingOnes and TotalCoeff 'The end 1 indicates how many flaws are in a column, and the total coefficient indicates how many operational/hierarchical coefficient pairs are extracted from the data stream.

TrailingOnes and TotalCoeff will be input into CAVLC-Level module 614 and CAVLC-ZL module 618, respectively. TrailingOnes also inputs CAVLC-L0 module 616, which corresponds to the _-level (such as DC) taken from bit stream buffer 602b. value). The CAVLC-level module 614 records the suffix length of the symbol (eg, the end, the number of 1), and calculates the level value (level[Idx]) stored in the hierarchical array 622 and the operational array 624 in combination with the LevelCode, the CAVLCJLevel module 614. According to the CAVLC_LVL instruction operation, the format of the CAVLC-LVL instruction is as follows: CAVLC-LVL DST, S2, S1, where = 46 200803526 51 = Idx (16-bit), 52 two suffixLength (16-bit), and DST = suffixLength (16 -bit). suffixLength indicates the character code length 'The input from the driver software 128 will provide the information of the suffixLength'. In the embodiment, since the suffixLength value is updated, DST and S2 can be obtained by the same temporary storage. . Here, you can also use the transfer register (retain the internal generated data of a specific module), such as F1 665 and F2 667 in Figure B, whether an instruction and the corresponding module use the transfer temporary H will be in the instruction. The phase transfer flag indicates that the symbol representing the transfer register has F1 (using the value of the transfer source), which can be represented by bit 26 in the instruction) and F2 (using the transfer source 2). The value, in one embodiment, can be indicated by bit 27 in the instruction. 'If using the transfer register, the CAVLC-LVL instruction will have the following instantiation format: CAVLC-LVL.F 1 .F2 DST, SRC2, SR1, Wherein, if F1 or F2 is set to 1, the specified forwarding source will be the input, and the forwarding register F1 corresponds to the hierarchical index (level[Idx]) generated by the CAVLCJLevel module 614, after an increment (increment) After the module is input to the multiplexer 630, the transfer register F2 corresponds to the suffixLength generated by the CAVLCJLevel module 614, and the input multiplexer 628, the multiplexer 603 and the other inputs of the multiplexer 628 are also EU. The register input (labeled EU in Figure 6A) is explained below. The CAVLCJLevel module 614 has another input levelCode, which is 47 200803526. It is provided by the CAVLC-LevelCode module 612. The CAVLCJLevelCode module 612 and the CAVLC_Level module 614 jointly calculate the decoding level value (the transform coefficient before scaling). The transform coefficient)), the instruction format of the CAVLC-LevelCode module 612 is as follows:

CAVLC LC SRCL — j where SRC1 = suffixLength (16-bit), if the transfer register F1 is used, the instruction is as follows: CAVLC - LVL.Fl SRC1, if F1 is set, then transfer SRC1 will be used as input In conjunction with Figure 6A, if F1 is set (eg, FI = 1), the CAVLC-LevelCode module 612 uses the SRC1 value (such as the suffixLength of the CAVLC-Level module 614) as input, otherwise (eg pi = 〇 ), the value of the EU register will be used as input. Returning now to the CAVLCJLevel module 614, the suffixLength input can be forwarded from the CAVLCJLevel module 614 via the multiplexer 628, or can be provided to the multiplexer 628 via the EU register, and the Idx input can also be transferred from the CAVLC_Level via the multiplexer 630. The delivery (which can be incremental or automatic increment by the incremental module) can also be provided to the multiplexer 630 via the EU register. The CAVLCJLevel module 614 also receives the levelCode input directly from the CAVLCJLevelCode module 612. In addition to the output passed to the transfer register, the CAVLCJLevel module 614 also provides a hierarchical index (level[idx]) output to the hierarchical array 622. As previously mentioned, the TrailingOnes output (eg, DC value) is transmitted to the 48 200803526 CAVLC-LO module 616, which is enabled by the following command: CAVLC LVLO SRC, where SRC = trailingOnes (coeff token), the output of the CAVLC-L〇 module 616 includes a hierarchical index (Level[Idx]) output to the hierarchical array 622, the coefficient values are encoded into a sign and a magnitude, and the CAVLC-L0 mode The group 616 provides the positive and negative values of the coefficients. The size value provided by the CAVC-Level module 614 is combined with the positive and negative values provided by the cVLC_L0 module 6 and is written to the hierarchical array 622, and the write position is specified by the level index (level[idx]). In an embodiment, each sub-block of the coefficient is a 4x4 matrix (the block is 8x8), not a raster sequence, which is later converted into a 4x4 matrix, in other words, the decoded coefficient level and The operation is not a scan format. Using the hierarchical-operational data, a 4x4 matrix can be reconstructed (but in a z-scan order) and then rearranged into a 4 X 4 matrix of scan order. The output TotalCoeff of the coeff_token module 610 is transmitted to the CAVLC-ZL module 618, and the CAVLC-ZL module 618 is enabled by the following command: , CAVLC-ZL DST, SRC1, where SRC1 = maxNumCoeff (16-bit) While DST = ZerosLeft (16-bit), maxNumC〇eff (H.264 standard) is used as the source value of the instruction. In other words, maxNumCoeff is set by the software. In some embodiments, maxNumCoeff is stored in the hardware. The transform coefficients are encoded into (level, operational) coefficient pairs representing the number of coefficients (hierarchy) encoded into 〇, and the CAVLC-ZL module 618 provides two outputs ZerosLeft and Reset (reset 49 200803526 =0) to the multiplexer 640 and The multiplexer 64 also receives the transfer register F2 from the CAVLC-Run module 620, and the multiplexer 642 receives the incremental (via the incremental module) transfer register from the CAVLC=Run module 620. The value ρι. The CAVLC-Run module 620 receives the ZerosLeft and Idx inputs from the multiplexers 64A and 642, respectively, and outputs the operational index (Run[IdxD to the operational array 624, as previously described, as the operation_length coding is used for further processing). Compact, so the coefficients are coded into (level, operational) pairs, for example, assuming a value of 10 12 12 15 19 1 1 1 〇〇〇〇〇〇1 〇, which is encoded as (10,0) (11^5 , 0)(19,0)(12)(0))(10)^ Usually shorter, the index is the corresponding index of the hierarchical index, and the CAVLCJRom module 620 is enabled by the following instructions: CAVLC-RUN DST, S2, S1, where, since the ZerosLeft value has been updated, DST and S2 can be obtained from the same register. The unsigned value of CVLC-Rim is as follows: 51 = Idx( 16-bit), 52 = ZerosLeft(16-bitX DST = Zerosleft( 16-bit) As shown in Figure 6A, if the transfer register is used, the format of the cavlc_run instruction is as follows: CAVLC.F1.F2 DST, SRC2, SRC1, where if F1 or F2 is set, it means The source of the transfer will be used as input. As for the two register arrays, the hierarchical array 622 corresponds to the hierarchy and operates. Column 624 corresponds to operation, each array includes 16 elements, 50 200803526 Each element of hierarchical array 622 contains a 16-bit signed value, and each element of operational array 624 contains 4 bits that are not positive or negative. The value of the number uses the following instructions to take the operation and level values from the operational array 624 and the hierarchical array: # READ—LRUN DST, where 'in the embodiment, the DST includes four 128-bit continuous registers ( Such as EU temporary or shared register), this operation will read (: gossip unit 530 in the level register 622 and the operation register 624, and store it in the target register DST, when reading Take the operation and store it in the scratchpad, the operation value will be converted into a 16-bit non-signal value. For example, 萷2 temporary storage is reserved for 16 16-bit levels (that is, the array is stored first). The pen has 16 coefficients), while the third and fourth registers retain 16 16-bit operational values. If more than 16 coefficients are exceeded, they are decoded into memory. In one embodiment, the values are in the following order. Write: In the first scratchpad, the least significant 16-bit contains LEVEL[0], bits 16-31 contain LEVa(1), etc., and so on until bits 112-127 contain LEVEL[7]; the least significant 16 bits in the second register contain !^\^1^[ 8] ~, the operating value also uses the same arrangement method. The other instruction format for clearing the operational array 624 and the hierarchical array 624 register is as follows: CLR-LRUN· The software (coloring crying program) of the aforementioned decoding system 200 (such as CAVLC unit 530) and hardware operations (such as modules) ) can be represented by the following virtual code: 51 200803526

Residnal_blQck_cavlc( coefi^evel, maxNumCoeff) {

CLR—LEVEL-RUN ' , , ____ :Λ} : ;- : : -:.v · ^ if( TotalCoeff( coeffJoken ) > 10. && TrailingOnes( coeff token) < 3 ) if(TotalC0eff( coeffJoken)>0) { suffixLength = 1

Else :sufBxLength.- 0 CAVLC_levelO〇; for( I = TrailingOnes(coeff_taken); I < TotalCoeflF( coeff token ); iH-){ CAVLC-leveldode (levelCode, suffi芩Lehgth); CAVLC-level “suffixLength, i, levelCode)

CAVLC 二ZerosLeft {ZerosLeft, maxNtimCoeff) for(i =,0;i<TotalCoeff( coeff_token) - 1; i-Η-) { \ CAVLC—run(i, ZerosLeft> READ-LEVEL-RUN (level, run) fun [ TotalC6cfF( coeff_token ) — 1 ] = zerosLeft Λ coeffNum._ for( i = TotalCoeff( coeff_token ) - 1; i >= 〇; i— ), { coeffNum += run[ i ] + 1 coeffLevel[ coefiNum ] = Leveli i ]

It should be emphasized that the above-described embodiments or "preferred" embodiments of the present invention are only intended to be illustrative, and are merely illustrative of the principles of the invention. The spirit and system of the systems and methods described herein are not excluded from the scope of this case and are covered by the scope of the patent application. 52 200803526 [Simplified description of the drawings] The implementation of the present disclosure is based on the following stipulations. The elements in the drawings do not limit the size ratio; the principles of the present invention are shown in the drawings. Phase =; Figure 1: Block diagram of an embodiment of a graphics processor system, embodiment of a decoding system (and method). She exemplifies the processing environment _, in which a variety of decoding systems can be implemented. The third figure: The second figure illustrates a block diagram of selected components in the processing environment. Fourth: The second and third figures illustrate computational core diagrams within a processing environment in which various decoding system embodiments can be implemented. a 选择 中 中 中 中 中 中 转 转 转 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择The fifth diagram: the block of the unit dragon path is implemented, and the towel can implement various decoding system embodiments. , Six Diagrams: The block diagram of the solution shown in the fifth figure. Figure 6B: Block diagram of a bit buffer embodiment of the decoding system of the sixth A. The content memory structure of the / / C picture / / / A picture decoding system is matched with the block diagram of the associated register embodiment. The block diagram of the form structure used by the decoding system used by the CAVLC decoding decoding system. 53 200803526 [Description of main component symbols] The components included in the diagram of this case are listed as follows:

施 仃 仃 early 70 set control and vertices / stream fast 208 contact map total 兀 early 曰, 曰 EU,, spring 302 texture filter unit

100 graphics processor system 104 display interface unit 110 memory interface unit 118 bus interface unit 124 system memory 128 driver software 202 graphics processor 304 pixel packaging component 308 writeback unit 402 execution unit input 406 memory access unit 41 Memory interface arbiter 102 display device 106 region memory 114 graphics processing unit 122 chipset 126 central processing unit 2 decoding system 204 computing core 306 command stream processor 310 texture address generator 404 execution unit output 408 L2 cache Memory 412 execution unit set 413 connection 420 execution unit 504 instruction cache memory controller 506 thread controller 508 buffer 510 shared register file 512 execution unit data path 514 execution unit data path FIFO buffer 54 200803526

516 description section register file 520 data rotation controller 526 register file 530 CAVLC unit 534 vector integer arithmetic logic unit 536 special purpose unit 538 multiplexer called register file * 542 operation signal line 544 current signal line 602夕 位 暂 _ _ stream buffer / direct memory access engine 604 giant block adjacent content memory 606 total register 608 area register 61 〇 coefficient register module 612 level code module 518 scalar register file 524 thread task interface 528 multiplexer 532 vector floating point unit 614 level module 618 zero level module 622 level array 626, 628, 630, 640 616 level 〇 module 620 operation module 624 Operating array 642 multiplexer

660 CAVLC logic circuit 665, 667 transfer register 683 upper indicator 685 left indicator 687 current indicator 661, 663 operand register 681 array element 684 left mbNeighCtx 686 current mbNeighCtx 658 feedback wiring 55

Claims (1)

200803526 X. Patent application scope: 1. A decoding system, which includes: a variable of a shader, a software programmable core processing unit, and a content-adaptive length C coding. a CAVLC) unit that performs CAVLC decoding of a video stream and provides a decoded data output. Among them, the CAV L C solution is implemented by means of a hard pulse recording. 2. The system of claim 1, wherein the cavlc decoding is performed by the hardware programmed in the graphics processing unit with the content of the graphics processing unit. 3. The system of claim 1, wherein the cAVLc unit further comprises a coefficient register (coeff__t〇ken) module for receiving the macro block information 'the first instruction according to one of the shaders ( CAVLC_TOTC) provides end 1 information and overall coefficient information. 4. The system of claim 3, wherein the CAVLC unit further comprises a level (CAVLC_Level) module for receiving the tail 1 information and the level code information, and the second instruction of the shader (CAVLC-LVL), providing suffix length information and level index (Level[Idx]) information. 56. The system of claim 4, wherein the CAVLC unit further comprises a level code (CAVLC-LevelCode) module for receiving the length information of the suffix, which is one of the shaders. The instruction (CAVLC_LC) provides the hierarchical code information to the hierarchical module. 6. The system of claim 5, wherein the hierarchical code module receives the suffix length information from a transfer register or an execution unit register. 7. The system of claim 5, wherein the hierarchical code module receives the suffix length information and the hierarchical index information from a transfer register or an execution unit register, the hierarchical index information It is incremental. 8. The system of claim 4, wherein the CAVLC includes a level 〇 (CAVLC-L0) module for receiving the tail end 1 The four instructions (CAVLCJLVL0) provide a second level index (Level[Idx]) information to the hierarchical array. 9. The system of claim 8, wherein the CAVLC unit further comprises a zero-level (CAVLC-ZL) module for receiving the coefficient of the whole coefficient and a maximum number of coefficients, which should be colored. One of the fifth commands (CAVLC-ZL) provides a left-side information and a reset value to the first multiplexer and the second multiplexer. The system of claim 9, wherein the CAVLC unit further comprises a CAVLCJRun module for receiving the left from the first multiplexer and the second multiplexer The side 0 information and the second index information, in response to one of the shader sixth instructions (CAVLC_RUN), provide a working index (Rini[Idx]) to the -^ operation array. The system of claim 1, wherein the first multiplexer and the second multiplexer receive the left side information from the first transfer register and the second transfer register respectively And the second index information. 12. The system of claim 10, wherein the hierarchical array and the operational array provide a decoding level value and a decoding operation value according to a seventh instruction (REad_lrun) of the shader, and corresponding to the shader One of the eighth instructions (CLRJLRUN) is cleared. 13. The system of claim 1, wherein the CAVLC uses a bit within an instruction to determine whether a previous operation result stored in an internal register is available, or is in a source operand. Whether the data can be used by one or more modules in the current calculation. 14. The system of claim 1, wherein the CAVLC unit is further a <direct 5 direct memory access (DMA) access group comprising a one-bit stream buffer And a DMA engine module that performs a one-finger 58 200803526 for each slice in response to the shader, automatically repeating the predetermined number of bits when a predetermined number of bits within the bit stream have been used The element corresponds to the video stream. 15. The system of claim 14, wherein the CAVLC unit delays the DMA engine module due to the possibility of a downward overflow in the bit stream buffer. 16. The system of claim 14, wherein the DMA engine module is configured to record the number of used bits in the bit stream buffer, and the number of the bits is greater than one. The predetermined value, the bit stream buffer operation is suspended, and control is transferred to a host processor. 17. A decoding method comprising the steps of: loading a shader into a programmable core processing unit having a CAVLC unit; executing the shader on the CAVLC unit to decode a ® video stream with CAVLC; • Provide a decoded data output. 18. The method of claim 17, wherein the CAVLC decoding is performed by hardware programmed in a graphics processing unit in conjunction with hardware programmed in a graphics processing unit data path. 19. The method of claim 17, further comprising the step of: 59 200803526 one of the CAVLC units is a coeff "oken" module that receives the macro block information; (CAVLC-TOTC), providing tail end 1 information and overall coefficient information; the CAVLC-level module (CAVLC-Level) module receives the tail end 1 information and the level code information; CAVLC-LVL), providing suffix length information and level index (Level[Idx]) information; the CAVLCJLevelCode module of the CAVLC unit receives the suffix length information; and the third instruction of one of the shaders (CAVLC JLC), providing the level code shoulder to the level module. The method of claim 19, wherein the hierarchical code module receives the suffix length information and the hierarchical index information from a transfer register or an execution unit register, the hierarchical index information It is incremental. 21. The method of claim 19, further comprising the step of: the CAVLC unit one level 0 (CAVLC-L0) module receiving the tail end 1 information; and the fourth instruction of the shader (CAVLC-LVL0) provides second level index information (Level[Idx]) to a hierarchical array. 22. The method of claim 21, further comprising the steps of: 200803526 One of the CAVLC modules of the zero level (CAVLC_ZL) module receives the total coefficient information and a maximum number of coefficients information; The fifth instruction (cAVLC_ZL) provides a left side 0 information and a reset value to the first multiplexer and the second multiplexer; one of the CAVLC unit operation (CAVLc_Run) modules respectively from the first multiplexer And the second multiplexer receives the left side information and the second index information; and provides a running index (Run[Idx]) to an operational array according to one of the shader sixth instructions (CAVLC_RUN). The method of claim 22, wherein the first multiplexer and the second multiplexer receive the left side from the first transfer register and the second transfer temporary storage, respectively. Information and the second index. The method of claim 22, wherein the hierarchical array and the operational array provide a decoding level value and a decoding operational value in response to a seventh instruction (READ_LRUN) of the shader. The method of claim 22, wherein the hierarchical array and the operational array are emptied by an eighth instruction (CLRJLRUN) of the shader. 26. The method of claim 17, further comprising the step of: the CAVLC unit using a bit within an instruction to determine whether a previous operation result stored in a portion of the 2008 20082626 register is available, or Whether the data in a source operand can be used by one or more modules in the current operation. 27. The method of claim 17, further comprising the step of: in response to the shader executing one of the instructions for each slice, automatically repeating the fill when a predetermined number of bits within the bitstream have been used The predetermined number of bits are entered, the bit corresponding to the video stream. 10 28. The method of claim 27, further comprising the step of: delaying the use of the bit in the bitstream buffer due to the possibility of a downflow in the bitstream buffer. 29. The method of claim 27, further comprising the steps of: recording the number of used bits in the bit stream buffer, and suspending the number of bits in the bit stream buffer based on detecting that the number of bits is greater than a predetermined value The bit stream buffer operates and transfers control to a host processor. 62