TW200821982A - Decoding method - Google Patents

Abstract

Various embodiments of decoding systems and methods are disclosed. One method embodiment, among others, comprises providing a shader configurable with a plurality of instruction sets to decode a video stream coded a plurality of different coding methods, loading the shader having one of the plurality of instruction sets to a variable length decoding (VLD) unit of a software programmable core processing unit for execution thereof, and decoding the video stream by executing the shader on the VLD unit.

Description

200821982 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to data processing systems, and more particularly to programmable graphics, shape processing systems, and methods. Ϊ ΓPrevious Technology 黾 黾 开 》 is a technique for generating images, images or other graphics or images with computer. Currently, many graphics systems are implemented through the use of interfaces, such as Microsoft's Direct3D interface, 〇penGL, etc., which can be used for multimedia hardware on computers running specific operating systems (eg Microsoft Windows systems) (eg : Graphics accelerators or graphics processing units (Gpu) provide control. The generation of images or images is generally referred to as rendering (rencjering), and the details of the above operations are mainly implemented by graphics accelerators. In a three-dimensional (3D) computer graphic, the surface (or volume) of an object in the scene (the represented geometry is converted into pixels (image elements) and stored in a frame buffer) It is then displayed on the display device. Each object or group of objects has specific visual properties related to the appearance of the surface (eg, material, reflection coefficient, shape, texture, etc.), which can be defined as objects or groups of objects. Rendering context 〇 computer graphics to increase consumer demand for games and other multimedia products Regulatory requirements and characteristics, generate more realistic images and improve processing speed and power consumption. Has developed a number of criteria, you can use fewer bits

Client’s Docket No·: S3U06-0014-TW TT,s Docket No:0608-A41247twf.doc/NikeyChen 5 200821982

Almost one-third of the z codecs, H.264-compatible codecs use only the number of bits used to encode | See the frequency and maintain a similar video product H.264 specification ^ for two types of entropy ( Encoding processing, including intra-adaptive arithmetic coding (CABAC) and content-adaptive variable length coding (CAVLC). In order to meet these continuous changes, many different pure software or pure hardware solutions have been proposed. However, known techniques result in higher inventory, immediate elimination techniques, and lack of flexibility in design. SUMMARY OF THE INVENTION The present invention discloses a multi-execution parallel calculation for a graphics processing unit.

One of the variable length decoding units, and the above solution Client's Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen includes: by executing _shader decoding embedded in a programmable The core processing list, as well as the above decoding system, is based on the complex number not 2008 21982 • the same encoding method, and provides a decoded data output. The above and other objects, features, and advantages of the present invention will become more apparent from the description of the preferred embodiments of the invention. The present invention discloses many embodiments of decoding systems and methods (wherein the above systems and methods will be collectively referred to as decoding systems). In one embodiment, the decoding system is embedded in one or more execution units of a graphics pr〇cessing unit (GPU), a multithread, and a parallel computation core. Use a combination of software or hardware to implement the decoding function. That is, video decoding is performed in the context of the programming of the graphics processing unit and the hardware implementation in the data path of the graphics processing unit. For example, in one embodiment, the decoding algorithm or method is performed by a shader having an extended instruction set (eg, a vertex shader), an execution unit data path of the graphics processing unit, and Additional hardware for automatic management of the bit stream buffer is implemented. Compared to existing systems, existing systems are solutions that deal with pure hardware or pure software, and therefore encounter some of the problems mentioned in the prior art. In the decoding system described herein, an encoding action of information decoding using complex entropy encoding techniques can be implemented. The decoding system can be based on the well-known international telecommunication alliance communication standard department (international telecommunication)

Client's Docket No·: S3U06-0014-Ding W TT's Docket No:0608-A41247twf.doc/NikeyChen η 200821982 union telecommunication standardization sector 9 ITU-T) CABAC and CAVLC for H.264 standard decoding, also according to MPEG-2 And the VC-1 standard for decoding. Different decoding system embodiments operate according to one of the complex modes, wherein each mode corresponds to one of the previously described standards and is executed: one or more slave graphics processing unit frames! Buffer memory or corresponding to The set of instructions received by the host processor's memory (eg, the central processing unit (CPU)) (eg, via known mechanisms such as preload or cache failure). The hardware can be reused to provide multiple types of decoding standards (ie, depending on the mode selected). Furthermore, the mode selected will also affect the way in which the content memory is initialized, used, and/or updated. Depending on the mode of decoding of the decoding, the decoding system may use, for example, Exp-Golomb encoding, encoding like Huffman (eg, CAVLV, MPEG-2, and VC-1) and/or arithmetic encoding (eg, CABAC). The entropy decoding method is performed by extending the instruction set corresponding to one or more execution units, and providing an additional hardware that automatically manages the bit stream to perform the content model in CAVLV decoding and CABAC decoding. In one embodiment, the entropy encoding table uses a different memory table or other data structure (e.g., a read only memory (R〇M) table). In addition, the automatic bit stream buffer has some advantages, for example, once the bit memory buffer's direct memory access (DMA) engine knows the location (address) of the bit stream, it automatically Manage the bit stream without further instructions. Compared to traditional microprocessor/digital signal processor (DSP) systems, bitstreams

Client's Docket No.: S3U06-0014-TW TT^ Docket No:0608-A41247twf.doc/NikeyChen 8 200821982 • 7 represents a large number of 'meta-quantity, bit stream buffer fee ^ again' used by tracking Bits of the present invention are decoding systems;, ::: Handling error bitstreams. (latency) ^ ^ Continuous action and not easy to use multi-execution order processing = AC decoding is very t-use-type forwarding: (fQm: so different, the embodiment is less effective depending on the ng) branches (such as temporary forwarding) Subtraction and multi-execution processing crying! / 夕冰5线 (deep-_eline) Let the instructions execute every cycle. There is a stealing order (fine ad) by checking the previous results of the transport (.,, ° like forwarding "the system of the meta-address, when the two are the same when the job = ^ = with the f command operation, the general forwarding Requires complex comparisons, etc., in the embodiment, whether it is two or two; in the part of the decoding system (four) or the result (for example, stored in the internal ^, will use different forwarding type 3 instructions to encode her For example: a total of 2 bits and each: H. In this way, the overall delay can be reduced to improve the efficiency of the processing pipeline. =1 ® shows the graphics processing system] (10) - the embodiment The embodiment of the M1 system and method is implemented in a graphics processing system. In some embodiments, the graphics processing system 100 can be a computer system. The graphics processor system touch 1 includes a display interface unit (DLsplay interface unit, DIU) 104-driven display device loading and local memory 106 (eg, may include display buffers, frame buffers, texture buffers, command buffers, etc.). Local memory 1〇6 may also be replaced by a map.

Clienfs Docket No.: S3U06-0014-TW TT s Docket No: 0608-A41247twf.doc/NikeyChen 200821982 • Frame buffer or storage unit. The local memory 106 is coupled to the graphics processing unit 114 via one or more memory interface units (MIUs) 110. In one embodiment, the memory interface unit 110, the graphics processing unit 114, and the display interface unit 〇4 are all coupled to a bus interface that is compatible with a high-speed peripheral component (t PCI-E). Unit (buS interface: unit, BIU) 118. In an embodiment, bus interface interface unit 118 may use a graphics address remapping table (GART), although other memory mapping mechanisms may be used. Graphics processing unit 114 includes a decoding system 200, which will be described later. In some embodiments 'although the decoding system 2 is shown as a component within the graphics processing unit 114' the decoding system 200 may also include one or more additional components or different components of the graphics processing system 1 shown. . The bus interface unit 118 is coupled to the chip set 122 (e.g., Northbridge wafer set) or a switch. Wafer set 122 includes interface electronic circuitry to enhance signals from central processing unit 126 (also referred to as a host processor) and to separate signals coming in and out of system memory 124 and from input and output (1/0) devices (not shown). signal. Although a PCI_E bus protocol is mentioned, in some embodiments other connections and/or communication methods may be used between the host processor and graphics processing unit 114, such as PCI, dedicated high speed bus, and the like. The memory 124 also includes a driver software 128 that can communicate the instruction set or commands to the scratchpad within the graphics processing unit 114 using the central processing soap unit 126. In some embodiments, additional graphics may be used through the wafer set 122.

Client's Docket No.: S3U06-0014-TW TT, s Docket No: 0608-A41247twf.doc/NikeyClien 200821982 / The processing unit is coupled to the elements in Figure 1 via a PCI-Ε bus bar protocol. In one embodiment, graphics processing unit 100 may include all of the elements shown in Figure i or fewer components and/or components other than those shown in Figure 1. Moreover, in some embodiments, additional components may be used, such as a south bridge wafer set coupled to the wafer set 122.

I Referring to Fig. 2, Fig. 2 is a block diagram showing the processing environment for implementing decoding: one of the embodiments of the system. In particular, graphics processing unit 114 includes graphics processor 202. Graphics processor 202 includes a multiple execution unit (EU) and computing core 204 (also known as a software programmable core processing unit). In an embodiment, the computing core 2〇4 includes a decoding system 200 (also referred to as a VLD unit) that is internal to the execution unit data path (EUDP), wherein the execution unit data path is assigned to One or more execution units. The graphics processor 202 also includes an execution unit set (eUP) control, a vertex/stream stream cache unit 206 (referred to herein as an execution unit set control unit 2〇6), and a fixed function logic unit (eg, including A graphics pipeline 208 of a triangle set-up unit (TSU), a grid-tile generator (STG), etc., which will be described later. The computing core 204 includes a collection of multiple execution units to meet the computational requirements of the coloring task of different shader programs, including shader shaders, geometry shaders, and/or pixel shader processing graphics pipeline 208. In one embodiment, the description of the graphics processor embodiment will be described when the shader performs the functions of the decoding system 200 through the computing core 2, and a particular embodiment of the decoding system 200 is illustrated.

Client's Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 11 200821982 The decoding system 200 can be implemented in the form of hardware, software, firmware, or a combination thereof. In the preferred embodiment, decoding system 200 is implemented in hardware and software, including any of the following techniques or combinations of techniques: discrete logic writes with logic gates and logic functions on data signals, An application specific integrated circuit (ASIC) with a suitable combination of logic gates, a programmable gate array (PGA), and a field programmable gate array (field programmable gate array) FPGA) and state machine. Referring to Figures 3 and 4, which are block diagrams of selected elements in an embodiment of graphics processor 202, respectively. As previously mentioned, an embodiment of the decoding system 2 can be a colorizer within the graphics processor 202 having an extended instruction set and additional hardware components, an embodiment of the graphics processor 202 and corresponding processing will be described in Rear. Although Figures 3 and 4 do not show all of the components of the graphics process, the components shown in Figures 3 and 4 are sufficient for those skilled in the art to understand the functionality and architecture of the associated graphics processor. Referring to Figure 3, the center of the programmable processing environment is computing core 204, which includes decoding system 200 and can process various instructions. Different types of shader programs can be executed or mapped to the computational core 204, such as vertex, geometry, and pixel shader programs. The computational core 204 of the multi-issue processor can process multiple instructions in a single clock cycle. Referring to Figure 3, the relevant elements of graphics processor 202 include computation core 204, texture filtering unit 302, pixel packer 304, command stream processor 306, write back unit 308, and texture address generation.

Client's Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 12 200821982 Generator 310. Figure 3 also includes an execution unit set control unit 206, wherein the execution unit set control unit 206 also includes vertex cache memory and/or stream cache memory. For example, as shown in FIG. 3, texture filtering unit 302 provides texel data to computing core 204 (input A and input B). In some embodiments, the texel data is 512 bit data. : Pixel wrapper 304 provides pixel shading input to computing core 204 (input C and input D), and the pixel shading input is also in 512-bit data format. In addition, the pixel wrapper 304 requests the execution unit collection control unit 206 for the pixel shading task, and the execution unit collection control unit 206 provides the specified execution unit number and thread number to the pixel wrapper 304. Pixel wrapper 304 and texture filtering unit 302 are known techniques and will therefore not be further described herein. Although the pixel and texel packet shown in FIG. 3 is a 512-bit data packet, the size of the packet can be changed in some embodiments depending on the desired performance characteristics of the graphics processor 202. Command stream processor 306 provides a triangle vertex index to execution unit set control unit 206. In the embodiment of Fig. 3, the index is 256 bits of data. The execution unit set control unit 206 combines the vertex shaded inputs from the stream cache memory and transmits the data to the compute core 204 (input E). Execution unit set control unit 206 also combines the geometric shading inputs and passes them to computing core 204 (input F). Execution unit set control unit 206 also controls execution unit input 402 and execution unit output 404 (Fig. 4). In other words, execution unit set control unit 206 controls each input stream and each output stream to computing core 204.

Client's Docket No.. S3U06-0014-TW TT^ Docket No: 0608-A41247twf.doc/NikeyChen 200821982 / I After processing, the calculation core 204 provides pixel shading output (transmission and output u) to the write back unit 3Q8. Pixel coloring rounds include color gamma, such as red/green/blue/transparency (RGBA) information, which is well known to those skilled in the art. The pixel shaded output can be two 512-bit data streams. Other embodiments may use other bit widths as well. Similar to the pixel shaded output, the compute core 204 also outputs texture coordinates (output K1 and output K2) including UVRQ information to the texture address generator 310. The texture address generator 31 sends a texture description symbol request to the L2 cache memory 4〇8 (input χ) of the calculation core 204, and the L2 cache memory 4〇8 (output w) of the calculation core 204 outputs the texture. The symbolic material is described to the texture address generator 310. Texture address generator 310 and write back unit 308 are known techniques and will therefore not be further described herein. Furthermore, although URVQ and RGBA are data shown as 512 bits, this parameter may also vary with different embodiments. In the third embodiment, the bus is divided into two 512-bit channels, each of which holds a four-pixel 128-bit RGBA color value and a 128-bit UVRQ texture coordinate. Graphics pipeline 208 includes graphics processing functions for fixed functions. In response to a command from the driver software 128, such as drawing a triangle, the vertex information is passed through a vertex shader logic unit within the compute core 204 to perform a vertex transformation. In particular, the object is transformed from the object space into a triangle of workspace and/or screen space. The triangle passes through the calculation of the core 204 to the triangle setting unit of the graphics pipeline 208, where the graphics pipeline 208 incorporates primitives and also performs known tasks such as bounding box generation, culling, edge functions. Edge function generation

Client's Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 14 200821982 . and triangle level rejection. The triangle setting unit passes the data to the grid and tile generating unit having the tile generating function in the graphics pipeline 208. Thus, the physical object is segmented into tiles (eg, 8 x 8, 16x16, etc.) and passed to other fixed functional units to perform depth (eg, z-value) processing, such as high-order z-values (eg, in similar Cheng » ! The order of the higher-order bits used in the higher order is less than the lower order. The z-value is then passed back to the pixel shaded logic element of compute core 204 as a function of the pixel shader function based on the received texture and pipeline data. The calculation core 204 outputs the processed values to the destination unit located within the graphics pipeline 208. The destination unit is used to perform the alpha test and the template test before the different cache memories need to update the internal values. It should be noted that there is also a 512-bit vertex cache memory overflow data transfer between the L2 cache memory 408 of the compute core 204 and the execution unit set control unit 206. In addition, two 512-bit vertex cache memory write data (output mi and output M2) are output from the calculation core 204 to the execution unit set control unit 206 for further processing. Referring to Figure 4, Figure 4 shows additional components of computing core 204 and associated components. The computing core 204 includes a set of execution units 412. In one embodiment, the set of execution units 412 includes one or more execution units 420a-420h (collectively referred to as execution units 420). Each execution unit 420 can process multiple instructions within one clock cycle. Thus, execution unit set 412 can process multiple threads simultaneously or substantially simultaneously at the peak. Although Figure 4 shows eight execution units 420 (labeled EU0-EU7), it can be understood that it is not intended to limit the number of execution units to 8, in the

Clients Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 15 200821982 The number of execution units can be increased or decreased in the mouth & At least one lamp unit (e.g., execution unit 4, EU〇) contains the implementation of the decoding system: column, which will be described later. The metering core '204/ also includes a memory access unit (memory access umt' MjOJ) 406' in which the memory access unit 4〇6 is connected to the L2 cache memory via the memory interface arbitration port 410_. L2 cache memory 4〇i from the execution unit #合控制 unit 2G6(4) job memory overflow material (input G) 'and provide vertex cache memory overflow data (output H) ^ execution unit collection control unit 206. In addition, the L2 cache memory address generator 310 receives the texture description symbol request (the request received by the input I ride provides the texture description symbol data (output w) to the texture address generator 31. The arbiter 410 The control video interface y is provided for the local video memory such as: face buffer or local memory 豸ι〇6). The bus interface interface provides 118 interfaces to the green as the Ρα_Ε bus. The memorizing body and the bus interface unit m provide an interface between the memory and the memory 408. In some embodiments, a cache memory 408 is accessed from the L2 cache memory and other memory via the memory access unit, the arbiter 410, and the bus interface unit. The unit address is converted to the actual memory address. & block virtual memory bit memory interface arbitrator ticker and cache memory 4, JI (such as read / write access), command / constant / Ziwei = fetch, direct Zfe body access (eg load/store), index of temporary access,

Client's Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 16 200821982 Temporary stolen overflow and vertex cache memory content overflow. The calculation kernel? 2〇4 $ includes the execution unit rounding and the execution unit =404' sub is used to provide input to the execution unit set and the execution unit set 412, respectively. The execution unit inputs 4〇2 to make 404 early. It can be a crossbar (_plus or other sinks) or other known input and output architectures.: Should!^ Unit input and receive from the execution unit The control unit is combined with two points* color input (input E) and several (four) color inputs (input F), and the execution unit set 412 is used by each execution unit to perform c: dry two' execution unit input 4. 2 receive pixel coloring input ( Input C and input D) and texel packets (input some packets are sent to the execution unit set 412 _ ; ^ processing. Furthermore, the execution unit input ^ ^ 订 early 420 for information (1) sell), and when needed The memory sample receives the set of elements 412. The alpha bingo is supplied to the execution unit. In the embodiment of Fig. 4, the single output 4〇4a and the odd output are performed. The similar rounds are assigned to the even unit output. 404 can be a crossbar switch: early 7L input 402, implementation architecture. Execution unit even output 404a processing even Bo: port or other known 420e and 420g output, and execute single early, 42~, row unit Only, side, only and 42 (J round out 4_ Processing odd output 404a and execution unit odd output 4〇4] Fortunately, the output of the even-line unit set 412, such as: UvRn, simultaneous reception from χ and RGBA 〇 this output can also be returned To the L2 cache memory 408, wash B-4 from the computing core 204

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 17 200821982 Output from output J1 and output J2 to writeback unit 308, or output to texture address via output K1 and output K2 The device 310. The execution unit flow of execution unit set 412 typically includes a plurality of levels including: depicting a content level, a thread or task level, and an instruction or execution level. At any point in time, each execution unit 420 may permit two «j depictions: content, wherein the content is identified by using a one-bit flag or other mechanism. The content information is delivered from the execution unit collection control unit 206 before the task belonging to this content starts. Content level information can include shader types, number of input/output registers, instruction start addresses, output maps, vertex identifiers, and constants in individual constant buffers. Each execution unit 420 of the execution unit set 412 can simultaneously store multiple tasks or threads (e.g., 32 threads in some embodiments). In one embodiment, each thread fetches instructions based on a program counter. Execution unit set control unit 206 may serve as a general schedule for tasks and assign appropriate threads within execution unit 420 using data-driven methods (e.g., vertices, pixels, and geometry packets within the input). For example, execution unit set control unit 206 assigns a thread to an empty thread slot within each execution unit 420 of execution unit set 412. When the thread is started, the data provided by the vertex cache memory, other components, or modules (depending on the shader type) will be placed in the general scratchpad buffer. Typically, graphics processor 202 uses programmable vertex, geometry, and pixel buffers. These components are not implemented as functions or operations of these components as individual fixed functional units having different designs and instruction sets.

Client's Docket No.: S3U06-0014-TW TT's Docket No: 0608-A41247twf.doc/NikeyChen 18 200821982. These operations are performed by a set of execution units 420a, 420b., .420n having a unified instruction set. Except for execution unit 420a (which includes decoding system 200, thus having additional functionality), each execution unit 420 is identically designed and used for programming operations. In an embodiment, each execution unit 420 can perform multiple thread operations simultaneously. When the vertex shader, geometry shader » t, and pixel shader produce different coloring tasks, these coloring tasks are passed to the individual execution unit 420 for execution. In an embodiment using a vertex shader, the decoding system 200 can be implemented with partial modifications P and/or differences from other execution units 420. For example, the difference between an execution unit (e.g., execution unit 420a) that includes decoding system 200 and other execution units (e.g., execution unit 420b) is that execution unit 420a uses a decoding system 200. The other execution units differ from the execution unit 420a in the arrangement of the decoding system 200 in one or more corresponding internal buffers. The data of decoding system 200 is received from memory access unit 406 via connection 413 and execution unit input 402. When an individual task is generated, the execution unit set control unit 206 will refer to these tasks to the threads available in the different execution units 420. When the task is completed, the execution unit set control unit 206 further manages the release of the relevant execution. In this regard, execution unit set control unit 206 assigns tasks of vertex shaders, geometry shaders, and pixel shaders to threads of different execution units 420, and records related tasks and threads. Specifically, the execution unit set control unit 206 maintains the threads of all execution units 420 and the resource table (not shown) of the memory. Execution unit The collection control unit 206 will explicitly know which thread is assigned to the task

Client5s Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 19 200821982=Which device will be released, how many are in use ^, π己^ 脰temporary state (register file Memory register ) Because = and how much free space each execution unit has. At the time, Burgundy-叩: assigns a task to the execution unit (for example, execution unit 420a) and all of them can be::::: Where: 206, the thread will be marked as busy, and the occupied temporary file is overwritten. The body vertex shader vertex shader, geometry: and; °; P; ^ fixed. Furthermore, each f-color recording can be set (4) or the vertex shader thread can require the area size. For example, the device, and the material (2) thread can be _= a total of 5 ^ memory ^ temporary storage register. Dong requires 5 shared scratchpad files to execute the thread's execution when the assigned guard is executed: : Execution unit set control unit 2. " : / k line is not used, and all threads share the scratchpad: add back to the available space. t all threads are (four) or inner = device file memory is allocated (or the rest of the temporary Save = = when the extra thread is executed), execution unit 420 2;: Wang Man, and the execution unit set control unit 2〇6 will not give the execution unit an extra or new thread. There is also a thread inside each execution unit that controls the crying or the various threads are in use (for example, in execution) or in the case of Bay, at least in the embodiment, when vertex coloring Is executing

Client's Docket No"S3U06-0014-TW TT,s Docket No:0608-A41247twf.doc/NikeyChen 20 200821982 When decoding the function of the system 200, the execution unit set control unit 2〇6 can avoid the geometry shader and the pixel shader in the same Time is executed. Figure 5 shows an execution unit 420a having the aforementioned graphics processor 202 and computing core 204, which includes an execution unit data path 512 of the embedded decoding system. Specifically, FIG. 5A is a block diagram of the execution unit 42A. In an embodiment, the execution unit 42A includes an instruction cache controller 504 coupled to the instruction cache controller 5〇4.

The controller 506, the buffer 508 (for example, a constant buffer), the common register file (CRF) 51 轻, the thread controller 5 〇 6 and the buffer 508, and the shared temporary storage The file data path (EU data path, EUDP) 512 of the file file 512, the first data path of the first in first out (FIFO) is executed. y scalar register file (SRF) 518, data private state 520 and thread task interface 524. As previously described, execution 420 receives input from the execution unit input 4〇2 and provides an output to the element output 404. The order thread controller 506 provides a control function of the execution unit 42A, and includes functions for managing the threads and determination functions, for example, determining the thread execution. Execution unit data path 512 includes decoding system 2 (8) executable step-by-step description, which typically includes performing Wei, ', which will perform floating-point and integer computing logic units (arithmetic logic = package AIAJ), shifting A logic circuit such as a bit logic function. Mt, data output control is 520 to move the completed data to the light one

Client's Docket No·: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 21 200821982 Some elements of the unit output 404, such as the vertices of the _ cache memory, write back unit ^^ 206 512 transmission "Task gentleman bundle,, _, the order of the data path knows the spear owed 1 Gongxun to the data output controller 520, Yutu knows that the spear force has been formed. The data rotation controller 520 Yakou Tasks (for example, 32 items rf Λ save the mouth to store the system in the system -, 'U Υ)) and a number of write 埠. Shenke fine work thieves 520 from the storage selected 阜 贝容 specified The location of the scratchpad, from the shared register hunting === the transfer of capital: ❹, and send the data to the execution unit round::. All dry eucalyptus. 匕 兀 兀 206. The task identifier will play early W Synthesizer 2G6 assigns a new task to the specific (for example, execution unit 420a). As an embodiment, the buffer can be divided into 16 blocks, and the ghost has 16 slots, and each slot has (3) The horizontal vector constant of the bit. The coloring is to use the transport 7L and the index to access the constant buffer slot. The index can be a temporary register including a 32-bit unsigned integer or a constant of 32-bit non-signed constants. The cache controller 5〇4 is to the thread controller 5 Interface block of 〇 6. When the thread controller read request exists (eg, extracting executable shader code from the instruction memory), the instruction cache controller is preferably by looking up the label table (not shown) Test with a hit/miss 〇nt/m1SS. For example, when the requested instruction is in the cache memory of the instruction cache controller 504, then a hit occurs. When the requested instruction will From L2 cache memory 408 or memory 1〇6

Client’s Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 22 200821982, the day $ ‘the miss occurred. When the hit occurs, the request for the day unit input 402 is performed, then the instruction cache is: 丄: there is no request for execution consent, because the instruction cache memory controller, 504 can take only one read/write file, and execute _ 504 instructions are fast, priority. Otherwise, if the miss 1 is 1 = element, the person 402 has the highest internal replaceable block and there is space. '§ Cache memory 408 data path FIFO buffer 514, the explicit execution unit 5〇 4 can agree to the request. In an embodiment, the cache memory of the δ 己 体 memory controller 504 has 32 groups, wherein the 亇7 取 6 6 hex memory controller block has a 2-bit status signal to indicate And there are 4 blocks. Effective, loaded, or valid. In the block, there is no "invalid" status; when waiting for the L2 data to be inserted into the L2 material, the block is evil, and when the L2 data is loaded, the block is always ", loaded". The unit data path is 512, ▲ put" state. Read and write. The single read in 402 is performed as the interface of the a, 4 word register file 516 420a. In one embodiment, the entry into the bedding and execution unit 8 items first buffers the buffer to buffer the incoming data. The execution unit can also transmit data to the instruction flash memory controller (10) command milk 2 memory and constant buffer 508. Execution unit input 4〇2 also: 拄 = recorder content. The executable unit output 404 is used as an interface for sending data from the execution unit 42A to the row unit set control unit 206, the L2 cache memory 408, and the w: unit 308. In one embodiment, the execution unit outputs a 4-item FIFO buffer for receiving arbitration requests, 3 η 5 it, ^

Client5s Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 23 200821982 The data of the execution unit set control unit 206 is executed. Execution unit output 404 includes a variety of functions including arbitration instruction cache read requests, data output write requests, and execution unit data path read/write requests. The shared scratchpad file 510 is used to store input, output, and temporary storage ! data. In one embodiment, the shared scratchpad file 5 10 includes eight banks having one of 128x128 bit register files, one read and one write, and one read/write. The read-and-write write is used by the execution unit data path 512 for the initial read and write accesses performed by the instruction. Memory banks 0, 2, 4, and 6 are shared by even threads, while memories 1, 3, 5, and 7 are shared by odd threads. The thread controller 506 compares the instructions of the different threads and confirms that the memory of the shared scratchpad file does not have a read or write memory conflict. A read/write buffer is used by the execution unit input 402 and the data output controller 520 to load the initial thread input data and write the final thread output to the execution unit set control unit data buffer and the L2 cache memory. 408 or other modules. Execution unit input 402 and execution unit output 404 share a single read/write input/output port, and in one embodiment, write versus readout has a higher priority. The 512-bit input data enters four different banks to avoid collisions when loading data into the shared scratchpad file 510. The 2-bit channel index, data, and 512-bit aligned base address are transmitted to specify the starting memory of the input data. For example, when the start channel index is 1, assuming the thread reference memory offset (offset) is 0, then the least significant bit is used.

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 24 200821982 The first 128 bits from the (lest significant bit, LSB) are loaded into memory bank 1, the next 128 The bits are loaded into the memory bank 2, etc., and the last 128 bits are loaded into the memory bank 0. It is worth noting that the two least significant bits of the thread ID are used to generate the memory offset to randomly rank the starting memory locations of each thread. j The shared scratchpad file register index and the thread ID can be used to create a unique logical address that allows the tag to compare the data written and read by the shared scratchpad file 510. For example, the address can be arranged in 128 bits, which is the width of the shared scratch file archive. By combining the 8-bit shared scratchpad file register index and the 5-bit thread ID, a 13-bit address can be created to generate a unique address. Each 1024-bit line has a label, and each bit line has two 512-bit items (characters). Each character is stored in four banks, and the two least significant bits of the shared scratchpad file index are added to the current library's memory offset to establish a bank selection. The tag comparison method allows the different scratchpads to use the shared scratchpad file 510 to effectively utilize the memory, because the execution unit set control unit 206 records the memory usage of the shared scratchpad file 510, and ensures that There is sufficient space before the new task of execution unit 420a is scheduled. The target shared scratchpad file index is checked against the size of all the shared scratchpad file registers of the current thread. The input data is expected to be stored in the shared scratchpad file 510 before the thread controller 506 proceeds to execute the thread and the colorizer execution begins. When the thread execution ends

Clienfs Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 25 200821982 f The fine data wheel controller 52 reads the output data from the shared register file 510. ,

The embodiment of the execution unit 420 includes a built-in decoding system 2: Example: execution unit data path 512 '5B shows the execution unit, and the path 512 is true. The execution unit data path # 512 includes a temporary storage file 526, a multiplexer 528, a vector floating point unit 532, a vector integer = a unit statement, a special purpose unit 536, a multiplexer 538, a temporary storage ', a buffer, and a decoding system. 200. The decoding system 2 includes a one or more variable length decoding (VLD) unit 530 that can decode - one stream. For example, the single-variable-length decoding unit 〇 解 can solve the singular-streaming 'two variable-length decoding units 530 (if the virtual 颂 颂 does not show its connection relationship for simplicity) can be decoded simultaneously: strings Flow and so on. For purposes of illustration, the following description is only directed to the operation of the decoding system of the length decoding unit 530, and the principles can be derived from more than one variable length decoding unit. As shown. As shown, the execution unit data path 512 includes some parallel data paths corresponding to the variable length 255, the floating point unit 532, the vector integer calculation logic, and the special purpose unit 536, the root = the received instruction Execution system (4). Temporary Storage (10) Case 526 receives 2兀 (marked WRC1#SRC2). In the embodiment, the register, field 526 may correspond to the shared temporary storage 51, shown in FIG. 5A, the associated register slot 516, and/or the scalar register file 518. It is worth noting that in some embodiments, additional operands may be used. The operation (function) signal line 542 provides a medium for each single a 53 〇 _53 6 |

Clienfs Docket No.: S3U06-0014-TW TT s Docket No:0608-A41247twf.doc/NikeyChen 26 200821982

The current signal line 544 is coupled to the multiplexer 528 and transmits the current value encoded as an instruction for each unit 53 〇 536 to perform an integer operation of a small integer value. An instruction decoder (not shown) provides an operand, an arithmetic (function) signal, and a current signal. The multiplexer 538 at the end of the data path (which may include the writeback phase) selects the output of the correct data path that has been selected and provides the output to the scratchpad: file 540. The output scratchpad file 54 includes the target component, which may be the same as the scratchpad file 526 or a different scratchpad component. It should be noted that in the embodiment, when the source and the target temporary storage include the same component, the bit provided by the instruction has the end source and the destination 4 used by the multi-common device to multiplex the data to/from Appropriate register slot case. Thus, execution unit 420a can be considered a multi-stage pipeline (e.g., a 4th-order pipeline with 4 computational logic units) and a solution operation occurs in 4 execution phases. A delay needs to be implemented to allow execution of the decoding thread. For example, when the bit stream buffers a down overflow (un(jer; Q〇w), waits for the initial content memory, waits for the bit stream to be loaded into the FIFO buffer, and the scratchpad ( The delay may be added during the execution phase when the processing time has exceeded the established threshold of time. As previously mentioned, in some embodiments, the decoding system 200 can use a single execution 420a Simultaneous decoding of two bitstreams. For example, according to the ~extended instruction set, the decoding system can use two data paths (for example, another variable length decoding unit 530) to simultaneously decode two streams. However, more or less streams can be decoded at a time (so more or fewer data paths are used.) When multiple streams are required, some embodiments of the decoding system 2 are not limited to simultaneous decoding. Furthermore, in some embodiments

Client's Docket No.: S3U06-0014-TW TTJs Docket No: 0608-A41247twf.doc/NikeyChen 27 200821982 Decoding of 'single-variable length decoding. In early 530, you can perform multiple streams at the same time.

The two threads can use the two data paths when the two systems are used, the execution, and the number of times of the case. In the implementation of two strings of ☆ decoding, for example, the thread gives:, 1 for two ' Assigning the first thread (the example decoding unit 530), and #, the first memory bank of the system 200: (that is, the second thread of the variable length code system 200 sends a second thread (for example, thread 1) to the solution. The length decoding unit)::::() column is as shown by the dotted line in FIG. 5B, and the variable operation is in the single-sympathy neighbor two μ. In the example, two or more threads can be embedded in the execution unit. In the embodiment, although the components of the decoding system are displayed, for example, C 512 μ, it may also include other logic circuits in the following control unit 206. ΐ::1 variable length gamma unit 530 and decoding system 200 It can be understood that the decoding system 2 can be subjected to the length decoding unit 53. One will describe the structure located under the decoding system, and the individual stone solutions are described below. In particular, in an implementation In the example, the following instructions proposed by the driver software 128 can be set. Different modes are further described as follows: • Command 1NIT-CTX (set decoding system 200 to CABAC processing mode), instruction INIT-CAVLC (set decoding system 200 to CAVLC processing mode), instruction INITJV [PEG2 (set decoding system 2〇0) For the MPEG-2 processing mode), and the instruction INITJVC1 (set the decoding system 2 to the VCM/WMV9 processing mode). In some embodiments, additional initialization can be provided via the INIT-AVS instruction, which initializes the audio video standard.

Client's Docket No,: S3U06-0014-TW TT^s Docket No: 0608-A41247twf.doc/NikeyChen 28 200821982 (audio video standard, A VS) bit stream coding. For the EXP-Golomb system, the EXP-Golomb coded symbols are used under CABAC and CAVLC encoding, so the iNIT CTX and the INIT-CAVLC are instructed to download the bit stream of the EXP-Golomb system. Among them, the EXP-Golomb system does not need to be initialized. For the column to be encoded, the computed coding flag received in the bitstream (eg, the bit set at the slice header level) will display the symbol Exp_G〇1〇mb, CABAC coding and CAVLC coding. When using EXP-Golomb encoding, execute the appropriate EXP_G〇i〇mb encoding instructions as set forth below. While these patterns affect the implementation of the encoding engine, they also affect the initial, usage, and method of updating memory, as described further below. Referring to Figure 5C, Figure 5C shows a functional block diagram of a variable length decoding unit for performing any of the complex decoding operations in accordance with the selected mode. The variable length decoding unit 530 includes a variable length decoding logic circuit 550, wherein the variable length decoding logic circuit 55 is coupled to a stream buffer/DMA engine 562 (also referred to herein as a DMA engine module). Bitstream buffer management and proximity context memory (NCM) 564 (also known as content memory). The variable length decoding unit 53A also includes one or more temporary storage locations 566' that are included for storing from the execution unit "o ("CQNTROL", for example using a control signal from a decoder of the execution unit to select variable length decoding The module of the logic circuit 550) temporarily stores the decoded data of the selected mode, the transport elements (eg, r Src 1 and "SRC2"), ', and the forwarding registers (eg, "F1" and rF2) "). SRE (} stream

Client's Docket No.: S3U06-0014-TW TT^ Docket No: 0608-A41247twf.doc/NikeyChen 29 200821982, buffer/DMA engine 562 includes SREG register (10) and bit stream buffer 562b, which will be further explained in Rear. In a consistent embodiment, the variable length decoding logic 55 includes a module (also referred to as a logic circuit) as shown in FIG. 5C. Variable length decoding logic, path 550, includes hardware that includes a scratchpad,/or a Boolean or computational logic to execute instructions and perform decoding in accordance with the selected mode. Further explained, the variable length decoding logic circuit 55 〇 & includes reading the adjacent content record module (read-NCM) 568, the check string (JNPSTR) module i 570, the read module 572, and the calculation leader 1 ( CL〇) module 574, calculation lead 〇 (0^;) module 576,]\/〇^0 module 578, 〇8; 6 people (: module 580, CAVLC module 582, and coupled to the calculation The Exp-Golomb module 584 of the leading 〇 (CLZ) module 576. The calculation leading 〇 (CLZ) module 576 and the 铀 铀 导 1 1 (CL〇) module 574 include decodable MPEG-2 and VC-1 bits. Flow instruction. With the Exp-Gol〇mb module 584, the Exp-Golomb symbol is encoded by some leading zeros following the 1 followed by some bits equal to zero. The calculation of the leading 〇 (CLZ) module 576 detection The number of leading zeros is set, and then these bits are added to add 丨 to record the number of leading zeros. Exp-Golomb module 584 reads the number of trailing bits (tramng blt) and performs calculation according to Exp-Golomb mode to determine The read proximity content memory module 568 includes logic circuitry corresponding to the generation of the address and the request for the memory read operation. In the body read operation, the fixed number of bits is read from the adjacent content memory 564 and the data is output to the target register. The adjacent content memory command reads the 32-bit data from the content memory 564 and passes the multiplex. 685 returns the value read to

Client?s Docket No.: S3U06-0014-TW TT^ Docket No: 0608-A41247twf.doc/NikeyChen 200821982 .. The target register of row unit 4. CABAC and cavlc encoding do not use adjacent content memory instructions, whereas for other variable length operations (eg, ^, ΜΡΕ (: Μ Asp (DivX)), content memory 564 can be used to maintain variable length decoding tables. And can use the read, take the adjacent content memory module to read the value in the variable length decoding table. The shell read module 'group 572 & contains logic to read s · temporary cry 562a, and from SREG The most significant bit (MSB) portion of the register 562a takes a specific number of bits, zero extension (zer〇Γ extend), and puts the value into the scratchpad. Therefore, the reading module s72 A logic circuit is included to perform a read operation that reads a particular number of bits and removes from the sreg register 562a to return a value that has no sign value to the target register. The check string module 570 is temporarily staging from the SREG The 562a reads the fixed number of bits, but does not remove any bits from the SREG register 562a (eg, does not change the index position) and returns a value that does not have a sign value to the target register. Module 568- The 584 is coupled to the multiplexer 586, wherein the multiplexer 586 is The mode selects a mode. In one embodiment, the output of the multiplexer 586 is provided to the target register for further processing. The output of the modules 569-582 is also provided to the multiplexer 586, which corresponds to a command, selection The outputs of modules 569-582 are provided as input to SREG register 562a. During the same operation, data from forwarding, control, and operation registers 566 are provided to CABAC module 580 and CAVLC mode 582. The Exp-Golomb module 584 is enabled via a receive control signal (expressed as EXP-GOLOMB-OP of Figure 5C). The Exp-Golomb module 584 receives the analog lead (CLZ) module 576.

Client's Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 31 200821982 inputs and provides output to multiplexer 586. The content memory 564 can be used by the CABAC module 58A and the CAVLC module 582.

For all modes except the CABAC and CAVLC modes, the read command reads n bits from the SREG register 562a, and the multiplexer 586 returns the read value to the execution unit 42. The target register of a. For modes other than the CABAC and :CAVLC modes, the inner memory is used to maintain the upper and left content values, which are automatically captured as part of the decoding process. These elements, as well as other elements of the variable length decoding unit 530, which are further interleaved in the latter modes in conjunction with different modes, are noted in some embodiments, the variable length decoding logic may include less than (or more) All of the displayed modules and/or multiplexed crying will describe the general functionality of the variable length decoding unit 530, and the operation of the variability decoding unit 530 configured in different modes will be further described. Putian: ^ CABAC decoding The following briefly explains CABAC decoding, and then illustrates some embodiments of the decoding system. In general, the CABAC decoding program of the H.264 standard can be described as a decoding engine including an encoded bit stream that parses the first syntax component, a content variable that initializes the second fragment, and a first syntax component, to be binarized. ). Next, each binary value (Μη) is decoded, and the program includes obtaining the decoding of the content module and the binary values of the syntax components until a meaningful word (c〇dew〇rd) alignment is obtained. Still further explained, the decoding system 200 decodes the syntax components, wherein

Client5s Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 32 200821982 Each grammatical component can represent quantization coefficients, motion vectors, and/or prediction modes, or other related macroblocks ( A macroblock parameter that represents a particular field or frame of an image or video. Each syntax component can contain consecutive one or more binary symbols or binary values, and each binary symbol is decoded to a value of 0 or 1. solution

The I I code system 200 controls the output bit length based on the probability of occurrence of the input binary symbol. When certain symbols (called primary symbols) are more likely to occur than others, CABAC encoders provide a highly efficient encoding method. These primary symbols can be encoded with a smaller bit/symbol scale. The encoder continuously updates the frequency statistics of the incoming data and adjusts the calculation of the coding calculus and the content model as appropriate. A binary symbol with a higher probability is called a most probable symbol (MPS), while other symbols are a low probable symbol (LPS). The binary symbol, in combination with its content model, has a content model corresponding to the likelihood of low probability symbols and high likelihood symbol values. In order to decode each binary symbol, decoding system 200 determines or receives a corresponding range, offset, and content model. The content model is selected from a plurality of possible content models based on the type of symbol and the content determined by the neighboring space (e.g., the current macroblock or the adjacent macroblock that belongs to the previous decoding). The content identification symbol can be determined by the content model and used to obtain a high probability symbol value and the current state of the decoding engine used to decode the program. The range represents an interval (interval), which is scaled down once every binary decoding.

Clients Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 200821982 The interval is divided into two sub-ranges, respectively m and low probability symbol values. By multiplying the high probability symbolic likelihood of the metric value = symbol value, it is known that the network technology specified by the 杈 杈 type has a low probability symbol sub-edge. The hunter subtracts the low probability symbol sub-range to calculate the sex symbol sub-range. The offset is the criterion for determining the value of the return value of the 匕 匕 1 1 1 , , , , , , , , , , 1 1 1 1 1 1 1 1 1 1 1 1 1 1 For the one-digit payment decoding and content model, when the stone r network gentleman, the 镐 夕 里 咼 咼 咼 咼 咼 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已The sexual symbol, ', jin is determined by the low probability symbol, the high probability symbol value related content, and the inverse value of the lower handle will be included in the 辄. The result of the decoding process is a continuous decoded binary value, which is evaluated to determine whether the sequence conforms to a meaningful word. The general description of the decoding system, the operation of the system, and the (10) ac solution are described below. The following describes the content of the lion CABAC decoding program: 200 The various components of the application can be adapted to the actual geese, 糸, 先 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 It is helpful to understand the different procedures and/or components described above, and then proceed to the description of the steps. Figures 6A to f6F show the blocks of the specific embodiment of the solution and related components. As shown, the decoding system · a CABAC unit 530 (in the 6A to the figure, the CABAC unit 530 used can be interchanged with the decoding system 2), so in an embodiment, the decoding system 200 can Decode single-bit stream. The same principle can be applied

Client's Docket No.: S3U06-0014-TW TT’s Docket No:0608-A41247twf.doc/NikeyChen 34 200821982 To, the decoding system with additional variable length decoding unit 2〇〇 can be solved simultaneously

A stream of (for example, two) streams. Briefly, the block diagram of the selected component of the 6A code system 200, and the figure (4) of the factory solution chain 1 , the Yang shake - the system shows the brothers and sisters to show the selection of the components and other components Party = and == code system 2〇. The block diagram of the content memory function and the 6D map show the block diagram of the mechanism used to decode the macroblock. Although the following description is about macroblock decoding, the principles of the present invention are applicable to various block decoding. Referring to FIG. 6A, the variable length decoding unit tears include an a logic module 580 and a memory module. The implementation logic module 580 includes three modules, namely a dual money (leg D) module 620, a get content (GCTX) module, and a binary decoding (BARD) engine 624. Binary calculation decoding engine gamma packet: state index (pStatddx) temporary storage n 6Q2, high probability symbol value () register 604, code length norm (c〇dlRange) register, and code length offset Register (C〇dlOffset) 608. The variable length decoding unit 53A further includes a memory module 650, which includes a content memory 564 (also referred to as a macroblock neighboring content (mbNeighCtx) memory or a content memory array), and a local register. 612, the overall register 614, and the SREG stream buffer/DMA engine 562 (also referred to as the DMA engine module, which will be further described in FIG. 6C), in addition to the scratchpad not shown. In one embodiment, the content memory 564 includes an array structure as shown in Figure 6C, as will be further explained hereinafter. The memory module 650 also includes a binstring register 616.

Clienfs Docket No.: S3U06-0014-TW TT's Docket No: 0608-A41247twf.doc/NikeyChen 35 Variable length decoding unit 530a Target (DST) bus 62δ, two = gamma interface including SRC·, sharing, and thread information The sink ^^ SR (four) 2 and the set bus 636. The target bus 628 is 634 on top, and delayed/heavy (eg, via intermediate cache, [tn data can be transferred directly or indirectly to the graphics processing unit 114 曰 M, rush, or memory) on the header 628 The data can be used in the video processing unit of the ββ section. Soft...丨 format or two=format-, including micro

Macro Block Parameters, Animal W Sampling The only length decoding unit 53A also includes a memory interface having an address bus 638 and a data bus _. By obtaining the address from the address bus (4), the surface can access the bit stream data for accessing the data received by the data bus (10) in the case of the case towel, the data bus _ The data Μ includes unencoded video streams, which include various hard parameters and other cues and formats. In some embodiments, a person storage operation can be used to access the bit stream data.

Before starting to explain the different elements of the variable length decoding unit brother (10), the overall operation of the execution unit 42A with respect to CABAC decoding will be briefly explained. Usually, according to the type of slice, the driver software 128 (Fig. 1) prepares and loads the CABAC shader to the execution unit 420a. The CABAC shader uses a standard instruction set, plus a binary instruction, a content instruction, and The binary computes the decode instruction to decode the bitstream. Since the table of contents used by the variable length decoding unit 530a can be changed according to the type of the segment, each of the segments is to be loaded. In one embodiment, CABAC is issued before other instructions are issued.

Client’s Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChei 36 200821982 Coloring! The first instruction executed by § ' contains the INIT_CTX instruction and the INIT-ADE instruction. These two instructions cause the CABAC unit 53 to start decoding the CABAC bit stream' and load the bit stream from the indicator that automatically arranges the stream decoding to the FIFO buffer, which will be described later. For parsing the bit stream, the bit stream is received from the data bus 64 of the memory f, and then buffered by the SREG stream buffer: the DMA engine 562. Bitstream decoding is provided from the fragment data parsing stage. That is, the bit stream (e.g., NAL bit stream) includes one or more pictures #, which will be cut into picture headers and a number of fragments. Fragments are usually associated with a continuous macro block «. In the implementation, the ( (4) (gp variable length decoding unit 兀 53Qa external) parses the NAL bit stream, decodes the fragment slot header, and transmits an indicator pointing to the location of the fragment data (eg, at the beginning of the segment). The hardware (plus software) can parse the H264 bit stream from the graph. However, in one embodiment, CABAC coding occurs only in the segment data and macroblock stages. Usually the 'driver' 128 handles the bit stream from the #segment:# segment, because this is the application and the functionality provided by the AP. The indicator pointing to the location of the fragment data also contains the first byte of the fragment data (eg: RBSPbyeAddress) and indicates the start or header position of the bit stream (eg, the bit offset indicator of sREGptO (eg one or more bits) The initialization of the bitstream will be explained later. In some embodiments, the host processor (eg, central processing unit it 126 of Figure 1) can be utilized to process external programs to provide image phase solutions and fragments. (d) Decoding. In some embodiments, due to the programming characteristics of the decoding system 200, decoding can be performed in any stage.

Client's Docket No.: S3U06-0014-TW TT's Docket No: 0608-A41247twf.doc/NikeyChe: 37 200821982 ~ Referring to Figure 5C and Figure 6A, the SREG stream buffer face-in engine 562 is used to receive the busbars respectively 632 and the bus bar SRC1 value of the bus bar 63〇 and the bus bar SRC2 value, and the data corresponding to the forwarding register and the control register. The SREG Stream Buffer/DMA Engine 562 includes an internal bitstream buffer 562b, which in one embodiment can be a 32-bit scratchpad in BigEndmn format and 8 128-bit (8-128) scratchpads. The sreg string, mash state/DMA engine 562 can be initially set by issuing an initialization command as described above via the driver software. Once initialized, the internal buffer 562b of the SREG stream buffer/DMA engine 562 is automatically managed. The SRE(} stream buffer/DMA engine 562 is used to preserve the position of the parsing bit. In a case where the 'SREG stream buffer/DMA engine 562 uses two temporary port fast % bit flip-flops With a slower 512 or 1 〇 24-bit memory moon beans. The bit stream uses bits. The SREG register 562a operates with bits and the bit k buffers 5 62b operate with bytes, which can Power is saved. Typically, the instruction operates in the SREG register 562a and uses a few bits (eg, 1-3 bits). When the SREG register 562 & uses more than one 7G group of data, the data (in bits) The tuple segment will be transferred from the bitstream buffer 562b to the SREG register 562a, and then the buffer indicator will reduce the number of bytes transferred. When the DMA of the SREG stream buffer/DMA engine 562 is detected. When 256 bits or more, 256 bits are taken from the memory moon bean & to refill the bit stream buffer 562b. Therefore, the variable length decoding unit 530a implements a simple circular buffer (256 bits) The meta-segment X 4 ) is used to record the bit stream buffer 562b and provide padding. You can use a single buffer, but a circular buffer required

Clients Docket No.: S3U06-0014-TW TT s Docket No:0608-A41247twf.doc/NikeyChen 38 200821982 More complex indicator calculations to keep up with the speed of the memory. The internal operation of internal buffer 562b can be accomplished using an initialization instruction, referred to as the INIT-BSTR instruction. In one embodiment, the INIT_BSTR instruction and other instructions described later are issued by the driver software ία. Knowing the byte address and bit of the bit stream location, the meta-offset, the INIT-BSTR instruction loads the data into the internal bitstream buffer: 562b and begins the hypervisor. For each call processing fragment data, an instruction of the following format will be issued: INIT - BSTR offset, RBSPbyteAddress f \ The INIT-BSTR instruction is issued to load the data into the internal buffer 562b of the SREG Stream Buffer / DMA Engine 562. The SRC2 register provides the byte address (RBSPbyteAddress) and the SRC1 register provides the bit offset. Thus, the following general instruction formats are available: INIT_BSTR SRC2, SRC1, where SRC 1 and SRC2 in this instruction and other values corresponding to I internal register 566 are not limited to these registers. In one embodiment, a 256-bit aligned memory fetch is used to access the bitstream data, which is written to the buffer register and passed to the 32-bit SREG of the SREG stream buffer/dma engine 562. The memory 562a. In one embodiment, the data in the bit stream buffer 562b is arranged in a byte group before any other operations begin with the operations of the registers or buffers. The arrangement of the data can be implemented by using the permutation instruction, which is called an ABST instruction. The ABST instruction arranges the data in the bit stream buffer 562b, where the decoding

Client's Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 39 200821982 In the program, the arrangement bits (for example: padding bits) will be discarded at the end. ‘ When the SREG register 562a uses data, the internal buffer 562b is filled with lean material. In other words, the internal buffer 562b of the SREG stream buffer/DMA engine 562 acts as a circular buffer modulo 3 (m〇dul〇) to input the 32-bit temporary of the SREG stream buffer/DMA engine 562. State 562a. The CABAC module 580, along with the read module 572, can use the READ command to read data from the SREG register 562a. For example, in the H.264 specification, 'some symbols are fixed-length codes, and the value is obtained by executing the READ instruction for these specific number of bits, and zeros to the size of the scratchpad. The format of the READ instruction is as follows: READDST, SRC1, where DST corresponds to the output or target register. In an embodiment, the SRC1 register contains an integer value n that is not signed. The n-bit is read from the SREG register 562a via the read instruction. When the 256-bit data (for example, decoding - or a plurality of syntax components) is used from the (1) tiling register 562a, the extraction operation is automatically started to obtain another 256-bit (four) material for writing to the internal buffer 562b. Save the file, and then enter the ^sreg temporary cry 562a for use. In some embodiments, if the data corresponding to the -symbol decoded SREG register 562a has been used for a predetermined number of bits or bytes ^ internal buffer n is no longer received, then cabac 580 can The delay is performed via the delay/reset bus 636 to perform the execution of the thread (eg, execution independent of the CABAC solution:

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 40 200821982 Like a vertex shader operation. The DMA engine using the SREG Stream Buffer/DMA Engine 562 can reduce all of the buffers needed to compensate for memory delays (e.g., in some graphics processing units, there will be more than three hundred cycles). When a bit stream is used, it is possible to request the flow of additional bit stream data. If the bit stream data is too

When t I is low and the bit stream buffer 562b has a risk of a down overflow (eg, a known number of cycles, allowing the signal to flow from the variable length decoding unit 530a to the processor pipeline), a delay signal can be passed to the processor. The pipeline suspends operation until the waiting data arrives at the bit stream buffer 562b. In addition, the SREG Stream Buffer/DMA Engine 562 originally had the ability to handle error bitstreams. For example, due to a bit stream error, it may not be detected at the end of the segment. This detection error can result in a complete decoding error and the use of bits in subsequent patterns or fragments. The SREG Stream Buffer/DMA Engine 562 records the number of bits used. When the number of bits used is greater than the preset limit (which can be changed for each segment), the handler is terminated and an exception signal is sent to the processor (for example, the host processor). The processor then performs the encoding to attempt to reply from the error. Please refer to FIG. 6A and FIG. 6B simultaneously to further explain the function of the variable length decoding unit 530a, especially the decoding engine (for example, the BARD engine or the module 624) and the initialization of the content variables. The content state and the binary computation decoding module 624 are initialized at the beginning of the segment and before decoding the syntax components corresponding to the first macroblock. In one embodiment, the driver software 128 issues an INIT-CTX instruction and an INIT_ADE instruction for initialization.

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 41 200821982 t The INIT-CTX command will initiate the CABAC decoding mode and initialize one or more table of contents (eg remote storage or on-wafer) Memory, such as ROM). The INIT-CTX instruction can be executed according to the following instruction format: INIT_CTX SRC2, SRC1 For the INIT_CTX instruction, depending on the bit position, the operand SRC1 can have one or more of the following H.264 macroblocks. The values of the parameters: cabac—init—idc, mbPerLine, constrained—intra—pred flag, ”NAL_unit—type(NUT), and MbaffFlag. It should be noted that constrained-intra-pred-flag, NAL-unit-type (NUT), and MbaffFlag correspond to known H.264 macroblock parameters. Further, according to the bit position, the operand SRC2 has the following values: SliceQPY and mbAddrCurr. In an embodiment, it is further explained that the execution of the INIT_CTX instruction (i.e., initialization of the CAB AC table of contents) requires a cabac"nit_idc and a sliceQPY (e.g., quantization) parameter. However, to initialize the entire CABAC engine requires three instructions, namely the INIT_BTSR instruction, the INIT_CTX instruction, and the INIT_ADE instruction. Therefore, the available bits in SRC1 and SRC2 ({columns such as: all 64 bits or 32 bits each) can be used. Pass other parameters for CABAC proximity content. Therefore, the two source registers SRC1 and SRC2 664 can contain the following values: SRC1[15:0] = cabac an init_idc SRC 1 [23:16] = mbPerLine SRC 1 [24] = constrained an intra-pred flag SRC 1 [27:25] - NAL_unit_type (NUT)

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 42 200821982 SRC1[;28Bu MbaffFlag SRC1[31:29]Two undefined SRC2[15:0] = SliceQPY SRC2[31: 16] = mbAddrCurr

The value of SliceQPY is used to initialize the bit stream: a state machine (not shown) within buffer 562b. Although a number of known patterns and fragment tea numbers have been provided as well, some parameters regarding the variable length decoding unit 530a are provided. In one embodiment, 'cabacjnit_idc' is defined for fragments that are not encoded as I-picture and switched I-picture (SI). In other words, cabac_init_idc can only be defined for P, SP, and B segments, and 'cabac-imt_idc' is the default when I and si segments are received. For example, when approximately 460 inner valleys (eg, I and SI fragments) are initialized, cabac_init_idc e can be again 3 (because the value of ca]3ac_init_idc can only be 0~2 according to the H.264 specification, A 2-bit is enabled to indicate that the fragment is I or SI. The variable length decoding unit 530a may also use the INIT_CTX instruction to initialize the local register 612 and the macroblock neighboring content memory 564 array structure or elements, including the temporary registers associated with the temporary neighboring macroblocks. Referring to Figure 6C, in one embodiment, the macroblock adjacent content memory 564 is located above the map. In one embodiment, the macroblock block is adjacent to the content of the macroblocks 64. The reference block neighboring content memory is arranged in a memory array to store data about the macroblocks (r〇w). As shown, the macroblock neighboring content memory 564 includes the array element mbNeighCtx[0,

Client’s Docket No.: S3U06-0014-TW TT’s Docket No:0608-A41247twf.doc/NikeyChen 200821982

1, i-1, i, i+1, ... 119] (labeled 601), each element is used to store one of the 12 macroblocks into a column (for example, corresponding to HDTV) 1920x1080 pixels). The mbNeighCtxCurrent register 603 is currently used to store the currently decoded macroblock, while the mbNeighCtxLeft register (8) 5 is used to store the previously decoded neighbors (left macroblock. In addition, using indicators 607a, 607b, and 607c (at section 6C) The figure is indicated by an arrow) to the registers 603, 605 and the array element 601. In order to decode the current macroblock, the decoded data is stored in the mbNeighCtxCurrent register 603. The content of the content of the CABAC decoding is known, according to the former The information collected during the decoding of the macroblock is decoded to decode the current macroblock, that is, the left macroblock is stored in the left mbNeighCtxLeft register 605 and pointed by the indicator 607b, and the upper macro block Stored in array element [i] and pointed to by indicator 607c. Continuing to interpret the initialization instructions, the INIT^CTX instruction is used to initialize adjacent to the current macroblock (eg, the element of the macroblock block adjacent to the content memory 564 array). The upper and left indicators 607c and 607b related to the macro block. For example, the left indicator 607b can be set to 〇 and the upper indicator 607c can be set to 1. In addition, the INIT_CTX command updates the total. The register 614. Regarding the initialization of the table of contents, the variable length decoding unit 530a establishes one or more content tables, also referred to as CTX-TABLE, in response to the INIT_CTX command. In an embodiment, the CTX_TABLE may be 4x460x16 bits. The metatable (8 bits for m, the other 8 bits for η, with positive and negative values) or other poor structure, each item of the table contains a slave state register 602 and a high probability symbol value. Stored in 604

Client’s Docket No_: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 44 200821982 Take the pStateldx value and the valMPS value. The INIT-ADE instruction initiates a binary calculation decoding module 624, also known as a decoding engine. In one embodiment, the INIT-ADE finger ♦ is called after the INIT_BTSR instruction is completed. The INIT-ADE refers to the i-decoding unit 530a to establish two registers, which are a code length range ί (codlRange) register 606 and a code length offset (codlOffset) register 608, having the following instructions or values: CodlRange - 0x01FE and codlOffset = ZeroExtend (READ(#9)5 #16) As such, in one embodiment, these variables can be 9-bit values. Regarding the codlOffset instruction, the 9-bit element is read from the bit stream buffer 562b, and the extension is stored in the 16-bit code length offset register 608. Some embodiments may also use other values. The binary calculation decoding module 624 uses the values stored in the registers 606 and 6.8 to determine whether to output 0 or 1 ' and these values will be updated after a carry decoding. In addition to the initialization code length range register 606 and the code length offset temporary state 608', the INIT-ADE instruction operation also initializes the binary string register 616. In one embodiment, binary string register 616 can be a bit register that receives the output bits from binary calculation decoding module 624. Other sizes of temporary crying may be used in some embodiments. When the macro block is programmed into I-P C Μ data, the binary calculation solution module 624 is also initialized. LPCM data is known to contain pixel data, and according to the H.264 specification, it does not apply a conversion or prediction model to the original video.

Client’s Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 45 200821982 · Digest. For example, I-PCM can be used for lossless (i〇ssless) coding applications. The architecture and instructions related to parsing the bitstream and initializing various decoding system elements have been described above. One or more procedures for binarization, reception model information and content, and decoding based on the model and content will be described below. In general, the variable length decoding unit 53A is used to obtain all possible binarizations of the syntax element (SE), or at least sufficient to obtain model information via the BD module 620 and the BIND command. The " Ai length decoding unit 530a obtains the content of the known syntax component by acquiring the content module 622 and the GCTX command, and performs arithmetic decoding by the binary calculation decoding module 624 and the BARD command based on the content and the model information. On the Bay, the GCTX/BARD command is called, the bit is output to the binary string register, and the 616 system finds that the meaningful code with the known syntax component constitutes a loop. In one embodiment, after each decoding of the binary value: a corresponding decoding bit is provided to the binary string register 616, and the binary bit (the string register is read back to the content module 622 until found Pairing. The decoding system architecture using the single variable length decoding unit 53A is explained in more detail, and the BIND instruction issued by the (4) software 128 is used to enable the binary module 62〇 with reference to the 6A and the first map. In one embodiment, the BIND instruction has the following format: , BIND DST, #Imml6, SRC1, where DST corresponds to the target register 652, and #Imml6 corresponds to the current value of the i6 bit, and SRC1 corresponds to the input register. SRC1.bind

Clients Docket No.: S3U06-0014-TW TT s Docket No:0608-A41247twf.doc/NikeyChen 46 200821982 The input of the instruction insert contains the syntax component (including the 16-bit current value Imm) and the content block type (ctxBlockCat). The syntax component can contain any syntax component type that conforms to the H.264 specification (for example: MBTypelnl, MBSkipFlagB, IntraChromaPredMode, etc.). Calling the BIND command causes the driver software 128 to read the syntax components from the form (or other data structure) stored in the memory (e.g., on-wafer memory or remote memory) and obtain the syntax component index (SEIdx). The grammar component index is used to access other forms or data structures to obtain the macro block parameters as described below. In an embodiment, target register 652 includes a 32-bit scratchpad having the following format: bit 0-8 (ctxIdxOffset), bit 16-18 (maxBinldxCtx), bit 21-23 (ctxBlockCat) , Bits 24-29 (ctxIdxBlockCatOffset), and Bits 31 (bypass flag). These values (e.g., ctxIdxOffset, maxBinldxCtx, etc.) are passed to the fetch content module 622 for use as a content model. In this embodiment, any undefined reserved bits may be 〇. The ctxIdxBlockOffset can be obtained via a form or other data structure stored on the remote or on-wafer memory based on the result of the syntax component index and the content block type. Table 1 illustrates the contents of a non-limiting embodiment: ccxJeNum (k) Coded a blockjDattem Intra_4x4 Inter 0 47 0 1 31 16 2 15 1 3 0 2 4 23 4 5 27 8

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 47 200821982 6 29 32 7 30 3 8 7 5 9 11 10 10 13 12 11 14 15 12 39 47 13 43 7 , 14 45 11 15 46 13 16 16 14 17 3 6 18 5 9 19 10 31 20 12 35 21 19 37 22 21 42 23 26 44 24 28 33 25 35 34 26 37 36 27 42 40 28 44 39 29 1 43 30 2 45 31 4 46 32 8 17 33 17 18 34 18 20 35 20 24 36 24 19 37 6 21 38 9 26 39 22 28 40 25 23 41 32 27 42 33 29 43 34 30 44 36 22 45 40 25 46 38 38 47 41 41

Client's Docket No..· S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 48 200821982 Table 1 If you receive an undefined content field, the mouth of the wire, the variable length decoding is early 53〇a can treat the undefined parameter as τ^ι 1 X υ The ctxIdxBlockOffset is considered to have a 〇 value. The beer called BIND will also make the reset Lu % ^ 〇. ιλ, and Rs-Signal output from the binary 楱 group 620 to the second gt; [Zheng Ji Zengchu, 4 different decoding module 624, illustrated below. To illustrate the various inputs and outputs of the binary module 620, the operation of the binary module (10) according to at least the embodiment is presented herein. Call, carry-up (4), then binary---------------------------------------------------------------------------------------------------------------------------------------------------- Using the affiliation component index, the binary module 62 looks up the form to obtain the corresponding values of maxBinldxCtx, ctxIdxOffset, and bypassFlag. This lookup value is temporarily stored in the predefined bit configuration of the target register 652. In addition, using the syntax component index and the content block type, the binary module 620 performs a second form lookup (e.g., remote memory or on-wafer memory) to obtain a ctxIdxBlockOffset value. The second lookup value is also temporarily stored in the target register 652. Therefore, the determined value will be used to establish the target register 652 as a 32-bit value output. For some syntax components, additional information (except for the syntax component and the content block type) can be used to start H. 264 decoding operation. For example, for macroblock parameters like SigCoeffFlag and lastSigCoeffFlag, array elements stored in the macroblock adjacent to the content memory 564 are used.

Client's Docket No.: S3U06-0014-TW TT?s Docket No:0608-A41247twf.doc/NikeyChen 49 200821982 The value in maxBinIdxCtx[ 1 ] and the input content block type value to determine the macro block map field code or Is the frame code. In some embodiments, even with different syntax components, the same number of grammatical components are used to identify these flags and then use mb-field-decoding_flag(mbNeighCtxf1) to identify them. In addition to the above-described functions relating to the binary module 620, it is noted that the group 620 can be combined with the binary index register 654, the multi-work unit 656, and/or the forwarding buffer F] ^ Office and F2. As for the binary index temporary stealing 654 and the multiplexer unit 656, the multiplexer provides the output SRC1 according to different input (for example, temporarily storing the value to the content module 622.) About the forwarding temporary storage indicated as F1 When the crying command produces a result, the result can be "two' * _D (or GCTX) register 052 and / or forward temporary crying 曰 曰 ( (for example, the target flag can represent an instruction and; should) modul = (4) The material 622 or binary calculation decoding module in the order is like the content module and F2. The value of the forwarding register F1 1 on behalf of the forwarding register is 0. In the embodiment, it can be 1 (ie, using the forwarding source and F2 (ie, using the forwarding source 2 date/bit 26) Represents) in the position of the bit). For the acquisition: ": can be the instruction calculation decoding module 624, the data can be transferred = 22 and the binary. X other rounds, as explained above, the binary module description about the acquisition content module 622 at

Clienfs Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 620 and related procedures, here is how the GCTX command surface can get the content of the 2008 200821982 model and the binary index. Briefly, the input to get content module 622 contains maxBinldxCtx, binldx, and CtxIdxOffset, as described below. The retrieved content module 622 uses the CtxIdxOffset and binldx values to calculate the value of Ctxldx (which is an output, representing an exemplary format of the content index instruction as follows: | GCTX DST, SRC2, SRC1, where SRC1 corresponds to output by multiplexer unit 656 The value is stored in the temporary state SRC1 ' and SRC2 corresponds to the value output by the target register 652 and stored in the register SRC2, and the DST corresponds to the target register. In one embodiment, each temporary memory The device has the following values: SRCl[7:0; hbinIdx; when the current syntax component contains codedBlockPattern, the value of SRC1 (output from multiplexer unit 656 and as input to get content module 622) may be a binary index temporary storage. The value of 654. SRC1 [15:8] can be levelListldx (when calculating sigC〇effplag), lastSigCoeffFlag or mbPartldx (when calculating the coded block pattern Ref-Idx or binldx). When the syntax component is sigC〇effplag Or lastSigCoeffFlag, multiplexer unit 656 can be used to transmit levelListldx 〇 SRC1 [16] can contain iCbCr flag, and when its value is ,, the block is Cb chrominance block. SRC1 [16] may comprise L0 / L1 value, if L0, a value of 0, this person familiar with the art of the present invention may be known L0 / L1 prediction of pattern compensation for moving the reference list (= Hst〇

Clienfs Docket No.: S3U06-0014-TW TT’s Docket No:0608-A41247twf.doc/NikeyChen 51 200821982

Ll = listl ). SRC1 [21:20] two mbPartitionMode SRC2 [8:0] two ctxIdxOffset SRC2 [18:16] two maxBinldxCtx SRC2 [23:31] = ctxBlockCat SRC2 [29:24] = ctxIdxBlockOffset SRC2 [31] two bypassFlag Again, DST This includes getting the output of the content module 622 with the following values: DST [15:00] = ctxldx DST [ 23:16] = binldx DST [ 27:24] = mbPartldx DST [29:28] = mbPartitionMode DST [30] = L0

The retrieved content module 622 can also interact with the forwarding register. Therefore, when using the forwarding register, the instruction can obtain the format of GCTX.F1.F2, and F1 and F2 indicate that the forwarding register is used, that is, there are 2 bits in the decoding (F1 and F2). If one or two forwarding flags are not obtained, the forwarding register is not used. When these bits are set (for example, &lt; 1), the value of the forwarding register (the internally generated value) is used. No Use the value of the source register. Therefore, the forwarding register provides a proposal to "-, when the product is the earliest time to issue instructions, to compile, and to have a high-order. Go. When using the Forwarding command, you may encounter a known source temporary crying ^^ delay. <Read after writing#

Client's Docket No.: S3U06-0014-TW TT s Docket No: 0608-A41247twf.doc/NikeyChen 52 200821982 For the GCTX instruction When the reset signal (Rst-gignai) is set, the value of SRC1 is 〇. When the operation (F1 &amp; Rst_signal) is established, SRC1 is the value of the binIdx from the internal content acquisition module 622 plus, otherwise SRC1 is the binldx value from the execution unit register. The output of the binary module 620 can be used as the GCTX instruction and the ί forward SRC2 value of the BARD instruction. In the following instructions, the BIND instruction will not be issued. The BARD instruction is used to forward the scratchpad. Further, the reset signal and the F1 forward signal are combined into a signal (e.g., a 2-bit signal) {Fl, reset} indicating whether the value of the SRC1 input to the acquired content module 622 includes a binldx value or a forward value. Another function of providing a reset signal is to clear and reset the binary string register 616 and reset the binary index register 654 to 〇. Continuing with the discussion of the content module 622 and the content information, in one embodiment, the information shown in Tables 2 and 3 below corresponds to the values of the structure neighboring content memory 564 and the mbNeighCtxCurrent register 603, respectively. The mbNeighCtxCurrent register 603 contains the decoded output of the current macroblock. At the end of the current macroblock processing, a CWRITE instruction is issued that copies the information from the mbNeighCtxCurrent register 603 to the location within the array of adjacent content memory 564. The copied information is then treated as the top neighbor value. Parameter Size (rice) transform_size_8x8_flag 1 0 mb-field_decode_flag 1 1 mb-skip-flag 1 2 lntra_chromajDred_mode 2 4:3 mb-type 3 7:5

Client's Docket No.: S3U06-0014-TW TT?s Docket No:0608-A41247twf.doc/NikeyChen 53 200821982 codedBlockPattemLuma 4 11:8 codedBlockPattemChroma 2 13:12 codedFlagY 1 14 coded FlagCb 1 15 codedFlagCr 1 16 codedFlagTrans 8 24:17 Refldx 8 32:25 predMode 4 36:33 Table 2 parameter size (ίϊΰΐ;) transform_size-8x8-flag 1 0 mb-field a decode-flag 1 1 mb-skip-flag 1 2 Intra-chroma_pred_mode 2 4:3 mbQpDeltaGTO 1 88 codedBlockPattemLuma 4 11:8 codedBlockPattemChroma 2 13:12 codedFlagY 1 14 codedFlagCb 1 15 codedFlagCr 1 16 codedFlagTrans 24 87:64 refldx 16 52:37 predMode 8 60:53 mb-type 3 63:61 Table 3 In an embodiment, The parameter codedFlagTrans is divided into three parts. For example, the first 4-bit system has a content block type of 0 or 1, and the upper 4-bit system has a content block type of 3 or 4. The upper 4 bits can be further divided into two parts, the lower 2 bits give iCbCr=0 and the other 2 bits give iCbCr=l. The parameter predMode has one of three options: predLO = 0, predL 1 = 1, and NiPred = 2. The 6D shows an embodiment of the parameter refldx structure of Reference Table 2 and Table 3. Note the parameter refldx and the reference map used in image restoration

Clienfs Docket No.: S3U06-0014-TW TT’s Docket No:0608-A41247twf.doc/NikeyChen 54 200821982 Like the index of the list. The above-mentioned knots ^μ 曰 , - mildew &amp; for the memory and logic circuit. As shown in the figure, the structure of the grammatical components of the five, + 丄I π includes the top column 009 of the giant python area i, the macro block block partition danmu block ϋ 11 (such as the four areas shouted), l〇 / li The value 613 and the value of each L0/L1 value are stored in the office-a bribe deposit value GtO (greater than 0) 615 and the storage bit value Gtl (greater than 1) 617, 017. Typically, the top neighbor f macroblock 609 needs to be accessed, whereas the bottom column of the macro block is also accessed, which is divided into 4X4 square arrays - an embodiment, resulting in four mbPartlt brains 611. For each pool leg 611, the L〇/U value (1) message is determined, but not a consistent value. About L〇 and U value is i or greater than! The judgment is decided. In the embodiment, mosquitoes are obtained by storing (10) 615 and (8) 617 two-dimensional elements, which are (4) calculated grammatical components. The further step is to illustrate the calculation of the syntactic component structure and the two optimizations are performed. In the -optimization, only 2 bits are maintained (although the reference value is conventionally large), and no more bits are needed for the variable length decoding unit to compute the decoding of the syntax components. Decode all values and maintain the execution unit's temporary memory or memory (for example: L2 cache). Only three elements are maintained for the third optimization (for example, two at the top and two at the left). The four elements are recycled, and the last value is written in the neighborhood by the CWRITE command, which is stored in memory. Thereafter, only 16 bits are maintained in the mbNeighCtxCmrent register 603, and only 8 bits are maintained in the mbNeighCtxLeft register 605 and the top mbNeighCtx element 601 of the array. The storage logic uses re-storage because all calculations of the decoded reference value are replaced by Boolean operations with fewer bits. The mb_type includes the following list four.

Client's Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 200821982 mbjype name 4,b000 SI 4,b001 I_4x4 or l__NxN 4'b010 1-16x16 4'b011 LPCM 4,b100 P_8x8 4, B101 B-8x8 4'b110 B-Direct__16x16 4'b111 Others Table 4 does not show that the extra scratchpad in Figure 6B can be used, such as mbPerLine (eg 8-bit, no sign), mb-qp-delta ( 8-bit, with sign), and mbAddrCurr (16-bit, current macro block address). For mbAddrCurr, the 1920x1080 array is implemented, although it only requires 13 bits. Some embodiments will use 16 bits to aid in the execution of 16-bit calculations. Values from the previously described scratchpad are also stored in the overall register 614. The values stored in the overall register 614 are copied and stored in the scratchpad to aid in hardware design. In one embodiment, the overall scratchpad 614 includes a formatted 32-bit scratchpad to contain values corresponding to mbPerlhie, mbAddrCurr, and mb_qp-delta, except for other values corresponding to NUT, MBAFF_FLAG, and chroma_format_idc. Outside. The different fields within the overall scratchpad 614 can be updated using the INSERT instruction. The exemplary format of the INSERT instruction is described as follows: INSERT DST, #Imm, SRC1 In the above INSERT instruction, an embodiment of #Imm includes a 1-bit number, where the first 5-bit width data and the above 5-bit designation

Clienfs Docket No.: S3U06-0014-TW TT’s Docket No:0608-A41247twf.doc/NikeyChen 200821982 ^The location where the data was inserted. Input parameters include the following:

Mask = NOT(0xFFFFFFFF«#Imm[4:0])

Data = SRC 1 &amp; Mask SDATA = Data«#Imm[9:5] SMask = Mask«#Imm[9:5]

f I Output: DST can be expressed as follows: : DST = (DST &amp; NOT(sMask)) I SDATA Need to notice some interceptions (for example: NUT ( NAL_UNIT_TYPE ), C ( (constrained an intra-pred one) The flag ) ) , MBAFF_FLAG, mbPerLine, and mbAddrCurr values may also be written/initialized to the overall register 614 using the INIT-CTX instruction. In an embodiment, the local register 612 includes a 32-bit scratchpad having Corresponds to b, mb_qp-delta, numDecodAbsLevelEql, and numDecodAbsLevelGtl. These fields can be updated using the INSERT instruction. Local register 612 is also initialized so that b2, mb-qp-delta^O, numDecodAbsLevelEql=- l and c) numDecodAbsLevelGtl = 0. The instructions used to provide initialization can use the following format: C WRITE SRC1 , where SRC 1 [15:0] = mbAddrCurr. CWRITE SRC1 updates the mbAddrCurr block of the general register 614. The additional functionality provided by the CWRITE instruction will be described after the adjacent element structure and its simple description of decoding.

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 57 200821982 In CABAC decoding, the syntax value is expected and is expressed from the block _° How to decode the =r30a embodiment to determine the left and above adjacent macroblocks to: Break the huge money is actually awkward. As described above, (4) The private order uses neighboring values (for example, from a macroblock or block to the top and to the left: to the left). In an embodiment, the binary meter: arithmetic decoding?丨 624 calculates the following equation, which uses the current number of macro blocks and is located in the first line.

(mbPerLme) The number of t macro blocks to calculate whether the address of the upper macro block and whether the left and upper macro blocks are available. For example, to determine if a neighboring macroblock (eg, left neighbor) is present (ie, valid), an operation (eg, paper_her% mbPerLine) can be performed to check if the result is 〇. In one embodiment, the following calculations can be performed: :(mbCurrAddr%mbPerLine) x mbPerLine a = mbCwrAddr - mbPerLine Note that mbCurrAddr is related to the current macro block location corresponding to the binary symbol to be decoded, and nibPerLine and each The number of macroblocks in a known column is related. The above calculation is performed using a division, a multiplication, and a subtraction. The decoding mechanism implemented by the binary computation decoding engine 624 is further described, with reference to Figure 6E, which shows the image to be decoded (16χ8 macroblock and mbPerLine 2). When decoding the 35th macroblock (mbCurrent is marked 35, and the 36th macroblock has not been fully decoded)

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 58 200821982 'Requires the upper macro block from the previous decoding (marked 19) and the left macro block (marked For 34) information. The information of the upper macro block can be obtained from mbNeighCtx[i], where mbCurrent%mbPerLine. So, for this example,! = 35% 16 ’ then i=3. After the current macroblock is decoded, the CWRITE instruction can be used to update the array: mbNeighCtxLeft 605 and mbNeighCtx[i] 601. As another example, consider the following: mbCurrAddr ε [Ο: max MB-l] where, maxMB is 8192 and mbPerLine is 120. In one embodiment, in addition to being implemented by multiplying (Ι/mbPerLine), it looks up a table of memory stored on the wafer (e.g., a table of 120 x 11 bits). When mbCurrentAddr is 13 bits, a 13x11 bit multiplier can be used. In one embodiment, the result of the multiplication operation is completed, the upper 13 bits are stored, and the 13x7 bit multiplication is performed to store the lower 13 bits. Finally, a 13-bit subtraction is performed to determine "a". The entire sequence of operations is used for 2 cycles, and the results are stored for use in other operations and again when the mbCurrAddr value changes. In some embodiments, a modulo operation will not be performed, instead a colored logic circuit within the execution unit may be used to provide a first mbAddrCurr value aligned to the first line of the slice. For example, the above-described coloring logic circuit can perform the following calculation: mbAd(keun_ absoluteMbAddrCurr - η * mbPerLine ° because, 咅p is divided into η 264

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 59 200821982 / Flexibility Macroblock Ordering (FMO) mode has some very complicated neighboring structures for copying These modes, the left/upper availability can be calculated in the extra shader of the decoding system 2, and loaded into one or more registers of the variable length decoding unit 530a. By leaving the load variable length decoding unit 530a, the complexity of the hardware can be reduced when all H.264 modes are activated for symbol decoding. The 'CWRITE instruction copies the appropriate block from mbNeighCtxCurrent 603 to mbNeighCtxTop[] 601 and mbNeighCtxLeft[] (eg, the left macro block of array 564 depends on whether mBaffFrameFlag (MBAFF) is set and whether the current and previous macro blocks are blocked. Or the frame corner code 'is specific mbNeighCtxTop[] 601 and mbNeighCtxLeft[] data is written. When (mbAddrCurr % mbPerLine = = 0) is established, the mark mbNeighCtxLeft 605 is not available (for example, it is initialized to 〇). The CWRITE instruction may remove the contents of the mbNeighCtx memory 564, the local register 612, and the overall register 614. For example, the CWRITE instruction moves the related content of the adjacent content memory 564 to the i-th macroblock (eg, mbNeighCtx[i Or the left and upper blocks of the current macroblock, and also clear the mbNeighCtxCurrent register 603. As described above, the upper indicator 607c and the left indicator 607b are related to the adjacent content memory 564. In the CWRITE instruction After that, the upper index is incremented by 1, and the contents of the current macro block are moved to the upper position and the left position within the array. The above mechanism may reduce the read / write memory when the read / write of the number of ports in the array. INSERT command may be used to update the contents of adjacent memory 564, local

Client’s Docket No·: S3U06-0014-TW TT,s Docket No:0608-A41247twf.doc/NikeyChen 60 200821982

as stated before. For example, the contents of the INSERT register 612 and the overall register 614, for example, an INSER instruction can be used (for example)

SmbNeighCtxCurrent-1, #Imml05 SRC1) to write the current giant block. Subsequent operations will not affect the upper indicator 60 and the left: the second two (ie, only write to the current position).

The INSERT command and the update from the binary computational decoding module 624 are broken into the mbNeighCtxCiirrent array 601 adjacent to the inner cell 564. The left indicator 607b points to the element of the memory 564, which is identical to the adjacent (near mbNeighCtx 601) array element (i.e., mbNeighCtx[i-l]). In view of the above regarding the content and model information, the binary calculation decoding module 624 and the calculation decoding will be discussed below based on the content and model information. The binary calculation decoding module 624 operates under the BARD instruction. The dry format of the BARD instruction is described as follows: BARD DST, SRC2, SRC1 It provides a binary calculation decoding operation in which each binary repeat decoding results in a single bit output. The input parameters are described as follows: SRC1 = binldx/ctxldx, to obtain the output of the content module 622; and SRC2 = bypassFlag, which is the output of the binary module 62〇. When using a forward register, an exemplary format may include BARD.FI.F2' which indicates a forwarding register. If you don't get one or two pairs

Client’s Docket No·: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 200821982 The forwarding flag should be 'silk_hair register, not manufactured. It is noted that the binary offset decoding module 624 also receives the weight (4) as described by the heart. After receiving the reset signal, the binary calculation decoding module phantom maintains the reset signal and receives the first-to-cut BARD signal. 1 In transport f: a carry-to-count decoding module 624 receives the |content index, the ctxldx value, and the indicator to the current bit analysis location from the retrieved content module milkpock decoding bitstream (bmldx). The binary calculation decoding module uses the partial privacy and range values from the code length offset register _ and the code length range temporary storage 606 to record the current interval state of the decoding engine (offset, offset + range) ). The binary calculation decoding module 624 uses the content index value to access the table of contents (CTX_TABLE), which in turn is used to access the target state pStateIdx and the high likelihood symbol value. Tateldx used (eg, from a form stored on the remote or on-wafer memory) to read the low probability symbol sub-values, T-high probability symbol values, and possible values for the next low probability symbol . Based on the state of the high likelihood symbol value, the next range, and the likelihood information, the binary calculation decoding module 624 calculates the high likelihood symbol value of the current binary symbol. The binary calculation decoding module 624 rotates the binary signals (bits or binary values, e.g., b〇, bi, ... bn) to the binary string register 616. The program is then repeated for the same or different content of the next binary, such as from the binary string register 616 to the feedback connection 658 of the retrieved content module 622. The binary calculation decoding module 624 updates the offset and the range value and possibly based on the selection of the high probability symbol value.

ClientDocket No.: S3U06-0014-TW TT s Docket No:0608-A41247twf.doc/NikeyChen 62 200821982 and =:ΐ=::Τ 624 will present the high possibility of this trait into the table of contents for later / Endure about forwarding register F1 and forwarding. Use, when the signal is forwarded, the command may be the same as the F2's = port, when the slave is purely _ hairline = yes = ° &gt; and there is a delay, and can be issued in the next cycle GCT = 622 The acquired content module 622 is forwarded to the binary computing decoding building. In use from . to 4 cycles. When a gctx, 24 is issued in the cycle, a B-order command is issued. The = command of the useful instruction fills in 4 views. In the delay decoding module 624 from the binary module 62q, there is no delay to the decoding module 624 forwarded to the acquired content module 622 = carry calculation

Two β:: can be issued in the period 〇+5) two S: I bit string is reserved and the binary calculation decoding module 丄-the carry group 620 has a switchover, then there is no extension: the binary string , can allow the issuing of BAR...ard means: i, bypassing the delay of the fork. The CAVLC decoding has described a variable length decoding unit 3 for CABAC decoding. The above will be referred to as a CAVLC embodiment of the decoding system, which is also referred to as a variable length decoding unit 5, such as the first The figure shows: Before the fantasy field CAVLC architecture, the first simple description of the variable length decoding

Clienfs Docket No.: S3U06-0014-TW TT^s Docket No: 0608-A41247twf.doc/NikeyChen 63 200821982 The H.264 CAVLC program of the contents of element 530b. It is known that the CAVLC program encodes the level (e.g., size) of the signal about the macroblock or its location, and when the level is repeated (e.g., how many cycles) to avoid the need to decode each bit. The bit stream 562b receives and analyzes the above-described lean, wherein the buffer is filled when the information is used by the decoding engine of the decoded variable length decoding unit 530b. Variable Length·Decoding The unit 530b reverses the encoding process and reconstructs the signal by learning the macroblock information with the level and run coefficients from the received bit stream. Therefore, the variable length decoding unit passes the bit stream buffer 562 to receive the macro block and analyzes the stream to obtain the level and the running value to the level and the temporary storage of the running array. For example, the fly-in and run-out array read corresponds to the block in the macroblock: zone:: prime then clears the level and runs the array for use by the next block. , = = 64 standard, software can use all the giants according to 4x4 building blocks. Now provide a general description about decoding macro block information. * CAVLC decoding program can be used in two columns 530b different components , can be in line with the real 1 and early code unit knife Dingkoukou | do not apply all kinds of considerations. Those skilled in the art will recognize that many of the following terms used in the second test are based on the h.264 specification 'for =, unless it is helpful to understand the different procedures and/or narration, one step description . Will be done again. Figure 7A shows the variable length decoding unit 53 (^-麻> block diagram. Figure 7A shows a single variable length two = example of the square 1 兀 530b, and single

Client's Docket No.: S3U06-0014-TW TT's Docket No: 0608-A41247twf.doc/NikeyChen 64 200821982, - Μ length decoding single s (four) heart in the f. The same principle can be used in the library, and the early 70-symbol system of the variable length decoding unit shows the selected elements of the variable length decoding unit 530b, and the 7th B system shows the CAVLCM^ Main # 兀 ' ' 隹 △ △ 的 的 的 的 △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △

It can be applied to various block decodings, and the same part I can be further inserted. The dual length decoding unit 53Gb is used to analyze the bit stream, initialize the decoding hard memory and the scratchpad/memory structure, and stage_run decoding. The above functions of the above-mentioned H.264 standard CAVLC decoding program will be described step by step. Regarding the bit stream buffer operation, the SREG stream buffer/DMA engine 562 is shared between the CABAC and cavlc operations, so the description will be omitted for the sake of brevity, except for the face, and the operational differences between the CABAC and CAVLC modes. The same part. Both CABAC and CAVLC decoding use the same content memory 564, but block

Bits (eg, structures) are not the same, which will be described later. Therefore, when the content memory 564 of the CAVLC operates similarly to the caBAC operation described above, the same portions will not be further described for the sake of brevity. In addition, the overall register 614 and the local register 612 are also used, and thus the same portions will not be further described. Referring to FIG. 7A, the variable length decoding unit 530b includes different modules of the hardware, including a token module (coeff_token) 710, a level code module (CAVLC-LevelCode) 712, and a level module. (CAVLC-Level) 714, Positioning Module (CAVLCJL0) 716,

Clients Docket No.: S3U06-0014-TW TT^s Docket No:0608-A41247twf.doc/NikeyChen 65 200821982, Zero Position Module (CAVLC_ZL) 718, Operation Module (CAVLC_Run) 720, Level Array (LevelArray) 722 and RunArray 724. The decoding system also includes a SREG stream buffer/DMA engine 562, an overall register 614, a local register 612, and a neighboring content memory 564 as previously described. The interface of the variable length decoding unit 530b. and the execution unit 420a includes one or more target buss and corresponding registers (eg, target registers) of the CABAC embodiment as described above and two sources. Stream &quot; stream and the corresponding scratchpad (SRC1 and SRC2, etc.). Generally, depending on the type of segment, the driver software 128 (Fig. 1) prepares and loads the CAVLC shader to the execution unit 420a. The CAVLC shader is used to display the command set plus an additional instruction set 'including coeff token, CAVLC A LevelCode, CAVLC-Level, CAVLC-L0, CAVLC-ZL, and CAVLC-Run instructions are used to decode the bit stream. The instructions of the quotation include READ-LRUN and CLRJLRUN instructions for the read and clear operations of the level array 722 and the run array 724. In one embodiment, the first instruction executed by the CAVLC shader includes an INIT-CTX instruction and an INIT-ADE instruction prior to issuing other instructions. These two instructions initialize the variable length decoding unit 530b to decode the CAVLC bit stream and load the bit stream from the index that automatically arranges the string decoding to the FIFO buffer, which will be described later. Thus, variable length decoding unit 530b can be used to analyze the bit stream, initialize the decoding hardware and register/record constant structure, and stage-run decoding. The CAVLC decoding of the 264264 standard = the above-mentioned functions of the sequence will be further described later.

Client's Docket No.: S3U06-0014-TW TT s Docket No:0608-A41247twf.doc/NikeyChen 66 200821982. The instructions for analyzing the bit stream are used in addition to the READ and INITJBSTR instructions previously described in the CABAC program. In addition to the program, there are two other instruction analysis bit stream accesses that are more related to the CAVLC program, namely the INPSTR instruction (corresponding to the check string module 570) and the INPTRB instruction (the previous load to the variable in the 5C picture) Length decoding logic 550). The INPSTR instruction and the INPTRB instruction do not need to be limited to CAVLC operations (for example, the above instructions can be used in other programs such as CABAC, VC-1, and MPEG). Use the INPSTR instruction and the 1 INPTRB instruction to detect whether a specific pattern (eg, data start or end pattern) appears in a fragment, a macro block, etc., to enable the entry of the bit stream without the need Perform a bit stream. In one embodiment, the order of the instructions includes the implementation of INPSTR and INPTRB and then the READ instruction. The irregular format of the INPSTR instruction is described as follows:

INPSTR DST wherein, in one embodiment, the bit stream is checked and passed back to the lower 16 bits of the target register of the SREG register 562a^. The upper 16 bits of the target buffer contain the sREGbitptr value. Due to this operation, the data is not removed from the SREG register 562a. The INPSTR instruction can be implemented according to the following pseudo-code (pseudocode): MODULE INPSTR (DST)

OUTPUT [31:0] DST

DST - {ZE (sREGbitptr), sREG [msb: msb-15]}; ENDMODULE

Client's Docket No.: S3U06-0014-TW TT^ Docket No:0608-A41247twf.doc/NikeyChen 67 200821982 Another instruction to analyze the bitstream is the INPTRB instruction, which checks the raw byte sequence payload. RBSP) Trailing bits (such as a bit stream arranged in a byte). The INPTrb instruction provides a read of the bit stream register 562b. The exemplary format of the INPTRB instruction is described below: INPTRB DST. In the INPTRB operation, no bits are removed from the SREG register 562a. ^ When the south significant bit of the SREG temporary 562a contains, for example, 1 〇〇, the SREG temporary state 562a contains the RBSP stop bit, and the remaining bits in the byte are alignment zero bits. The INPTRB instruction can be implemented according to the following exemplary pseudo code: MODULE INPTRB(DST) OUTPUT DST; REG [7:0] P; P = sREG [msb: msb-7];

Sp = sREGbitptr; T [7:0] = (P » sp) « sp; DST[l]-(T = -0x80)? l:〇;

DST[0] = ! (CVLC_BufferBytesRemaining &gt;0); ENDMODULE Provides the RE AD instruction for data alignment in the bit stream buffer 5 62b. The extra bit string buffering of the variable length decoding unit 530b will now be described.

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 68 200821982 The device operation will now describe the initialization of the CAVLC operation, especially the memory, the scratchpad structure and the decoding engine ( For example: initialization of CAVLC mode, and 5 8 2 ). The global register 614, the local register 612, and the CAVLC module 582 are initialized at the beginning of the segment and before decoding the syntax components corresponding to the first macroblock register structure. In one embodiment, the driver software 128 issues an INIT-CAVLC instruction for initialization. The exemplary format of the INIT-CAVLC instruction is described as follows: INIT—CAVLC SRC2, SRC 1

Where 'SRC2 includes the number of bytes decoded in the fragment data. Its value is written in the internal CVLC-bufferBytesRemaining: SRC1 [15:0] = mbAddrCurr ; SRC1 [23:16] = mbPerLine ; SRC 1 [24] = constrained—intra—predflag ; SRC 1 [27:25] = NAL -unit-type (NUT); SRC1 [29:28] = chroma-format-idc (----------------- Other sampling mechanisms); and SRC1 [31:30]=undefined. Regarding the INIT-CAVLC instruction, the value in SRC1 is written to the corresponding bit in the overall register 614. Furthermore, the value in SRC2 is written to the internal scratchpad set by the INIT instruction (for example: CVLC_bufferByteRemaining register). use

Clients Docket No.: S3U06-0014-TW TT^ Docket No:0608-A41247twf.doc/NikeyChen 69 200821982 • CVLC—bufferByteRemaining register to restore any error bit stream, as described above. For example, variable length decoding unit 53A (e.g., SREG stream buffer/DMA engine 562) records information that analyzes buffer bits in the bitstream of a known slice. When a bit stream is used, the variable length decoding unit 530b counts and updates the CVLC_bufferByteRemaining value. When the value is below 0, the value below 〇 indicates the end of the buffer or bit stream error 'prompt processing' and returns to application control or is controlled by the driver software 128 to handle the recovery. : The INIT-CAVLC instruction also initializes the variable length decoding unit 530b

Different storage structures, including adjacent content memory 564, mbNeighCtxLeft register 605, and mbNeighCtxCurrent register 603, which are similar in some respects to the previously described CABAC program. Knowing the content nature of CAVLC decoding, the current macroblock is decoded according to the information collected by the CAVLC_T〇TC command when decoding the macroblock, that is, the left macroblock is stored in the left mbNeighCtxLeft register. 605 is pointed to by indicator 607b, and the upper macroblock is stored in array element (1) 6〇1 and pointed to by indicator 607c. The upper indicator 607c and the left indicator 607b are initialized using the INIT_CAVLC instruction, and the overall register 614 is updated. In order to determine whether a neighboring macroblock (eg, left neighbor) is present (ie, valid), an operation can be performed by the CAVLC-TOTC instruction (eg, mbCurrAddr% mbPerLine), which is similar to the same procedure performed in the CABAC embodiment, thus Will not be described. Similar to the described CABAC program, the contents of the adjacent content memory 564 can be removed using the CWRITE instruction, and the INSERT instruction can be used.

Clients Docket No.: S3U06-0014-TW TT's Docket No: 0608-A41247twf.doc/NikeyChen 70 200821982 Update the content of the adjacent content memory 564, the local register 612, and the overall register 614, where the INSERT instruction can be used to For writing to the mbNeighCtxCurrent register 603. The structure of the data maintained in the adjacent content memory 564 can be described as follows: , mbNeighCtxCurrent[01:00] : 25b : mbType i mbNeighCtxCurrent[65:02] : 4?b : TC[16] mbNeighCtxCurrent[81:66] : 45b ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Length decoding unit 530b initial content memory structure and initialization, how variable length decoding unit 53A (especially CAVLC-TOTC instruction) uses neighboring content information to calculate total coefficient (TotalCoeff, TC), which will be described later Used to determine whether a CAVLC table should be used to decode symbols. Typically, CAVLC is decoded using a variable length decoding table (herein referred to as a CAVLC table) described in the H.264 specification, "based on previously decoded symbols" The content selects the CAVLC table to decode each symbol. That is, for each cell symbol, it is a different CAVLC table. Figure 7B shows the basic table structure, which is a variable size two-dimensional array. Providing an array table (each table is a particular symbol ^), and each symbol Huffman table (Huffman) encoding Huan Huffman code is stored as the following structure: struct Table {unsigned head;

Client^ Docket No.: S3U06-0014-TW TT’s Docket No:0608-A41247twf.doc/NikeyChe] 71 200821982 struct table { unsigned val; unsigned shv; }table[]; }Table[];

I. A method for matching (MatchVLC function) according to a unique prefix encoding will be described below. Generally, a CAVLC table includes a variable length portion and a fixed length portion. The alignment can be simplified by performing some fixed-size index lookups. In the MatchVLC function, the READ operation can be performed without removing the bit from the SREG register 562a. Therefore, for the bit stream buffer 562b that processes the bit stream, the READ operation is different from the READ instruction described above. In the MatchVLC function described below, some bits (fixL) are copied from the bit stream buffer 562b and then looked up in a specified table. Each item in the specified table contains a specific format (for example: value and size in bit type). Use the size of the project to make a bit stream. FUNCTION MatchVLC(Table5 maxldx) INPUT Table; INPUT maxldx;

Idxl = CLZ(sREG);//count number of leading zeros Idxl = (Idxl &gt; maxldx)? maxldx : Idxl; fixL = Table[Idxl].head; SHL(sREG,Idxl+#1); //shift buffer Idxl + 1 bit left

Client’s Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 72 200821982

Idx2 - (fixL)? 0 : READ(fixL); (val5 shv) - Table[Idxl][Idx2]; SHL(sREG,shv); return val;

ENDFUNCTON

I Fig. 7B is a block diagram showing an exemplary two-dimensional array of the above table structure for describing the MatchVLC function in the content of CAVLC decoding. An example when nC == -1 is obtained from Table 9-5 in the H.264 standard, which is described as follows:

Coeff—token TrailingOnes TotalCoeff Head Value Shift 1 1 1 〇33 0 01 ^ 0 Infertile; 0Π 001 2 2 〇66 0 000100 -/000101 person; 卞000110 ΐ 〇:f ^ 12 ' , 1 , 2 / ' -T - _, 2 rounds 4 000111 r ' 000010 0 4 1 4 1 000011 0 3 3 1 -—---- 1 0000010 0000011 : ^ 3 1 — 67 Esmr 00000010 2 4 1 68 —1.β 1 00000011 1 &quot;&quot;^&quot;77 ~ &quot;^7&quot;&quot;&quot;............. 4 36 I ^Γ^ Face: 妗, 卜转Q霸 in pseudocode (pseudocode) The above table can be expressed as follows Table9_5[8] = { 〇, {{33,0}}, 〇, {{〇,〇}}, 〇, {{66,0}},

Client's Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 73 200821982 2, {{2, 2}, {99, 2}, {34,2}, {1, 2}} , 1,{{4, 1},{3, 1}}, 1,{{67, 1}"35, 1}}, 1,{{68, 1},{36, 1}}, 〇, {{1〇〇, 〇}} }; Using the above table structure, the above-mentioned MatchVLC function can be used to implement CAVLC decoding. Due to the MatchVLC function, the bit stream is executed to access the known syntax components. Further, by calculating whether the value of the leading zero is greater than the maximum value of Idx, the MatchVLC function can initiate a computational pre-derivative operation (eg, in some embodiments, using the pre-computation module 576 and the reading module 572), Then return to maxldx (the case for which it is handled is 0000000, as shown in the table in Figure 7B). Another advantage of the MatchVLC function and table structure is that no multiple instructions are needed to handle these situations, which are handled by the MatchVLC section below. :Idx 1 = CLZ(sREG) Calculates the number of leading zeros, and Idx 1 = (Idx 1 &gt; maxldx)? maxldx : Idxl. Next, use the following section of the MatchVLC function to remove the used Bits: SHL(sREG, Idxl+#1). Use the following MatchVLC section to read the header of the sub-array: fixL = Table[Idxl].head, and Idx2=(!fixL)? 0 : READ(fixL), which transfers the maximum number of bits to be read indefinitely. The leading 〇 can be the same, but the size of the trailing bits can be changed. Therefore, in one embodiment, the CASEX category description can be implemented ( Use more memory, but a simpler code structure).

Client’s Docket No.: S3U06-0014-TW

Docket No:0608-A41247twf.doc/NikeyChen 74 200821982 : Use (val,shv) = Table[Idxl][Idx2] and SHL(sREG,shv) to read the actual value of the table, which also shows how many bits are actually The grammatical component is used. These bits are removed from the bitstream and the value of the syntax component is returned to the target scratchpad. The method of VLC matching and the configuration of the table structure have been described, and then reference is made to Figure 7A to describe the CAVLC decoding engine or program (e.g., CAVLC module 582). Once the bit stream is loaded, and the decoding engine, memory structure, and scratchpad are loaded, 'the CAVLC-TOTC command can be issued by the driver software 128 to activate the coefficient register module 71. In one embodiment, the CAVLC_TOTC instruction has the following exemplary format: CAVLC_TOTC DST5 S1 where 'S1 and DST respectively include an input register and an internal output register, having the exemplary format provided below: SRC1 [3: 0] = blkldx SRC1 [18:16] = blkCat SRC1 [24] = iCbCr The remaining bits are undefined. The output format is described as follows: DST [31:16] = TrailingOnes DST [15:0] - TotalCoeff Therefore 'as shown in the figure', the coefficient register module 71 receives an indication corresponding to mbCurrAddr, mbType, whether the chroma channel is being processed. (for example: iCbCr ), and blkldx (for example: block index, because the image can be divided into many blocks). For known macroblocks accessed from the bitstream buffer 562b, blkldx is transmitted, whether it is an 8x8 pixel block or 4x4

Client's Docket No.: S3U06-0014-TW TT^ Docket No:0608-A41247twf.doc/NikeyChen 75 200821982 The pixel block is being processed at a known location. The above information is provided by the driver software 丨28. The coefficient signature module 710 includes a lookup table. According to the lookup table input to the coefficient register module 710 as described above, the number of trailing coefficients (TrailingOnes) and the number of η of non-zero coefficients (TotalCoeff) can be obtained. TrailingOnes transmits how many 1s are in a column, and T〇taic〇eff transmits how many run/level pair coefficients are on the block data extracted from the bitstream. TrailingOnes and TotalCoeff are provided to CAVLC level module 714 and zero level module 718c, respectively. Trailing〇nes are also provided to level 0 module 716, which corresponds to the first bit retrieved from bit stream buffer 562b. Quasi (for example: direct current (DC) value). The level module 714 records the length of the suffix of the symbol (eg, the number of trailing 1), and the level module 7丨4 combines the level code (levdc〇de, to calculate the level value (leV_X))' The scale values are then stored in the level array 722 and the run array 724. The level module 714 operates under the CAVLC-LVL command and has the following format: CAVLC_LVL DST, S2, S1, where: 51 - Idx (16-bit) 52 ^ suffixLength (16-bit); and DST = suffixLength (16-bit) 〇 suffix length (suffixLength) The large J of the transmitted codeword (c〇dew〇rd), why. The input from the driver software 128 provides the designation The length of the suffix length J, in addition, in an embodiment, because the suffix length value is ^,

Clienfs Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 76 200821982 ·· DST and Μ can be selected as the same register. It is further noted that 'forwarding registers (e.g., maintaining data generated internally by known modules) can also be used, such as F1 and F2. The instruction is indicated by a forwarding flag within the known command and whether the corresponding module uses the forwarded staging j symbol F1 (ie, the value of the forwarding source 丨 is used, which may be indicated by bit 26 in the command in an embodiment). And the symbol F2 (i.e., using the value of forwarding source .2, as indicated by bit 27 in the instruction in one embodiment) may indicate that f% forwards the temporary descent. When using the forward register, the CAVLC_LVL· command can (^ have the following exemplary format: – CAVLC LVL.F1.F2 DST, SRC2, SR1, where when F1 is not F2 is set (for example, established), the specified forwarding The source is treated as an input. In the case of level module 714, forwarding register F1 corresponds to a level index (level[Idx]) generated by level module 714, which is incremented in an increment module. And input to the multiplexer 730. Similarly, the forwarding register F2 corresponds to the suffixLength, which is generated by the level module 714 and input to the multiplexer 728. The multiplexer 730 and the multiplexer 728 Other inputs include an execution unit register input (labeled EU in Figure 7A), as described below. The other input to the level module 714 is the level code provided by the level code module 712. The combination operation of the quasi-code module 712 and the level module 714 decodes the decodable level value (the level is the conversion coefficient value before scaling). The instruction can be enabled by the instruction with the following exemplary format.

Client's Docket No.: S3U06-0014-TW TT’s Docket N〇: 0608-A41247twf.doc/NikeyChen 77 200821982 Code Module 712. CAVLCJLC SRC1 , where SRC 1 = suffixLength (16 bits). When using the forward buffer F1, the command can be expressed as follows: r » CAVLC_LVL.F1 SRC1, where if 卩1 is set, the forward 3 feet 01 is treated as an input. As shown in the figure of the seventh person, when F1 is set (e.g., FI = 1), the level code module 712 obtains the forwarded SRC1 value (e.g., the suffix length from the level module 714) as an input, otherwise the input is from Obtained by the execution unit register (for example, F Bu 0). Returning to the level module 714, the suffix length input can be forwarded by the level module 714 via the multiplexer 728 or via the execution unit register multiplexer 728. In addition, the Idx input can also be forwarded by the level module 714 via the multiplexer 730 (and incremented by the incremental module, or in some embodiments, can be automatically incremented without incrementing the module), or via execution. The unit register is provided by the multiplexer 730. Furthermore, the level module 714 also receives the level code input directly from the level code module 712. In addition to the output to the transfer register, the level module 714 also provides a level index (level[idx]) output to the level array 722. As mentioned earlier, TrailingOnes outputs to level 0 module 716. The level register module 716 is enabled via the following instructions:

CAVLCJLVLO SRC

Client's Docket No.: S3U06-0014-TW TT^ Docket No: 0608-A41247twf.doc/NikeyChen yg 200821982, where SRC = trailingOnes(coeff-token). The output of the level module 716 includes a level index (Level[Idx]) that is provided to the level array 722. The coefficient value is encoded as a sign and a size. The register module 716 provides a positive value for the coefficients. Combined with the CAVLC level module 714

The I size value and the sign value from the level register module 716 are: written to the level array 722. Use the level index (levei[idx]) to specify the location of the write. In one embodiment, the coefficients are within a 4x4 matrix of sub-blocks (blocks 8x8), not in raster order. The array is then converted to a 4x4 matrix. In other words, the decoded coefficient level and operation are not raster format. From the level-run data, the 4x4 matrix can be reconstructed (but in the orthodontic scan order) and then rearranged into a raster order of 4x4. The TotalCoeff output from the coefficient register module 710 is supplied to the zero position module 718. The zero level module 718 can be enabled via the following instructions: CAVLC_ZL DST, SRC1 where SRC1 = maxNumCoefi (16 bits) and DST 2 ZerosLeft (16 bits). maxNumCoeff is given by the H.264 standard and is resent as the original value of the instruction. In other words, maxNumCoeff is set by the software. In some embodiments, maxNumCoeff can be stored in hardware. The transform coefficients are encoded into a (level, run) format that is related to the number of coefficients (levels) that are encoded as zero. The zero level module 718 provides two outputs, ZerosLeft and Reset (reset = 0), which are provided to the multiplexer 740 and the multiplexer 742, respectively. The multiplexer 740 also receives from

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 79 200821982 . The forwarding register F2 of the running module 720. The multiplexer 742 receives the forwarded register F1 from the run module 72G that has been incremented (in some embodiments, via an incremental module or otherwise). The run module 720 receives ZerosLeft from the multiplexer 74A and the multiplexer 742, respectively, and the Idx input and provides a run index (R, un[Idx]) output to the run array 724. As described earlier, because the run length encoding is used for further compression, the coefficients are encoded into a (level, run) format. For example, suppose you have the following values: 1〇12 12 15 19丨丨1(3)(4)(10) '10, then you can encode it as (1〇,〇) (12J) (15,〇) (19,〇) U,2) ( 〇, 5) (1,0) (〇, 〇). This code word is usually shorter. The index is the corresponding index of the level index. The run module 720 can be enabled via the following instructions: CAVLC - RUN DST, S2, S1, wherein DST and S2 can be selected as the same register since the ZerosLeft value is updated. Therefore, the demonstration of the CAVLC-RUN instruction does not have a sign value as follows: , SI = Idx ( 16-bit), S2 two ZerosLeft ( 16-bit), DST = Zerosleft (16-bit) 〇 Refer to Figure 7A, Forwarding The memory is used, in which the CAVLC_RUN instruction can be obtained in the following format: CAVLC.F1.F2 DST, SRC2, SRC1

Client’s Docket No.: S3U06-0014-Ding W

TT^ Docket No: 0608-A41247twf.doc/NikeyChen gQ 200821982 'where' When F1 is not F2 is set as a round. Then the appropriate forwarding source. For the two register temporary columns, the level alignment array 724 corresponds to the operation. In j corresponds to the level, and the element,. For the level array 722, the two or two arrays contain 16 positive and negative signs. Use the following instructions to read the level and run values from the level array and column 724, respectively. Dry ~... and run array READ_LRUN Dst , where, in one embodiment, the dst operation takes a variable length decoding unit, θ 叩). The above \ scratchpad is stored to the target scratchpad. When this: quasi H and run the scratch register, the run value is converted to 16 bits, saying that the first two registers maintain 16 levels of 16 bits =. The array stores the first 16 coefficients), while the third and fourth temporary crying = 5 has been thought. In a case, the values are written in the following order: in the first register, the least significant 16 bits contain the LEVEL [〇] value, and the bit 22 contains the LEVEL [1] value, etc. until the bit 112·127 contains the LEVEL[7] value. Next, for the first register pair, the least significant 丨6 bits include LEVEL[8] and so on. The same method is applied to the run value. According to the following exemplary instruction format, the CLR-LRUN instruction can be used to clear

Clienfs Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 200821982 In addition to the level array 722 and the register that runs the array 724. The software (shading program) and hardware operations (e.g., modules) of the variable length decoding unit 530b described above, particularly the CAVLC module 582, can be described using the following pseudo code.

L

Residual_block__cavlc( coeffLevel, maxNumCoeff) { &quot;&quot;&quot;&quot;CLR-LEVEL-RUN ' ' coeff-token if( TotalCoeff( coeff_token) &gt; 0) { _if(TotalCoeff(coeffJoken)&gt;l〇&amp;&amp; TrailingOnes(coeffjoken) &lt;3) suffixLength = 1 Else &quot; suffixLength = 0 CAVLCJevelOQ; _f〇r( I = TrailingOnes(coefF_taken); I &lt; TotalCoeff( coeffjoken); i++){ _CAVLCJevelCode(levelCodeysufFixLength); _ _CAVLCJevel(suffixLength , i,levelCode) CAVLC^ZerosLeft(ZerosLeft, maxNumCoeff) for( i = 0; i &lt; TotalCoeff( coeffjoken) -1; i++) { CAVLC_run(i, ZerosLeft) READ_LEVEL, RUN(level, nm) mn[ TotalCoeff( Coeff—token) -1 ] = zerosLeft coeffNum = -1 fo"( i = TotalCoeff( coeff"oken) -1; i &gt;= 0; i-) { _coeffNum += run[ i ] +1 _coeffLevel[ coeffNum ] = \eye\[i] MPEG decoding The decoding system described above for CABAC decoding (variable length decoding unit 530a via CABAC module 580) and CAVLC decoding (variable length decoding unit 530b via CAVLC module 582) has been described. 200, pick up

Client's Docket No.: S3U06-0014-TW TT's Docket No: 0608_A41247twf.doc/NikeyChen 82 200821982 An MPEG embodiment of the decoding system 200 will be described below, referred to herein as a variable length decoding unit 53A. The variable length decoding unit 53A is operated in accordance with an operation performed by the MPEG module 578 (shown in Fig. 5C). For the sake of simplicity, features common to CABAC and CAVLC embodiments (including bitstream buffers and corresponding fingers, commands) are omitted, except for the following: Points to note. The INIT instruction sets the variable length decoding unit 530 to enter the MPEG mode, and uses a mixture of READ, NPSTR, INPTRB (explained above) and VLC__MPEG2 instructions to decode the MPEG-2 bit stream. The color program program determines which method to use. The MPEG-2 bit stream has a fully deterministic grammar, and the shading code performs a method for decrypting the grammar. In one embodiment, for MPEG-2 processing, the implementation table is Huffman decoded in the MatchVLC-X function, as described below. Therefore, the two instructions are loaded into the MPEG module 578, including the INIT-MPEG2 instruction and the VLC-MPEG2 instruction. The INIT-MPEG2 instruction loads the bit stream and sets the variable length decoding unit 530 to enter the MPEG2 mode. In this mode, when I, the first coefficient is direct current (DC), the overall register 614 holds the value. There are one or more streams in MPEG-2 that are identical, but have different interpretations depending on whether they are DC or parent. The bit is loaded into the VLD-globalRegister. The InitDC register is used instead of creating another instruction. Note that the scratchpad corresponding to the overall scratchpad 614 (eg, mapped to the overall scratchpad 614 (eg, globalregister[0])) is used in CABAC and CAVLC modes, but has different interpretations due to the MPEG2 mode ( And therefore the label is different). Therefore, in the macro block

Client's Docket No.: S3U06-0014-TW TT^ Docket No: 0608-A41247twf.doc/NikeyChen 83 At the beginning of 200821982, the value (the bit in the VLD-globalRegister.InitDC register) is initialized to 1. When the MatchVLC-3 function is used, whether the bit in the VLD-globalRegister.InitDC register is truncated is 1 or 〇. If it is 1, the bit is changed to 〇 for decoding by the discrete cosine transform (DCT) symbol skin after the known macro block. The above values are set by the color picker and internal reset. In the entity part, the VLD_globalRegister.InitDC bit is a flag value that conveys whether the decoded DCT symbol is the beginning of the DCT symbol of the known macroblock. f MPEG Module 578 decodes using a very specific grammar with symbols that are decoded using a defined number of Huffman tables. The analysis of the grammar is performed in a colorimeter having a particular symbol value, which is obtained using a VLC-MPEG2 instruction having a #Imm 16 value for a particular Huffman table, which should be used to decode a particular symbol . Before describing the different elements of the variable length decoding unit 530c, the hardware and the simple structure of the software structure for implementing the different tables of the MPEG-2 standard are described below. In the MPEG-2 standard (ISO-IEC 13818-2 (1995)), the codes used are defined in Tables B-1 through B-15, which are known tables provided by the MpEG_2 standard. In a different embodiment of the variable length decoding unit 53A, one or more of Tables B-1 through B-15 are implemented in a professional hardware format, such as a logical gate. Depending on the implementation (eg Hdtv, HDDVD, etc.) or the hardware arrangement required, some tables can be implemented without hardware, but other instructions can be used (eg: EXP-GOL-UD instructions that will be described later) Or through the rEad command).

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChei 84 200821982 For example, although the number of logic gates in Table B-2, Table B-3, and Table-ll-ll is not large, The addition used may require an additional multiplexer phase, which means speed and latency. In some embodiments, Tables B-5 through B-8 are not supported by hardware because they do not require support profiles. However, some of the examples can provide the above-mentioned support by referring to different instructions that have the least impact on the effect (for example: INPSTR, EXP-GOLJLJD, and READ instructions). Table B-1 (' (Macroblock— Address—increment, Table B-10 (motion_code), and Table B-9 (coded_block_pattern) have similar structures. Due to partial similarity, the above three tables can be implemented and described using the MatchVLC function executed by MPEG Module 578. For Table B-9 and Table B-10, the exemplary table structure is expressed as follows: struct Table { unsigned head; //The number of bits in the table address struct table { ( unsigned val:6; //Table In B-10, it is 5-bit unsigned shv:2; //The actual number of bits}table[]; }Table[]; For Table Bl, the exemplary table structure is expressed as follows: struct Table { unsigned head; // The number of bits in the table address struct table {

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 85 200821982 unsigned val:5; unsigned shv:3; //actual bit number}table[]; }Table[]; ϊ In the following functions: only the SHL operation can remove data from the SREG register 562a. Unlike the shader RE AD instruction, the READ function in the Match VLC function can be used to remove a bit from the SREG register 562a without removing any bits from the SREG register 562b. The following describes the use of the MatchVLC function that implements the table in MPEG-2 to provide as Hough Very Decode. FUNCTION MatchVLC—1{ T=READ(2); /骝2 bits SHL(2); · CASE(T){ 00:〇UTPUT(1); 01 : OUTPUT(2); 10:{ Q = READ (1); SHL(1); CASE (Q){ 0: OUTPUT (9); 1 :〇UTPUT(3); 11 :{ ldx = CLO(sREG);/^fS;?|*1

Idx = min(ldx,7); shv = (Idx != 7) ldx+1: Idx; SHL(shv); 〇UTPUT(4+ldx); FUNCTION MatchVLC_2{

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 86 200821982 T = READ(2); / Take 2 bits SHL(2); CASE (T){ 00 : OUTPUT( O); 01 : OUTPUT(1); 10 : OUTPUT(2); 11 :{

Idx = CLO(sREG); say ten-calculated boot 1 ΙςΙχ = min(ldx,8); shv = (Idx != 8) ldx+1 : Idx; SHL(shv); 〇UTPUT(3+ldx); FUNCTION MatchVLC_3 { INIT_MB DC = TRUE; T = CLZ(sREG); SHL(T+1); CASE (T){ 0: IF(DC){ DC = FALSE; Q = READ(1); SHL(1); 〇UTPUT ({0,SGN(Q)*1});} ELSE{ 〇=READ(1);

/ IF (!Q) {〇UTPUT({63,0}); shv=1} // E〇BV ELSE {R=READ(1);〇UTPUT({0,SGN(R)*1}); Shv=2} SHL(shv); } Q = READ (3); CASE (Q){ 1XX: OUTPUT({1, SGN(Q[1])*1}); shv = 2; 01X: OUTPUT({2, SGN(Q[0])*1}); shv = 3; 00X:〇UTPUT({0, SGN(Q[0])*2}); shv = 3; } SHL(shv); } 2:{ Q = READ(2); SHL(2);

Clienfs Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 87 200821982 CASE (Q){ 00:{ R = READ (4); CASE (R){ 000X :〇UTPUT({16, SGN (R[0])*1}); 001X : OUTPUT({5, SGN(R[0])*2}); 010X:〇UTPUT({0, SGN(R[0])*7}); 011X :〇UTPUT({2, SGN(R[0])*3}); 100X :〇UTPUT({1,SGN(R[0])*4}); , 101X:〇UTPUT({15, SGN (R[0])*1}); 110X : OUTPUT({14, SGN(R[0]ri}); 111X:〇UTPUT({4, SGN(R[0])*2}); }

Shv = 4; } 01X: SGN = READ(1); OUTPUT({0, SGN*3}); shv = 1 10X: SGN = READ(1); OUTPUT({4, SGN*1}); shv= 1 11X: SGN = READ(1); OUTPUT({3, SGN*1}); shv = 1 } SHL(shv); } 3:{ 〇=READ(3); CASE (Q){ 00X:〇UTPUT({7 , SGN(Q[0])*1}); 01X: 〇UTPUT({6, SGN(Q[0])*1}); 10X: 〇UTPUT({1, SGN(Q[0])*2 }); 11X: OUTPUT({5, SGN(Q[0])*1}); } SHL (3); } 4:{ Q = READ (3); CASE (Q){ 00X:〇UTPUT({2, SGN( Q[0])*2}); 01X: 〇UTPUT({9, SGN(Q[0])*1}); 10X: 〇UTPUT({0, SGN(Q[0])*4}); 11X: 〇UTPUT({8, SGN(Q[0])*1}); } SHL (3); } 5: Q = READ(19); OUTPUT({Q[18:13], Q[12:0] }); 6:{

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 88 200821982 Q = READ(4); CASE (Q){ 000X:〇UTPUT({16, SGN(Q[0]) *1}); 001X: 〇UTPUT({5, SGN(Q[0])*2}); 01 OX: OUTPUT({0, SGN(Q[0])*7}); 011X: 〇UTPUT( {2, SGN(Q[0])*3}); 100X: 〇UTPUT({1, SGN(Q[0])*4}); 101X: 〇UTPUT({15, SGN(Q[0]) *1}); 110X: 〇UTPUT({14, SGN(Q[0])*1}); 111X:〇UTPUT({4, SGN(Q[0])*2}); } SHL(4) ; } 7,8,9,10,11:JVLC(TabjeC[Tl); FUNCTION MatchVLC_4{ T = CLZ(sREG); SHL(T+1); CASE (T){ 〇:{ Q = CL〇(sREG ); R = min(Q,7); shv=(R!=7)R+1 :R; SHL(shv); CASE (R){ 0: S = READ(1); OUTPUT({0, SGN (S)*1}); shv=1; 1 : S = READ(1); 〇UTPUT({0, SGN(S)*2}); shv=1; 2:{ R=READ(2); SHL(2); CASE (R){ OX: OUTPUT({0, SGN(R[0]r4}); 1X:〇UTPUT({0, SGN(R[0])*5}); 3:{ R=READ(3); SHL(3); CASE (R){ 00X:〇UTPUT({9, SGN(R[0])*1}); 01X:〇UTPUT({1, SGN(R[0 ])*3}); 10X: 〇UTPUT({10, SGN(R[0])*1}); 11X: 〇UTPUT({0, SGN(R[0])*8});

Clienfs Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 89 4:{200821982 R=READ(3); CASE (R){ OXX:〇UTPUT({0, SGN(R[ 0])*9}); shv=2; 10X: 〇UTPUT({0, SGN(R[0])*12}); shv = 3; 11X: 〇UTPUT({0, SGN(R[0] )*13}); shv = 3; } . SHL(shv); } 5::{ R=READ(2); SHL(2); CASE (R){

OX: 〇UTPUT({2, SGN(R[0])*3}); 1X: 0UTPUT({4, SGN(R[0])*2}); 6 : S = READ(1); OUTPUT( {0, SGN(S)*14}); shv=1; 7: S = READ(1); 〇UTPUT({0, SGN(S)*15}); shv=1; } SHL(shv); Q = READ(2); SHL(2); CASE (Q){ OX:〇UTPUT({1, SGN(Q[0])*1}); 10:OUTPUT({63,0}); // &lt;EOB&gt; 11 : R= READ(1); SHL(1); OUTPUT(0,SGN(R)*3}); Q = READ(2); SHL(2); CASE (Q){ 00: { R = READ(4); shv = 4; CASE (R){ OOOX: 0UTPUT({1, SGN(R[0]r5}); 001X :〇UTPUT({11,SGN(R[0])* 1}) 010X: 〇UTPUT({0, SGN(R[0])*11}) 011X: OUTPUT({0, SGN(R[0])*10}) 100X: 〇UTPUT({13, SGN( R[0])*1}) 101X: 0UTPUT({12, SGN(R[0]ri})

Clienfs Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 90 200821982 110X:〇UTPUT({3, SGN(R[0])*2}); 111X: OUTPUT({1, SGN(R[0])*4}); 01 : R = READ(1); 〇UTPUT({2,SGN(R)*1}); shv=1; 10 : R = READ(1); 〇 UTPUT({1,SGN(R)*2}); shv=1; 11 : R = READ(1); 〇UTPUT({3,SGN(R)*1}); shv=1; } SHL(shv ); , } 3:{ Q = READ(3); SHL(3); CASE (Q){ 00X: OUTPUT({0, SGN(Q[0])*7}); ◦1X:〇UTPUT({ 0, SGN(Q[0])*6}); 10X: 〇UTPUT({4, SGN(Q[0])*1}); 11X: 〇UTPUT({5, SGN(Q[0])* 1}); 4:{ Q = READ(3); SHL(3); CASE (Q){ OOX: 0UTPUT({7, SGN(Q[0])*1}) 01X: 〇UTPUT({8, SGN(Q[0])*1}) 10X: 〇UTPUT({6, SGN(Q[0])*1}) 11X: 〇UTPUT({2, SGN(Q[0])*2}) 5 : Q = READ(19); OUTPUT({Q[18:13], Q[12:0]}); U 6:{ Q = READ(2); SHL(2); CASE (Q){ 00: R= READ(1); 0UTPUT({5, SGN(R)*2}); shv=1; 01 : R = READ(1); 〇UTPUT({14, SGN(R)*1}); shv =1; 10:{ R=READ(2); shv = 2; CASE (R){ OX:〇UTPUT({2, SGN(R[0])*4}); 1X: 0UTPUT({16, SGN (R[0])*1}); 11 : R= READ(1); 〇UTPUT({15, SGN(R)*1}); shv=1;

Clienfs Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChen 91 200821982 A SHL(shv); } ; 7,8,9,10,11: JVLC(TableCm); } } From above The MatchVLC function notices that the least significant bit that is usually decoded determines the sign of the value, so it can be checked using the SGN function, which is described as follows: : : : FUNCTION SGN(R){ RETURN (R 2 2 1)? 1 : 1;} It is more noticed that for MatchVLC_3 and MatchVLC-4, the table is / common (or at least a superset), so the following table can be used to access the function. FUNCTION JVLC(Table){ Q - READ(5); SHL(5); {R,L} =Table[Q]; RETURN {R,L}; } (j to the interface of MatchVLC, or should say MatchVLC_X (where The function of X equals 1, 2, etc.) is the following instruction: VLC_MPEG2 DST, #Imml6, where #Imml6 value is used to select the appropriate table, and thus to decode a specific syntax component. Use #Imml 6 as the index of the table (for example: 〇 1, 2, 3) and access the table from the instruction. The relationship between the value of #Imml6 and the corresponding method, syntax component, and MPEG-2 table is described in Table 5 below.

#lmm16方法 Syntax ^ MPEG-2VLC

Client's Docket No.: S3U06-0014-TW TT,s Docket No:0608-A41247twf.doc/NikeyChen 92 200821982 0 MatchVLC(B-1,7) MacrobIock__address_increment B-1 1 MatchVLC(B-9,8) Coded_blockjDattem B- 9 2 MatchVLC(B-10,6) Motion_code B-1〇3 MatchVLCJ Dct_dc__sizejuminance B-12 4 MatchVLC-2~' Dct_dc_size_chrominance B-13 5 MatchVLC-3 DCT coefficients (Table 0) B-14 6 MatchVLC — 4 DCT coefficients (Table 1) B-15 Table 5 EXP_GOLOMB Decoding Γ Described as CABAC decoding (variable length decoding unit 530a via CABAC module 580), CAVLC decoding (variable length decoding via CAVLC module 582) The decoding system 200 of the unit 53〇b) and the MpEG decoding (via the variable length decoding unit 53〇c of the MPEG module 578), the Exp_G〇1〇mb embodiment of the decoding system 200 will be described next, which is referred to herein as Variable length decoding unit 530d. The variable length decoding unit 53〇d operates in accordance with the operation of the EXP-Golomb module 584 (shown in Fig. 5C). The variable length decoding unit 530d uses the same hardware and the same bit stream buffer arrangement as used by the CABAC and CAVLC embodiments. Therefore, features common to the CABAC and CAVLC embodiments are omitted, except for the following points that require attention. Before describing the variable length decoding unit 53〇d, a brief description about EXP-Golomb is proposed. In EXP-Golomb, the data contains the prefix and suffix formats, as shown below: codeNum Range 1 0 ◦ 1 x〇 12

Client's Docket No.: S3U06-0014-TW TTs Docket No:0608-A41247twf.doc/NikeyChen 200821982 0 0 1 X1 0 0 0 1 X2 0 0 0 0 1 Xa 0 0 0 0 0 1 X4 x〇3-6 Xi X〇7-14 x2 Xi x〇15-30 Xs x2 Xi x〇31-62

Because most: the codeword is shorter, compression is obtained. Again, most codewords are unique and easy to decode. In H.264, there are four EXP-Golomb encoding methods used: no sign, unary, sign, and map (codewords are mapped to tables). These methods are used to encode the encoded macroblock pattern and truncation. In the variable length decoding unit 530d, a single instruction is provided to perform decoding of the EXP-Golomb code of a different type as shown in Table 6 below. The truncated EXP-Golomb decoding is described below. codeNum = EXP-GOLOMB-UD t = CLZ SHL(t+1) val = READ(t) &quot;val is not signed codeNum = 2 -1 + να/ codeNum = EXP—G〇L〇MB_CD(k〇rder) IZ := CountLeadingZero(sREG); sREG := {(sREG «(lz+1)), bitStreamBuffer[0:lz]}; J := Iz+k0rder-1; val := (J &gt;= 0)? ZeroExtend(sREG[0:J]): 0; sREG := {(sREG «(lz+1)), bitStreamBuffer[0:lz]}; codeNum := (1 «(Iz + kOrder)) + (OxFFFFFFF « kOrder) + val; Seval = EXP-GOLOMB-SD k=EXP-G〇L〇MB_UD (-1) (4) Cez7 Ask Seval = cbp = EXP_G〇L〇MB-MD(Type) k=EXP—G〇L〇 MB—UD cbp = TableCBP[Type][k]

Table 6

Clienfs Docket No.: S3U06-0014-TW TT,s Docket No:0608-A41247twf.doc/NikeyChen 94 200821982

Further explaining these instructions, the EXP_GOLOMB_UD instruction decodes a coded symbol of a . The EXP_GOLOMB_SD instruction decodes a coded symbol with a signed one-element code. As shown in Table 6, for the EXP_G〇L〇MB_SD instruction, when k is 0, there is no difference between positive 0 and negative ,, so the value returned is 0. EXP GOLOMB MD » D - (SRC1) The instruction decodes the mapped code symbol, where SR: C1 = Type, which is related to the macro block parameter and the coded_block_pattern. The value of Type will result in the following coded—block—parameter : f Type = 0 Intra 4x4

Type Inter can use a table (for example, on-wafer memory or a table in remote memory) to specify a value to coded_block_parameter according to the macroblock prediction mode (eg, code number, k). The EXP-Golomb instruction of the -Golomb symbol is further described as follows: EXP GOLOMB TD DST, SRC 1 Ci , where SRC 1 is the range. In at least one embodiment, when truncating Exp-Golomb encoding is performed, the range needs to be known first. Then, the truncated Exp-Golomb encoding can be derived as follows: codeNum = EXP_GOLOMB-TD(range){ else if(range==l) return READ(1)A1; else return EXP-GOLOMB-UE; } Therefore, The EXP_GOLOMB_D instruction is provided.

Client’s Docket No.: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 95 200821982 • It is useful to explain the difference between the transport code and the driver and software instructions. In general, when designing an ISA, there are at least two effects at work: (1) Decoding the decoding to be simpler and complete (ie, fast) in a single pipeline phase' and (2) 瓖 programmer support ( Mnem〇nics) is simpler. Referring to the operation of the five EXP-Golomb benchmarks, these operations are different from the user's point of view. Furthermore, there are two different formats: all of the EXP-Golomb benchmarks output the same value, but only some of the operations have one input (except for the bitstream contained in the operation), which provides at least one basic difference. Traditionally, CPU instructions do not have implicit input, but pass through operations including implicit input. However, the bit stream is not exposed through computation, but is internally managed automatically and initialized using the INIT instruction. From a hardware point of view, all other EXP-GOLOMB-UD operations can be performed using the same core of the same hardware hardware of the EXP-GOLOMB-UD (or at least) and small additions to the core hardware (eg in software) It is similar to the part of CASE/SWITCH). So the compiler/translator can map all operations to a single instruction. Again, these operations are fixed (for example, the \ operation does not change dynamically). Refer to the pseudonym line in Table 7 below, noting that for EXP-GOLOMB-UD and EXP-GOLOMB-SD operations, SRC 1 can be added (or ignored by the core) with mechanisms to distinguish these operations. Again, note that no single source instruction packet exists, but can be mapped to a scratchpad-immediate packet. By using a distinct immediate number of different instructions as shown in Table 7, the distinction between these instructions can be obtained, thus resulting in only one primary/secondary opcode instead of five, which includes a meaningful store. That is, only one secondary opcode is used because

Client's Docket No&quot; S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 96 200821982 You can use the immediate format command and complete the different EXP_Golomb by encoding the immediate 'data block with the appropriate data and specifying Pseudonym The difference between instructions. EXP-GOL〇MB_D Dst5 #Type5 Srcl.lane ,, which can be determined by the following list S#Type/#Type Pseudonym instruction 0x0 EXP-G〇L〇MB_UD Dst EGOLD Dst, 0x0, Src1 0x1 EXP-GOLOMB-SD Dst EGOLD Dst, 0x1, Src1 0x2 EXP-G〇L〇MB-TD Dst, Src1 EGOLD Dst, 0x2, Src1 0x3 EXP_GOLOMB_MD Dst, Src1 EGOLD Dst, 0x3, Src1 0x4 EXP-G〇L〇MB-CD Dst, Src1 EGOLD Dst , 0x4, Src1 Table 7 further explains Table 7. For #type=0x0 or shot; 叩6=0\1, no Srcl field is needed, and there is no need to specify these instructions to another major or secondary To operate the code group, because you can specify the dummy Src or Src and Dst can be marked as the same. The EXP-Golomb code symbols are encoded as shown in the following figure (for example including 0 or more boots 0, followed by 1, and then some bits corresponding to the number of boots 0): codeNum Range 1 0 0 1 X〇 1-2 0 0 1 X1 x〇3-6 0 0 0 1 X2 Xi x〇7-14 0 0 0 0 1 X3 x2 Xi x〇15-30 0 0 0 0 1 X4 X3 X2 Xi X〇31-62

Client's Docket No.: S3U06-0014-TW TT's Docket No:0608-A41247twf.doc/NikeyChe] 97 200821982 / How these bits are interpreted depends on the specific G〇1〇mb type (here according to H.264 Three types and the fourth type of Avs). Use UD and SD (without sign and sign) to calculate the logical unit to calculate the value. For example, 'When the bit stream is _1〇1〇, the value of the fairy is (1«3)-1+2 = 9, and the value of SD is (_1)Al〇*ceii(9/2) = +5. (3) A 6-bit real Inter has a similar procedure. However, for MD, the form lookup is performed (for example, when the UD is programmed, the value is decoded, then the value is used as an index to enter the table, and the value of 6 bits is returned (stored as ', value in the table) However, it is said that the value is extended from 〇 to the width of the scratchpad.) There are two tables in the example. One table is Intra coded and the other table is coded. An example of how the above instruction conversion is used in the case of the EXP-Golomb solution, the exemplary pseudo code decoded by the H.264 fragment header portion is shown below. ' sliceHeaderDecode: EXP_GOL〇MBJJD firstMBSlice EXP—G〇L〇MB-UD sliceType EXPJ3〇L〇MBJJD picParameterSetlD READ frameNum, Nval IB_GT frameMbsOnlyFlag, ZERO, $Label1 READ fieldPicFlag, ONE B-EQ fieldPicFlag, ZERO, $Label1 READ bottomFieldFlag, ONE Label 1 : ISUBI t1, #5, nalUnitType IB-NEQ ZERO, t1, $Label2 EXP-GOLOMB_UD idrPicID Labe 丨2: Old NEQ ZERO, picOrderCntType, $Label3 READ picOrderCntLSB, Nvalt Label3:

Clienfs Docket No.: S3U06-0014-TW TT,s Docket No:0608-A41247twf.doc/NikeyChen 98 200821982 ICMPLEQ p1,〇NE,fieldPicFlag

[p1]MOV nfieldPicFlag, ZERO

[!p1]MOV nfieldPicFlag, ONE AND t1, picOrderPresentFlag, nfieldPicFlag B_NEQ ONE, t1,$Label4 EXP__GOLOMB_SD deltaPicOrderCntBottom

Label4: Car exclusive to sliceHeaderDecode: EGOLD firstMBSIice, #0, ZERO EGOLD sliceType, #0, ZERO EGOLD picParameterSetID, #0, ZERO READ frameNum, Nval IB-GT frameMbsOnlyFlag, ZERO, $Label1 READ fieldPicFlag, ONE IB_EQ fieldPicFlag, ZERO , $Label1 READ bottomFieldFlag, ONE LabeH: ISUBI t1, #5, nalUnitType B—NEQ ZERO, t1, $Labe!2 EGOLD idrPicID, #0, ZERO Label2: B—NEQ ZERO, picOrderCntType, $Label3 READ picOrderCntLSB, Nvalt Label3 : ICMPI_EQ p1, ONE, fieldPicFlag [p1]M〇V nfieldPicFlag, ZERO [!p1]M〇V nfieldPicFlag, ONE AND t1, picOrderPresentFlag, nfieldPicFlag B—NEQ ONE, t1,$Label4 EGOLD deltaPicOrderCntBottom, #1, ZERO VC- 1 decoding

It has been described for use as CABAC decoding (variable length decoding unit 530a via CABAC module 580), CAVLC decoding (variable length decoding unit 530b via CAVLC module 582), MPEG decoding (variable length via MPEG module 578) Decoding unit 530c Ώ J Μ and EXP-Golomb decoding (variable via the EXP-Golomb module 584

Client's Docket No.: S3U06-0014-TW TT's Docket No: 0608-A41247twf.doc/NikeyChen 99 200821982 • Decoding System of Decoding Unit 530 d) Next, a VC-1 embodiment of decoding system 200 will be described next, This is referred to herein as a variable length decoding unit 53〇e. The variable length decoding unit 53A operates in accordance with the calculation of the preamble 1 module 574 and the calculation preamble module 576. vC_i uses Huffman coding and has more tables. Instead of creating q and testing these tables, since the bit rate needs to be compared

I is low, but 疋'13⁄4 δ is relatively cost-effective, and the necessary forms are loaded into the adjacent content memory 564. The table format is the same as that used by MPEG-2, and the READ, VLC-CLZ, VLC-CLO, and INPSTR instructions are used to decode the value stream. f For example, use the following pseudocode to execute a specific table: 1

//TABLE -1 Picture CBPCY VLC TABLE

VLC_CLZDST0,#8 CASE DSTO 0: VALUE = 0; BREAK; //USE MOVL 1:VLC^_CLZ DST1#5 CASE DST1 1:T=READ(2);

CASET 0: VALUE = 48; BREAK; 1 : VALUE = 56; BREAK; 2: GO20; BREAK; 3: VALUE = 1; BREAK; CASE_END 2: VALUE = 2; BREAK; 3: VLC_CLODST2, #5 CASE DST2 0: VALUE = 28; BREAK; 1: VALUE = 22; BREAK; 2: VALUE = 43; BREAK; 3: VALUE = 30; BREAK; 4: VALUE = 41; BREAK; 5: VALUE = 49; BREAK;

CASE—END 4: T = READ(1); VALUE = (T)? (READ(1) ? 31 : 54): 27; BREAK; 5: VALUE = 6; BREAK;

Client’s Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 100 200821982

/ CASE_END 2: VLC_CLZ DS1 #4 : CASE DST1 1: VALUE = 3; BREAK; 2: T = READ(1); VALUE = (T)? 19 : 36; BREAK; 3:T = READ(2) ;

CASET 0: VALUE = 38; BREAK; 1: VALUE = 47; BREAK; 2: VALUE = 59; BREAK; 3: VALUE = 5; BREAK; CASE_END 4: VALUE = 7;

CASE_END 3: T = READ(1); VALUE = (T)? 16 : 8; BREAK; f 4: T = READ(1); VALUE = (T) GO10 ? : 12; BREAK; 5: VALUE = 20; BREAK; 6: VALUE = 44; BREAK; 7: T = READ(1); VALUE = (T)? 33: 58; BREAK; //USE SEL?? 8: VALUE =15; BREAK;

CASE—END GO10: INPSTR S1, #3 READ-NCM S2, #0, off+S1»2 VALUE = S2&amp;0x63; Q = (S2 »6)&amp;0x3; READ SO, Q RETURN;

G〇20: INPSTR S1, #4 READ_NCM S2, #0, off+s1»2 VALUE = S2&amp;0x63; Q = (S2 »6)&amp;0x3; READ SO, Q RETURN; In some embodiments, available The branch instruction replaces the CASE statement. Therefore, VC-1 like MPEG-2 has an easily defined grammar. The symbols in the grammar have a specific method (table) that can be executed as a colorizer.

Client’s Docket No·: S3U06-0014-TW TT’s Docket No: 0608-A41247twf.doc/NikeyChen 101 200821982 as shown in the above code. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

II [Simplified Schematic] FIG. 1 is a block diagram showing an embodiment of a graphics processor system in which different decoding systems (and methods) can be executed; and FIG. 2 is a block diagram showing an exemplary processing environment in which decoding can be performed. Different embodiments of the system; Figure 3 is a block diagram showing the selection elements of the exemplary processing environment shown in Figure 2; Figure 4 is a block diagram showing the core of the exemplary processing environment shown in Figures 2 and 3, where Performing different embodiments of the decoding system; FIG. 5A is a block diagram showing selection elements of the execution unit of the computing core in FIG. 4, in which different embodiments of the decoding system can be executed; FIG. 5B is a block diagram showing the execution unit data path , in which a different embodiment of the decoding system can be executed; FIG. 5C is a block diagram showing an embodiment of the decoding system in FIG. 5B, which is applicable to a complex coding standard, and an embodiment in which a corresponding bitstream buffer is further displayed; 6A shows a block diagram of a decoding system embodiment in FIG. 5C for CABAC decoding; FIG. 6B shows a decoding system embodiment in FIG. 6A Block diagram;

Client's Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 102 200821982 * Figure 6C shows the block diagram of the content memory structure of the decoding system and the associated register embodiment of Figure 6A Figure 6D shows the macroblock partitioning mechanism using the decoding system in Figure 6A; Figure 6E shows the demonstration performed using the decoding system in Figure 6A;

Block diagram of the II macroblock decoding mechanism; Figure 7A shows a block diagram of the decoding system embodiment in Figure 5C for CABAC decoding; and, Figure 7B shows the decoding system used in Figure 7A. A block diagram of a table structure embodiment. ~PCI-E bus interface unit 122~ chipset

Execution unit set control and vertex/streaming cache unit [main element symbol description] 100~ graphics processor system 104~ display interface unit 110~memory interface unit 118 124~system memory 12 8~drive software 202~ graphics processing 206 to 208 to graphics pipeline 304 to pixel packager 308 to writeback unit 402 to execution unit input 404a to execution unit even output 102 to display device 106 to local memory 114 to graphics processing unit 126 to central processing unit 200 to decoding The system 204 to the calculation core 302 to the texture filtering unit 306 to the command stream processor 310 to the texture address generator 412 to the execution unit set 404b to the execution unit odd output

Client's Docket No.: S3U06-0014-TW TT's Docket No: 0608-A41247twf.doc/NikeyChen 103 200821982 406~ Memory Access Unit 410~ Memory Interface Arbiter 4卯~L2 Cache Memory 504~ Instruction Cache Memory controller

506~Thread Controller 510~Common Register File 514~Executing Unit Data Path 516~Present Register File 520~Data Output Controller 526~Scratch File 532~Vector Floating Point Unit 5Q8~Buffer 51 , 2 ~ execution unit data path): 518 ~ scalar register file 524 ~ thread task interface 530 ~ variable length decoding unit 534 ~ vector integer calculation logic unit 536 ~ special purpose unit ^ dry child 54 〇 ~ temporary storage 562~SREG stream buffer/dma engine', 562a~SREG register 564~contiguous content memory 562b~bit stream buffer 568~read adjacent context memory module

570~Check string module 574~Compute boot module 578~MPEG module 582~CAVLC module 602~state index 606~code length range 612~local register 616~binary string register 572~ Read module 576~calculation guide module 580~CABAC module 584~Exp_Gol〇mb module 604~high probability symbol value 6087^code length offset 614~total register 620~binary module

Client's Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 104 200821982 622~ Get Content Module 624~ Binary Calculation Decoding Engine 628~ Target 630~ SRC2 632~ SRC1 634~ Share and Execute Information 636~ Delay/Reset 638~ Address 640~ Data 650~ Memory Module 654~ Binary Index 710~Coefficient Charging Module 712~ Registration Module 714~ Leveling Module 716~ Level 0 module 718~zero level module 720~ running module 722~ level array 724~ running array

Client’s Docket No.·· S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen

Claims (1)

200821982 X. Patent application scope: 1. A decoding method, comprising: providing a shader configured with a complex instruction set to decode a video stream, wherein the video stream is loaded with the above-mentioned complex reduction command set according to a complex number The above coloring = a variable length decoding unit of a software programmable core processing unit for execution by the variable length decoding unit described above; The above video stream is decoded by the above-described shader performing the variable length decoding unit described above. 2. The decoding method of claim 2, wherein the loading further comprises initializing the variable length decoding unit, wherein the decoding is performed in a content programming of a graphics processing unit. The hardware of the material path and the one-bit stream buffer are used to automatically manage the additional hardware, and the above-mentioned complex encoding method includes the inner valley adaptive one-pass encoding (CABAC), and the content adaptation variable Two or more of length coding (CAVLC), EXP-Golomb, animation expert group (MpEG_2), and VC-1. 3. The decoding method according to claim 2, wherein the above instruction set for initializing comprises at least one INIT-CTX and init_ade for CABAC angle dry stone horse, INIT-CAVLC for CAVLC corner army horse INIT-MPEG2 for MPEG-2 decoding, INIT-VC-1 for VC-1 decoding and INIT_CTX or INIT_CAVLC for EXP-Golomb decoding' and more including INIT_AVS for decoding according to an audio video standard. Client's Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 106 200821982 ' 4. The decoding method according to claim 2, wherein the above initial: further includes: at least initialization a content memory array, a plurality of registers, a complex table of contents, and a decoding engine; updating the block of the register corresponding to the decoding operation or initializing the block of the register, wherein the update The method includes: moving a value between the temporary register and the content memory array; and reading the content memory array, wherein the instruction set for moving or initializing includes a CWRITE instruction for updating The above instruction set includes an INSERT instruction, and the above instruction set for reading includes a READ-NCM instruction 0. 5. The decoding method according to claim 2, wherein the initializing further comprises initializing a bit stream. a buffer and a related register for receiving the video stream segment, wherein the bit stream buffer is initialized and related The above instruction set of the memory includes an INIT_BSTR finger {, a command for loading data corresponding to the video stream to the bit stream buffer, and starting the automatic management of the bit stream buffer and the associated register. a program. 6. The decoding method of claim 5, further comprising arranging the data of the bit stream buffer in a byte manner, wherein the instruction set for arranging in a byte manner comprises an ABST instruction. 7. The decoding method according to claim 5, further comprising reading data from the relevant register when the data is used during decoding, wherein Clienfs Docket No.: S3U06-0014-TW TT's Docket No :0608-A41247twf.doc/NikeyChen 107 200821982 The above instruction set for reading data includes a READ instruction. 8. The decoding method according to claim 5, further comprising checking a bit stream of the bit stream buffer or a related register for a specific pattern that does not need to execute the bit stream. The above instruction set for checking includes at least one of the following: t I an INPSTR instruction corresponding to the check of the associated register, and a predetermined number of most significant bits to a target register corresponding to the above check One of the return; and an INPTRB instruction, the original byte sequence corresponding to the associated register carries the check of the trailing bit. 9. A decoding method comprising: decoding a video stream by performing a shader, the shader being embedded in a variable length decoding unit of a programmable core processing unit, and wherein the decoding system is different according to a complex number An encoding method; and providing a decoded data output. 10. The decoding method according to claim 9, wherein the I decoding is performed in a content programming of a graphics processing unit, by performing hardware processing on a data path of a graphics processing unit, and automatically managing a bit stream buffer. Complete with additional hardware, and wherein the above complex coding methods include content adaptive binary arithmetic coding (CABAC), content adaptive variable length coding (CAVLC), EXP-Golomb, dynamic expert group (MPEG-2), and VC-1 Two or more. 11. The decoding method according to claim 9, wherein the decoding according to CABAC includes: Client's Docket No.: S3U06-0014-TW TT^ Docket No: 0608-A41247twf.doc/NikeyChen 108 200821982 成八ΓΓ , within the group 'receive-the first information, package w&quot; into a knife and a content block type; _ corresponding to the above-mentioned shader of the m-leveling module Lai Xing, the commander's roots turned over the content model ―” providing two-component gas corresponding to one or more macro block parameters. Receiving the second information in a content module; the internal character—corresponding to the above-mentioned execution of the content module The first instruction of the shader provides a binary information for binary decoding and a content recognition poor message, wherein the above content corresponds to a high value or a low probability symbol probability; The carry calculation decoding module receives the binary information, the content identification information, an offset, and a range; and corresponding to the coloring state performed by the binary computing decoding module The second instruction, which decodes one or more binary symbols. The decoding method according to claim 11, wherein the decoding according to CABAC further comprises the following combination: ... receiving one or more decoded two The carry symbol is in a binary string register, the above-mentioned or a plurality of decoded binary components are decoded; the updated content information is provided; and the write-to-content memory array is The writing system is based on a Boolean logic operation including a value conversion from a temporary storage device that supplies the content memory to the above-mentioned content recording body array. 13. The decoding method according to claim 9 of the patent application, further includes 矣Client's Docket No.: S3U06-0014-TW TT5s Docket No:0608-A41247twf.doc/NikeyChen 109 200821982 One of the following: / ^ The order of the order determines whether to use one of the results stored in the internal temporary operation 'Or in the -source operator - the data should be used in - or multiple modules - the current operation; the field, the number of bits in the number is used for decoding, repeated and automatic stream buffer The predetermined number of bits of the red, the above-described bit coefficient corresponding to said video stream; ^The delay should be buffered in the expected downward overflow in the above-mentioned bit stream buffer; and the number of bits used in the above bit stream buffer, corresponding to the j-bit parameter is greater than the "established number" _, stop the above bit stream buffer state transfer, and switch control to a host processor. 14. The decoding method according to claim 9, wherein the decoding according to the CAVLC comprises: receiving a macroblock information in a coefficient register module of the CAVLC unit; corresponding to one of the shaders The fourth instruction (CAVLC-TOTC) provides a trailing coefficient (TrailingOnes) information and a non-zero coefficient (TotalCoeff) information; and receives the trailing coefficient information and a quasi-code in one of the CAVLC unit level modules. Corresponding to the fifth instruction (CAVLC-LVL) of one of the above shaders, providing a suffix length information and a quasi-index (Level[Idx]) information; receiving in one of the CAVLC unit level code modules The above-mentioned suffix length Client's Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 110 200821982 information; and: Corresponding to the sixth instruction (CAVLC_LC) of one of the above shaders, the above-mentioned level code is provided Information to the above level module. 15. The decoding method of claim 14, wherein the suffix length information and the level index information are in-position mode via a forwarding register and a execution unit register The group is received, wherein the level index information is incremented. 16. The decoding method according to claim 14, wherein the decoding according to the i' CAVLC further comprises the following combination: receiving the above-mentioned trailing coefficient information and corresponding in one of the CAVLC unit level 0 modules; Providing a second level index information to a quasi-array in a seventh instruction (CAVLC-LVL0) of the above shader; receiving the non-zero coefficient information and coefficient information in one of the zero level components of the CAVLC unit One of the maximum values; corresponding to one of the above shader eighth instructions (CAVLC_ZL), providing a zero residual information and a reset value to a first and a second multiplexer; operating the module in one of the CAVLC units Receiving the zero residual information from the first and second multiplexers and the second level index information respectively; corresponding to one of the shader ninth instructions (CAVLC-RUN), providing a running index to a run Array; corresponding to one of the above-mentioned shader tenth instructions (READ_LRUN), respectively, the above-mentioned level array and the above-mentioned running array respectively provide a decoded level Clients Docket No.: S3U06-0014- TW TTs Docket No: 0608-A41247twf.doc/NikeyChen 111 200821982 Value and a decoded running value; and: Corresponding to one of the above shaders, the eleventh entry, the step (CLR-LRUN), clear The above level array and the above running array. 17. The decoding method according to claim 16 of the patent application, in the basin, the first: the multiplexer system (4) receives the above-mentioned zero surplus from the -^ forwarding register: the remaining multiplexer The system uses the second level index information from the second forwarding register. Χ 18. The decoding method of claim 9, wherein the decoding according to / EXP-Golomb comprises: detecting and tracking in the combined-bit stream buffer n crying 0 and guiding 1 The quantity, 曰 which is based on the above-mentioned decoding system of ΕΧΡ-Golomb, uses a single opcode to perform the complex EXP-Golomb operation, each of which: the above-mentioned number of EXP-Golomb operations can be used immediately in one of the shader instructions. That is, the individual values of the Bellows field values are distinguished, and the above-mentioned detection and tracking guidance system is based on the calculation of the guidance 〇U (CLZ) instruction and the above-mentioned _ and tracking bows! The instructions are based on a computed Boot 0 (CLO) instruction, and wherein the above shader instructions corresponding to the EXP-(5)omb decoding include an EXP-GOLOMB-D instruction. 19. The decoding method of claim 9, wherein the decoding according to MPEG-2 comprises: executing an MpEG standard table using one or more MatchVLC functions, each of the one or more MatchVLC functions corresponding to an imaginary number In a different syntax into Client's Docket No.: S3U06-0014-TW TT5s Docket No: 0608-A41247twf.doc/NikeyChen 112 200821982 n points, the above table selection is based on one of the above shader instructions, where corresponds; in the MatchVLC function The above shader instructions include a VLC-MPEG2 instruction. 20. The decoding method of claim 9, wherein the decoding according to VC-1 comprises: I selectively loading a VC-1 table to a content memory array, wherein the decoding is based on the above selectivity The form to load. Client’s Docket No.: S3U06-0014-TW TT’s Docket No:0608-A41247twf.doc/NikeyChen