TW200813884A - Decoding of context adaptive binary arithmetic codes in computational core of programmable graphics processing unit - Google Patents

Abstract

Embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a context-adaptive binary arithmetic (CABAC) unit configured to execute a shader, the shader configured to implement CABAC decoding of a video stream and provide a decoded data output.

Description

200813884 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a data processing system, and more particularly to a programmable graphics processing system and method. [Prior Art] The computer green image is a computer generated image, image or other graphic or image information. The current drawing system contains several <faces, such as Microsoft's Direct3D interface and OpenGL, etc. Therefore, it is possible to control multimedia hardware such as graphics accelerators or graphics processing units (GPUs) on a computer running a specific operating system (such as Microsoft's WINDOWS). The generation of images and images is often called j " "Drawing", the details of such operations are generally carried out by a graphic speed device, in the three-dimensional (3D) electric lining diagram, the geometry of the objects in the scene or the object is transformed into a figure (graphics) Unit: in the frame buffer, then displayed in the display; = quality two or: the group has a specific visual object or object related to the appearance of the surface: group description, etc. 'These can (10) degrees and Energy consumption has been developed by Xu. == 200813884 The number of bits in the car's father produces better image quality, such as g 264 in the standard (also known as ISO 昼 expert group MPEG-4 part 10) is A compression digital view Coding standard, compared to MPEG-2 compatible encoding, Η·264 compatible encoding requires only about one-third of the number of bits to store video of the same video quality. The .264 standard provides two entropies. (entr〇py) Decoding program 'C疋ntext_adapHve binary arithmetic coding (CABAC) and context-adaptive variable length coding (CAVLC), about CABAC The decoding operation is usually processed sequentially, which requires a large number of calculations to obtain parameters such as range, compensation, and content (c〇ntext) information. Currently, the CABAC decoding structure can meet some of the needs of consumers, but there are still designs in it. [Description of the Invention] The present invention discloses a content adaptive adaptive arithmetic coding (CABAC) decoding system and method (hereinafter referred to as a decoding system), which is applied to a graphics processing unit (graphics processing unit, Multithreaded parallel computing core within GPU). Simply put, in one embodiment, the system includes a soft A programmable core processing unit having a CABAC unit therein for performing a shader that performs CABAC decoding of the video stream and provides a decoded data output. The method embodiment includes loading the shader with The CABAC unit 6 200813884 ^-type core processing element, (10) from performing the coloring (10) CABAC solution-video stream, sub-providing a decoded data output. After reviewing the following drawings and detailed descriptions, if the show performs other systems, methods, features and advantages, all such derivations, methods, features and advantages belong to the scope of the present invention. , subject to the protection of the patent scope of the attached statement. [Embodiment] The present invention discloses a plurality of content adaptive binary arithmetic coding-systems and methods (hereinafter generally referred to as a decoding system). In an embodiment, the decoding system is embedded in a graphics processing unit. (4) Chonghua pro·—She, GP chat program, multi-thread, parallel computing core, _ or more execution units, use software to combine hardware to achieve decoding function, that is, video decoding is graphical The content of the processing unit (pr〇gramming) is done in conjunction with the hardware implemented in the data path of the graphics processing unit. For example, the decoding operation or method is a colorizer with an extended instruction set. (shader, such as vertex coloring), execution unit data path of the graphics processing unit, and additional hardware for automatic management of bit stream buffers and context modeling in the cabac processing environment, not Like the known old systems, only CABAC processing methods with simple hardware or simple software' are therefore more or less encountered in the prior art. The problem mentioned. 7 200813884 In addition, the automatic bit stream buffer has some advantages, for example, once the bit "丨L buffered direct memory access (this (4) mem〇ry café, DMA) engine knows the location of the bit stream ( The address is automatically managed by the bit stream without further instructions. This mechanism is different from the traditional microprocessor or digital U tiger processor (digkai sjgnai pr〇cess〇r, dsp). Management no longer represents a large amount of overhead, and again, by recording the number of bits used, the bitstream buffer mechanism can detect and process the wrong bitstream. Another advantage of the decoding system of the present invention is that the instruction delay can be reduced, because CABAC decoding is a very continuous action, and it is not easy to utilize the eve thread, so in various embodiments, a turn-reduction delay is used, such as a temporary register. Transfer (4)ister fGrwardii= ^

Step interpretation, deep-pipeline and multi-threaded processors can't execute instructions in each cycle with the same thread. Some systems use general fomarding by checking the previous generated operations. The fperand address and the instruction operand address (if the same, the previous generation of the operand is used), this general transfer requires complex comparisons and multiplex operations. In some decoding pure implementations, 'will use different delivery methods, whether using the previous calculation results (such as retained in the internal register) or the data of the operation elements, all bits in the instruction (for example, total The 2-bit, per-operating element is encoded using the bit). In this way, the overall delay can be reduced and the efficiency of the processor pipeline can be improved. The standard department (induction) The decoding system described here can utilize the known International Telecommunications Union

Telecommunication Union 8 200813884

Telecommunication Standardization Sector (ITU-T) H.264 standard, based on the implementation of the memory received from the graphics processing unit buffer memory or main processing fast (such as central processing unit (CPU)) Multiple instruction sets (such as by known mechanisms such as preload (prel〇ad) or cache failures, etc.), multiple decoding system embodiments can perform operations. The first diagram is a block diagram of an embodiment, in which a decoding system and method are described. In some embodiments, the graphics processor system 100 can be a computer system, wherein the graphics processor system The display device 102 and the area memory i〇6 (which may include a display buffer, a buffer buffer, a texture buffer, a command buffer, etc.), which are driven by a display interface unit (DIU) 104, may be included. The area memory 106 may be replaced by a face buffer or a storage unit, and the area memory is connected to a graphics processing unit (GPU) 114 through one or more memory interface units (MIUs) 110. In one embodiment, the memory interface unit 11 (), the graphics processing unit 114, and the display interface unit 1〇4 are connected to a high-speed peripheral component interconnect express (PCI-E) twist-capacity bus interface. A bus interface unit (BIU) 118. In one embodiment, the bus interface unit 118 can use a graphical address repainting table (graphics address re Mapping table, GART), of course, other memory drawing mechanisms can also be used. Graphics processing unit 114 includes decoding system 200, which will be further described later, although in some embodiments graphics processing unit 114 will be The decoding system 200 is organized into one component, but the graphics decoding system 200 of the 200813884 graphics processor system 100 may actually include more or no components. Bus interface unit; Chara s R A + connected to day group 122 (such as North Bridge chipset) or switch, wafer fine A person, 匕δ interface circuit (interface electromcs) to enhance from the center

Unit, C guide 26 (also known as the main / 兀 (sub-W P_SSing / ^) is the signal received, and separate from the 记忆 memory 124 into the ^ 骑 骑 认 ^ ^ (5) 仏旒 and 从In and out (I/O) devices in and out signals, although mentioned here PCI_E remittance pick

η row agreement, but other connections and / or money can be used to communicate domain 1, (four) shaped processing unit 114 (such as PCI, dedicated high-speed bus, etc.), system memory 124 also package = dynamic software la ' can The profit processing unit 126 transmits the instruction set or the command to the register in the graphics processing unit 114. In some embodiments, the graphics processing unit may be additionally configured to be connected to other elements of the first diagram via the chipset 122 using a PCI-E bus protocol or other communication protocol. In an embodiment, the graphics processing unit may include -All trees of the graph' may also eliminate, add or change certain components 'for example' may additionally add a south bridge chipset 0 connected to the wafer and 122. Please refer to the second figure, which is a block illustrating the processing environment. Figure, wherein the application-decoding system 200' graphics processing unit 114 includes a graphics processor 202, a graphics processor 202, j includes a plurality of execution units (four) coffee (10) also, EU) and t computing core 2〇4, in one implementation In the example, the computing core 2〇4 includes the execution unit data path (executi〇n__, the brain decoding system 2GG, the data is allocated to the ❹(four) row unit, and the 200813884 graphics processor 202 also includes execution. Unit set (executi〇n unit p〇〇1) control and vertex/streaming cache unit 2〇6 (hereinafter referred to as EU set control unit 206) and with fixed function logic (for example, including triangle setting unit) a drawing pipeline 2〇8 of a triangle set-up unit (TSU), a raster-tile generator (STG), etc., the computing core 204 includes a plurality of joint execution units to conform to different shader programs. For the calculation of the coloring task, the shader program may include a vertex shader, a geometry shader, and/or a pixel shader, so that the drawing pipeline 2〇8 can process the data, and the colorizer of the different core 204 can perform the decoding system. 2 邛 邛 功能 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The decoding system 200 may include hardware or software, using the following known techniques or a combination thereof, for example, a discrete logic circuit having a logic gate to perform a logic function on a data signal, and an application having an appropriate combination of logic gates. Integrated circuit (ASIC), programmable gate array (PGA), ~-programmable gate array (field programmable gate array, FPGA) and other components. The third and fourth figures of the eye tea test, which is a block diagram of the embodiment of the graphics processor 2〇2, as described above, the decoding system 2〇〇 It may be a colorizer in the graphics processor 202, plus an extended instruction set and other hardware components. Embodiments of the graphics processor 202 and corresponding programs will be described below, although the second and fourth figures do not depict graphics. All the elements used in the processing 200813884 - the center of the programmable processing environment is the computing core 204 'which contains the decoding system and can handle various types of color program, such as vertex ':" program, etc. The computational core of the processor can process multiple instructions in the early clock cycle.

In the third figure, the relevant components of the graphics processor 202 include a computational core, a texture filtering single illusion 02, a pixel packing component 〇4, a command stream processing of 306, a writeback singularity 8, and a texture address generator. Then, the EU set control unit 2〇6 in the third figure also includes vertex cache memory and/or stream cache memory. In addition, the third_texture filter and unit 302 provide texel data for calculation. Core 2〇4 (enters a and B), in some embodiments, the texel data is 512-bit data. The pixel packing component 304 provides pixel shader input (ps input, inputs C and D) to the computing core 204, the input is also in the 512-bit data format, and in addition, the pixel packing component 3〇4 requests the pixel shader from the EU collective control unit 206. The task, and the EU collection control unit 206 provides the fingerprint execution unit number (EU#) and the thread number (thread #) to the pixel packing component 304, since the pixel packing component 304 and the texture filtering unit 302 are known techniques. Therefore, the third figure shows that the pixel and texel packets are 512-bit data packets, but the size of the graphics processor 202 can be changed according to the embodiment. The command stream processor 306 provides a triangle vertex index to the EU set control unit 206. In the embodiment of the third figure, the index is 256 bits. 12 200813884, the EU set control unit 206 combines and receives from the stream cache. Go to the vertex shader input and send the data to compute core 204 (input E); EU set control unit 206 also combines the geometry shader inputs and sends the data to compute core 204 (input F); EU set control Unit 206 additionally controls execution unit input (EU input) 4〇2 and execution unit output (EU output) 404 (fourth diagram). In other words, EU set control unit 2〇6 controls each input stream and output of computation core 204. flow. After processing, compute core 2 提供 4 provides pixel shader output (ps output, outputs J1 and J2) to writeback unit 308, which includes color information such as red/green/blue/transparency (RGBA) information. Regarding the data structure in the embodiment, the pixel shader output can be two 512-bit data streams, and other embodiments can use other bit widths.

In addition to the pixel colorimeter output, the discriminating core 204 also outputs texture coordinates (TC, outputs K1 and K2) to the texture address generator 310, which includes UVRQ information, and the texture address generator 31 is directed to the computing core 2〇4 The L2 cache memory 408 issues a texture description symbol request (τ#request, input X)' and then computes the core 204's L2 cache memory 4〇8 to output texture description symbol data (τ# data, output w) to the texture The address generates the piano 31〇, because the texture address generator 310 and the write back unit 3〇8 are known techniques, and will not be described here, and again, although the picture shows that urvq&rgba is a 512-bit data. However, this parameter can also be changed according to different embodiments. In the embodiment of the third figure, the bus bar is divided into two 512-bit channels, and at the same time, four images of the bit RGBA color value and 128 bits 13 200813884 Drawing pipeline 208 includes graphics processing functions for fixed functions, for example,

In response to the command to draw a triangle from the driver software, the vertex information is converted to the vertex shader logic element in the core 204 for vertex conversion, and the object will be changed from the object space to the workspace and/or the opening of the screen space. The dipole reaches the triangle setting unit of the drawing pipeline 208 through the different core 204, and performs known tasks in combination with the primitive, such as generating a bounding box, culling, and edge function. Generation) and triangle level rejection, etc., and then the triangle setting unit transfers the data to the grid and tile generation unit having the tile generation function in the drawing pipeline 208, so that the data object is divided into tiles (for example, 8χ8, 16χ16, etc.), and passed to other mosquito function sheets ^, for depth (z_value) processing, such as the high order of ζ·values (the same procedure uses less bit seams in higher order than lower order) Pass the z-value back to the pixel outline logic component of the computational core class to ride the pixel shader function according to the pipeline and data. Gang ί processing of the output value to the target is located within the line 208 earlier Wu _ 'early target for α 7L before testing and stencil test values of the respective portions will be _ cache. Please note that the core 204's L2 cache memory 408 and EU, and the control unit have a 512-bit top (spm) data transmission (input G), and the different core 204 output! 512-bit _ teacher to take the butterfly vc) Writer: EU collection control unit for further processing. Please refer to the fourth figure, which shows the other meta-sides of the calculation core. 200813884

The closing element 'computing core 204' includes an execution unit set (eu set) 412 having one or more execution units 420a-4 (hereinafter collectively referred to as execution unit gammas), each of which can be processed in one clock cycle Multiple instructions, therefore, the execution unit aggregation can simultaneously process multiple threads at the same time f at the same time, although the fourth figure rides 8 execution orders (EU0~EU7)' but does not mean that the number is 8 The U.S. embodiment can increase or decrease the number, wherein at least one execution unit (4) such as ETO^Oa has a decoding system 2, as described in detail below. Computation core 204 pure money, money take shirt (me_y _ss MXU) 4G6 'memory access list ^ tear by memory interface arbitration 410 and L2 cache memory 4〇8 connection, L2 cache slave collection control Unit 2〇6 receives the vertex cache memory overflow data (input G), sub-provids the top job memory overflow (four) (= control unit shift, in addition, L2 cache memory from the texture; J generator 3U) receives the texture The description symbol request (τ# request, the input provides the texture description symbol data (Τ# data, output W) to the texture address generator 31. The memory interface arbiter 410 provides the area video memory. The control interface (such as the gold surface buffer or the area memory touch), the bus interface ς π 118 provides the interface of the system 'which can be the pci_E bus, the interface interface arbiter 410 and the bus interface unit 118 as The memory and the silk memory are placed on the interface, and some of the implementations are implemented. u fast ^ f body 408 is connected by the memory access unit ° and the bus interface unit 118; e::= 15 200813884 L2 cache memory and other blocks get virtual The memory address is converted into the actual memory address. This body; I face arbitration $ 41 〇 provides L2 cache memory memory access (such as read / write access), extractable instructions / constant / data / texture, direct Memory access (such as load/store), index temporary access, scratchpad secret, vertex cache, content overflow, etc. The calculation core 204 also contains execution unit input (EU input) 402 and _ ^ 仃 兀 兀 output (EU output) </ br> is used to provide the input of the execution unit set "12 and receive the output of the execution unit set 412, the execution of the input and execution unit output 404 can be a switch (deletion sbar) Or busbars, or other known input and output mechanisms. ^Execution unit input 402 receives the vertex from the EU set control unit lion (input E) and geometric coloring II (input F) After the absence, the information is provided to the execution unit set M2, and the execution units 42 are removed for processing; and the 'execution unit input 4〇2 receives the pixel shader input (transmission and D) and the texel packet (input and B) and transport these packets to execution The meta-collection 412 'let each execution unit it 42G to process; further, the execution unit input 402 is taken from the L2 cache memory 4〇8), and the information is provided to the execution unit of the fourth diagram embodiment when the money is woven. The output 404 is divided into an even output 4〇4a and an outputtable 404b, and the execution unit output 4〇4 and the execution unit input can be exchange switches or busbars, or other known architectures, and the single-coupled output 404a is processed. Execution unit gamma, tear, strip, output, shouting unit odd wheel processing odd execution unit 働, 16 200813884 4 Shi, salt, view output, in short, two He and Na jointly receive the execution unit integration round, such as = and delete the A data, these rounds can be returned to the L2 cache memory, or = from the different core, 2G4 via: η and j2 output to write back γ output from Κ1 and Κ2 to the texture address generator 31 Hey. Or hey! The execution unit stream of the 4^ row unit set 412 usually contains several levels, such as the level of the hierarchy, the thread or the task level,

ί任=:Γ: Execution unit 420 may permit two two-in-ones to use the bit 70 flag or other mechanism to identify the content of its content 2 before the task begins, from the collection control unit to write two?: The information can be shader type, input/output constant = ^ 420 . 21 ^ command. In the shell, each thread executes a similar set of data-driven buttons according to the program counter. (eg, input _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The appropriate thread, for example, the lion assignment - the thread to the execution unit set 412 == 420 within the empty thread position, when the thread has started other components or modules (based on The shader type) is placed in the shared scratch buffer. Typically, the graphics processor 202 uses programmable vertex, geometry, and pixel 17 200813884 buffers, and these components are no longer considered to have different designs and Each component of the command group has its own merits and functions, and each of these components is executed or operated. Instead, the execution order of the command group is 70 42Ga, 42Gb, ... 42Gn, and the command group is executed in addition to the order 70 42 ( ^ (This execution unit contains the decoding system 2, which has additional functions), the design and structure of each execution 420 for the program operation are the same, in one embodiment, each one Single 兀42〇 can enter multiple thread operations, when the vertices Color shaders, geometry shaders, pixel shaders, etc., produce different color shader tasks that are sent to individual execution units 420 for execution. In one implementation, the decoding system can use a vertex shader, The other execution units are the same as, for example, the execution unit 42A uses a decoding system, 乂疋, he does not have it (as in side b of the fourth figure) because the code system 200 manages one or more corresponding The internal buffer % is obtained by the connection port and the execution unit input from the memory bank = element 406. When an individual task is generated early, the EU collective control unit 2 〇 6 tasks are given to the non-row unit. The job control thread spear ^ ^ collection control unit finely manages the release of the relevant thread, two spears: point:: 'EU collection control unit is responsible for assigning vertex shader, geometric color and pixel shader tasks to the execution unit The thread δ has recorded the relevant tasks and threads. Specifically, Eu: the implementation of all the execution unit-like threads and memory = not much explanation), the EU collection control unit is assigned to where Tasks use, know which one of the threads of the 181813884 to release, know how much shared register file memory (register file memory register), know each execution = -: available space. So much, if a task has been assigned to an implementation of a 420a 'EU collection control unit 2〇6 will this thread as in, then all the shared scratchpad broadcast memory minus each 'green' The number of the scratchpad file body (f00tpring) is j. The shader, geometry shader, and pixel shader are executed. A shaded pure segment can have a size of _body. For example, the thread can be used. The memory file temporary storage 2 color filter thread can only require 5 registers. When a thread completes its assigned work, the running unit 420 will send a signal to Eu ^ _仃, the person's control set list... will update the resource table 2 = use, the line share the register Between the number of cases, when all the threads are busy or n: the file memory has been allocated (or the reserved scratchpad space = accommodate additional threads), then the execution unit 420 It is already, the system: the control unit 206 will not assign a new thread to the executable = set ... the mother also has an execution inside the execution unit to manage or label each thread is in time (or Available, in this regard, in one of the Dingzhong) or 疋 解 细 细 的 】 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The figure illustrates an execution unit 420a having the aforementioned graphics processor 202 and computing core 204 features, which includes an execution unit data path 512 embedded with a decoding system 200. Specifically, the fifth A diagram is a block diagram of an execution single το 420a. In an embodiment, Containing instruction cache controller 504, connected to the instruction cache memory controller 5〇4 the thread J 506 4 ENGINEERING Greek state buffer 508, a common groove pattern register (register comin〇n

File ' CRF ) 51〇, the execution unit data path (Εϋ data patti, EUDP) 512 connected to the thread controller 5〇6 and the buffer 5〇8 and the shared temporary file 510, the execution unit data path advanced first Output, buffer (such as β such as t FIFO) 514, the description of the register register, 516, scalar register file (SRF) 518, the shell output controller 520 and The thread task interface 524, as previously described, executes an input unit 420 that receives input from the execution unit input 4〇2 and then provides an output to the execution unit output 404. Execution, the controller 506 provides the control function of the entire execution unit 42A, including managing each thread and decision function, for example, determining how to execute the t thread, and the EUDP 512 includes the decoding system 200, which can perform various calculations, including images. It is a logic circuit such as floating-point arithmetic calculation logic unit (4) hmetie _ umt ' ALU), shift logic function. The port ... output controller 52G can move the completed data to some execution and execution = for example, the EU set control unit 2 ° 6 Di Di, ' - write back unit 308, etc., EUSP512 transmits "Ren Ί i system 520 contains the storage part to store the completed tasks (such as 20 200813884 2::, select the task, and then according to:: 疋 暂 位置 , , , , 从 丑 丑 蕲 。 。 μ μ μ μ μ μ μ μ μ , Mengde temperament temporary storage "case 510 read all the output '^目' and then send the reading to the execution unit round and tear. Do not give ==== 24^(4) 42Ga completed task identification system -/, σ The 'task identifier' will inform the eu collection "live: 06" has a specific execution unit with a thread resource, and can assign a new task to the execution unit (such as 4). (1) In the embodiment, the buffer ( Such as the constant buffer) can be divided into blocks, each block has 16 128-bit horizontal vector constant positions, Bodhi crying the field, biting the Buji J-book number 詈: nose element and an index access A constant buffer ^^ is an integer constant containing % bits or nearly 32 bits without positive and negative 旒7 取. 己|^ Body controller 5〇4 is the thread controller 鄕 interface with a thread controller read request (such as from the instruction memory to change the shader code), instruction cache memory The controller 5〇4 will look up the 仏 wearing table (tree out) and perform the hit/miss (10)/miss) test, for example, if the requested instruction is located in the cache of the instruction cache controller 5〇4 In the body, it indicates a hit. If the command to be requested is to be extracted from the cache memory 408 or the memory (10), it means no wipe, if it is hit, and the same B heart has the execution unit input 4〇2. The request, the instruction cache controller 504 can agree to the request, because the instruction cache memory, the controller 504 instruction cache memory has only one read/write port, and the execution single 7G input 4〇2 has the highest value. Priority; conversely, if not, and 21 200813884 L2 cache memory 408 has a replaceable block and there is space EUm> FIFO 514 'the instruction cache controller 504 can agree to the request. In an embodiment, the cache memory of the instruction cache controller 504 is cached. Contains 32 groups, each group has 4 blocks, each block has a 2-bit status signal, which can represent three states, respectively, invalid, loaded, or valid state, before the block is loaded with L2 f material The block is in the "invalid" state. When it waits for the L2 data to be in the "load" state, it becomes "active" when the L2 data is completely loaded.

The facsimile path 512 can be read and written to the staging register slot 516. The execution unit input 4G2 is used as the interface for entering the data and executing the single unit 42a. In an embodiment, the execution unit input 402 includes a The 8 item first-in first-out buffer buffers the incoming data, and the execution unit input operation can also reach the instruction cache memory and constant buffer of the instruction cache memory controller 5〇4. The implementation of the unit's execution unit can also retain the shader content. Performing the early output as the output data from the execution control unit, the L2 cache memory, and the write back to the early 7G, &quot; face, in one embodiment, the execution unit output 4〇4 contains: 4 item silk First Saki _, rib receives the bribe request, and buffers the data of the control unit 2%, the execution unit output 404 package = seed m read the age of silk record dragon read out the write request, EUDP read / write request . The keel shared register file 510 is used to store the input data 'in the embodiment, the shared register TAN (four) heart: (4) the m X 128 bit temporary register broadcast case and one read and write and two 22 200813884埠, a write-write system is used for EUDP 512, for read and write accesses of instruction execution, even threads share memory pages 2、, 2, 4, 6, and odd threads share 圮 页 1, 3, 5, 7, the thread controller 5〇6 pairs the instructions of different threads, and confirms that the memory of the shared scratchpad file does not read or write the memory page conflict. The read/write buffer is used by the execution unit input 402 and the data output controller 52 to load the initial thread input data and write the final thread output to the EU collection control unit data buffer and the L2 cache memory 4〇8. Or other modules, the execution unit input 402 and the execution unit output 4〇4 share a read/write I/O #. In one embodiment, the write has a higher priority than the readout, and the 512-bit input data enters 4 A different memory page to avoid conflicts when loading data into the shared scratchpad file 510. The 2-bit channel index data is aligned with the 512-bit aligned base address to specify the beginning of the input data. Memory page, for example, if the channel index is started, memory page 1 loads the first 128 bits from the least significant bit (LSB), and the next 128 bits 70 is loaded into the memory page. 2, and so on, assuming that the thread reference memory page compensation is 0, the last 128 bits are loaded into the memory page, please note that the two least significant bits of the thread ID are used to generate a memory page compensation, to random row Each thread of memory start page location.

CRF register index and thread Π) can be used to create a unique logical address 'tag matching (tag matching) shared register structure 51 〇 read and write data, for example, the address can be arranged into 128 The bit, just like the width of the shared scratchpad file memory page, is composed of a combination of 8-bit CRF 23 200813884 register index and 5 imitation 13-bit address, each - 2: Ding Xu 1D, can There are two erroneous bit items (words and lines with one label) in each line, and the parent word of the CRF side is stored in 4 memory page memory page compensation, the least effective The bit force recognizes that the current thread only fills 1 Bay from the establishment of the memory page selection. The file file = the second method allows the different registers of the scratchpad to share the shared temporary memory utilization memory, and the EU collection control unit 206 records

Γ 420 (4) The degree of use of the 51G in the case of the case, it is sufficient to have enough space for the new task of the 420a. The target CRF index of the private-eye two threads accounts for the large number of all crf registers. In the implementation of the controller 5G6, the thread and the colorizer ^^4 are started. The input tribute should be stored in the shared register. In the file 510, the field execution ends and the execution ends, and the data output controller 52 reads the output data from the shared register structure 510. The implementation of the unit, the unit of the example has the time to decode the secret EUDP 512, the fifth B diagram illustrates an EUDP 512 embodiment, EUDP 512 package 3 temporary storage file 526, multiplexer 528, vector floating point (FP) Unit 532, inward integer arithmetic logic (ALU) unit 534, special purpose unit 5%, multiplexer 538, scratchpad file 54〇, and decoding system 2〇〇, decoding system 2〇〇 includes one or more The CABAC unit 530 can decode one or more streams. For example, a single CABAC unit 53 can decode a single stream, and two CABAC units 530 (shown by dashed lines, but the connection is not drawn for brevity). The two streams can be decoded at the same time, etc. For the sake of clarity, the following description is only for the use of a single CABAC unit 53〇24 200813884, and the operation of the decoding secret 200 is more than the red unit. As shown, EUDP 512 white #η has 3 corresponding to some parallel data paths of CABAC decoding unit 530, vector floating point unit 532, vector unit, special unit: unit 536, each unit can be received according to The instruction executes the corresponding operation, and the register file 526 receives the operation element (not referred to as SRC1 and SRC2). In the embodiment, the register Φ = the common register file 51 shown in FIG. The temporary register broadcast 5i6, and / or the scalar register 518, please note that in some embodiments I, you can also use more operand operations (function) signal line % ^ yuan 53 (four) 6 receive operation The means of signal 'current signal line (10) continuous time to multiplex ☆ 528 ' can be transmitted into the current value of the instruction, for each p 530~536 small integer value integer operation, instruction decoder (not mentioned, operation element, operation (Function) signal, and the current signal, the multiplexer 538 at the end of the chanting path (which can include the write-back phase) selects the positive path (4) The output result is sent to the temporary storage (4) case 54 (), the case 540 package order one day 栌 ^ from π 什 才 才 才 才 ^ ^ ^ ^ ^ ^ " Broadcasting 526 or other temporary 4, note that in the embodiment, when the source and destination registers contain = the same 70 pieces of instructions, the bits have source and target s pieces for multiplex processing to process from/send To the appropriate temporary storage of the file information. Therefore 'execution unit 42〇a can be regarded as a multi-stage pipeline (such as 4th-order tube: 'senior, there are 4 arithmetic logic units)' CABAC decoding operation in 4: two occur 'Need a delay to let CABAC decode the thread action, burdock, child, when the bit stream buffer occurs downward overflow (underfl〇w), etc. 25 200813884 waiting for the initialization of the content, the singer The buffer and sREG temporary storage (10) are transferred, and/or the processing coffee has exceeded the expected time, etc., and the delay can be added during the execution phase. As described above, in some embodiments, the decoding system 2 utilizes a single Execution unit 420a simultaneously decodes _bits &amp; for example, according to _ a set of expansion instructions, the decoding system can use two data paths (such as adding another CABAC unit 530) to simultaneously decode two streams, of course Can decode more or less streams (then "Multiple or less, data path" 'When multiple streams are involved, some decoding systems are not limited to simultaneous decoding. In addition, in some embodiments, 'single cabac unit can perform multiple simultaneous streams. Decoding. In the example of the Bayesian, when the decoding system 200 uses two data paths and two threads to run off, for example, in the case of two streams of solutions, the number of restricted threads is two. The first thread (such as the thread) is assigned to the first memory page of the decoding system 200 (ie, CABAc single = 30). The second thread (such as the thread) is assigned to the decoding system. A suffix page (ie, the dashed CABAC unit of Figure 5B), in some embodiments, two or more threads can run on a single memory page, additionally: although the decoding system 2 is shown here Embedded in £11〇1&gt;512, it can also contain other components, such as the logic in the EU collective control unit 2〇6. Some embodiments of execution unit 420a, EUDP 512, and CABAC unit 53A have been described. The following briefly explains CABAC decoding, and then illustrates some embodiments of decoding system 200, typically H.264 CABAC solution 26 200813884 code private order may include parsing The coded bit stream of the $1 method component, the content variable of the first syntax component and the decoding, and the binarization. Then, for each binary decoding, the program further includes obtaining one. The content model and the binary decoding of each set of component components 'until a meaningful codeword pairing is obtained, further + interpretation, the decoding system 200 decodes the syntax components, and each syntax component can represent a quantized coefficient, an action vector, And/or prediction mode, or other parameters relating to macroblocks, which are used to represent a particular field or frame of an image or video, each of which may contain a series of carry symbols. Or binary value, the ride-two binary age is decoded into ^ or 1 value 'decoding system 2〇〇 according to the probability of occurrence of the input binary symbol Output bit length. It is known that CABAC encoders provide highly efficient coding methods when certain symbols (called primary symbols) are more likely to occur than other symbols. These primary symbols can be encoded with a smaller bit/symbol ratio, and the encoder continues to enter (10). Frequency statistics of poor materials, suitable for adjusting the coded content model ^ There is a higher probability of the binary symbol called high probability = number: = symbGl ' M (9) ' (four) his symbol is low _ _: ίsymbo1 'LPS The 'binary symbol is linked to its content model, and the parent-(10) model corresponds to the LPS probability and the -Mps value. In order to determine each binary symbol, the decoding system fan or receives a corresponding range, compensation and fleshy y, number category and adjacent tiles (such as current, heavy block) In the choice of environment model, 27 200813884 The context identifier can be determined by the content model, so as to obtain the MPS value and the current state of the decoding program _ code spleen, the range is not an interval, every time the binary decoding is performed Will narrow the scope once. ,

The interval is divided into two sub-ranges, which correspond to the Mps value and the Lps probability respectively. The range and the LPS probability specified by the known content model are multiplied to obtain the Lps sub-norm. 'Fill the _ to the LPS sub-norm to obtain the MPS sub-range The compensation is determined by the code binary value, and the f is the initialization of the 9-bit kernel from the coded bit stream. For the known binary symbol decoding and the inner valley model, if the compensation is less than the MPS sub-range , the binary value is the Peng value, the range used for the next-time decoding is the Mps sub-range, and conversely, the = carry, the LPS, the inverse of the MPS value is placed in the relevant content model * with WF (four) It is set to the LPS sub-range, and the result of the decoding process: ., , : a series of binary values, which will be used to determine whether the string value meets the meaningful summary description of the relationship between the decoding system and the cabac decoding. CABAC decoding program _ the towel decoding system ^. A kind of 7-pieces can be used to test various deformations in accordance with the actual application. ##° Many terms used in riding are from the place: for the sake of (4), it will not be repeated, unless it is helpful to understand the same procedure. And / or components, will be done again - step description. Figures A through 6F are diagrams illustrating the decoding system and related components/maps in which the decoding system has a single-CABAC single- (in the eighth to sixth F-pictures, the used cabac unit 28 200813884 530 The second decoding system 2 (8) is interchanged, so in the embodiment, the decoding system 200 can be solved, the single_bit stream, the same principle can be applied to the decoding system 2 with multiple CA^AC units, and multiple decodings can be simultaneously performed. (e.g., two) The melon is simply said, the sixth picture A is the selection component of the decoding system 200, the /, = diagram is the function block of the sixth A picture selection element plus other elements, and the sixth C picture is for decoding The block diagram of the stream buffer provided by the system is finely illustrated. The sixth figure and the figure are block diagrams illustrating the function of the internal system of the decoding system, and the sixth figure is for decoding. The block diagram of the example tf mechanism of the giant tile, although the following description is about the decoding of the giant tile, this principle can be applied to various tile decoding. The CABAC unit 530 has a CABAC logic module 66 and a memory module 650. In one embodiment, the CABAC logic module 66 includes three modules. They are a binary module 620, a get content (GCTX) module 622, and a binary arithmetic decoding (BARD) engine 624 in the CABAC unit 530, respectively. The BARD engine 624 further includes a state index (pStateldx) register. 602, MPS value (valMPS) register 604, code length range (codlRange) register 606, and code length compensation (c〇dl〇ffset 608, memory module 65 of CABAC unit 530 includes giant Tile adjacent content (mbNeighCtx) memory 610 (also known as context memory array), region register 612, total scratchpad 614, and shift register (SREG) string Stream buffer/direct memory access (DMA) engine 618 (also known as DMA engine module, which will be further explained in Figure 6), in addition to the unillustrated register, 29 200813884 In the example, the mbNeighCtx memory 610 includes an array structure as in the sixth D diagram, after which To further illustrate, the memory module 650 further includes a binary string register 616. The interface between the CABAC unit 530 and the execution unit 420a includes a target bus 628, two source buses (SRC1 632 and SRC2 630), Command and thread information bus 634, and delay/reset bus 636, the data on target bus 628 can be transmitted directly or indirectly (eg, via intermediate cache, scratchpad, buffer, or memory) To the video processing unit inside or outside the graphics processing unit 114, the data on the target bus 628 may be Microsoft's DX API format or other formats, including data, macro block parameters, motion information, and/or IpCM. For sampling or other poor materials, the CABAC unit 530 also includes a memory interface consisting of the address bus 638 and the lean bus 640. After the address is obtained from the address bus 638, the data can be accessed by the data bus 64. 〇 The obtained data is entered into the 兀 stream read access. In the embodiment, the data bus is 64 • • The stomach material may include an unencrypted video stream, including various signal parameters and Other materials and formats, in some embodiments, a load-store operation can be used to access the bitstream data. Before beginning to illustrate the various components of the CABAC unit 53, simply say Ca CABAC ^^it 420a ^ It 苇 according to the slice form, the driver software (10) (first picture) prepares the CABAC color state to load it into the execution unit 4, the shader uses the fresh instruction group plus the BIND instruction, the gctx instruction, and the RD. 7 The bit stream can be decoded, since the context table used by the |cmAC unit 30 200813884 530 can be changed according to the slice type, so each slice is loaded, and in one embodiment, other instructions are issued. The first instruction executed by the CABAC shader consists of iNT-CTX and INIT-ADE. These two instructions cause CABAC unit 530 to start decoding a CABAC bit stream and load the bit stream from the stream decoding point. The buffer is set to 'The two instructions will be explained later. Regarding the parsing of the bit stream, the bit stream is received from the data bus 64 of the memory interface, and then buffered by the SREG stream buffer/DMA engine 618, and the bit stream decoding stage provides bit stream decoding, bit stream ( Such as nal bit turbulence) includes one or more pictures, which are cut into headers and a number of slices. A slice usually contains a series of giant tiles, in one embodiment, external The program (ie, CABAC unit 53 〇 external) parses the NAL bit stream, decodes the slice header, and transmits the indicator pointing to the slice data (such as the beginning of the slice). The hardware (plus software) can be parsed from the graph 圧%^ bit^ In the embodiment of the stream m, the CABAC code only appears in the slice data and the giant tile. Generally, the driver software 128 processes the bit stream from the slice data, and S is the function provided by the remainder and the API, and the indicator pointing to the position of the secondary material. The pass also involves the first bit position Z of the slice data (such as RBSPbyeAddress) and the bit compensation indicator (such as a bit or multiple bits) indicating the start of the bit stream or the position of the header ^ SREGpt〇, ^ * Initialization of the meta stream As will be explained later, in some embodiments, an external process may be utilized to provide picture decoding and slice header decoding using a processor (such as central processing unit 126 of the first figure), and in some embodiments decoding system 20G The programmable feature can be decoded at any stage: 200813884 See the sixth C diagram, which is the SREG stream buffer of the CABAC unit 530. 1§, /^]\^(4) 618 depends on the component part and other components The figure includes the meta-storage ports 662 and 664, and receives the SRC1 and SRC2 values from the bus bars 632 and 630, respectively, and then transfers them to the scratchpad coffee and 668^ other components as described in the sixth diagram, unless stated otherwise. Needlessly, for the sake of brevity, the SREG stream buffer/DMA engine 618 includes an internal bit stream buffer 618, which in one embodiment can be a 32-bit register and a _128 bit in the BigEndian format. The scratchpad: The initialization command of the driver software sends it{ at the beginning of the mosquito SREG stream buffer/DMA engine 618, and when it is started, it automatically manages the internal buffer 708b of the trick stream buffer state/DMA engine 618, SREG Stream buffered two/DMA engine 618 retains the bits to be resolved The location, in one embodiment, 'SREG Stream Buffer/DMA Engine 618 uses two registers, a fast 32-bit flip-flop with a slower 512 or 1 〇 24-bit memory, bit stream Bits are used, shift register 618a operates in bits, and bit stream buffer 618b operates in bytes, which saves energy. The shift of the temporary register 618a operation uses a small number of bits. (e.g., \~3 bits), when the shift register 618a uses more than one tuple of data, the poor material (byte segments) will be transferred from the bit stream buffer 618b to the shift register 618a, The buffer indicator then reduces the number of bytes transferred. When the DMA engine of the SREG stream buffer/DMA engine 618 detects the use of 256 bits or more, it extracts 256 bits from the memory. The bit stream buffer 618b, such that the CABAC unit 530 implements a simple loop buffer (256 bit segments X4) to track the bit stream buffer 32 200813884 and fill it, in some embodiments Use a single buffer' but a circular buffer needs to be more complicated Standard calculation up to speed memorized body. The internal buffer 618b is interacted with by an initialization instruction, referred to as a T-BSTR instruction. In one embodiment, the INIT-BSTR instruction is issued by the driver software 128 and other instructions are described later, if the bit position of the bit stream is known. Tuple address and bit compensation, INIT-BSTR instruction loads the data into the internal bit stream buffer 618b, and starts the management program. Each time the call is processed, the slice data will be issued in the following format. · INIT-BSTR Offset, RBSPbyteAddress This instruction is used to load data into the internal buffer 618b of the SREG stream buffer/DMA engine 618, the SRC2 register 664 provides the byte address (RBSPbyteAddress), and the SRC1 register 662 provides the bit. Compensation, so, the following general instruction formats can be used: INIT-BSTR SRC2, SRC1, where SRC1 and SRC2 and other signals in this instruction are values corresponding to 10 internal registers 662 and 664, but are not limited to these In one embodiment, the 256-bit memory extraction is used to access the bitstream data and write it to the buffer register and to the SREG string. The 32-bit shift register 618a of the buffer/DMA engine 618, in an embodiment, before the operations of the registers or buffers, the data in the bitstream buffer 618b is a bit The group arrangement, the data arrangement can be implemented by the arrangement instruction, also known as the ABST instruction, the ABST instruction will arrange the data in the bit stream buffer 618b, and in the decoding process, the bit 33 200813884 (such as the padding bit) Yuan) will be discarded at the end. When the shift register 618a uses the data, the internal buffer 618b fills the data. In other words, the internal buffer 618b of the SREG stream buffer/DMA engine 618 is similar to a loop of 3 (m〇dul〇). The buffer is input to the 32-bit register 618a of the SREG stream buffer/DMA engine 618. The CABAC logic module 660 can read data from the shift register 618a using the rEAD instruction. The format of the READ command is as follows: READ DST, SRC1, where DST corresponds to an output or target register. In an embodiment, the SRC1 register 662 includes an integer value n that is not positive or negative, and passes through the shift register 618a. Obtaining n bits, when 256-bit data is consumed from the 32-bit scratchpad 618a (such as decoding one or more syntax components), the extraction operation is automatically started to obtain another 256-bit material, which is written The register of internal buffer 618b is then entered into shift register 618a for use in the next cycle. w. In some embodiments 'if the data corresponding to a symbol decoded shift register 618a has been used for a predetermined number of bits or bytes, and the second buffer 6 does not receive any further data, then The cabac logic module 660 can delay via the delay/reset bus _ to perform other reliances (eg, threads that are unrelated to CABAC decoding), such as vertex shader operations. Using the SREG Stream Buffer/DMA Engine 618 # dma can reduce the number of required _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 200813884 The stream 'can request to flow into the following bitstream data, if the bitstream data is too small, the bitstream buffer 618b is at risk of a downflow (eg, it is known to have the signal flow from the CABAC unit 530 to the processor). The number of cycles of the pipeline) can pass a delay signal to the processor pipeline, suspend operation, and wait for data to arrive at the bitstream buffer 618b. stupid

In addition, the 'SREG Stream Buffer/DMA Engine 618 originally has the ability to handle the error bit stream. For example, because the bit stream is incorrect, the slice end mark may not be detected. This detection error may result in The decoding is completely wrong, and the bits of the subsequent pattern or slice are used. The sreg stream buffer/DMA engine 618 records the smoke number, if the number of bits used is greater than the preset threshold (can be changed for each slice) Then, the handler is terminated and the removed signal is sent to the processor (such as the main processor), and then the processor performs an encoding attempt to reply from the error. / Please refer to the sixth A picture and the sixth (four) at the same time to further explain the function of the caba unit 53〇, especially the initialization decoding engine (ie the bard reference field group gamma) and the content variable 'at the beginning of the slice, in the decoding corresponding a Before the syntax component of the megablock, the content state and the bar module 624 are initialized. In the embodiment, the driver software i28 issues two ^mIT_ctx and INIT_ADE for this initialization, and the CABAC decoding mode is initialized and green. , or 夕_谷表 ((4) end storage or storage in the face), Li _CTX command can have INIT-CTX SRC2, SRC1 operand SRC1 has response to INIT-CTX instruction 'according to bit position 35 200813884 and H.264 giant map The values related to the block parameters: cabac_init_idc, mbPerLine, constrained_intra_pred_flag, NAL_unit_type (NUT), MbaffFlag, etc. Please note that constrained_intrajpred_flag, NAL_unitJ; ype (NUT), and MbaffFlag correspond to H.264 giant block parameters. In addition, according to the bit position, the operand SRC2 has the following values: SliceQPY and mbAddrCurr, further explained, executing the INIT_CTX instruction (ie, initialization) The CABAC table of contents) requires the cabac_init_idc and sliceQPY (such as quantization) parameters. However, to initialize the entire CABAC # engine requires three instructions, namely INITJBTSR, INIT_CTX, and INIT_ADE, so SRC 1 and ^ SRC2 (such as the full &quot; The available bits in 64 4 or two 32-bit elements can pass other parameters for CABAC neighboring content, so the two source registers SRC1 662 and SRC2 664 can contain the following values: SRC1[15:0 ] = cabac—initidc, SRC 1 [23:16] = mbPerLine SRC 1 [24] = constrained—intra_pred—flag ❿ SRC1 [27:25] = NAL—unit—type (NUT)

SRC1[28] = MbaffFlag SRC1[31:29]=undefined, SRC2[15:0] = SliceQPY • SRC2[31:16] = mbAddrCurr

The value of SliceQPY is used to initialize a state machine (not shown) within bit stream buffer 618b. While various known graphics and slice parameters have been discussed above, a further reference is made to 2008 13884 for some parameters relating to the CABAC unit 530. In one embodiment, the cabac-init-idc is not coded as i_picture(1) and switched to I_picture (SI). Slice (I), in other words, cabac-init_idc can only be defined for P, SP, and B slices. When receiving J and SI slices, cabac-initjdc is the default value. For example, when you want to initialize Into 46 内 内谷 (such as I and SI slices), you can set the cabac-丨仙-say to 3 (because the value of cabac-init-idc can only be 〇~2 according to the H.264 specification), enabling A 2-bit indicates that the slice is I or si. The CABAC unit 530 can also use the INIT-CTX instruction to initialize the area register 612 and the mbNeighCtx memory 610 array structure or component, such as the temporary register associated with the temporary neighboring giant block, see Figure 6D, In one embodiment, the mbNeighCtx memory 610 is located above the graph, and the macroblock reference adjacent content memory of the mbNeighCtx memory 610 is arranged into a memory array to store data about the macroblock column, and the mbNeighCtx memory 610 includes an array. The element he gradually becomes the team i, R i, i+l, ... 119] 601, each element can store a huge block of 12 巨 giant tiles in the block (because HDTV is ΐ92〇χ ι〇8〇) Pixel), currently mbNeighCtx 603 is used to store the currently decoded giant tiles, while the left mbNeighCtx 605 is used to store previously decoded (left) giant tiles, and, in addition, using indicators 607a, 6〇7b and 607c (in the sixth) In the figure D, the arrow • the table does not point to the register 603, 6〇5 and the array element 601. When decoding the current giant tile, the decoded data is stored in the current, when the content nature of the CABAC decoding is known. According to the previous solution The rich information collected in the giant block is used to decode the current giant tile, that is, the left giant tile storage 37 200813884 is on the left side mbNeighCtx 605 and is pointed by the indicator 607b, and the upper giant tile is stored in the array element [i ] and use the indicator 6〇7c for pointing. Continuing to explain the initialization instructions, the INIT-CTX instruction is used to initialize the upper and left indicators 607c and 607b related to the giant tile adjacent to the current giant tile (such as the element of the mbNeighCtx memory 610 array), for example, 'left side The indicator 607b can be set to 〇 and the upper indicator can be set to }, and the INIT-CTX instruction also updates the total register 614. Regarding the initialization content table, in response to calling INIT-CTX, the CABAC unit 530 creates one or more content tables, also referred to as ctx-TABLE. In one embodiment, the table of contents may be a 4x460 x 16-bit table (8 bits). m, 8 bits for η, a signed value or other data structure, each entry of the table of contents contains pStateldx values and valMPS values accessed from pStateldx register 602 and valMPS register 604. The INIT-ADE instruction initiates the BARD module 624, also known as the decoding engine. In one embodiment, after the INIT-BTSR instruction is completed, the call T-ADE is called. After the INIT-ADE instruction is executed, the CABAC unit 530 establishes two. The registers are C0CjlRange register 6〇6 and codlOffset register 608, respectively, with the following instructions or values: codlRange = 0x01FE and codlOffset = ZeroExtend (READ(#9)5 #16) In one embodiment, these The variable can be a 9-bit value. For the codlOffset instruction, the 9-bit is read from the bitstream buffer 618b, and the zero-extended is stored in the 16-bit c〇dl〇fftet register 608. Other embodiments may also use other values. The BARD module 624 uses 38 200813884 = stored in the temporary &amp; 6G6 and 6G8 values to determine whether to output 〇 or 卜. Although the carry decoding is completed, these values will be updated. „In addition to initializing the C〇dlRan register 606 and the codloffset temporary store 608, the INIT-ADE operation simultaneously initializes the binary string register 6 in the example of a pin, the one-bit string register 616 may be % bit. The meta-register receives each output bit from the BARD module 624, and of course _ can use other sizes of registers. When the giant block is encoded into I-PCM data, the BARD module 624 is also initialized. It is known that I-PCM data contains pixel data. According to the Η264 specification, the conversion or prediction model is not applied to the original video data. For example, I-PCM can be applied to lossless coding.

The architecture and instructions relating to parsing bitstreams and initializing various decoding system components have been described. The following describes procedures for binarization, acquisition of model information and content, and decoding based on models and content, typically used by CABAC unit 530. Parsing all possible binarizations of the syntax component (Syntax eiement, SE), or obtaining at least model information via the module 620 and the BIND 10 command, and the CABAC unit 530 further obtains the content of the known syntax component via the GCTX module 622 and the GCTX command. According to the content and model information, the BARD module 624 and the BARD command are subjected to arithmetic decoding. In fact, the GCTX/BARD command is called, and a bit is output to the binary string register 616 until the match is known. The intentional i subcode of the grammatical component will constitute a loop, that is, in one embodiment, after decoding the binary value, the corresponding decoding bit is provided to the binary string register 616, followed by GCTX. Module 622 reads back the contents of binary string register 39 200813884 until a matching word is found. The decoding system architecture using a single CABAC unit 530 is explained in more detail here. Please refer to the sixth A diagram and the sixth B diagram at the same time. The BIND command sent by the driver software 128 enables the 611^1) module 62〇, in one implementation. In the example, the BIND instruction has the following format: BIND DST, #Imml6, SRC1, where DST corresponds to DST register 652, #Imml6 corresponds to the current value of 16 bits, and SRC1 corresponds to input register SRC1 662,BINd The different inputs contain the syntax component (SE, containing the 16-bit current value imm) and the content block type (ctxBlockCat). The syntax component can contain any grammatical component type that conforms to the H.264 specification (eg MB1ypeIia,

MBSkipFlagB, IntraChromaPredMode, etc.), squeaking the BIND command causes the driver software 128 to read the grammatical component from the form (or other data structure) stored in the memory (such as on-wafer memory or remote memory) and obtain the grammar The component index (SEIdx), which is used to access other forms or data structures to obtain the various tile parameters. In one embodiment, the DST register 652 includes a 32-bit scratchpad having the following format: bit 〇_8 (ctxIdxOffset), bit 1 卜 18 (maxBinldxCtx), bit 21-23 (ctxBlockCat), Bits 24-29 (ctxIdxBlockCatOffset), and bit 31 (bypass flag), these numbers

Values (eg, ctxIdxOffset, maxBinlndxCtx, etc.) are passed to the GCTX module 622 for use as a content model analysis. In this embodiment, any undefined remaining bits may be 〇, based on the syntax component index and ctxBlockCat pairing results. , ctxIdxBlockOfftet can be obtained from the remote storage 200813884 or a form or other data structure stored on the on-chip memory. Table 1 illustrates the contents of a non-limiting embodiment: Table 1

codeNum (k) Coded_block_pattem Intra-4x4 Inter 0 47 0 1 31 16 2 15 1 3 0 2 4 23 4 5 27 8 6 29 32 7 30 3 8 7 5 9 11 10 10 13 12 11 14 15 12 39 47 13 43 7 14 45 11 15 46 13 16 16 14 17 3 6 18 5 9 19 10 31 20 12 35 21 19 37 22 21 42 23 26 44 24 28 33 25 35 34 26 37 36 27 42 40 28 44 39 29 1 43 30 2 45 31 4 46 32 8 17 33 17 18 34 18 20 41 200813884 35 20 24 36 24 19 37 6 21 38 9 26 39 22 28 40 25 23 41 32 27 42 33 29 43 34 30 44 36 22 45 40 25 46 38 38 47 41 41 If an undefined ctxBlockCat is received, CABAC unit 530 can treat the undefined parameter as 0, so treat ctxIdxBlockOffset as a 0 value. Calling BIND will also cause the reset signal (Rst_signal) to be output from BIND module 620 to BARD. Module 624 is illustrated below.

In order to explain various inputs and outputs of the BIND module 620, at least one embodiment is described herein to illustrate the operation of the BIND module 620. When the BIND module 620 is called, the BIND module 620 extracts the syntax components and provides a method via the software k. The component index (SEIdx), using the syntax component index, the module 620 looks up the form to obtain the corresponding values of maxBjnidxCtx, ctxIdxOffset, and bypassFlag, and these search values are temporarily stored in the pre-defined bit of the dst register 652 with f, in addition, Using the grammatical component and ctxBlockCat, the BIND module 620 performs a second form lookup (such as from a remote clock or (9) on the memory). For the value of 畑(10)(4), the first search value is temporarily stored in the DST register, so the decision value will be used to create the DST register, 652, as the ^ bit value output target. 42 200813884 For some grammatical components, other information (except for ctxBlockCat) can be used to start the 264264 decoding operation. For example, SigCoeffFlag and lastSigCoeffFlag, array elements stored in the macroblock adjacent to the content memory 610. The values in the macro block and the input ctxBlockCat value can be used to determine whether the giant block is field code or frame code. SigCoeffFlag and lastSigCoeffFlag will be different depending on whether the picture is field code or frame code. The encoding, in some embodiments, even for different syntax components, these flags use the same number of syntax components and then distinguish them using mb-field-decoding_flag ( mbNeighCtx[l]). In addition to the functions listed above for the BIND module 620, in the sixth b diagram, the BIND module 620 is also associated with the binldx register 654, the multiplexer unit 656, and/or the transfer register 666 and/or 668 ( In the sixth c-picture, the F1) connection, the multiplexer unit 650 provides an output SRC1 (such as the value in the register SRC1) to the GCTX module 622 according to each input. As for the transfer register labeled F1, when the BIND (or GCTX) Lu command produces a result, the result is written to the target register (such as DST register 652) and/or the transfer indicated as F1. 666 and 668, an instruction and corresponding module (such as GCTX module 622 or BARD module 624). 疋 No use of transfer registers 666 and 668 will use the transfer flag table in the instruction. The symbols representing the transfer registers 666 and 668 are F1 666 (using the value of forwarding source 1, which can be represented by bit 26 in the instruction in one embodiment) and F2 668 (using the value of forwarding source 2, In one embodiment, the bit 27 in the command can be indicated), and the data is forwarded to the GCTX module 622 43 200813884 and the BARD module 624 ' respectively. The BIND module 620 and related programs have been described. Here, how the GCTX module 622 and the GCTX command can obtain the binary index of the known model. In short, the rounding of the GCTX module 622 includes maxBinldxCtx and binldx. And CtxIdx〇ffset, the GCTX module uses the CMdxOffset and binldx values to calculate the value of CtxIdx (for rounding, representing the content index). ^ The sample format of the GCTX instruction is as follows: • GCTX DST, SRC2, SRC 1, where SRC1 corresponds to the output value of multiplexer unit 656 and is stored in register SRC1 662, and SRC2 corresponds to the output value of DST register 652. And stored in the scratchpad SRC2 664, and the DST corresponds to the target register. In one embodiment, each register has the following values: SRC1 [7:0] = binldx ; if the current syntax component contains a codedBlockPattern, then The value of SRC1 (output from multiplexer unit 656 and as input to GCTX module 622) may be the value of binidx * register 654. SRC1 [15:8] can be levelListldx (when calculating sigCoeffFlag, lastSigCoeffFlag) or mbPartldx (when 'calculating code block pattern Ref_Idx or binldx), that is, when the .syntax component is sigCoeffFlag or lastSigCoeffFlag, the multiplexer unit 656 can be used to transfer levelListldx. SRC1 [16] may contain the iCbCr flag. When the value is 0, the block is a Cb chrominance block. In addition, SRC1 [16] may contain L0/L1 44 200813884 value, and if it is L0, its value is 0. Those skilled in the art will appreciate from the teachings of the present invention that L0/L1 is a graphical reference list for motion compensated prediction (LO = listO, LI = listl). SRC1 [21:20] = mbPartitionMode SRC2 [8:0] two ctxIdxOffset SRC2 [18:16] = maxBinldxCtx SRC2 [23:31] = ctxBlockCat SRC2 [29:24] = ctxIdxBlockOffset 畚SRC2 [31] = bypassFlag Come again, The DST includes the output of the GCTX module 622 and has the following values: DST [15:00] = ctxldx DST [ 23:16] = binldx DST [ 27:24] = mbPartldx DST [29:28] = mbPartitionMode DST [30] = L0 ^ GCTX module 622 can interact with the transfer register, so the instruction format using the transfer register can be GCTX.F1.F2, where jq and F2 represent the use of transfer registers 666 and 668, respectively. That is, there are two elements (F1 and F2) in the instruction code. If one or two transfer flags are missing, then the transfer register is used, and if these bits are set (for example, δ is converted into 1), it means using the value of the transfer register (internal generated value), otherwise 'use the value of the source register'. Therefore, the protection of this transfer register is that when the earliest instruction is issued, Provide compiler hints: Fruit: There is a use of forwarding, the order in the source register may be encountered after writing ^ 45 2008138 84 (read-after-write) risk. For the GCTX instruction, if the reset signal Rst_Signal is set, the value of the Bay 1J SRC1 is 〇 'if (F1 &amp; rst - dish 1), then the value of srci will be the value in the GCTX module 622 plus the SRC1 will It is the binldx value obtained from the execution of the single buffer. The output of the BIND module 620 can be used as the value of SRC2 for the GCTX and BARD instructions. At this time, the BIND will not be issued until the BARD instruction uses the transfer register. The instruction further explains that the Rst-Signal and F1 forwarding signals will be combined into a single signal _ 唬{F1,reset) (2-bit signal), indicating that the SRC1 value input to the GCTX module 622 includes the binldx value or the forwarding value. Another role of providing Rst-Signal is to clear and reset the binary string 616 and reset the binIdx register 654 to 〇. Continuing to discuss the GCTX module 622 and obtaining content information, in one embodiment, Tables 2 and 3 list (4) respectively correspond to the Didi (3) memory 610 and the current mbNeighCtx register 6〇3, as described above. , mbNeig, hCtx register 603 contains the decoding output of the current giant block, when the end of the processing of the δ uranium giant block, the CWRITE command is issued, and the information of the current mbNeighCtx register and 603 is copied to the heart level. The corresponding position of the array of memory 610, this copied information will later be used as the top-adjacent value. Table 2 transform size 8x8 flag mb field decode flag mb skip-flag_ Intra-chroma_pred-mode mb tvoe —number (bit) — 0 1 2 2 4:3 7:5 Parameters 46 200813884

codedBlockPattemLuma 4 11:8 codedBlockPattemChroma 2 13:12 codedFlagY 1 14 codedFlagCb 1 15 codedFlagCr 1 16 codedFlagTrans 8 24:17 refldx 8 32:25 predMode 4 36:33 Table 3 Parameter Number of Bits (Bit) transform_size_8x8_flag 1 0 mbfielddecodeflag 1 1 Mb_skip_flag 1 2 Intra_chroma_pred_mode 2 4:3 mbQpDeltaGTO 1 88 codedBlockPattemLuma 4 11:8 codedBlockPattemChroma 2 13:12 codedFlagY 1 14 codedFlagCb 1 15 codedFlagCr 1 16 codedFlagTrans 24 87:64 refldx 16 52:37 predMode 8 60:53 mb_type 3 63 : 61 In an embodiment, codedFlagTrans is divided into three segments. For example, the first 4 bits are related to ctxBlockCat being 0 or 1. The higher 4 bits are related to ctxBlockCat being 3 or 4. The higher 4 bits are also divided into two. In part, when the lower 2 bits are used for iCbCr 2, and the other 2 bits are used for iCbCr 2, the prediction mode (predMode) has three options: predLO == 0, predLl =^ NiPred = 2 ° Figure E shows the structure implementation of one of the refldx in Table 2 and Table 3. In 2008, the example of refldx is used to reconstruct the graphics to provide memory and logic circuits. The shape of the best graph; =: The knot refldx structure includes the first column of the series 6〇9'\Fig. (oil (4) 611 (4 in the figure), L0/Ll value 613, ^= L0 and L1 values There are on the other side of the German - and the parent = 疋 _ (greater than 0) 615 and ^;, although the need is the giant block of the bottom column, usually the access is the upper adjacent giant block _, giant Tile reference

:, form 4 giant block partitions 611, for each value of 613, but not the true value, that is, the value of touch L0 and L1 is i or greater than! That is, in the embodiment, the judgment is completed by storing 2 bits (10) and 617, which is used to calculate the syntax component (refldx). Further advancement to the domain of the dx structure is performed twice. If optimization is performed, only 2 bits are reserved (although the reference value is usually large), CABAC unit 530 does not need to decode refldx. The bit is decoded and stored in the execution unit register or memory (such as L2 cache 408). The second optimization only retains 4 elements (2 left and 2 above). These four elements are reused, and the final value is written to the adjacent element by the CWRITE instruction, because currently the mbNeighCtx register 603 only needs to retain 16 bits, the left mbNeighCtx register 605 and the array 010 above the mbNeighCtx element 601 only It requires 8 bits, so it can save memory. At the same time, because it no longer counts the decoding reference value, it replaces the B〇〇iean operation with fewer bits, which also saves the computational logic circuit. 48 200813884 Table 4 shows the included mb_type : Table 4

Mb_type name, 4fb000 SI 4Ab001 I_4x4 or I-NxN 4'b010 work 16x16 4, b011 I_PCM 4, bl00 P_8x8 4, bl01 B-8x8 4'bllO B_Direct_l6x16 4, bll Others You can also use the sixth B picture without the output or The scratchpads discussed are like mbPerLine (8-bit, no sign), mb-qp-delta (8-bit 'with sign), and mbAddrCurr (16-bit, current giant block address), for AddrCurr, which provides a 1920 χ 1 〇 8 〇 array, although only 13 bits are needed, some embodiments may use 16 bits to improve 16-bit computational efficiency. The total register 614 also stores values obtained from the above registers (e.g., mbPerline, mb AddrCurr, and mb_qp-delta), that is, the values stored in the total register 614 are also stored in other temporary stores. In an embodiment, the total register 614 includes a 32-bit scratchpad, internally including values corresponding to mbPerline, mb AddrCurr, and mb qp delta, and others corresponding to the NUT , MBAFF_FLAG, and the value of chroma_format_idc. The INSERT instruction can be used to update the stalls of the total register 614. The format of the INSERT instruction can be: INSERT DST, #Imm, SRC1 49 200813884 In this INSERT instruction, #Imm contains 10 digits, the first 5 bits of the data. The width and the upper 5 bits specify where the data will be inserted. The input parameters have the following format:

Mask = NOT(0xFFFFFFFF«#Imm[4:0])

Data = SRC 1 &amp; Mask SDATA = Data«#Imm[9:5] SMask = Mask«#Imm[9:5] The output DST can be expressed as:

# DST = (DST &amp; NOT(sMask)) I SDATA At least some fields (such as NUT (NAL_UNIT_TYPE), C (constrained-intra)) red-flag), MBAFF FLAG can also be used with the INIT_CTX instruction. The values of mbPerLine, and mbAddrCurr) are written/initialized to the scratchpad 614. In an embodiment, the area register 612 includes a 32-bit scratchpad including intercepts corresponding to b, mb_qp_delta, numDecodAbsLevelEql, and numDecodAbsLevelGtl, which can be updated by using the INSERT instruction to initialize the area temporary storage. After 612, b = 0, mb_qp-delta = 0, numDecodAbsLevelEql two-1, and numDecodAbsLevelGtl = 0, can be performed using the following format instructions: • Initialization: , CWRITE SRC1, where SRC 1 [15:0] = mbAddrCurr, CWRITE SRC1 Updates the mbAddrCurr block of the total scratchpad 614, and the CWRITE instruction has other functions 'to discuss the adjacent element structure early and how to use it in the decoding program 50 200813884, which will be further explained. In the CABAC decoding process, based on the prediction and/or pattern analysis syntax values of adjacent giant tiles (eg, left and above), several methods are described below to describe how the CABAC unit 530 determines the left and upper adjacent giant tiles. And determining whether the macroblocks exist, the symbol decoding stage utilizes the mbPerLine parameter, as previously described, the decoding program uses neighboring values (such as giant tiles or blocks on the top, side or left side), in one embodiment, the BARD module 624 uses the current giant block number and the number of giant blocks (mbperL (4) to calculate the following formula to calculate the upper block address and determine whether the left and top giant blocks exist. For example, to judge Whether an adjacent giant tile (such as the left giant tile) exists (valid), an operation (such as mbCurrAddr % mbPerLine) must be performed to check whether the result is 〇. In one embodiment, the following equation is performed: mbCurrAddr - x mbPerLine :[mbCurrAddr VombPerLine) mbCurrAddr mbPerLine

mbCurrAddr represents the current giant tile position corresponding to the binary symbol to be decoded, and mbPerLine represents the number of giant tiles for each column. The above calculation uses a division, a multiplication, and a subtraction. Further explaining the decoding mechanism of the BARD module 624, please refer to the sixth F picture, which shows the graphic to be decoded (16 χ 8 giant tiles, thus mbPerLin=16), if the decoding giant block 35 (mbC cloud nt is 35) , the huge block 36 has not been completely decoded), the data of the upper block and the left block 34 of the previous decoding are needed, and the information of the upper block can be obtained from 200813884 mbNeighCtx[i], where i = mbCuirent % mbPerLine In this example, i = 35% 16 = 3. When the current giant tile is decoded, the left mbNeighCtx register 605 and the mbNeighCtx[i] 601 in the array are updated with the CWRITE instruction. In another example, consider the following formula: mbCurrAddr s [〇: maxMB-\] where maxMB is 8192 ' and mbPerLine = 120. In one embodiment, multiplication and a form stored on the memory on the wafer may be utilized ( For example, 12〇χ11 bit table) find (Ι/mbPerLine) for division. If mbCurrentAddr is 13 bits, use 13 χΐΐ multiplier. In one embodiment, 'the result of multiplication is taken as an integer. The upper bit performs 13x7 multiplication, stores the lower 13 bits, and finally performs 13-bit subtraction to determine a. The entire operation requires 2 cycles. This result can be stored for other operations. Calculated once mbCurrAddr changes. In some embodiments, no modulo operation is performed, and the color filter logic in the execution unit (e.g., execution unit 420a, 420b, etc.) provides the first mbAddrCmr value, which is assigned to the first slice. The first line 'For example, this shader logic can perform the following calculations: mbAddrCurr = absoluteMbAddrCurr - nx mbPerLine because the mac·264 flexible macr〇bl〇ck ordering (FMO) pattern has some complicated phases Neighboring structure, in order to process these modes, a colorizer of the decoding system 200 is added to calculate the left/upper availability and loaded into one or more registers of the CABAC unit 530, if not loaded 52 200813884 (off-loading The CABAC unit 530, when enabling all η.264 modes to support symbol decoding, can reduce the complexity of the hardware. The CWRITE command is copied from the appropriate field of the current mbNeighCtx 603 to the upper mbNeighCtx[] 601 and the left mbNeighCtx[] (such as the left macro block in array 610), according to whether mBaffFrameFlag (MBAFF) is set and the current and previous giant blocks are The decoding method is field decoding or frame decoding. The specific factor 'writes the data to the specific upper m] 3NeighCtx[] 601 and the left mbNeighCtx[], when (mbAddrCurr % mbPerLine two = . 0), the left mbNeighCtxLeft 605 is marked as Does not exist (eg, initialized to 0) 'The CWRITE command can be used to "move" 111|5]^6丨811 (1^memory 610, area register 612, and total register 614 contents, for example, The CWRITE instruction moves the relevant inner valley of the mbNeighCtx memory 610 to the left and upper blocks of the i-th macroblock (such as j^NeighCtxfi) or the current giant block), and clears the mbNeighCtx register 603, as described above. The two indicators related to the mbNeighCtx memory are the left indicator 6〇7b and the upper indicator 607c. After the CWRITE instruction, the upper index is increased by 1, ❿ while the current giant block content is moved to the upper position and the left position of the array. The above system can reduce the number of read/write ports of the memory array to one read/write port. The mbNeighCtx memory 610, the _ region register 612, and the total register 614 can be updated by the 1NSERT instruction. Content, for example,

Use the INSERT instruction (such as INSERT #ImmlO, SRCl) to write the current giant tile. The subsequent operations will not affect the left indicator 607b and the upper indicator 6〇7c (only the current position is written). 53 200813884 The INSERT command and the update of the BARD module 624 will be written to the current mbNeighCtx array element 6〇ι of the mbNeighCtx memory 610, and the left indicator 607b points to the element of the memory 610, which is adjacent to the adjacent array element (next to mbNeighCtx 601, for example, mbNeighCtx[ii]j is the same. The above describes the content and model information. Next, the BARD module 624 and how to decode and decode according to the content and model information, the BARD module 624 is operated by the BARD command, BARD. The format of the instruction can be: ° BARD DST, SRC2, SRC 1, providing a carry-in nose decoding 彳 ' ' 'Every binary decoding to form a single bit output, the input parameters are as follows: SRC1 = biuldx/ctxldx, this is The output of the GCTX module 622 is SRC2 = bypassFlag, which is the output of the BIND module 620. If the transfer register is used, the format can be BARD.F1.F2, where jq and F2 represent the transfer registers 666 and 668, If one or two forwarding flags are missing, this means that the corresponding forwarding register is not used. As mentioned earlier, the BARD module 624 receives the RST_Signal and receives it. After the signal, RST_Signal is reserved until the first call to the BARD command, and then the signal is cleared. ... During the operation, the BARD module 624 receives the content index (ctxldx) value from the GCTX module 622 and the current bit parsing position to the encoded bit stream. The indicator (binldx), the BARD module 624 uses the compensation and range values received from the c〇dl〇ffset register 608 and the codlRange register 606 to record the current interval of the decoding engine at 54 200813884 (compensation, compensation + Scope) state, BARD loose group 624 uses the content to access the table of contents (ctX-Table), sequentially use the inner table to access the current possibility state pStateIdx and MPS value, pstateldx read (from storage) The form of the memory on the remote memory or on the wafer) LPS sub-range value, next Mps value, and next Lps probability 0

According to the state, the next range and the possibility information of the MPS value, the BARD module 624 calculates the MPS value of the current binary symbol, and the BARD module 624 outputs a binary symbol (bit or binary value, such as bG, br· • bn) to the carry string register 616, which is then repeated for the same or different contents of the next binary value, as shown in the figure from the binary string 616 register to the GCTX module 622. The feedback wiring 658, according to the selection of the MPS value, the BARD module 624 also updates the probability state of the compensation, the range value, and the second-two-digit value. In addition, the BARD module 024 writes the current MPS and the possibility state to the content table. For later use. Regarding the use of the transfer registers 666 and 668, if the notification "can be delayed or not delayed", for example, there is no delay in forwarding from the bind module 620 to the GCTX module 622, so in the next cycle, The GCTX command is issued; and the transfer from the GCTX module 622 to the BARD module 624 takes 4 cycles. If the GCTX command is issued in the cycle j, the BARD command may be issued in the cycle (j+5) with no instruction gap in the middle. Then fill in 4 NOPs; there is no delay in forwarding from BIND module 620 to BARD module 624; if BARD module 624 is forwarded to GCTX module 622 55 200813884, if BARD command is issued in cycle j, then in the cycle (j+5) issue the GCTX command; if the second binary string is reserved and switched, the BARD module 624 is forwarded to the BIND module 620 without delay. To retain the second binary string, It is possible to issue a bard to bard '々; there is a delayed bypass.

It should be emphasized that the above-described embodiments or "preferred" embodiments of the present invention are only possible examples, and are merely illustrative of the principles of the present invention, even if the above-mentioned implementations are modified, modified, and modified. However, they do not deviate from the spirit and rewards of the system and the greens mentioned in this article. All such changes should be covered in the scope of this case. [Simplified description of the schema] The implementation of the method disclosed herein can be referred to the lower touch to obtain a deeper understanding of the elements of the type 1 towel without limiting its size _, only for clearing the original picture of the present invention The middle phase (four) reference numerals represent block diagrams of corresponding portions of the graphics processor system embodiment in which a decoding system (and method) embodiment can be implemented. The financial processing environment (4), its + can perform a variety of decoding systems. The third figure: The second figure illustrates the block diagram of the selected components in the processing environment. Fourth Figure: Second and Third Figures illustrate a computational core block within a processing environment 56 200813884 Figure - 'T' can implement a variety of decoding system embodiments. The fifth a picture: the fourth time calculation core -, its t can be implemented in a variety of decoding pure embodiment. 70. Mei Element Block Figure 5B: Embodiment of the decoding system of the execution unit data path. Ghost map, which can be implemented in a variety of six-figure diagrams. The fifth embodiment of the decoding system embodiment = six B-picture: the block diagram of the sixth A-picture decoding system. ‘Different C C: The bitstream block diagram of the sixth a-picture decoding system. The sixth D figure · The sixth A picture decoding system content block diagram of the register embodiment. The sixth figure is a block diagram of the giant example of the decoding system of the sixth A picture. The sixth F map uses a block diagram of the sixth A picture decoding mechanism. Mosquito diagram buffer embodiment embodiment of the memory structure and related tile segmentation mode embodiment of the giant block decoding [main component symbol description] The s parts included in the diagram of this case are as follows: 1 〇〇 graphics processor System 1 显示 4 display interface unit 11 () memory interface unit 118 bus interface interface unit 102 display attack 106 area memory H4 graphics processing unit 122 chip group 57 200813884 124 s s 体 126 central processing unit 128 driver software 200 decoding system 2〇2 graphics processor 204 computing core 2〇6 execution unit set control and vertex/streaming memory unit drawing pipeline 302 texture filtering unit 304 pixel packing element 308 write back unit 402 execution unit input 4〇6 Memory access unit 41 〇 memory interface arbiter 413 wiring 306 command stream processor 310 texture address generator 4 〇 4 execution unit output 408 L2 cache memory 412 execution unit set 420 execution unit 504 instruction cache memory Controller 5〇6 thread controller 508 buffer 51〇shared register (4) commit unit data path 514 execution unit data path first First in first out buffer

516 section temporary register file (10) scalar ^ device file, data output controller, like thread task interface 526 register file ^ ^ ns 532 vector floating point unit series unit 530 CABAC unit 534 vector integer arithmetic logic 536 special Destination unit 540 register file 544 current signal line 6〇2 state cable bow register 538 multiplexer 542 operation signal line 601 array element 603 current mb]SfeighCtx 58 200813884 604 high possible symbol value register 605 left mbNeighCtx 606 code length range register 607 indicator 608 code length compensation register 609 giant block column 610 giant picture block adjacent content memory 611 giant picture block partition 612 area register 613 L0/L1 value 614 total Memory

615 Gtl 617 GtO 616 binary string register

618 shift temporary storage ^ stream buffer ϋ / direct memory access platter 620 binary module 622 acquisition content module 624 binary arithmetic decoding 丨 丨 628 target bus 632 source bus 636 delay / reset convergence 640 data bus 652 DST register 656 multiplexer unit 660CABAC logic module 664 operation unit register 668 transfer register 630 source bus 634 command and thread information bus 638 address bus 650 memory Module 654 Binldx register, 658 feedback wiring 662 operation unit register 666 transfer register 59

Claims (1)

200813884 X. Patent application scope: 1. A decoding system, comprising: a software programmable core processing unit having a context-adaptive binary arithmetic 'CABAC' for performing a shader a unit that performs CABAC decoding of a video stream and provides a decoded data output, wherein the CABAC decoding is performed using a hardware-compatible software. 2. The system of claim i, wherein the CABAC decoding is performed by the hardware programmed in the graphics processing unit with the contents of the graphics processing unit programming. The system __________ as described in claim 1 of the patent application scope includes a binary (BIND) module for receiving the first language; the component and the content block type a message, at the same time, should bind~; the group executes the shader---the instruction, according to the first-number, provides the second information of the 7 or more story block parameters, for the content model to be distracted. 3 Yun Xuan _, the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ For the purpose of binary decoding. 200813884: The system of the highest possible symbol value two === yuan &amp; Rjli range of the fourth item, wherein the CABAC single: bit value binary ar arithmetic decoding (bard) module For receiving the binary module execution::::, "compensation, and - range, and because of the bard person - the third instruction, decoding a binary symbol. 7 yuan package application - patent model The system of item 6, wherein the CABAC unit is connected to the string register to receive the decoded binary bit The defending is for updating the content information. For example, the seventh paragraph of the patent application scope is used for the receiver/speaker, the first one of the digits, and the first digit of the grammar component. If the patent application scope is in item i, the yuan is based on the position in the command, wherein the CABAC single shipment has been a# θ 70, and is judged to be stored in the previous supply of the internal register; Yes - whether the data in the source operand can be used by one or more modules in the current operation. For example, the system described in claim 1 of the patent scope, wherein the CABAC 61 200813884 ^ direct access has been accessed (direct Memory access, DMA) engine module, which has a turbulence buffer and a DMA engine, and the 3 fMA engine module uses the bit for each slice executed by the shader. The predetermined number of bits in the stream are automatically re-inputted into the bit of the phase 1 corresponding to the video stream. The system of claim 10, wherein the CABAC Zhuo 7 〇因 should bit ##佐佐:口_Λ/ΓΑ, there is a possibility of a downward overflow in the claw buffer, delaying the DMA engine module. 12. If the patent application is used to record the system described in the item, where the DMA reference (4) is used Bit reading, and according to the calculation, and control: transfer the bit stream buffer to transport 'L two please = the system described in item 1 'more include - content memory array package: t base decoding And corresponding to the use of the scratchpad, wherein the content GCTX module is executed, and the elements of the current and adjacent giant block are stored in accordance with the logic of the Boolean logic carrier - the fifth instruction 'the GCTX module root The memory shifts the content memory array including values from the ^ to the side content memory array. 14·^ Kind of exhaustion method, the system (4) (4): The test color is loaded into a processing unit with a CABAC unit 62 200813884 processing unit; the device is decoded by CABAC to execute the colored video stream on the CABAC unit; And provide a decoded data round. M claims the method of claim 14, wherein the CABAC port rf is performed by the graphics processing unit programming content in conjunction with the hardware processing in the graphics processing early lean path. 16. The method of claim 14, further comprising the step of: the BIND pull group receiving the first information including the grammar component and a content block type; and ^# responsive to the BIND module executing the shader One of the first instructions provides a second information corresponding to one or more giant tile parameters for the content model analysis based on the name. .17. The method of claim 16, further comprising the step of: • receiving, by the GCTX module, the second information; and generating, by the GCTX module, a second instruction of the shader to generate a binary carry A value and a content identifier for binary decoding, wherein the internal identifier corresponds to a high possible symbol (MPS) value or a low possible number (LPS) probability. 18. The method of claim 17, further comprising the step of: 63 200813884 A BARD module receives the binary value and content identifier, a compensation, and a range; and the BARD module performs the A third instruction of the shader that decodes one or more binary symbols. 19. The method of claim 18, further comprising the step of: receiving, by the binary string register, the one or more decoded binary symbols, the one or more decoded binary symbols representing A syntax for decoding || components; and providing updated content information. 20. The method of claim 14, further comprising the step of: using a bit within an instruction to determine whether a previous operation result stored in an internal register is available, or in a source operation element Whether the data can be used by one or more modules in the current calculation. • 21. The method of claim 14, further comprising the step of: automatically repeating the predetermined number of bits when the decoding program has used a predetermined number of bits within the bit stream, the bit Corresponds to the video stream. 22. The method of claim 14, further comprising the step of: delaying the DMA engine module in response to the possibility of a downflow in the bit stream buffer. 64 200813884 23. The method of claim 21, further comprising the steps of: recording the number of bits used in the bit stream buffer, and detecting that the number of bits is greater than a predetermined value, The bitstream buffer operation is suspended and control is transferred to a host processor. 24. The method of claim 14, further comprising the step of: writing a content memory array for CABAC decoding according to a Boolean logic operation, including a value from a scratchpad as the content memory Move to the content memory array. 65