CN103678159B - Data storage device and a data writing method - Google Patents

Data storage device and a data writing method Download PDF

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CN103678159B
CN103678159B CN201310753090.7A CN201310753090A CN103678159B CN 103678159 B CN103678159 B CN 103678159B CN 201310753090 A CN201310753090 A CN 201310753090A CN 103678159 B CN103678159 B CN 103678159B
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memory
data
block
memory block
address
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CN103678159A (en
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蔡金印
赖义麟
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威盛电子股份有限公司
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Abstract

一种数据储存装置及其数据写入方法,其中数据储存装置包括一非易失性存储器单元及一控制单元,非易失性存储器单元包括至少一第一存储器芯片及一第二存储器芯片,第一存储器芯片至少包括一第一存储器区块以及一第二存储器区块,第二存储器芯片至少包括一第三存储器区块以及一第四存储器区块,控制单元将来自主机的第一储存数据和第二储存数据并行地分别储存至非易失性存储器单元的第一存储器区块及第三存储器区块,并将第一储存数据和第二储存数据复制至非易失性存储器单元的第二存储器区块及第四存储器区块。 A data storage device and a data writing method, wherein the data storage means comprises a non-volatile memory unit, and a control unit, a nonvolatile memory cell comprising at least a first memory chip and a second memory chip, the first a memory chip comprising at least a first memory block and a second memory bank, second memory chip memory block comprises at least a third and a fourth memory block, the control unit stores data from the first host and second storage data are stored in parallel to the non-volatile memory cell of the first memory bank and the third memory bank, and store the first data and the second copy data is stored to the nonvolatile memory cells of the second memory bank and the fourth memory blocks.

Description

数据储存装置及其数据写入方法 Data storage device and a data writing method

技术领域 FIELD

[0001]本发明涉及数据储存技术,特别是涉及一种数据储存装置及其数据写入方法。 [0001] The present invention relates to data storage technology, particularly to a data storage device and a data writing method.

背景技术 Background technique

[0002]随着半导体技术的进步,存储器的容量已大幅提升,其单价则相对降低。 [0002] With the advancement of semiconductor technology, memory capacity has been significantly improved, its unit price is relatively decreased. 其中,快闪存储器(Flash Memory)因具有非易失性、省电、体积小与无机械结构等的特性,特别适合使用于便携式电子产品,因此近年来也发展出一种使用与非门(NAND)快闪存储器做为数据储存媒介的固态储存装置(Solid State Disk,SSD)。 Wherein the flash memory (Flash Memory) because of having nonvolatile characteristics, low power consumption, small size and no mechanical structure or the like, particularly suitable for use in portable electronic products, and therefore in recent years developed a NAND gate using ( the NAND) flash memory as a data medium solid state storage device (solid State Disk, SSD) storage. 固态储存装置的特别之处在于利用快闪存储器的特性来取代传统储存装置的机械结构,藉由区块写入和擦除的方式进行数据存取,因此可大幅提升储存装置的读写效率,与传统的储存装置相较,具有低耗电、耐震、稳定性尚、耐低温等优点。 Special solid state storage device is to utilize the characteristics of the flash memory to replace the mechanical structure of a conventional storage device, by way of a block for data write and erase access, thus greatly enhance the efficiency of the storage device reader, compared with the conventional storage device, having a low power consumption, shock, yet stable, low temperature resistance and other advantages.

[0003] NAND快闪存储器可分为单层存储单元(Single Level Cell,SLC)NAND快闪存储器与多层存储单元(Multi Level Cell,MLC)NAND快闪存储器。 [0003] NAND flash memory can be divided into single memory cell (Single Level Cell, SLC) NAND flash memory and multi-layered memory unit (Multi Level Cell, MLC) NAND flash memory. 其中,SLC NAND快闪存储器使用一组高低电压以区分出两种电荷值(包括0、1),而MLC NAND快闪存储器则采用较高的电压驱动,并通过不同级别的电压记录两位的信息(包括00、01、11、10),因此MLC NAND快闪存储器数据记录的密度会比SLC NAND快闪存储器多一倍。 Wherein, SLC NAND flash memory using a set of low voltage to distinguish two kinds of charge value (including 0), and the MLC NAND flash memory is used a high voltage drive, and the recording of two different levels of the voltage information (including 00,01,11,10), so the data recording MLC NAND flash memory will be more than double the density of SLC NAND flash memory.

[0004]在SLC NAND快闪存储器中,每次写入数据至页面时能对此页面进行多次的编程,因此在SLC NAND快闪存储器中每次编程的数据量可小于一个页面。 [0004] In the SLC NAND flash memory, each time data is written to this page to the page can be programmed several times, each time the amount of programming data in the page may be smaller than a SLC NAND flash memory. 然而,在MLC NAND快闪存储器中每次写入数据至页时仅能对此页编程I次,因此在MLC NAND型快闪存储器中会以一个页的数据量为单位进行编程。 However, MLC NAND flash memory page programming, each write data only to this page I times, therefore the amount of data to be programmed in units of a page MLC NAND flash memory.

[0005]此外,MLC NAND快闪存储器包括多个实体区块(block),每个实体区块又包括多个实体页(page)。 [0005] Further, MLC NAND flash memory comprises a plurality of physical blocks (block), each entity comprises a plurality of physical blocks and pages (page). 在MLC区块中写入数据需依照其页面顺序依序写入。 MLC write data block are sequentially written in accordance with the required page order thereof. I个MLC实体页可以写入2个页数据,其中写入同一个MLC实体页的这二个页数据被称为配对页。 I can write a page entity MLC two pages of data, wherein the page data is written to these two entities with a MLC page is called page pairing. 假设在配对页中的第一个页数据写入MLC实体页后,而且在配对页中的第二个页数据尚未完成写入前,MLC快闪存储器发生了断电事件(或其他不可预期的干扰事件)而中断了所述第二个页数据的写入操作。 After the pairing is assumed that the first page in a page data write MLC physical page, the second page and the page data in the pair before writing, MLC flash memory power outage event occurs has not been completed (or other unexpected interference events) interrupted the write operation of the second page of data. 在重新上电后,配对页中的所述第二个页数据会再一次被写入所述MLC实体页。 After the power on again, the pairing of the second page in the page data can be written to the MLC again page entity. 然而,重复对所述MLC实体页写入所述第二个页数据除了会使所述第二个页数据发生数据错误外,还会造成所述MLC实体页中的所述第一个页数据佚失。 However, repeated writing the page data to the second entity MLC page data in addition to data error occurred on the second page of the cause, it will also result in the MLC entity page data on a page get lost. 因此,传统MLC快闪存储器会因为发生断电事件而可能造成数据错误/佚失。 Therefore, the traditional MLC flash memory because of the power outage event occurs which may result in data errors / get lost.

发明内容 SUMMARY

[0006]本发明提供一种数据储存装置及其数据写入方法,可在写入数据时避免因断电或其他事件而造成数据错误/佚失。 [0006] The present invention provides a data storage device and a data writing method for writing data can be avoided due to power failure or other event causing data errors / get lost.

[0007]本发明的数据储存装置,包括非易失性存储器单元以及控制单元。 The data storage apparatus [0007] according to the present invention, comprising a nonvolatile memory cell and a control unit. 其中非易失性存储器单元包括至少第一存储器芯片及第二存储器芯片,第一存储器芯片包括至少第一存储器区块以及第二存储器区块,第二存储器芯片包括至少第三存储器区块以及第四存储器区块。 Wherein the nonvolatile memory cell includes at least a first memory chip and the second memory chip, the first memory chip comprises at least a first memory bank and a second memory bank, second memory chip comprising at least a third memory bank and a second four memory blocks. 控制单元耦接非易失性存储器单元,其中控制单元将来自数据储存装置外部的主机的第一储存数据和第二储存数据并行地分别储存至第一存储器区块及第三存储器区块,以及将第一储存数据和第二储存数据并行地分别复制至第二存储器区块及第四存储器区块。 The control unit is coupled to the non-volatile memory cells, wherein the control unit stores data from the first external data storage device and a second storage main data are stored in parallel to the first memory bank and the third memory bank, and storing the first data and the second data storage are copied in parallel to a second memory block and the fourth memory bank.

[0008]本发明的数据储存装置的数据写入方法包括下列步骤。 [0008] The data writing method of data storage device according to the present invention comprises the following steps. 将来自数据储存装置外部的主机的第一储存数据和第二储存数据并行地分别储存至第一存储器区块及第三存储器区块。 A first and a second data storage storing data from the host data storage device of the external storage, respectively, in parallel to the first memory bank and the third memory bank. 将第一储存数据和第二储存数据并行地分别复制至第二存储器区块及第四存储器区块。 Storing the first data and the second data storage are copied in parallel to a second memory block and the fourth memory bank.

[0009]基于上述,藉由将来自主机的多笔储存数据并行地储存至不同的存储器芯片(第一/第三存储器区块),并将这些储存数据于各个存储器芯片内并行地做复制(第二/第四存储器区块),以达到避免数据写入多层存储单元快闪存储器区块时因断电造成数据错误/佚失的情形。 [0009] Based on the above, by the pen storing a plurality of parallel data from a host to a different memory storage chips (first / third memory block), and the data stored in the respective memory chips in parallel by copying ( second / fourth memory blocks), to avoid the situation in order to achieve data errors due to power storage unit when data is written to the flash memory block multilayered / to get lost. 籍由同时地存取多通道的数据储存装置中各存储器芯片中性质相同的存储器区块(SLC区块或MLC区块),以加快储存数据的储存速度。 Ji same data storage device is accessed by multiple channels simultaneously in each of the memory chips in memory bank properties (SLC or MLC block tile), to accelerate the speed of storing data is stored.

[0010]为使本发明的上述特征和优点能更明显易懂,下文特举实施例,并结合附图详细说明如下。 [0010] To make the above features and advantages of the invention more comprehensible, several exemplary embodiments, in conjunction with the accompanying drawings and described in detail below.

附图说明 BRIEF DESCRIPTION

[0011 ]图1〜图5示出了本发明实施例的数据储存装置的示意图。 [0011] FIG. 1 ~ FIG. 5 shows a diagram of a data storage device of the present invention according to the embodiment.

[0012]图6〜图9示出了本发明实施例的数据储存装置的数据写入方法的步骤示意图。 [0012] FIG. 6 ~ FIG. 9 shows a step of the present invention, the data storage device writing method according to a schematic embodiment.

[0013]附图符号说明 [0013] BRIEF DESCRIPTION OF REFERENCE NUMERALS

[0014] 100:数据储存装置 [0014] 100: data storage means

[0015] 102:非易失性存储器单元 [0015] 102: a non-volatile memory cell

[0016] 104:控制单元 [0016] 104: control unit

[0017] Dl〜Dn:存储器芯片 [0017] Dl~Dn: memory chip

[0018] BI〜B2n:存储器区块 [0018] BI~B2n: memory block

[0019] SLC:单层存储单元快闪存储器区块 [0019] SLC: single memory cell block of a flash memory

[0020] MLC:多层存储单元快闪存储器区块 [0020] MLC: multi-layered memory cell block of a flash memory

[0021] Al〜A4:地址区段 [0021] Al~A4: address segment

[0022] A〜H、A,〜D,:页数据 [0022] A~H, A, ~D ,: page data

[0023] S602 〜S604、S702 〜S706、S802 〜S810、S902 〜S910:数据写入 [0023] S602 ~S604, S702 ~S706, S802 ~S810, S902 ~S910: data write

具体实施方式 Detailed ways

[0024]〔第一实施例〕 [0024] [First Embodiment]

[0025]图1示出了本发明一实施例的数据储存装置的示意图。 [0025] FIG. 1 shows a diagram of a data storage device according to an embodiment of the present invention. 请参照图1,数据储存装置100包括非易失性存储器单元102与控制单元104,非易失性存储器单元102耦接控制单元104。 Referring to FIG. 1, the data storage device 100 includes a nonvolatile memory unit 102 and control unit 104, a nonvolatile memory cell 102 is coupled to the control unit 104. 如图1所示,非易失性存储器单元102可例如包括多个存储器芯片Dl〜Dn,其中η为正整数。 1, the nonvolatile memory unit 102 may include a plurality of memory chips, for example, Dl~Dn, wherein η is a positive integer. 控制单元104可以对存储器芯片Dl〜Dn进行多通道(mult1-channel)存取。 The control unit 104 may be a multi-channel (mult1-channel) access to the memory chips Dl~Dn. 各个存储器芯片Dl〜Dn中的第一存储器芯片Dl包括但不限于第一存储器区块BI与第二存储器区块B2,第二存储器芯片D2包括第三存储器区块B3与第四存储器区块B4……,第η存储器芯片Dn包括第(2η-1)存储器区块Β(2η-1)与第2η存储器区块Β2η。 The first memory chip Dl Dl~Dn respective memory chips include but are not limited to the first memory bank and a second memory block BI B2, D2 the second memory chip includes a third memory block B3 and the fourth memory bank B4 ......, Dn comprises a first memory chip of η (2η-1) memory block Β (2η-1) and the second memory block 2η Β2η. 以下以非易失性存储器单元102包括2个存储器芯片Dl和D2来说明,但本发明不限于此。 The following non-volatile memory cell comprises two memory chips 102 Dl and D2 will be described, but the present invention is not limited thereto. 控制单元104可先将来自该数据储存装置100外部的主机(未绘示)的第一储存数据和第二储存数据分别储存至第一存储器区块BI及第三存储器区块B3,然后再将第一储存数据和该第二储存数据分别复制至第二存储器区块B2及该第四存储器区块B4。 A first and a second data storage control unit 104 may store data of the data storage device 100 external to the host from the first (not shown) are stored to the first memory block BI and a third memory block B3, then a first data storage and the second storage data are copied to a second memory block of the fourth memory block B2, and B4. 第一和第二储存数据的存储和复制操作可并行地在第一和第二存储器芯片Dl和D2中进行,也可按照主机发送第一和第二储存数据的顺序依序地在第一和第二存储器芯片Dl和D2中进行。 Memory copy operation and the first and second data storage can be performed in parallel in the first and second memory chip Dl and D2, may be transmitted in accordance with the first and second data stored sequentially in the order of the host and the first the second memory chip Dl and D2 performed. 藉由重复写入储存数据至非易失性存储器单元102的各存储器芯片的不同性质的存储器区块,即可避免储存数据写入时发生断电而造成数据错误/佚失的情形。 By repeatedly written to the data storage nonvolatile memory cells in each memory block different nature of the memory chip 102, to prevent a power failure caused by a data error / get lost when storing the case data is written.

[0026]详细来说,在本实施例中,第一存储器区块B1、第三存储器区块B3…第(2n_l)存储器区块B(2n-1)均为单层存储单元(Single Level Cell,SLC)快闪存储器区块,第二存储器区块B2、第四存储器区块B4…第2n存储器区块B2n均为多层存储单元(Mult1-Level Cell,MLC)快闪存储器区块。 [0026] In detail, in the present embodiment, the first memory block B1, B3 ... of the third memory block (2n_l) memory block B (2n-1) are single storage unit (Single Level Cell , the SLC) flash memory bank, the second memory block B2, B4 ... fourth memory blocks of memory block B2n 2n memory cells are multi-layered (Mult1-Level cell, MLC) flash memory block. 控制单元104于接收到主机的多笔储存数据(例如前述的第一及第二储存数据)后,可先将多笔储存数据储存至各存储器芯片的单层存储单元快闪存储器区块中(亦即第一存储器区块B1、第三存储器区块B3…第(2n-l)存储器区块B(2n-1)),然后再将这些多笔储存数据复制至多层存储单元快闪存储器区块中(亦即第二存储器区块B2、第四存储器区块B4…第2n存储器区块B2n)。 After the control unit 104 to the received host data storing multiple pens (e.g. the first and second data storage), a first plurality of data storage to store the pen single flash memory cells of each memory bank in the memory chip ( i.e., the first memory block B1, B3 ... of the third memory block (2n-l) memory block B (2n-1)), and then copy the stored data to the multi-pen unit multilayer flash memory storage area block (i.e., a second memory block B2, B4 ... fourth memory blocks of memory block 2n B2n). 此多笔储存数据的存储和复制操作可并行地在各个存储器芯片中进行,也可按照主机发送这些储存数据的顺序依序地在各个存储器芯片中进行。 This multiple copy operations and storage to store pen data may be performed in parallel in each of the memory chips, these sequences may be transmitted sequentially storing data in the respective memory chip in accordance with the host. 在一实施例中,如图1所示,控制单元104可在将第一储存数据和该第二储存数据分别储存至第一存储器区块BI的第一地址区段Al及第三存储器区块B3的第二地址区段A2后,再将来自该主机的一第三储存数据和一第四储存数据分别储存至该第一存储器区块BI的第三地址区段A3及第三存储器区块B3的第四地址区段A4,之后控制单元104再将位于第一地址区段Al的第一储存数据与位于第三地址区段A3的第三储存数据复制至第二存储器区块B2中,同时控制单元104也将位于第二地址区段A2的第二储存数据与位于第四地址区段A4的第四储存数据复制至第四存储器区块B4中。 In one embodiment, shown in Figure 1, the control unit 104 may store the first data and the second data are stored to the first memory storing a first address segment block BI and a third memory bank Al a third storage storing data and a fourth data address segment A2 B3 of a second, then from the host are saved to the first memory block BI third address segment and a third memory block A3 a fourth address block B3, A4, and then after the control unit 104 stores data of the replication of the first Al a first address segment and a third segment of the third address A3 to the second data storage memory block B2, the At the same time the control unit 104 will be located in the second section A2 second storage address to copy data to the fourth memory block B4, and the fourth storage sections located at the fourth address A4 of the data. 在本实施例中,前述「复制」操作可于当前被存取的SLC存储器区块(亦即第一存储器区块B1、第三存储器区块B3…第(2n-l)存储器区块B(2n-l))被写入固定数据量(如述的2个地址区段的数据量)后进行,在其它实施例中,「复制」操作也可于当前被存取的SLC存储器区块写满或者一定数量的SLC存储器区块被写满后进行。 In the present embodiment, the "copy" operation may be accessed SLC to the current memory block (i.e., a first memory block B1, B3 ... of the third memory block (2n-l) memory block B ( after 2n-l)) is written in a fixed amount (the amount of data as described later two address segment of) the data, in other embodiments, "copy" operation may also be accessed in the memory bank write current SLC or a number of full blocks of SLC memory after being filled. 前述「复制」操作可以是数据的合并(merge)操作。 The aforementioned "Copy" operations can be consolidated data (merge) operation.

[0027]在本实施例中,多笔储存数据先写入各存储器芯片的单层存储单元快闪存储器区块(如第一存储器区块BI和第三存储器区块B3)中,由于单层存储单元快闪存储器区块的存取速度快于多层存储单元快闪存储器区块,因此数据的写入速度得以加快。 [0027] In the present embodiment, the multi-pen writing data stored in each memory chip to the memory cell monolayer flash memory block (e.g., a first memory block BI, and the third memory block B3), since the single the storage unit access speed is faster than the flash memory block storing unit multilayer flash memory block, thus data writing speed is accelerated. 同时,由于本发明籍由对多个存储器芯片Dl〜Dn进行多通道(mult1-channel)存取,进一步加快了写入速度。 Meanwhile, since the membership of the present invention is accessed by a plurality of memory chips Dl~Dn multichannel (mult1-channel), and further accelerate the write speed.

[0028]图2示出了本发明另一实施例的数据储存装置的示意图,请参照图2。 [0028] FIG. 2 shows a diagram of a data storage device according to another embodiment of the present invention, please refer to FIG. 2. 图2示出图1的数据储存装置100将储存在各存储器芯片Dl〜Dn的各单层存储单元快闪存储器区块中的储存数据复制至多层存储单元快闪存储器区块中的情形。 FIG. 2 shows a data storage device 100 stored copy of the data stored in each memory chip of each monolayer Dl~Dn memory cells in a flash memory block to the case of multi-layered memory cells in the flash memory block. 同样以非易失性存储器单元102包括2个存储器芯片Dl和D2为例来说明,控制单元104于进行「复制」操作时,将位于第一地址区段Al的第一储存数据与位于第三地址区段A3的该第三储存数据合并至第二存储器区块B2的第五地址区段A5中,同时控制单元104也将位于第二地址区段A2的第二储存数据与位于第四地址区段A4的第四储存数据合并至第四存储器区块B4的第六地址区段A6中。 Similarly to the first data storage nonvolatile memory cell comprises two memory chips 102 Dl and D2 will be described as an example, the control unit 104 to perform "Copy" operation, located at a first address and a third segment Al the third storage address segment A3 merged data to a second memory block B2 A5 fifth address segment, the control unit 104 while the second data stored in the second address segment is located at the fourth address A2 fourth storage section to merge the data A4 and B4 of the fourth memory block A6 of the sixth address segment. 由于多层存储单元快闪存储器区块(亦即第二存储器区块B2、第四存储器区块B4…第2η存储器区块Β2η)可储存的数据密度会比单层存储单元快闪存储器区块(亦即第一存储器区块B1、第三存储器区块Β3…第(2η-1)存储器区块Β(2η-1))多一倍,因此第二存储器区块Β2和第四存储器区块Β4复制储存数据所需使用到的页数仅需第一存储器区块BI和第三存储器区块Β3所使用的页数的一半。 Since the multi-layered memory cell block of the flash memory (i.e., a second memory block B2, B4 ... fourth memory blocks of memory block 2η Β2η) store data density than the single block of flash memory storage unit (i.e., the first memory block B1, ... beta] 3 of the third memory block (2η-1) memory block Β (2η-1)) twice, the second memory block, and fourth memory blocks Β2 Β4 required for replication of data pages stored using only half the number of pages of the memory block and the third block BI Β3 used in the first memory.

[0029]在位于第一地址区段Al与第三地址区段A3的储存数据复制至第二存储器区块Β2后,以及位于第二地址区段Α2与第四地址区段Α4的储存数据复制至第四存储器区块Β4后,位于第一地址区段Al与第三地址区段A3的储存数据以及位于第二地址区段Α2与第四地址区段Α4的储存数据成为无效(invalid)数据(如图2所示的斜线部份),控制单元104可擦除第一存储器区块BI中位于第一地址区段Al与第三地址区段A3的储存数据以及第三存储器区块B3中位于第二地址区段A2与第四地址区段A4的储存数据。 [0029] In the rear section Al and a first storage address data of the third address segment A3 is copied to the second memory block Β2, and in the second and the fourth address segment Α2 address segment data stored copy Α4 after the fourth memory block to Β4, located at a first address segment to store the data Al to A3, and the third address segment storing data for a second address segment positioned Α2 Α4 fourth address segment becomes invalid (invalid) data (hatched portion shown in FIG. 2), the control unit 104 can be erased at a first address segment to store the data Al to A3 of the third address segment in a first memory bank and the third memory block BI B3 located in the second and the fourth address segment address A2 stored in the data section A4. 在部分实施例中,亦可等到第一/三存储器区块B1/B3所储存的数据达到预设数据量时才擦除第一/三存储器区块BI/B3中已被复制的数据。 In some embodiments, it may wait until the first / three memory banks B1 / B3 stored data reaches a predetermined amount of data erase only data of the first / three memory banks BI / B3 has been copied.

[0030]值得注意的是,本实施例虽以多通道的方式同时对多个存储器芯片进行写入动作为例进行说明,然在部分实施例中,非易失性存储器单元102亦可仅包括一个存储器芯片,此外,各个存储器芯片亦不限于仅包括一个第一存储器区块BI与一个第二存储器区块B2。 [0030] It is noted that, while the present embodiment, although a plurality of memory chips by way of the write operation as an example of a multi-channel, then in some embodiments, the non-volatile memory cell 102 may include only a memory chip, in addition, each memory chip includes not only restricted to only a first memory bank and a second memory block BI B2. 此外,上述第一地址区段Al与第二地址区段A2所储存的数据量可依实际应用情形设定,在部分实施例中第一地址区段Al与第二地址区段A2所储存的数据量亦可对应到多个SLC存储器区块。 Further, the amount of data of the first address and the second address segment Al section A2 stored in accordance with practical application scenarios set, in some embodiments, a first address segment and a second address Al stored in the section A2 amount of data can correspond to a plurality of blocks of SLC memory.

[0031]由于单层存储单元快闪存储器的物理特性,对单层存储单元快闪存储器区块进行写入时并不会有因断电而产生数据错误/佚失的情形,因此藉由在存储器芯片中划分出少部分的存储器做为单层存储单元快闪存储器区块,并先将欲储存至多层存储单元快闪存储器区块的储存数据先储存至单层存储单元快闪存储器区块中,然后再储存至多层存储单元快闪存储器区块,如此即使在对多层存储单元快闪存储器区块进行写入时发生断电的情形,复电后仍可自单层存储单元快闪存储器区块中再取得未写入完成的储存数据,因此可避免储存数据因断电而发生数据错误/佚失的情形。 [0031] Since the physical characteristics of the memory cell monolayer flash memory, a flash memory cell when single memory block does not have to write data errors due to power case / get lost, and therefore by the a memory chip is divided into memory as a single small part of the memory cell blocks of the flash memory, and stores data to be stored in first storage unit multilayer flash memory block to a single memory cell to store a flash memory block , and then stored to the storage unit multilayer flash memory block, thus the case of power failure occurs even when a multilayer memory cell block write flash memory, still after power storage unit from the single flash storing the acquired memory block and then the data is not written to complete, thereby avoiding data storage data errors due to power / get lost situation occurs.

[0032]〔第二实施例〕 [0032] [Second Embodiment]

[0033]图3示出了本发明另一实施例的数据储存装置的示意图,请参照图3。 [0033] FIG. 3 shows a diagram of a data storage device according to another embodiment of the present invention, referring to FIG 3. 数据储存装置300与图1的数据储存装置100相同标号的元件的名称与功能均相同,在此不再赘述。 Data storage means data storage device 300 of FIG. 1 with the function name of the same reference numerals 100 are the same elements, which will not be repeated herein. 图3与图1实施例的不同之处在于,在本实施例中,假设第一存储器区块B1、第三存储器区块B3…第(2n-l)存储器区块B(2n-1)均为多层存储单元快闪存储器区块,第二存储器区块B2、第四存储器区块B4…第2n存储器区块B2n均为单层存储单元快闪存储器区块。 FIG 3 differs from the embodiment of FIG. 1 in that, in the present embodiment, it is assumed the first memory block B1, B3 ... of the third memory block (2n-l) memory block B (2n-1) are flash memory cells are single memory cell block is a multi-layered memory block of a flash memory, a second memory block B2, B4 ... fourth memory blocks of memory block 2n B2n. 如前所述,多层存储单元快闪存储器区块中的数据是以配对页(Paired Pages)的形式储存,即一最低有效位(Least Significant Bit,LSB)页数据会与一最高有效位(Most Significant Bit,MSB)页数据对应储存。 As described above, the multilayer data storage unit of a flash memory block is page pairing (Paired Pages) stored in the form, i.e., a least significant bit (Least Significant Bit, LSB) and the page data is a most significant bit ( Most Significant Bit, MSB) corresponding to the page data storage. 上述的多笔储存数据(以下以前述的第一及第二储存数据为例说明)可能是LSB页数据也可能是MSB页数据。 The above-described multi-pen storing data (hereinafter, in the stored first and second data as an example) may be the LSB MSB page data may be page data. 控制单元104接收到主机的第一及第二储存数据后将判断写入非易失性存储器单元102的第一及第二储存数据是否为LSB页数据,若第一及第二储存数据为LSB页数据,控制单元104并行地将各LSB页数据的储存数据分别写入不同的存储器芯片(如Dl和D2)的多层存储单元快闪存储器区块(亦即第一存储器区块BI和第三存储器区块B3)中,并且将各LSB页数据分别复制至存储器芯片Dl和D2的单层存储单元快闪存储器区块(亦即第二存储器区块B2和第四存储器区块B4)中。 After determining whether the first and second data storage control unit 104 receives a host write nonvolatile memory cell of the first and second data storage 102 for LSB page data, if the first and second data storage LSB page data, the control unit 104 stores data in parallel with the respective LSB page data are written into the memory cell of the flash memory block of the multilayer different memory chips (e.g., Dl and D2) (i.e. the first and the second memory block BI three memory block B3), and the respective LSB page data are copied to the memory chip Dl and D2 single block of memory cells of the flash memory (i.e., a second memory block B2 and the fourth memory block B4) in . 相反地,若第一及第二储存数据为MSB页数据,则控制单元104并行地将各MSB页数据的储存数据分别写入不同的存储器芯片(如Dl和D2)中而不进行复制的动作。 Conversely, if the first and second MSB page data to the stored data, the control unit 104 in parallel with the write operation different memory chip (such as Dl, D2) are stored without copying MSB data of each page data, respectively .

[0034]举例来说,图4示出了本发明另一实施例的数据储存装置的示意图。 [0034] For example, FIG. 4 shows a diagram of a data storage device of the present invention according to another embodiment. 假设在图3实施例中有4个存储器芯片(亦即n=4),主机先依序发送LSB页数据的储存数据,包括页数据A〜D,后来主机又依序发送与页数据A〜D配对的MSB页数据,包括页数据E〜H。 Suppose there are four memory chips (i.e., n = 4) in the embodiment of FIG. 3, the host sequentially transmits the stored data to the LSB page data, page data including A~D, and then the host sequentially transmits the page data A~ MSB page data D pairing, including page data E~H. 此外在本实施例中页数据A'、B'、C'、D'为页数据A、B、C、D的复制数据,控制单元104可先并行地将页数据A、B、C、D储存至各存储器芯片Dl〜D4的多层存储单元快闪存储器区块(亦即存储器区块B1、B3、B5和B7)中,当控制单元104判断出储存数据为LSB页数据(亦即页数据A〜D)时,随即还将页数据A'、B'、C'、D'复制至各存储器芯片Dl〜D4的单层存储单元快闪存储器区块(亦即存储器区块B2、B4、B6和B8)中,即是说,当判断到一储存数据为LSB页数据时,控制单元104会将该储存数据在MLC区域和SLC区域各写一次以做备份。 Further, in the present embodiment, page data A ', B', C ', D' of page data A, copy the data B, C, D, the control unit 104 may first parallel a page of data A, B, C, D storing each of the memory chips to the memory cell Dl~D4 multi block of the flash memory (i.e. memory block B1, B3, B5 and B7), when the control unit 104 determines that the stored data is LSB page data (i.e., page data A~D), then also the page data a ', B', C ', D' copy to each of the memory chips Dl~D4 single memory cell block of the flash memory (i.e. memory block B2, B4 , the B6 and B8), that is to say, when the stored data is determined to a LSB page data, the control unit 104 will write the data stored in each of SLC and MLC area region to make a backup. 随后当主机依序发送与页数据A〜D配对的MSB页数据E〜H时,控制单元104判断出储存数据为MSB页数据(亦即页数据E〜H),则控制单元104分别将MSB页数据的页数据E〜H分别储存至具有与页数据E〜H配对的页数据(亦即页数据A〜D)的各存储器芯片中,其中页数据E〜H为储存至多层存储单元快闪存储器区块(亦即存储器区块B1、B3、B5和B7)中。 When the host then sequentially transmits page data A~D paired MSB page data E~H, the control unit 104 determines that the stored data is the MSB page data (i.e., page data E~H), the control unit 104 are respectively the MSB E~H page data to the page data are stored in each memory chip having a page data (i.e., page data A~D) paired with E~H page data in which page data is saved to a multilayer E~H fast storage unit flash memory bank (i.e., memory blocks B1, B3, B5 and B7) in the. 此外,当与单层存储单元快闪存储器区块(亦即存储器区块B2、B4、B6和B8)中的LSB页数据配对的MSB页数据(页数据E〜H)都被储存至多层存储单元快闪存储器区块(亦即存储器区块B1、B3、B5和B7)中之后,单层存储单元快闪存储器区块中的数据(页数据A'〜D')即成为无效(invalid)数据而可以擦除。 Further, when the single block of memory cells of the flash memory (i.e. memory block B2, B4, B6 and B8) LSB page data paired MSB page data (page data E~H) are stored to the multi-layered memory after the block of the flash memory cells (i.e., memory blocks B1, B3, B5 and B7), the data (page data A'~D ') single memory cell in a flash memory block becomes invalid (invalid) data can be erased. 在某些实施例中,控制单元104还每隔一预设时间擦除各存储器芯片的单层存储单元快闪存储器区块(亦即存储器区块B2、B4、B6和B8)中的无效数据,或当存储器芯片的单层存储单元快闪存储器区块中的数据达到预设数据量时再擦除。 In certain embodiments, the control unit 104 also every predetermined time of each memory chip erase single block of memory cells of the flash memory (i.e. memory block B2, B4, B6 and B8) invalid data , or a single layer and then erasing the data storage unit when the flash memory block of the memory chip reaches a preset data amount.

[0035]如此藉由将LSB页数据的储存数据复制至单层存储单元快闪存储器区块中,利用单层存储单元快闪存储器区块的写入不受断电影响而产生写入数据错误/佚失的特性,即可避免储存数据因断电而发生数据错误/佚失的情形。 [0035] By thus storing the replicated data to a single LSB page data storage unit block flash memory, the flash memory using a single memory cell block write outages not generate an address data error / characteristics get lost, the data can be stored to avoid data errors due to power / get lost situation occurs. 且由于单层存储单元快闪存储器区块的写入速度较多层存储单元快闪存储器区块的写入速度快,本实施例藉由先同时写入LSB页数据的储存数据至多层存储单元快闪存储器区块,然后再同时备份LSB页数据的储存数据至单层存储单元快闪存储器区块。 Since the fast write speed and write speed single memory cell block in the flash memory layer of the memory cell large block flash memory, the present embodiment by first LSB page data is written while the data storage unit according to the multilayer storage a flash memory block, then back up stored data to a single block of flash memory storage unit LSB page data. 如此可避免同时对多层存储单元快闪存储器区块与单层存储单元快闪存储器区块进行写入,而使单层存储单元快闪存储器区块的存储器芯片须等待多层存储单元快闪存储器区块的存储器芯片完成写入后才能进行下一次的写入动作的情形发生,因而可提高储存数据的储存速度。 This avoids simultaneous multilayer flash memory block and the memory cell monolayer memory cell block write flash memory, the flash memory block of the memory cell monolayer memory chips have to wait for the flash memory cell multilayer the case of the memory chip to complete the memory block for the next write operation after write occurs, thus improving the speed of storing data is stored.

[0036]〔第三实施例〕 [0036] [Third Embodiment]

[0037]请参照图5,本实施例假设第一和第三存储器区块BI和B3为单层存储单元快闪存储器区块,第二和第四存储器区块B2和B4为多层存储单元快闪存储器区块,且储存数据亦包括LSB页数据与MSB页数据,LSB页数据与MSB页数据构成配对页储存于多层存储单元快闪存储器区块区域。 [0037] Referring to FIG. 5, for example, assumed that the first and third memory blocks BI and B3 is a single memory cell block of a flash memory according to the present embodiment, the second and fourth memory blocks B2 and B4 multilayer storage unit a flash memory block, and stored data also includes MSB LSB page data and page data, page data with the LSB MSB page stored in the page data constituting the multilayer paired memory cell block of the flash memory area. 控制单元104先将第一及第二储存数据并行地分别储存至各存储器芯片的单层存储单元快闪存储器区块(如第一及第三存储器区块B1、B3)中,本实施例与第二实施例的不同之处在于,在本实施例中,控制单元104在判断写入非易失性存储器单元102的第一及第二储存数据为LSB页数据,且控制单元104又判断出随后来自主机的第三及第四储存数据为与LSB页数据(第一及第二储存数据)配对的MSB页数据时,控制单元104首先将原先储存在各存储器芯片的单层存储单元快闪存储器区块(如第一及第三存储器区块B1、B3)中对应该MSB页数据的LSB页数据复制至多层存储单元快闪存储器区块(如第二及第四存储器区块B2、B4),再将MSB页数据(第三及第四储存数据)也储存至多层存储单元快闪存储器区块(如第二及第四存储器区块B2、B4)中。 The control unit 104 firstly first and second parallel data stored in each memory chip are stored to memory cells of a flash memory block monolayer (as in the first and third memory blocks B1, B3), the present embodiment is the second embodiment differs from the embodiment in that, in the present embodiment, the control unit 104 is written in the nonvolatile memory cells store data determining the first and second LSB page 102 for data, and the control unit 104 determines that the turn then the third and fourth storing data from the host when the LSB page data (first and second data storage) the MSB page data pair, the control unit 104 previously stored in the first memory chip is a flash memory cell monolayers memory block (e.g., the first and third memory blocks B1, B3) to be replicated in the MSB LSB page data to the page data storage unit multilayer flash memory block (e.g., the second and fourth memory block B2, B4 ), then the MSB page data (third and fourth storage data) is also stored to the storage unit multilayer flash memory block (e.g., the second and fourth memory block B2, B4) in the. 此外,当单层存储单元快闪存储器区块(如第一及第三存储器区块B1、B3)中的数据都被复制到多层存储单元快闪存储器区块(如第二及第四存储器区块B2、B4)中之后,单层存储单元快闪存储器区块中的数据即成为无效(invalid)数据而可以擦除。 Further, when the data blocks of single flash memory storage unit (e.g., first and third memory blocks B1, B3) in the multi-layered memory are copied to the flash memory cell blocks (e.g., the second and the fourth memory block B2, then B4), the single data storage unit of a flash memory block becomes invalid (invalid) data may be erased. 在某些实施例中,控制单元104还每隔一预设时间擦除各存储器芯片的单层存储单元快闪存储器区块(如第一及第三存储器区块B1、B3)中的无效数据,或当存储器芯片的单层存储单元快闪存储器区块中的数据达到预设数据量时再擦除,以确保单层存储单元快闪存储器区块有足够的空间进行储存数据的备份。 In certain embodiments, the control unit 104 also every predetermined time to erase each memory chip is a flash memory cell monolayer memory block (e.g., the first and third memory blocks B1, B3) invalid data , or a single layer and then erasing the data storage unit when the flash memory block of the memory chip reaches a preset amount of data to ensure that the single block of memory cells of the flash memory has enough space to store the backup data.

[0038]举例来说,图5示出了本发明另一实施例的数据储存装置的示意图。 [0038] For example, FIG. 5 shows a diagram of a data storage device of the present invention according to another embodiment. 假设在图5实施例中有4个存储器芯片(亦即n=4),主机先依序发送LSB页数据的储存数据,包括页数据A〜D,后来主机又依序发送与页数据A〜D配对的MSB页数据为页数据E〜H。 Example Suppose there are four memory chips (i.e., n = 4) in FIG. 5, the host sequentially transmits the stored data to the LSB page data, page data including A~D, and then the host sequentially transmits the page data A~ MSB page data to the page data D paired E~H. 在本实施例中页数据々'3'、(:'、0'为页数据4、8、(:、0的复制数据,控制单元104可先并行地将页数据4、8、(:、0储存至各存储器芯片Dl〜D4的单层存储单元快闪存储器区块(亦即存储器区块B1、B3、B5和B7)中。图5的实施例与图4的不同之处在于,控制单元104先将LSB页数据储存于单层而非多层存储单元快闪存储器区块,且并不会随即复制页数据A'、B'、C'、D',而是随后当主机依序发送与页数据A〜D配对的MSB页数据E〜H时才做复制,即当控制单元104判断出储存数据为与LSB页数据配对的MSB页数据后,控制单元104可先将LSB页数据A'、B'、C'、D'并行地分别写入存储器芯片Dl〜D4的多层存储单元快闪存储器区块(亦即存储器区块B2、B4、B6和B8)中,然后再将MSB页数据E、F、G、H也并行地分别存储至具有与页数据E〜H配对的页数据(亦即页数据A〜D)的存储器芯片中,即各存储器芯片D In the present embodiment, page data 々 '3', (: '0' is 4, 8 page data, (0 :, copy data, the control unit 104 may be parallel to the page data 4,8, (:, 0 is stored in each memory chip to the memory cell monolayer Dl~D4 block of the flash memory (i.e. memory block B1, B3, B5 and B7) in. FIG. 5 differs from the embodiment of Figure 4 is that the control unit 104 first LSB page data is stored in a single layer rather than multilayer flash memory storage unit block, and then not copied page data A ', B', C ', D', but when the host then sequentially MSB page data and page data transmitting A~D paired E~H only by copying, that is, when the control unit 104 determines that the stored data after MSB LSB page data and page data pair, the control unit 104 may first LSB page data a ', B', C ', D' are written into the memory chip in parallel Dl~D4 flash memory storage unit of the multilayer tile (i.e. memory block B2, B4, B6 and B8), the then memory chip MSB page data E, F, G, H are also stored in parallel with the page data (i.e., page data A~D) E~H paired with page data, i.e. each memory chip D l〜D4的多层存储单元快闪存储器区块(亦即存储器区块B2、B4、B6和B8)中。 l~D4 multilayer memory cell block of the flash memory (i.e. memory block B2, B4, B6 and B8) are.

[0039]如此藉由并行地将各LSB页数据的储存数据先储存至单层存储单元快闪存储器区块中,利用单层存储单元快闪存储器区块的写入不受断电影响而产生写入数据错误/佚失的特性,即可避免储存数据因断电而发生数据错误/佚失的情形。 [0039] By thus storing the data in parallel, each of the first LSB page data is saved to flash memory cell monolayer memory block by writing of the flash memory block of the memory cell monolayer is not generated outages error writing data / properties get lost, the data can be stored to avoid the case of data errors due to power / get lost occurs. 而只有在写入LSB页数据对应的MSB页数据时,才会将原本储存在单层存储单元快闪存储器区块中的LSB页数据复制到多层存储单元快闪存储器区块中,随后再储存对应的MSB页数据,由于LSB页数据因断电而发生数据错误/佚失的情形只会出现在写入与之配对的MSB页数据时,因此若不写入配对的MSB页数据,则无需将LSB页数据复制至多层存储单元快闪存储器区块,本实施例籍由将其保留在单层存储单元快闪存储器区块中,可进一步节省储存空间并减少存取次数。 LSB page copying of data only when writing the page data corresponding to the MSB LSB page data originally stored only in a single layer cell flash memory of the memory block to the multilayer storage unit block flash memory, and subsequently storing data corresponding to the MSB page, the page data of the LSB data error occurs due to power due to the / MSB page will get lost in the case of data when data is written to the MSB page paired, so if writing pairing occurs, LSB page no need to copy data to the flash memory block storing unit multilayer, the present embodiment retains its membership from the storage unit in a single layer in the flash memory block, it may further save storage space and to reduce access times.

[0040]〔第四实施例〕 [0040] [Fourth Embodiment]

[0041]图6示出了本发明一实施例的数据储存装置的数据写入方法的步骤示意图,请参照图6。 [0041] FIG. 6 shows a step of the present invention, the data storage device writing method according to a schematic embodiment, referring to FIG. 6. 归纳上述数据储存装置的数据写入方法可包括下列步骤。 It said data writing method summarized data storage means may comprise the following steps. 首先,将来自数据储存装置外部的主机的第一储存数据和第二储存数据并行地分别储存至非易失性存储器单元中的第一存储器区块及第三存储器区块(步骤S602)。 A first and a second data storage storing first data, the data from the external host storage device are stored in parallel to the first memory bank and the third memory bank (step S602) in nonvolatile memory cells. 接着,将第一储存数据和该第二储存数据分别复制至非易失性存储器单元中的第二存储器区块及该第四存储器区块(步骤S604)。 Next, the first data storage and the second storage data are copied to a second memory block in the nonvolatile memory cell and the fourth memory block (step S604). 其中第一存储器区块与第二存储器区块同属于第一存储器芯片,第三存储器区块与第四存储器区块同属于第二存储器芯片。 Wherein the first memory bank and the second memory blocks belong to the first memory chip, the third and the fourth memory bank belonging to the same memory bank of the second memory chip. 如此藉由重复写入储存数据至非易失性存储器单元的各存储器芯片的不同性质的存储器区块,即可避免储存数据写入时发生断电而造成数据错误/佚失的情形。 By thus repeatedly written in each memory block different nature memory chip to store data in non-volatile memory cells, to prevent a power failure caused by a data error / get lost when storing the case data is written.

[0042]〔第五实施例〕 [0042] [Fifth Embodiment]

[0043]图7示出了本发明另一实施例的数据储存装置的数据写入方法的步骤示意图,请参照图7。 [0043] FIG. 7 shows the steps of the present invention, the data storage apparatus of the embodiment schematic view of another embodiment of the writing method, please refer to FIG. 7. 在本实施例中,上述的第一存储器区块及第三存储器区块可例如为单层存储单元快闪存储器区块,而第二存储器区块及第四存储器区块可例如为多层存储单元快闪存储器区块。 In the present embodiment, the above-described first memory bank and the third memory bank, for example, a single layer may be a flash memory block storage unit, and the fourth memory bank and the second memory bank, for example, may be stored in a multilayer flash memory cell blocks. 详细来说,上述第一及第二储存数据分别复制至非易失性存储器单元中的第二及第四存储器区块的步骤可如图7所示,将来自主机的第三储存数据和第四储存数据并行地分别储存至非易失性存储器单元中的第一存储器区块及第三存储器区块(步骤S701)。 In detail, the first and second data storage are copied to the second and fourth memory cell blocks in the nonvolatile memory may be a step 7, and the third storage data from the host storing four parallel data are stored to the first memory block in the nonvolatile memory cells and a third memory block (step S701). 判断第一存储器区块中的第一地址区段与第三地址区段,以及第三存储器区块中的第二地址区段与第四地址区段是否被写入数据(步骤S702)。 Determining a first address of a first memory block address segment and the third segment, and a third memory block if the second address segment is an address segment and the fourth write data (step S702). 若第一存储器区块中的第一地址区段与第二地址区段以及第三存储器区块中的第二地址区段与第四地址区段未皆被写入数据,则回到步骤S701,继续将储存数据储存至非易失性存储器单元中的第一及第三存储器区块。 If the first memory block in the first section and the second address and the third address segment of the second memory block address segment are not data to be written and the fourth address segment, the process returns to step S701 continue to store data stored to a first memory bank and the third non-volatile memory cells. 而若第一存储器区块中的第一地址区段与第二地址区段及第三存储器区块中的第二地址区段与第四地址区段皆被写入数据,将位于第一地址区段与第三地址区段的储存数据复制至第二存储器区块,并将位于第二地址区段与第四地址区段的储存数据复制至第四存储器区块(步骤S704)。 And if the first memory block of the first address section and a second section of the second address and the third address segment of the memory block are data to be written and the fourth address segment, located at a first address storing the data section and the third address segment copied to the second memory block, and in the second address segment data replication and the fourth address segment is stored to the fourth memory block (step S704). 然后,擦除第一存储器区块的第一地址区段与第二地址区段,并擦除第三存储器区块的第二地址区段与第四地址区段(步骤S706),以确保非易失性存储器单元中的第一及第三存储器区块有足够的空间继续写入储存数据。 Then, erasure of the first block of the first address memory section and a second address segment, the third memory block and a second erase address segment and the fourth address segment (step S706), in order to ensure that non- volatile memory cells of the first and third memory banks continue to have enough space to store the write data.

[0044]〔第六实施例〕 [0044] [Sixth Embodiment]

[0045]图8示出了本发明另一实施例的数据储存装置的数据写入方法的步骤示意图,请参照图8。 [0045] FIG. 8 shows a step of the present invention, the data storage apparatus of the embodiment schematic view of another embodiment of the writing method, please refer to FIG. 8. 在本实施例中上述的第一存储器区块及第三存储器区块可例如为多层存储单元快闪存储器区块,而第二存储器区块及第四存储器区块可例如为单层存储单元快闪存储器区块,且储存数据包括LSB页数据与MSB页数据,其中LSB页数据与MSB页数据为配对页。 In the above-described first embodiment of the memory bank and the third memory bank, for example, may be a multilayer block flash memory storage unit, and the fourth memory bank and the second memory bank, for example, may be a single layer in the present embodiment the storage unit a flash memory block, and storing data including data MSB LSB page page data, wherein the page data with the MSB LSB page data page pairing. 在本实施例中,上述将第一及第二储存数据并行地分别复制至非易失性存储器单元中的第二及第四存储器区块的步骤可如图8所示,其包括,判断储存至第一及第三存储器区块的第一及第二储存数据是否为LSB页数据(步骤S802)。 In the present embodiment, the above-described parallel first and second, respectively, store data copied to the second and the fourth memory bank of nonvolatile memory cells may be a step 8, which comprises determining storage to the first data storage and first and second memory block whether the third LSB page data (step S802). 若储存数据为LSB页数据,将LSB页数据(即第一及第二储存数据)分别复制至第二及第四存储器区块(步骤S804)。 If the stored data is LSB page data, respectively LSB page copying data (i.e., the first and second data storage) to the second and the fourth memory block (step S804). 相反地,若储存数据为MSB页数据,则结束(步骤S806)。 Conversely, if the stored data is the MSB page data is ended (step S806).

[0046]在执行步骤S804后,可继续判断与第一及第二储存数据配对的MSB页数据是否已经分别储存至第一及第三存储器区块(步骤S808)。 [0046] After the execution of step S804, the MSB determines whether the page may continue to be paired with the first and second data storage data are stored to have a first and a third memory block (step S808). 若否则回到步骤S402。 If otherwise returns to step S402. 若是,将第二及第四存储器区块中的第一及第二储存数据的复制数据(如图4的复制数据A'、B'、C'、D')标识为无效(invalid)(步骤S810)。 If yes, copy the data of the second and the fourth memory block in the first and second data storage (FIG. 4 of copy data A ', B', C ', D') marked as invalid (invalid) (step S810). 在某些实施例中,当第二或第四存储器区块中的数据已经过一段预设时间未被擦除,或第二或第四存储器区块中的数据已达到预设数据量,则将第二或第四存储器区块擦除。 In certain embodiments, the second or fourth memory when the data block has not been erased over a preset period of time, or the second or the fourth data memory block has reached a predetermined amount of data, the second or fourth memory block erasing.

[0047]〔第七实施例〕 [0047] [Seventh Embodiment]

[0048]图9示出了本发明另一实施例的数据储存装置的数据写入方法的步骤示意图,请参照图9。 [0048] FIG 9 shows a step of the present invention, the data storage apparatus of the embodiment schematic view of another embodiment of the writing method, please refer to FIG. 9. 在本实施例中上述的第一存储器区块及第三存储器区块可例如为单层存储单元快闪存储器区块,而第二存储器区块及第四存储器区块可例如为多层存储单元快闪存储器区块,且储存数据包括LSB页数据与MSB页数据,其中LSB页数据与MSB页数据为配对页。 In the above-described first embodiment of the memory bank and the third memory bank, for example, a single layer may be a flash memory block storage unit, and the fourth memory bank and the second memory bank may be stored, for example, a multilayer unit of the present embodiment a flash memory block, and storing data including data MSB LSB page page data, wherein the page data with the MSB LSB page data page pairing. 在本实施例中,上述将第一及第二储存数据并行地分别复制至非易失性存储器单元中的第二及第四存储器区块的步骤可如图9所示,其包括,判断储存至第一及第三存储器区块的第一及第二储存数据是否为LSB页数据,且判断随后来自主机的第三及第四储存数据是否是与第一及第二储存数据配对的MSB页数据(步骤S902)。 In the present embodiment, the above-described parallel first and second, respectively, store data copied to the second and the fourth memory bank of nonvolatile memory cells may be a step 9, comprising, determining storage to the first data storage and first and second memory block whether the third LSB page data, and then determines whether the third and fourth storage data from the host is paired with the first and second MSB page data storage data (step S902). 若是,则首先将原先储存在第一及第三存储器区块中的第一及第二储存数据(LSB页数据)分别并行地复制至第二及第四存储器区块(步骤S904)。 If yes, the first of the previously stored first and second data storage (LSB page data) in the first and third memory banks, respectively, in parallel to the second and the fourth copy memory block (step S904). 再将第三及第四储存数据(MSB页数据)分别并行地储存至第二及第四存储器区块(步骤S908)。 Then the third and fourth storing data (MSB page data) are stored in parallel to the second and the fourth memory block (step S908). 当将第一及第二储存数据(LSB页数据)分别并行地复制至该第二及该第四存储器区块之后,可将原先储存在第一及第三存储器区块中的第一及第二储存数据(LSB页数据)标识为无效(invalid)数据而可以擦除(步骤S910)。 When the first and second data storage (LSB page data) are copied in parallel to the second and the fourth memory block after, may be previously stored in the first and third memory banks in the first and second two data storage (LSB page data) marked as invalid (invalid) data may be erased (step S910). 在某些实施例中,每隔一预设时间擦除第一及第三存储器区块中的无效数据,或当第一及第三存储器区块中的数据达到预设数据量时再擦除。 In certain embodiments, every first and third predetermined time to erase the memory block is invalid data, or when the data in the first and third memory banks reaches a predetermined amount of data and then erased .

[0049]综上所述,本发明藉由将来自主机的多笔储存数据储存至各存储器芯片的MLC或SLC区块中,并将储存数据复制至各存储器芯片的SLC或MLC区块中,以达到避免数据写入时因断电造成数据错误/佚失的情形。 [0049] In summary, the present invention is by the pen storing a plurality of data storage from the host to each of SLC or MLC memory chip block, and copy the data stored in each memory chip to SLC or MLC blocks, when data is written to achieve avoid errors due to power outages caused by data / scenarios get lost in. 籍由同时地存取多通道的数据储存装置中各存储器芯片性质相同的存储器区块(SLC区块或MLC区块),以加快储存数据的储存速度。 The data storage device accessed by a simultaneous membership in each of the multi-channel memory chips of the same nature memory block (SLC or MLC block tile), to accelerate the speed of storing data is stored.

Claims (6)

1.一种数据储存装置,包括: 一非易失性存储器单元,包括至少一第一存储器芯片及一第二存储器芯片,该第一存储器芯片包括至少一第一存储器区块以及一第二存储器区块,该第二存储器芯片包括至少一第三存储器区块以及一第四存储器区块;以及一控制单元,耦接该非易失性存储器单元,其中该控制单元将来自该数据储存装置外部的一主机的一第一储存数据和一第二储存数据并行地分别储存至该第一存储器区块及该第三存储器区块,以及将该第一储存数据和该第二储存数据并行地分别复制至该第二存储器区块及该第四存储器区块, 其中该控制单元还于将该第一储存数据和该第二储存数据并行地分别储存至该第一存储器区块的一第一地址区段及该第三存储器区块的一第二地址区段后,再将来自该主机的一第三储存数据和一第四储存数据并行地分 A data storage apparatus, comprising: a nonvolatile memory cell, comprising at least a first memory chip and a second memory chip, the first memory chip comprises at least a first memory and a second memory block block, the second memory chip memory block comprises at least a third and a fourth memory block; and a control unit, coupled to the nonvolatile memory cell, wherein the control unit from the external data storage device a first data store and a host of a second store data are stored in parallel to the first memory block and the third memory block, and storing the first data and the second data storage in parallel, respectively copied to the second memory block and the fourth memory block, wherein the control unit is also a first address in the first data store and the second store data are stored in parallel to the first memory block a third storage storing data and a fourth data segment as a second address and the third memory block, and then from the host parallel sub 储存至该第一存储器区块的一第三地址区段及该第三存储器区块的一第四地址区段,之后该控制单元再将位于该第一地址区段的该第一储存数据与位于该第三地址区段该第三储存数据复制至该第二存储器区块,同时将位于该第二地址区段的该第二储存数据与位于该第四地址区段的该第四储存数据复制至该第四存储器区块。 A fourth address storage section to a third section of the first address of the memory block and the third memory block, then the control unit after the data stored at the first address of the first segment and the third section is located in address storing data of the third copy to the second memory block, while the data stored at the second address of the second and the fourth segment of the stored data is located at the fourth address segment copy to the fourth memory block.
2.如权利要求1所述的数据储存装置,其中该第一存储器区块及该第三存储器区块为单层存储单元快闪存储器区块,该第二存储器区块及该第四存储器区块为多层存储单元快闪存储器区块。 2. The data storage device as claimed in claim 1, the second memory block and the fourth memory region, wherein the first memory block and the third memory block flash memory as a single block of memory cells, a flash memory cell block is a multi-layered memory block.
3.如权利要求2所述的数据储存装置,其中该控制单元还于将该第一与该第三储存数据复制至该第二存储器区块,同时将该第二与该第四储存数据复制至该第四存储器区块后,擦除该第一存储器区块的该第一地址区段与该第三地址区段,并擦除该第三存储器区块的该第二地址区段与该第四地址区段。 3. The data storage device according to claim 2, wherein the control unit is further copied to the first and the third data storage to the second memory block, while the second and the fourth storage data replication after the fourth memory block to erase the first memory block of the first address segment and the third address segment, and the third memory block to erase the second address segment with the The fourth section addresses.
4.一种数据储存装置的数据写入方法,其中该数据储存装置包括一非易失性存储器单元,该非易失性存储器单元包括至少一第一存储器芯片及一第二存储器芯片,该第一存储器芯片包括至少一第一存储器区块以及一第二存储器区块,该第二存储器芯片包括至少一第三存储器区块以及一第四存储器区块,该数据写入方法包括: 由一控制单元将来自该数据储存装置外部的一主机的一第一储存数据和一第二储存数据并行地分别储存至该第一存储器区块及该第三存储器区块;以及由控制单元将该第一储存数据和该第二储存数据并行地分别复制至该第二存储器区块及该第四存储器区块, 其中将该第一储存数据和该第二储存数据并行地分别复制至该第二存储器区块及该第四存储器区块的步骤包括: 于将该第一储存数据和该第二储存数据并行地分别储存至该第一存 A data writing method for a data storage apparatus, wherein the data storage means comprises a nonvolatile memory cell, the nonvolatile memory cell includes at least a first memory chip and a second memory chip, the second a memory chip comprising at least a first memory block and a second memory block, the second memory chip memory block comprises at least a third and a fourth memory block, the data writing method comprising: by a control a host cell from the external data storage device storing a first data and a second store data are stored in parallel to the first memory block and the third block of memory; and the control means by the first store data and storing the second data in parallel are copied to the second memory block and the fourth memory block, wherein the parallel, respectively, a first copy and the second data storage storing data to the second memory region and the fourth step of block memory block comprising: a parallel to the first storage data are stored and the stored second data to the first memory 储器区块的一第一地址区段及该第三存储器区块的一第二地址区段后,再将来自该主机的一第三储存数据和一第四储存数据并行地分别储存至该第一存储器区块的一第三地址区段及该第三存储器区块的一第四地址区段;以及将位于该第一地址区段的该第一储存数据与位于该第三地址区段该第三储存数据复制至该第二存储器区块,同时将位于该第二地址区段的该第二储存数据与位于该第四地址区段的该第四储存数据复制至该第四存储器区块。 After a second section of a first address segment address reservoir block and the third memory block, then a third data storage from the host and a fourth storage data are stored in parallel to the a third section of the first address of the memory block and the third block a fourth memory address segment; and storing the first data at the first address segment and the third address segment located the third store data copied to the second memory block, while the data stored at the second address of the second section and the fourth copy of the stored data is in the fourth address segment to a fourth memory region Piece.
5.如权利要求4所述的数据写入方法,其中该第一存储器区块及该第三存储器区块为单层存储单元快闪存储器区块,该第二存储器区块及该第四存储器区块为多层存储单元快闪存储器区块。 5. The data writing according to claim 4, wherein the first memory block and the third memory cell block flash memory as a single block of memory, the second memory block and the fourth memory a flash memory cell block is a multi-layered memory block.
6.如权利要求5所述的数据写入方法,还包括: 将该第一与该第三储存数据复制至该第二存储器区块,同时将该第二与该第四储存数据复制至该第四存储器区块后,擦除该第一存储器区块的该第一地址区段与该第三地址区段,并擦除该第三存储器区块的该第二地址区段与该第四地址区段。 5 6. The data writing method according to claim, further comprising: copying the first and the third data storage to the second memory block, while the second copy of the data to the fourth storage after the fourth memory block, erasing the first memory block of the first address segment and the third address segment, and the third memory block to erase the second and the fourth address segment address section.
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