1352441 九、發明說明： 【發明所屬之技術領域】1352441 IX. Description of the invention: [Technical field to which the invention belongs]
本發明係關於一種發光元件，尤其是關於一種水平式發 光二極體元件結構。 X 【先前技術】 發光二極體（Light-emitting Diode)在具有光電轉換特 性的固態元件裡十分重要。一般而言，它具有一發光層(AcUve Layer)，被兩種不同電性的半導體層& η#% semiconductor layers)所包夾而成。當於兩半導體層上之接觸 電極施加一驅動電流時，兩半導體層之電子與電洞會注入發 光層，於發光層中結合而放出光線，其光線具全向性，會通 過此發光一極體元件的各個表面而射出。 發光二極體元件是一種被廣泛使用的光源。相較於傳統 的白熾燈泡或螢光燈管，發光二極體除了具有省電盥使用壽 命較長的優異雜外，更具有整舰的成本優勢，因此逐漸 ^代傳統光源，而制於各鮮騎域，如交通麟、背光 模組、路燈照明、醫療設備等產業。 ，者發光二極體光源的應用與發展，對於亮度的要求越 二增加其發光效率而提高其亮度，成為產業 '"' ° 、重要方向。目前習知方法之一，係利用基板 性:ΐ長基板移除，轉換成另- 高亮度。”、、，如峨罐嫩率而提 5 1352441 第9圖為利用基板轉移技術所得之一般InGaN (Flip-Chip)的發光二極體元件結構圖。其製程步驟係 Sapphire基板(圖未示)上，形成一 ρ電極與η電極同側之平 式結構設計的發光疊層902 ;再將此發光疊層9〇2，連处於 面具有Ρ電路圖案903與η電路圖案9〇6設計之 (SUbm〇Unt)901 ;最後，於封裝基板901上之ρ電路圖ϋ〇3 906中所預留的打線電極，進行打線卫程、，電 ΐ連接Ϊ線904與9〇5 ’如此可獲得如圖9所示之覆晶式發 ^極體猶_ ^由於此製程步驟，係將晶片（即^ 基板上形成之發光#層9〇2)先進行切割成—顆顆 後，再分別連結於封裝基板9〇1之上，並製造 使得生產效率難以有效提I -沾序過於複雜， 【發明内容】 具有η電關_ ρ電路_設計；—發^，水久基板 極與- ρ電極’並與永久基板對連 f s =^^，電路圖案==疊 本發明之一目的在於提供一發光元件包含·· 具有一 η電 層打線開口，分別露出“路圖案 打線區域’以作為後續打線製程之導線連接位置。電案之 含：=造方法包 Z層十-上 後將成長基板盥永久案與一 p電路圖案；然 連接電路m，P電極電性連接ρ電路圖案；再將 6 5Ξ光”蝕,兩個打線開口，而露出n電 切割^ 減輯；最類财久基板進行 結構本基板轉肋卿奴發光元件 二電路醜.’八―表關時具有—第—電路圖案與一第 第二電二案二發光疊層’其一表面同時具有-第-電極與- 接ΐΐ路㈣位連結，使得第—電極電性連 電’分職出該第—電關案與該第二 片、^ί兩個打線區域。上述之發光元件結構，係先進行晶 後’再利用活性離子束钱刻技術，餘刻出打線開口；最 ii订切縣片製程，將⑼切割成晶粒後，再進行後段封ί 制相較於傳統之覆晶式發光二極體元件，此結構可以簡。 日日粒製程，並大幅提升生產效率。 【實施方式】 第6圖係本發明之一實施例的發光二極體元件6〇〇結 圖。本實施例係利用一基板轉移技術，所製作而成之一水平 發光二極體結構’其製程步驟主要包含晶片黏結製程、基板^多 除(substrate lift-off)製程、及活性離子束蝕刻讲咖加i〇n b_ etching)製程。詳細步驟如第！圖〜第5圖所示，說明如下。 第1A-1B圖為本實施例之第一製程步驟。如第1A圖所 示，係首先於一成長基板101上，形成一緩衝層（圖未示)以及 一半導體發光疊層，係包含一 n型半導體層1〇2與一 p型半 體層103 ’然後分別於η型半導體層1〇2與p型半導體層1〇3 之上方’分別形成一 η電極104與一 ρ電極105。並請參0照第 係第1A圖之上方俯視圖，其俯視平面是倾數個n電極 & 電極105以直條狀間隔排列而成之圖案。如上所述之 土板101 ’例如為藍寶石基板(Sapphire substrate),可以使 於ΐ上之InGaN半導體發光疊層於長晶過程中，不至於 生大量的晶格錯位(dislocation)或晶格缺陷(defects)。n電極 1與ρ電極1〇5 ’例如是銀(Ag)或链(Α1)或金(Au)或其合金所 才最成。 第2A-2B圖為本實施例之第二製程步驟。如第2A圖所示 係於一永久基板201上，形成一 n電路層2〇4與p電路層2〇5。 ^請參照第2B圖係第2A圖之上方俯視圖，其俯視平面是由 複數個η電路層204與p電路層205，以直條狀間隔排列而成 之圖案。複數個η電路層204並透過另一垂直於每一個η電路 層204之線條圖案，相互連結而導通，形成一電性相連之11電 路圖案；同時複數個ρ電路層2〇5也透過另一垂直於每一個ρ 電路層205之線條圖案，相互連結而導通，形成一電性相連之 Ρ電路圖案。其中，上述之η電路層2〇4與ρ電路層2〇5，例 如是銀(Ag)、鋁(Α1)或金(Au)或其合金所構成。永久基板2〇1 係散熱性良好之基板，例如金屬基板、矽基板或高導熱陶瓷基 板。 第3A-3B圖為本實施例之第三製程步驟。如第3A圖所示 係利用一連結製程’先將成長基板1〇1之η電極與ρ電極 105以及永久基板201之η電路層204與ρ電路層205進行對 位後(如第3Β圖所示），將兩基板進行連結製程。其中連結製 程可以是直接連結或金屬連結;直接連結一般係在高溫條^ (>400°C)，施加一固定的輔助壓力，使連結界面兩邊的材料熔 融在一起而產生黏結。金屬連結係於兩連結界面上，先各自形 成一金屬層，然後再施以一較低溫度(2〇〇°C〜300°〇及一固定 1352441 辅助壓力，將兩金屬層連結起來。 第4圖為本實施例之第四製程步驟。如圖所示係利用基板 移除技術將成長基板101移除。其中基板移除技術為雷射剝離 技術:係利用準分子雷射(Excimer laser)由成長基板ιοί遠離 發光疊層的表面入射。此時，大部分的雷射能量被成長基板 101上之緩衝層與成長基板101之界面所吸收，進而分解緩衝 層’達到的移除成長基板101之目的。 第5A-5B圖為本實施例之第五製程步驟，其包含兩個步 驟。首先，如第5A圖所示，利用活性離子束蝕刻(Reactive ioi>beam etching)技術對發光層進行餘刻，分別電極1〇4 與ρ電極105之上方’敍刻形成打線開口 304與3〇5，而直接 露出η電極104與ρ電極1〇5。其中活性離子束蝕刻(Reactive ion-beam etching)具備多項優點’如選擇性良好、蝕刻速率快、 反應參數可獨立控制及無殘渣問題等，因此在半導體製造過、程 中有逐漸以活性離子束蝕刻取代濕式蝕刻之趨勢。本實施例以 感應搞合電聚活性離子飯刻系統(ICP-Rie)進行乾式钱刻，並 以蝕刻參數分析的方法，藉由改變反應氣體(BC13/Ar)流量、壓 力、感應耦合電漿功率ICP(IndUCtivdy coupled Plasma)及奸 功率（即DC-bias偏壓），找出它們和蝕刻速率、蝕刻選擇性、 蝕刻方向性、蝕刻表面平整度以及參數’蝕刻出開口 3〇4與 305。再者，如第5B圖所示，對晶片501 (包含永久基板2〇1 與發光疊層102)進行切割，形成複數個分離的晶粒5〇2。 第6圖為本實施例之第六製程步驟。本步驟是利用開口 304與305，進行打線接合工程，其中n導線4〇4連接n電極 104且ρ導線405連接ρ電極1〇5。然後，對ρ型半導體層 之表面進行粗縫化工程，例如以姓刻或奈米壓印等方法，使得 9 P型半導體層102之表面，產生規則或不規則之凹凸表面。如 此一來，當電流由導線，傳導至半導體發光疊層所產生的光， 會因為此出光面之粗糙化設計，使光之摘出效率提高，同時也 使得發光二極體元件600的發光效率，獲得整體提昇。 由於本貫》c*例係先將晶片與永久基板連結後，再利用活性 離子束蝕刻技術，蝕刻出打線開口，最後進行切割，將晶片切 割成晶粒，即獲得發光二極體元件600之結構。而一般覆晶式 發光一極體元件，係先對晶片進行第一次切割成複數個晶粒 後’再將各晶粒與承載基板(sub-mount) --進行對位連结， 最後再對承載基板(sub-mount)作第二次切割裂片，而獲得發光 二極體元件900。相較之下，本實施例只要進行一次晶片對位 連結與一次切割製程步驟便可完成，但一般覆晶式發光二極體 元件’不僅需要將各晶粒與承載基板(sub_m〇unt)--進行對位 連，，還要進行兩次的切割裂片製成，才能完成。由此可知， 本實施例可以大幅簡化製程步驟，因而能夠提升生產效率與降 低生產成本。 第7圖係本發明之背光模組結構圖，其中背光模組裝置 700包含.由依本發明上述任一實施例之發光二極體元件 所構成的一光源裝置710 ; 一光學裝置72〇置於光源裝置71〇 3 光做適#處理後出光；以及—電源供應系統 730，棱供上述光源裝置71〇所需之電源。 第8圖係本發明之照明裝置結構圖。上 街?浐電筒、路燈、或指示燈等等。其中照‘ 置 匕3 .光源裝置810，係由依本發明上述之任一實施 光二極體元件811所構成；一電源供應系统82〇，^供 先源裝置810所需之電源；以及一控制元件83〇控制電流& 1352441 光源裝置810。 係，發明第-製程步驟之元件結構圖£ 係第1A圖之上方俯視圖。 係本發明第二製程步驟之元件結構圖。 係第2A圖之上方俯視圖。 係本發明第三製程步狀元件結構圖。 係本發明第三_步驟之·示意圖。 係本發明第四製程步驟示意圖。 係本發明第五餘步驟之第-示意圖。 係本發明第五製程步驟之第二示意圖。 係本發明之發光二極體結構圖。 係本發明之背光模組結構圖。The present invention relates to a light-emitting element, and more particularly to a horizontal light-emitting diode element structure. X [Prior Art] A light-emitting diode is important in solid-state components with photoelectric conversion characteristics. In general, it has an illuminating layer (AcUve Layer) sandwiched between two different electrical semiconductor layers &η#% semiconductor layers. When a driving current is applied to the contact electrodes on the two semiconductor layers, the electrons and holes of the two semiconductor layers are injected into the light-emitting layer, and the light is combined to emit light, and the light is omnidirectional, and the light is passed through the pole. Each surface of the body element is ejected. A light-emitting diode element is a widely used light source. Compared with the traditional incandescent bulbs or fluorescent tubes, the LEDs have the advantages of long life and long life, and have the cost advantage of the entire ship. Therefore, they gradually replace the traditional light source. Fresh riding areas, such as transportation Lin, backlight modules, street lighting, medical equipment and other industries. The application and development of the light-emitting diode light source, the second requirement for brightness increases its luminous efficiency and increases its brightness, becoming an industry '"' °, an important direction. One of the conventional methods is to use substrate properties: the substrate is removed and converted to another high brightness. ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, A light-emitting layer 902 having a flat structure design on the same side of the ρ electrode and the η electrode is formed; and the light-emitting layer 9 〇 2 is connected to the surface with a Ρ circuit pattern 903 and an η circuit pattern 9 〇 6 design. (SUbm〇Unt) 901; Finally, the wire-bonding electrode reserved in the circuit diagram ϋ〇3 906 on the package substrate 901 is subjected to a wire-wiring process, and the electric connection wires 904 and 9〇5' are thus obtained. The flip-chip type body shown in FIG. 9 is a process in which the wafer (ie, the light-emitting layer 9 formed on the substrate) is first cut into pieces, and then respectively connected to On the package substrate 〇1, and manufacturing makes it difficult to effectively improve the production efficiency, and the smear is too complicated. [Invention] η _ _ _ circuit _ design; - hair ^, water long substrate pole and - ρ electrode ' And connected to the permanent substrate fs = ^ ^, circuit pattern = = stacked one of the purposes of the present invention is to provide a light Η member comprises a dielectric layer having ·· wire openings are exposed "path pattern bonding area 'as a wire connection position subsequent routing of the wires. The inclusion of the electric circuit: = manufacturing method package Z layer ten - after the growth of the substrate 盥 permanent case and a p circuit pattern; then the connection circuit m, P electrode is electrically connected to the ρ circuit pattern; then 6 5 ” light eclipse, two A wire opening, and exposed n electric cutting ^ reduction; the most class of financial long-term substrate to carry out the structure of the substrate ribbed nucleus light-emitting components two circuit ugly. 'eight-time off when there is - the first circuit pattern and a second electricity The second case of the two-layer light-emitting stack has a surface--electrode and --connected (four)-bit connection, so that the first-electrode is electrically connected to the first-electrode and the second piece, ^ ίTwo wire-bonding areas. The above-mentioned light-emitting element structure is firstly post-crystallized' re-use of active ion beam engraving technology, and the remaining wire opening is made; the most ii-cut county process, after cutting (9) into crystal grains, Compared with the conventional flip-chip light-emitting diode element, the structure can be simplified, and the production process can be greatly improved. [Embodiment] FIG. 6 is an embodiment of the present invention. Light-emitting diode element 6〇〇 junction diagram. This embodiment utilizes a substrate The shifting technique, which is a horizontal light-emitting diode structure, is mainly composed of a wafer bonding process, a substrate lift-off process, and a reactive ion beam etching process. The detailed steps are as shown in the first figure to the fifth figure. The first step is the first process step of the embodiment. As shown in FIG. 1A, the first step is on a growth substrate 101. Forming a buffer layer (not shown) and a semiconductor light emitting stack comprising an n-type semiconductor layer 1〇2 and a p-type half layer 103' and then respectively to the n-type semiconductor layer 1〇2 and the p-type semiconductor layer 1 Above the 〇3, an n-electrode 104 and a ρ-electrode 105 are respectively formed. Referring to the top view of the first aspect of the first embodiment, the top view plane is a plurality of n-electrodes & the electrodes 105 are arranged in a straight line. The pattern 101. The earth plate 101' as described above is, for example, a sapphire substrate, so that the InGaN semiconductor light-emitting layer on the enamel can be laminated in the crystal growth process without causing a large amount of lattice dislocation. Or lattice defects (defects). The ρ electrode 1〇5' is, for example, silver (Ag) or chain (Α1) or gold (Au) or an alloy thereof. The second embodiment is the second process step of the embodiment. An n-circuit layer 2〇4 and a p-circuit layer 2〇5 are formed on a permanent substrate 201. Referring to FIG. 2B, a top plan view of FIG. 2A, the plan view plane is composed of a plurality of n-circuit layers 204. And the p circuit layer 205 is arranged in a straight stripe pattern. The plurality of η circuit layers 204 are connected to each other through a line pattern perpendicular to each of the η circuit layers 204, and are electrically connected to each other to form an electrical connection. 11 circuit pattern; at the same time, a plurality of ρ circuit layers 2 〇 5 are also connected to each other through a line pattern perpendicular to each ρ circuit layer 205 to form an electrically connected Ρ circuit pattern. The η circuit layer 2〇4 and the ρ circuit layer 2〇5 are, for example, made of silver (Ag), aluminum (Α1) or gold (Au) or an alloy thereof. The permanent substrate 2〇1 is a substrate having good heat dissipation properties, such as a metal substrate, a tantalum substrate or a highly thermally conductive ceramic substrate. 3A-3B is a third process step of the embodiment. As shown in FIG. 3A, the n-electrode of the growth substrate 1〇1 and the p-electrode 105 and the n-circuit layer 204 of the permanent substrate 201 are aligned with the p-circuit layer 205 by a bonding process (eg, FIG. 3). Show), the two substrates are connected to the process. The joining process may be a direct joint or a metal joint; the direct joint is generally applied to a high temperature strip (>400 ° C), and a fixed auxiliary pressure is applied to melt the materials on both sides of the joint interface to form a bond. The metal joint is attached to the two joint interfaces, and a metal layer is formed first, and then a lower temperature (2 ° C to 300 ° 〇 and a fixed 1352441 auxiliary pressure are applied to join the two metal layers. The figure is the fourth process step of the embodiment. The substrate substrate removal technique is used to remove the growth substrate 101 as shown in the figure. The substrate removal technology is a laser stripping technique: using an excimer laser (Excimer laser) The growth substrate ιοί is incident away from the surface of the light-emitting layer. At this time, most of the laser energy is absorbed by the interface between the buffer layer on the growth substrate 101 and the growth substrate 101, and the buffer layer is removed to remove the growth substrate 101. 5A-5B is a fifth process step of the embodiment, which comprises two steps. First, as shown in FIG. 5A, a reactive ion beam etching (Reactive ioi> beam etching) technique is used to carry out the luminescent layer. The electrodes 1〇4 and ρ electrodes 105 are respectively formed to form the wire openings 304 and 3〇5, and the n electrode 104 and the p electrode 1〇5 are directly exposed. Reactive ion-beam etching is performed. With It has many advantages, such as good selectivity, fast etching rate, independent control of reaction parameters and no residue problem. Therefore, there is a tendency to replace wet etching with active ion beam etching in the process of semiconductor fabrication. Inductively integrated electro-active ion-ion engraving system (ICP-Rie) for dry-type engraving, and by etching parameter analysis method, by changing the reaction gas (BC13/Ar) flow, pressure, inductively coupled plasma power ICP (IndUCtivdy Coupled Plasma) and power (ie DC-bias bias), find them and etch rate, etch selectivity, etch directionality, etched surface flatness, and parameters 'etch out openings 3〇4 and 305. Again, as As shown in Fig. 5B, the wafer 501 (including the permanent substrate 2〇1 and the light-emitting layer 102) is cut to form a plurality of separate crystal grains 5〇2. Fig. 6 is a sixth process step of the embodiment. The step is to perform the wire bonding process by using the openings 304 and 305, wherein the n wire 4〇4 is connected to the n electrode 104 and the p wire 405 is connected to the p electrode 1〇5. Then, the surface of the p-type semiconductor layer is rough-slited, for example. The surface of the 9 P-type semiconductor layer 102 is caused to have a regular or irregular concave-convex surface by a method such as a surname or a nanoimprint, etc. Thus, when a current is conducted from the wire to the light generated by the semiconductor light-emitting laminate, Because of the roughening design of the light-emitting surface, the light extraction efficiency is improved, and the luminous efficiency of the light-emitting diode element 600 is also improved as a whole. Since the C* example is to connect the wafer to the permanent substrate first, Then, the active ion beam etching technique is used to etch the wire opening, and finally the cutting is performed to cut the wafer into crystal grains, that is, the structure of the light emitting diode element 600 is obtained. In general, a flip-chip light-emitting one-pole element is obtained by first cutting a wafer into a plurality of crystal grains, and then performing a para-join connection between the respective crystal grains and a sub-mount. A second cutting lob is performed on the sub-mount to obtain a light-emitting diode element 900. In contrast, this embodiment can be completed by performing a wafer alignment bonding and a single cutting process step, but generally the flip-chip LED component requires not only the respective die and the carrier substrate (sub_m〇unt)- - Perform the alignment, and also make two cutting lobes to complete. From this, it can be seen that this embodiment can greatly simplify the process steps, thereby improving production efficiency and reducing production costs. Figure 7 is a structural diagram of a backlight module of the present invention, wherein the backlight module device 700 comprises a light source device 710 composed of the light-emitting diode elements according to any of the above embodiments of the present invention; The light source device 71〇3 is configured to emit light after the processing; and the power supply system 730 supplies the power source required for the light source device 71. Figure 8 is a structural view of a lighting device of the present invention. Go to the street? 浐 flashlights, street lights, or lights and so on. The light source device 810 is configured by any one of the above-described optical diode elements 811 according to the present invention; a power supply system 82, a power supply for the source device 810; and a control device 83〇 control current & 1352441 light source device 810. The structure of the component of the invention-process step is the top view of Figure 1A. It is a structural diagram of the components of the second process step of the present invention. The top view of Figure 2A. It is a structural diagram of the third process step element of the present invention. A schematic diagram of the third step of the present invention. A schematic diagram of a fourth process step of the present invention. It is a schematic diagram of the fifth step of the present invention. A second schematic diagram of the fifth process step of the present invention. It is a structural diagram of the light-emitting diode of the present invention. It is a structural diagram of the backlight module of the present invention.
【圖式簡單說明】 第1Α圖 第1Β圖 第2Α圖 第2JB圖 第3Α圖 第3Β圖 第4圖 第5Α圖 第5Β圖 第6圖 第7圖 第8圖 第9圖 係本發明之照明裝置結構圖。 係一般覆晶式發光二極體之結構圖。 102〜η型半導體層 104〜η電極 201〜永久基板 205〜ρ電路圖案 502〜晶粒 404〜η導線 【主要元件符號說明】 101〜成長基板 103〜p型半導體層 105〜p電極 204〜η電路圖案 501〜晶片 304,305〜打線開口 1352441 405〜p導線 700〜背光模組裝置； 711〜發光二極體元件； 800〜照明裝置； 811〜發光二極體元件； 830〜一控制元件； 901〜封裝基板； 903〜η電路圖案， 904〜導線 600〜發光二極體元件 710〜光源裝置； 720〜光學裝置； 810〜光源裝置； 820〜電源供應系統； 900〜水平式發光二極體 902〜發光疊層； 906〜ρ電路圖案， 905〜導線BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A, 1st, 2nd, 2nd, 2nd, 3rd, 3rd, 4th, 5th, 5th, 6th, 7th, 8th, 9th, 9th Device structure diagram. It is a structural diagram of a general flip-chip light-emitting diode. 102 to n-type semiconductor layer 104 to n-electrode 201 to permanent substrate 205 to ρ circuit pattern 502 to die 404 to n-th wire [Description of main element symbols] 101 to growth substrate 103 to p-type semiconductor layer 105 to p-electrode 204 to η Circuit pattern 501 ~ wafer 304, 305 ~ wire opening 1352441 405 ~ p wire 700 ~ backlight module device; 711 ~ light emitting diode element; 800 ~ lighting device; 811 ~ light emitting diode element; 830 ~ a control element; Package substrate; 903~η circuit pattern, 904~ wire 600~ light emitting diode element 710~ light source device; 720~ optical device; 810~ light source device; 820~ power supply system; 900~ horizontal light emitting diode 902~ Light-emitting laminate; 906~ρ circuit pattern, 905~ wire
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