TWI346884B - A method of merging designs of an integrated circuit from a plurality of sources - Google Patents

A method of merging designs of an integrated circuit from a plurality of sources

Info

Publication number
TWI346884B
TWI346884B TW096116426A TW96116426A TWI346884B TW I346884 B TWI346884 B TW I346884B TW 096116426 A TW096116426 A TW 096116426A TW 96116426 A TW96116426 A TW 96116426A TW I346884 B TWI346884 B TW I346884B
Authority
TW
Taiwan
Prior art keywords
merging
designs
sources
integrated circuit
integrated
Prior art date
Application number
TW096116426A
Other languages
English (en)
Other versions
TW200802016A (en
Inventor
Sreeni Maheshwarla
Amitay Levi
Elizabeth Cuevas
Original Assignee
Silicon Storage Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Storage Tech Inc filed Critical Silicon Storage Tech Inc
Publication of TW200802016A publication Critical patent/TW200802016A/zh
Application granted granted Critical
Publication of TWI346884B publication Critical patent/TWI346884B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/02—CAD in a network environment, e.g. collaborative CAD or distributed simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW096116426A 2006-06-12 2007-05-09 A method of merging designs of an integrated circuit from a plurality of sources TWI346884B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/452,032 US20070288881A1 (en) 2006-06-12 2006-06-12 Method of merging designs of an integrated circuit from a plurality of sources

Publications (2)

Publication Number Publication Date
TW200802016A TW200802016A (en) 2008-01-01
TWI346884B true TWI346884B (en) 2011-08-11

Family

ID=38823394

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096116426A TWI346884B (en) 2006-06-12 2007-05-09 A method of merging designs of an integrated circuit from a plurality of sources

Country Status (4)

Country Link
US (1) US20070288881A1 (zh)
JP (1) JP2007335864A (zh)
CN (1) CN100592307C (zh)
TW (1) TWI346884B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7945869B2 (en) * 2007-08-20 2011-05-17 Infineon Technologies Ag Mask and method for patterning a semiconductor wafer
TWI386841B (zh) * 2008-08-22 2013-02-21 Acer Inc 立體圖形化使用者介面產生方法、系統，及電腦程式產品
JP5293572B2 (ja) * 2009-11-17 2013-09-18 富士通セミコンダクター株式会社 設計検証装置、設計検証方法及び設計検証プログラム
CN101866829A (zh) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 一种保护集成电路参数化单元的知识产权的方法
US8694950B2 (en) 2010-07-24 2014-04-08 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness
CN102880763B (zh) * 2012-10-17 2018-07-31 上海华虹宏力半导体制造有限公司 Ip核检测版图、版图设计系统及版图设计方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049659A (en) * 1995-12-26 2000-04-11 Matsushita Electric Industrial Co., Ltd. Method for automatically designing a semiconductor integrated circuit
US6041269A (en) * 1997-08-11 2000-03-21 Advanced Micro Devices, Inc. Integrated circuit package verification
JP4142176B2 (ja) * 1998-10-20 2008-08-27 株式会社ルネサステクノロジ インタフェース仕様定義を記録した記憶媒体、及び接続検証方法、及び信号パタン生成方法
US6625780B1 (en) * 2000-02-28 2003-09-23 Cadence Design Systems, Inc. Watermarking based protection of virtual component blocks
US6904527B1 (en) * 2000-03-14 2005-06-07 Xilinx, Inc. Intellectual property protection in a programmable logic device
JP2002134621A (ja) * 2000-10-30 2002-05-10 Seiko Epson Corp マスクデータ合成方法、マスクデータ検証方法及び半導体集積装置
US6668360B1 (en) * 2001-01-08 2003-12-23 Taiwan Semiconductor Manufacturing Company Automatic integrated circuit design kit qualification service provided through the internet
US6976236B1 (en) * 2002-04-05 2005-12-13 Procket Networks, Inc. Method for automatically routing connections between top side conductors and bottom side conductors of an integrated circuit package
TW571410B (en) * 2002-12-24 2004-01-11 Via Tech Inc BGA package with the same power ballout assignment for wire bonding packaging and flip chip packaging
US7272801B1 (en) * 2003-03-13 2007-09-18 Coventor, Inc. System and method for process-flexible MEMS design and simulation
US7096439B2 (en) * 2003-05-21 2006-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for performing intellectual property merge
US7384568B2 (en) * 2006-03-31 2008-06-10 Palo Alto Research Center Incorporated Method of forming a darkfield etch mask

Also Published As

Publication number Publication date
JP2007335864A (ja) 2007-12-27
CN100592307C (zh) 2010-02-24
TW200802016A (en) 2008-01-01
US20070288881A1 (en) 2007-12-13
CN101089860A (zh) 2007-12-19

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