TWI345790B - Method and apparatus for dual data-dependent busses for coupling read/write circuits to a memory array - Google Patents
Method and apparatus for dual data-dependent busses for coupling read/write circuits to a memory array Download PDFInfo
- Publication number
- TWI345790B TWI345790B TW096128071A TW96128071A TWI345790B TW I345790 B TWI345790 B TW I345790B TW 096128071 A TW096128071 A TW 096128071A TW 96128071 A TW96128071 A TW 96128071A TW I345790 B TWI345790 B TW I345790B
- Authority
- TW
- Taiwan
- Prior art keywords
- line
- bus
- mode
- bit
- word line
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/461,352 US7486587B2 (en) | 2006-07-31 | 2006-07-31 | Dual data-dependent busses for coupling read/write circuits to a memory array |
| US11/461,369 US7499366B2 (en) | 2006-07-31 | 2006-07-31 | Method for using dual data-dependent busses for coupling read/write circuits to a memory array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200823921A TW200823921A (en) | 2008-06-01 |
| TWI345790B true TWI345790B (en) | 2011-07-21 |
Family
ID=38997822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW096128071A TWI345790B (en) | 2006-07-31 | 2007-07-31 | Method and apparatus for dual data-dependent busses for coupling read/write circuits to a memory array |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP2062263B1 (cg-RX-API-DMAC10.html) |
| JP (1) | JP5201143B2 (cg-RX-API-DMAC10.html) |
| KR (1) | KR101465557B1 (cg-RX-API-DMAC10.html) |
| AT (1) | ATE556411T1 (cg-RX-API-DMAC10.html) |
| TW (1) | TWI345790B (cg-RX-API-DMAC10.html) |
| WO (1) | WO2008016948A2 (cg-RX-API-DMAC10.html) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12412620B2 (en) | 2021-05-26 | 2025-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Second word line combined with y-mux signal in high voltage memory program |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8279704B2 (en) | 2006-07-31 | 2012-10-02 | Sandisk 3D Llc | Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same |
| US8958230B2 (en) | 2012-08-31 | 2015-02-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
| GB2545264B (en) * | 2015-12-11 | 2020-01-15 | Advanced Risc Mach Ltd | A storage array |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6229845B1 (en) * | 1999-02-25 | 2001-05-08 | Qlogic Corporation | Bus driver with data dependent drive strength control logic |
| US6856572B2 (en) * | 2000-04-28 | 2005-02-15 | Matrix Semiconductor, Inc. | Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device |
| JP4322645B2 (ja) * | 2003-11-28 | 2009-09-02 | 株式会社日立製作所 | 半導体集積回路装置 |
| CN1977337A (zh) * | 2004-05-03 | 2007-06-06 | 统一半导体公司 | 非易失性可编程存储器 |
| US7286439B2 (en) * | 2004-12-30 | 2007-10-23 | Sandisk 3D Llc | Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders |
| US7054219B1 (en) * | 2005-03-31 | 2006-05-30 | Matrix Semiconductor, Inc. | Transistor layout configuration for tight-pitched memory array lines |
-
2007
- 2007-07-31 TW TW096128071A patent/TWI345790B/zh not_active IP Right Cessation
- 2007-07-31 JP JP2009523029A patent/JP5201143B2/ja active Active
- 2007-07-31 AT AT07840621T patent/ATE556411T1/de active
- 2007-07-31 WO PCT/US2007/074901 patent/WO2008016948A2/en not_active Ceased
- 2007-07-31 KR KR1020097004226A patent/KR101465557B1/ko not_active Expired - Fee Related
- 2007-07-31 EP EP07840621A patent/EP2062263B1/en not_active Not-in-force
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12412620B2 (en) | 2021-05-26 | 2025-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Second word line combined with y-mux signal in high voltage memory program |
| TWI920129B (zh) * | 2021-05-26 | 2026-04-01 | 台灣積體電路製造股份有限公司 | 記憶體裝置、記憶體系統及其操作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2062263A2 (en) | 2009-05-27 |
| ATE556411T1 (de) | 2012-05-15 |
| EP2062263B1 (en) | 2012-05-02 |
| JP2009545837A (ja) | 2009-12-24 |
| KR20090057373A (ko) | 2009-06-05 |
| KR101465557B1 (ko) | 2014-11-26 |
| WO2008016948A3 (en) | 2009-01-08 |
| JP5201143B2 (ja) | 2013-06-05 |
| WO2008016948A2 (en) | 2008-02-07 |
| TW200823921A (en) | 2008-06-01 |
| EP2062263A4 (en) | 2009-08-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |