TWI344106B - Artifact-free transitions between dual display controllers - Google Patents

Artifact-free transitions between dual display controllers Download PDF

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Publication number
TWI344106B
TWI344106B TW96110222A TW96110222A TWI344106B TW I344106 B TWI344106 B TW I344106B TW 96110222 A TW96110222 A TW 96110222A TW 96110222 A TW96110222 A TW 96110222A TW I344106 B TWI344106 B TW I344106B
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TW
Taiwan
Prior art keywords
display
display controller
controller
step
processor
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Application number
TW96110222A
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Chinese (zh)
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TW200745940A (en
Inventor
Mark J Foster
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One Laptop Per Child Ass Inc
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Priority to US78506506P priority Critical
Priority to US90612207P priority
Application filed by One Laptop Per Child Ass Inc filed Critical One Laptop Per Child Ass Inc
Publication of TW200745940A publication Critical patent/TW200745940A/en
Application granted granted Critical
Publication of TWI344106B publication Critical patent/TWI344106B/en

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363Graphics controllers
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Description

1344106 IX. Description of invention: [Technical field to which it belongs] Second; system = display system with dual display controller and display = and ::: no distortion transmission between dual display control [previous technology] In the system, the central processor (coffee) outputs a letter-out signal and then drives the second (10) after the arithmetic processing and then inputs the -double two = := : piece output image. To cry, you must set up two display systems: and C to display the controller and the second display controller, and: the main and the younger ones are not independently controlled by the center. And the display element can be used by JL. One§ , . , control, switch the control of the main controller. However, in the meantime, the main and the first display controller are synchronized to prevent the display element from displaying the gold output nickname, and the beauties are distorted. The purpose is to enable the primary and secondary display controls:: 2: The well-known "-" technology 'this technology allows the primary and the first non-controllings to operate simultaneously' and combines the signals they output - no Component output - a complete image; but this synchronized and numbered technology requires expensive and complex electronic circuitry. Another traditional technique is to transmit the main control; the control segment is transmitted to the second display controller and the modulating effect is performed, and the segment picture can be displayed in any one of the display controls; The fragment picture needs to be operated by the relay and the technical continuity of the adjustment. However, the above-mentioned technology will inevitably have the following shortcomings, because the traditional Fang Gao requires two display controllers to operate at the same time, and the processor also needs to do the trick: the broken processing 'causes the system must consume a lot of energy; but the second: The technical solution can eliminate the need for the processor to perform a complicated operation and then the complicated circuit design. The arguments of Youwan and II!t must be improved for the main and second display controllers; firstly, the operator must reduce the continuity of the == without the need for r continuity; It is more economical to use the system without any application; in addition, the system with low monthly consumption is also the goal to be pursued. - [Description of the Invention] The system is to provide a dual display controller with the dual display controller. The method can be used to control the display device with the display system. The display system and the 1 driver provide an operation with a dual display controller to achieve the operation of the display device

Guben I month proposed a number of implementations to achieve the above display system of the M UL system, including: - at: two non-defense state, - second display controller; one - use the picture buffer cry. Chu __ ° , · Should not be the controller of the controller, · and ten (four) 帛 - no buffer used by the controller. Wherein, the processor sends a plurality of display screens to the first display controller; the controller transmits the second display = no-face and then transmits the first-display without writing the display to the second display == the second display The situation in which the controller can be positively operated is not at least one-handed in the piano: the image of the device is rotated. in. The processing will be used to display the number of buffers used in the display: '第::第-display controller output image, if the screen used by the first display controller is moved to the previous The display screen is in the screen buffer of the '3 haidi two display control, and then the second 孽 is; the controller is pulsing: the image clock is transmitted by the first: display (four) g to _ i, processing 2 The first - display (four) 11 can be switched to the idle mode. VII. Even if the processor does not display any farm display image, the used surface is written to the state of the first display controller. After the second display controller displays the image for the predetermined time with the same picture signal, the second display is replaced with the idle mode. At any time, when a new buffer that is written to the second display controller is not present, the control will be followed by the trailing edge of the vertical sync pulse to return to the display controller. The first - display controller. In the present invention

lJ^lUO • In the example, when the processor receives the external device, the second display control crying can be stopped by the door f _4, Ί °, and 5 Μ 1 switch to the startup mode. All signal transmissions, such as the first: = two = execution face. Both the wonderful and the Γ^ Γ 而 可 可 可 可 可 可 可 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无The second display =: = r reduces the energy consumption. Comprehensive == =: ί system and its display system - with dual display control system to control the display device, can be achieved in the first low-energy display system * to achieve distortion-free image output hardware and more suitable for The application of the present invention is based on the embodiment of the present invention. The display system can be used in one, heterogeneous The display is not driven by the system, the first, the method and the computer program with the === shadow; _ system includes: - processor; - the painting used = punch controller; a first display controller punch; and 1 亍 μ - brother two display controller used to slow the picture,,, page not installed . The display device can be driven by the first display control 13.44106 ^ inactive to display an image, and the surface is written into the first display controller: the control device of the display device, the first display For the 'display', the switch is switched to the lean-phase- 3, the second display controller performs the V: weight of the display device: the first display controller is switched to the control of the first set The weight is performed by the trailing edge of the vertical sync pulse of the follower, and the second == into the other: In the embodiment, 'When a new display is written, the weight is combined:;, the buffer used 'The display device: .mL indicates that the controller switches to the first-display control: the same line 'this control right switching action is between the vertical blanking period / please refer to the first figure, which is the invention A schematic diagram of the system 1GG, section 2 is applicable: a plurality of embodiments of the present invention. The system-wide i i port is a different device, but a typical device includes: a processor (10), a - display Controller just, the controller 106 and a display station 1ne fighters one, the second" no The device (10) can control the first display controller 04 and the second display control 〇6; the first display controller 104 can be built in the processor 〇2, It is also possible to distinguish between the different functions of the circuit and the processor 1. The computer computing device J is a notebook computer, a palmtop computer, a desktop computer, a calculator, a portable telephone or a personal digital assistant (PDA). Similarly, the display device 8 can be a liquid crystal display (LCD), a cathode ray tube (CRT) or a plasma display 9 1344106; the processor 102 can be typically disposed in a computer computing device. a central processing unit (CPU), and the first display controller 104 and the second display controller 106 can be a conventional video graphics array (VGA) controller or an application specific integrated circuit (ASIC) controller, the above example It is a possible hardware device, but not limited thereto. In this embodiment, the second display controller 106 supports six interfaces; the first interface is a thin film transistor (TFT) input port for receiving The output of the first display controller 104 The second interface is a double edged transistor-transistor logic (DETTL) liquid crystal output port, which is directly connected to the thin film transistor panel driver of the integrated circuit for use in a suitable thin film transistor. The liquid crystal display is outputted on the display device; the third interface is a system management bus (SMBUS) sequence, which has an operating frequency of at least ΙΟΟΚΗζ and is connected to the setting register inside the second display controller 106, and The register can be read and written; the fourth interface is a set of single input/output or multiple input/output terminal interfaces, which can be managed by the first display controller 104 and the second display controller The critical timing switching between 106; the fifth interface is a synchronous dynamic random access memory (SDRAM) interface, which can be connected with a low power synchronous dynamic random access memory to store a single complete display surface, the second The display controller 106 can cause the display device 108 to perform a spontaneous update by capturing a display screen from the synchronous DRAM. The sixth interface is directly connected to a crystal of 14.31818 MHz, which can ignore the state of the image input port and provide a separate picture update pixel clock. The independent picture 1344106 updates the pixel clock at the picture update rate of 5 UHz's 愔' teeth are 5w. In addition, the independent facet update 2 is used to store the age, dynamic random access (4) = interface timing. _ ', and according to another embodiment of the present invention, 兮筮_._八一一一弟 - display controller 106 further package 'which is a plurality of terminals to connect to 1 〇 2' the connection relationship can be in the process When the interface is::, the second display controller 106 is switched from the idle mode = in addition, the second display controller 106 has various functions, and the second display controller 106 supports the color mixing. ° swiping)" allows the display device 1〇8 to display a faceplate as in the conventional μ position (7). This, the color mixing replacement (c〇1〇r swizznng) technique can be perceived as not causing a difference. Reduce the number of bits. The second display 拎 state is more anti-aliasing, which can be increased

The device 108 displays the sharpness of the text; further, the second display control two \ = can support the monochrome mode (monochrome) to automatically locate the book in the de-order mode. ..., turning into ash and additionally 'the second display controller 1 〇 6 can make a subsequent display transparency (transparency) under a pass-through m 'de, that is, in the transfer mode (pass_thr0Ugh m〇de) The second display controller 1〇6 will transmit the first display control cry 104 to the display face without any operation calculation (mai^_ati〇ns). In this way, a simple basic LCD timing control chip and an automated fly-by mode 1344106 can be achieved; the fly-by mode avoids unnecessary writing of the synchronous DRAM buffer. It can reduce the overall energy consumption' and can be applied to the setting of minimum power consumption. The second display controller 106 can support the debugging of the three primary color (RGB) panels, and also has the = self test (self_test) function at the production line end. Since the second display controller 1〇6 can be turned into a pass-through mode, no operation calculations are performed on the display, so that the second can be tested at the time of production. Whether the controller 1〇6 is normal is displayed. The above discussion of the second display controller 106 can be coordinated with the second figure. 々月β考卓图, which is a sound diagram of the display system 200 of the present invention, the first display controller 1〇4 is connected to a plurality of clock generators 2〇6 and a buffered state 202; however, for convenience It is noted that the clock generators 2〇6 are built in the first display controller 104, and the first display controller 104=includes at least one register (not shown) (not shown); - second display control: and: connecting a plurality of clock generators 2 〇 8 and a buffer buffer 2 〇 4; ...... For convenience of explanation, the clock generators 208 are π#%% # - =Η6 internal, and the second display controller 1% further includes a sub- 21 〇, a second terminal 212, a second terminal 216, a 筮7 乐一鳊子214, a fourth not shown ). ^ child 218 and at least one register (four) is (four) (illustration control ί = : 〇 2 system outputs a plurality of display display screens to the first display (10) of the second display controller 1 〇 6 to refresh - display device display Device=: The number of display screens is sufficient to refresh the display of 1〇8, and the display surface is displayed by the image of the 12 1344106 > ψ , . The pixel data (pixel_by_pixel_) is composed, and the buffer buffers 2〇2, 2〇4 are used to store the display surfaces, and the display device 108 can be used by the first display controller The controller is driven by any one of the second display controllers H) 6; the terminals are used to control the control of the display device 108 on the first display controller 1〇4 and the second display control 1G6 Switch between. The processor 1Q2 outputs a plurality of display screens for the first display control processor 1〇2 to write the display screen to the screen buffer 2〇2, and the display controller H)4 is responsible for driving the display device. 1〇8 refreshes the screen; if the processor 102 does not write the display screen to the buffer buffer, the display of the display (10) switches to the second display controller]%. The processor 1 〇 2 again writes the display face to the face buffer 202, and the control of the display device (10) returns to the first display controller (10). The control right of the display device (10) may cause written facts when the first display controller just switches the display controller 1G6〇, and the switching mode proposed by the present invention can avoid distortion, please refer to the third to Five maps. , cattle == the flow chart of the method for driving the display device 108 of the present invention, the display controller 104 receives the buffer from the processor 102 = and the display face data is stored in the face buffer step 304 ' + Zhuangban (8) ring ng int called '= 2nd _108 control right during the occlusion period controller 106 _ switching period 1 〇 4 and the second display 』 (blanking interval) refers to the vertical synchronization pulse at 1344106 (v-syncpuise) or the time interval between the trailing edge of the horizontal sync pulse (H_Syncpulse) and the next scan line, the scan line will display the entire column of pixel data displayed by the display device 108; here is the use The vertical blanking period 'and the switching action occurs at the rear end of the vertical sync pulse. In one embodiment, the display device 1〇8 is used by the first display controller 1. 〇4 is driven' and no display picture data is written to the picture buffer

The control of the display device f1〇8 is changed to the second display by the knife. Controller 106. Conversely, the display device 1〇8 is driven by the second display controller 106, and there is a new display to display the face buffer 202, and the display device is controlled to return to the ship. The first display controller 104. Step 306, after the control is switched, the display device 1 刷新 8 refreshes the display screen 2 according to the driving control of the display controller having control of the display device 1 〇 8 at the first display controller. The method of replacing the knives with the second display controller 1G6 will be explained in more detail in the fourth and fifth figures. The fourth A diagram and the fourth B diagram are flowcharts of the method in which the control right of the display device 1〇8 is switched to the second display controller 1〇6 by the first-display controller H)4. When the picture buffer is continuously written by the writer, the following display controller 104 is responsible for driving the display device ι 8 to display the display controller 104 to transmit the display to the _ dan The display buffer 2〇4 is used by the "弟一", the controller controller 106; thereafter, the second display controller 撷 captures the display screen by the screen balancer 2〇4 to drive the display 14 1344106 « Display device 108. The second display controller 106 can perform at least one operation calculation on the display screen, for example, adjusting the frequency of the output face, performing color swizzling, and An operation such as anti-aliasing is used to refresh the display device 108. However, according to another embodiment of the present invention, the second display controller 106 may not record the display screen to the picture buffer 204. Performing at least one operation calculation on the display screen, for example, adjusting the frequency of the output face, performing color swizzling, anti-aliasing, etc., and using To refresh the display device 108. Referring to FIG. 4A, in step 402, the first display controller 104 is responsible for driving the display device 108 to display an image; and step 404 is to determine whether a new display surface is written to the image buffer. If the picture buffer 202 is continuously written into the new display screen, the first display controller 104 is responsible for driving the display device 108 to display the image according to step 402; conversely, if there is no new display When the buffer buffer 202 is written, step 406 is performed to set the first terminal 210 of the second display controller 106 to a low state; then, in step 408, a new display screen is written. The screen buffer 204 is inserted; as described below, the second display controller 106 performs a display load cycle at the trailing edge of the vertical sync pulse (V-Sync pulse). The display load cycle That is, the step of writing a new display face to the face buffer 204, the write operation starts at the trailing edge of a vertical sync pulse (V-Sync pulse) and is next to the vertical sync pulse ( V-Sync pulse) The trailing edge of the vertical sync pulse 1344106 (V-Sync pulse) refers to the terminal that displays the picture in the display and the beginning of a new display picture; that is, the second display controller 1〇6 will Starting from the first scan line, recording pixd data to the trailing edge of a vertical sync pulse (V-Syncpuhe), and the trailing edge of the vertical sync pulse (V-Sync puise) or the second display control The timing of the output display screen of the device 1〇6 is input by the processor to the second display controller 106 through the second terminal 212, and the second terminal 212 starts from the first scan line to a vertical sync pulse (V-Sync). The trailing edge of pulse) is kept in a low state. The second terminal 212 is maintained in a high state during a vertical blanking period. The processor 丨〇2 synchronizes the control rights between the first display controller 1〇4 and the second display controller by using the state of the second terminal 2]2, when a complete The picture is written to the second A picture buffer S 204 'the second display controller is executed to switch control back to the second display controller 1 6 itself. In step 410, the second display controller 106 determines the timing of the plurality of _th display control nm as the timing of the plurality of third display controllers 〇6. According to the present invention, the above-mentioned conversion action is immediately followed by The trailing edge of the vertical sync pulse (V-Sync puise), that is, the time between the start of the vertical sync pulse called c Ρ·) and the end of the vertical blanking period. In addition, the first display controller (10) can also switch the clock generated by the clock generator to the clock generated by the clock generation ϋ2〇8, and the clock generator 2〇6 and the track I have a phase _ Solution, but the clock generator is not synchronized with the clock benefit 206. However, the function of first outputting (Fim in First 16 M44106 FIF〇) can be used to correct the timing of the display surface input by the first display controller 104 to the display controller 106 and the second display. The timing of state 106 is matched. However, in another embodiment of the present invention, the timing of the first display controller 104 and the timing of the second display controller 1〇6 are respectively in a blanking interval of a horizontal synchronization pulse (H-Sync pulse). Modulation is performed, and the synchronization of the picture can be achieved by phase-locked back (Phase Locked Loop, PLL) and thus can be displayed continuously. In step 412, the second display control n 1Q6 will control the plurality of registers in the first display f and the second display control. . A plurality of registers in 106 are reset to (9). In the step "the first display controller i 〇 6 switches the buffer 2 (10) from the input 2 to the read mode. In the embodiment of the present invention, the switching phase modulation is performed simultaneously. That is, the adjustment of the image timing is completed: 2, the controller 1〇6 uses the buffers and the clock generator to cry an image wheel. The image output includes the player's face extracted from the screen buffer. The display surface can be obtained by operation calculation ^anlpu^_s) or completely without operation calculation (_咖_二^ and °Xuanxian does not control the switching of the device 108, the above temporary storage: clock generator ~ under At the beginning of a line start, in step 416, the controller ΚΗ switches to the control device: the control device is controlled by the first display controller 丨〇6 from the bottom! The second display controller 106' and the second display The beginning of the control scan line begins to refresh the face of the display device 1344, 106, and the second display controller 1 6 independently refreshes the display according to the display of the face buffer 204. The screen of the device 1〇8; in step 418, the 5H processing & 1〇2 and the first display control stomach are switched Inactive mode; conversely, in another embodiment of the present invention, the first display controller! 〇4 is switched to the idle mode (i cafe mode), but the processor! 02 is held in one The startup mode (10) ve is out (4), and when the second display controller 1〇6 refreshes the display device (10) to the number of times using the same display screen, the second display controller: 〇6 can be switched to the idle mode. (inactive m〇de); and the predetermined number of times is stored in the temporary register of the second display controller 1〇6. The fifth figure shows that the control right of the display device 1〇8 is controlled by the second benefit. 6 is a flow chart of the method of switching to the first display controller. At S = 〇:, the display device (10) is responsible for 2 new by the second display controller ι 6 . Step 504, then _ whether there is a new display The face is written to the face buffer 202; if not (N〇), then return to step 5〇2, the second display controller is responsible for refreshing the display device 1〇8; conversely (10) =^ enter the step The first terminal (10) is set in a high state, and the state will be θε _ ^ white I The controller (10) is located in the high-energy write state of the model, and the display controller 106 stores the display buffer in the picture buffer 202 in the picture buffer 204. ' ' In step 508, the second display controller touches the timing plate of the controller 104 to perform the first _g., and the shoulder does not change; at the same time, the first:==the factory controller 1〇6 adjusts the first display between the timings. The controller 106 performs the modulation of the clock generators 18 1344106 and 208. In one embodiment of the invention, the modulation is performed immediately after the trailing edge of a vertical sync pulse (V-Sync pulse); In another embodiment, the modulation is performed during a blanking interval of a horizontal sync pulse (H_Syncpulse).

When the first display controller 04 is in a low-order state (1〇w state), the clocks generate β 206 'image timing and the register that the first display controller has just included The processor 1 〇 2 is re-initialized 'and at the same time the processor M 〇 2 also reinitializes the clock generators 206 and the clusters synchronously. According to another embodiment of the invention. The clock is generated by the clock, and the image sequence and the register included in the first display controller ι4 are re-interrupted by an interrupt input by a third terminal. Initialization, the third terminal 214 can perform an interrupt at the beginning of a predetermined sweep line and the second display controller 〇6 == performs a plurality of functions according to the type of the interrupt, the error of the interrupt is determined by a fourth terminal 216 indicates the processor 102. According to still another embodiment of the present invention, the second display x indicates the type of the interrupt. And after (10) 疋 through a plurality of initializations, the (4) is controlled; the coffee is in step (4). , the second; the second will execute the remaining 1 Λ., the control of the set 08 is switched to the first place == then the first display control tao according to the write 102 to the far picture buffer 2 〇 2 Next ': : Line: The = burner can produce shadow 2: save the gister) and the clock production 19!3441〇6 brother six figure is the second display controller 1〇6 from idle mode (_twe _de) Flow chart of the method of starting. In step _, (4) two, the controller 1G6 is kept in the idle mode (inaetivemQde);

Immediately, it will detect whether the processor (10) receives an input signal from the wheel device, such as a keyboard, a touchpad, a *line trigger event ((10)〇, a cursor control panel or a mouse; The processor 1〇2 does not receive an input signal (No) from an input device, and returns to step 6〇2, that is, the second display is maintained in an idle mode (__ and wide). 102 receives an input signal from an input device (Yes), then proceeds to step 606'-the fifth terminal is determined by the processor 1 227 as a _high state (_state) and the second display controller is 〇 6 is changed from the idle mode to (10) 丨 ... mode) to the active mode (active mode); when the fifth terminal is set to a high state and the second display controller 106 is in the active mode, the second display The controller 1〇6 will reset the display timeout register, and the display timing terminates the temporary storage. The first display controller 1 〇6 can refresh the time value of a display screen, and After the time value has elapsed, the second display controller 1〇6 switches the inter-mode In another mode, in accordance with another embodiment of the present invention, when the processor 102 receives an input signal from an input device, the software built into the processor 102 drives the second display controller. 6 is initiated from the inactive mode. Step 608 'detects the processor 〇 2 whether to update a new display screen to the buffer buffer 202; if not (No), then proceeds to step 614: # The second display controller 106 starts to update the display device according to the 20 1344106 zero stored in the buffer buffer 204. 4 display control $1G6 to reset, right, then the second m know the register (10) coffee blanking

In the case of a non-register operation, the second system 11106 will drive the display device (10) to display the file and the display device (10) will return to the normal state. If the result of "^ _ is yes, then go to step 610, the sub-Μ: will execute - interrupt and make the second display * control 11 106: one does not loop (display iGad cyele), and then enter the person Step 612, the = display controller touches a display cycle (dis (four) - eyde); at step _614 the second display controller (10) independently drives the display: 1 〇 8 display screen. For the method of driving the display device and the relationship between the state and time of the 7L device in the system, the seventh to ninth drawings will be described in more detail below. "The seventh circle is an embodiment of the present invention, the control right of the display device 1 由 8 is switched by the first display controller 104 to the second display controller] shame corresponds to a time change relationship diagram, the figure shows Switching of control of the display device 1〇8 during a vertical blanking interval. The figure further shows different components in the display system 2, including the first display controller 104, the second display. The relationship between the controller 106, the picture buffer 2〇4, the clock generator 2〇6, the first terminal 2 and the second terminal 212, and the time, in the seventh figure t, the X-axis Representing the change of time 'Y axis is the state of each component. 1344106 The eighth figure is an embodiment of the present invention, the protection right of the display device ι 8 is switched by the second display controller 106 to the first display control Cry 1〇4$ should be a time-varying relationship diagram showing the control of the display device 1〇8 in a vertical blanking interval, and this figure further shows the display system 2不中不^Component, including the first display The controller 104, the second display controller 1〇6, the clock generation ^2〇6, the first terminal 210, the second terminal 212, and the third terminal 214 are in the form of: (9) and time relationship, in the eighth In the figure, the χ axis represents the change of time, and the Υ axis is the state of each component. The ninth figure shows that the second display controller (10) of the present invention is started by the idle mode (in) The relationship of time: This figure also shows the different components of this display system, including the first-display controller 104, the second display controller, the picture buffer cry 2, 2, the buffer buffer, The third state? 214 and the fifth end? 218 two states (her) relationship with time; in the ninth figure, Μ represents the change of time 'Υ axis is the state of each component. For example, display control The device may be implemented by an (ASIC), programmable logic controller or a portable device. For purposes of explanation, 'the implementation of the present invention (second display controller 106) will be described in detail, including hard Body, such as processor, integrated circuit, sub- and temporary settings. The following settings will allow The person skilled in the art can realize the technology of the present invention. The second display controller 〇6 register setting: 22 ^ 44106 register type index code preset value second display controller 106 identification and proofreading 0 dcoih Display mode of the second display controller 106 1 0012H Horizontal Resolution 2 0458H (1200 Decimal) Horizontal Total 3 04E8H (1256 Decimal) Horizontal Sync 4 1808H (24,8 Decimal ) Vertical Resolution 5 0340H (900 Decimal) Vertical Total 6 0390H (912 Decimal) Horizontal Sync 7 0403H (4,3 Decimal) Display Timeout 8 FFFFH Scanline Interrupt 9 0000H backlight-free brightness 10 XXXFH Reserved 11-127 User input wheel-out (1/〇) terminal definition of the second display controller 106: Second display controller 106 Special Application Circuit (ASIC) Output Terminal - lM (512Kx 16) Synchronous Dynamic Random Access Memory (SDRAM) Configuration Geode Display Interface Terminal Geode Pixel Clock (Pixei clo Ck) GFDOTCLK 1 Geode Red Data GFRDAT0-5 6 Geode Green Data GFGDATO-6 7 Geode Blue Data GFBDAT0-5 6 23 1344106 'V ·

Geode Vertical Synchronization (VSync) GFVSYNC 1 Geode Horizontal Synchronization (HSync) GFHSYNC 1 Geode FP_LDE GFP-LDE 1 5] 2Kxl6 SDRAM Interface Terminal FBRAM Data FBD0-15 16 FBRAM Address FBDA0-10 11 FB Column Addr Strobe FBCAS/ 1 FB Row Addr Strobe FBRAS/ 1 FB Data Masks FBDM0-1 2 FBRAM Chip Select FBCS/ 1 FBRAM Write Enable FBWE/ 1 FBRAM Clock FBCLK 1 FBRAM Clock Enable FBCLKE 1 Crystal for secondary display controller 106 Self-Refresh Display XTAL In DCONXI 1 Display XTAL Out DCONXO 1 System Interface Pins System Reset RESET 1 EC Power On Request ECPWRRQST 1 Second Display Controller 106 Interrupt Output DCONIRQ/ 1 The second display controller 106 displays the load command Load Command Request DCONLOAD 1 Second Display Controller 106 Status Pins DCONSTAT 2 Second Display Controller 1 06 Blanking Status DCONBLNK 1 24 1344106 » *

Secondary display controller 106 Register I/O SMB Clock DCONSMBCLK 1 secondary display controller 106 Register I/O SMB Data DCONSMBDATA 1 DETTL / Panel Interface Pins Panel Pixel Data 0 DOOO-DOOl 3 Panel Pixel Data 1 DO10-DO11 3 Panel Pixel Data 2 DO20 -DO21 3 Source Dot Clock SCLK 1 Data Interface Polarity Control REV 1-2 2 Graphics Output Enable (Gate driver enable) GOE 1 - INV 1 - CPV 1 - STV 1 - FSTH 1 - BSTH 1 - TP 1 LCD Backlight Enable BACKLIGHT 1 Display Backlight Control (PWM) DBC 1 Driver Polarity Signal 1 POL1 1 LCD VDD Enable VDDEN 1 Bum-In / Test Mode AGMODE 1 Color / Monochrome Panel Bias Select COLMODE 1 Total User I/Os 94 and the minimum cycle time for ECPWRRQST startup is less than approximately ]00 nS. The embodiment of the present invention described above is directed to a display system, and the package 25 includes a display device, a processor, a 笸-writing system, a second display controller, a Μ controller, and a second display controller. The included meaning, .$ 'in addition' the second display (four) ϋ has a plurality of terminals.

The embodiment proposed by the horse is described in the method of the present invention. The method achieves no distortion: the system: the display is displayed by the display device after the first display controller and the second display: == modulation Output, this modulation is followed by

The trailing edge of the sync pulse is performed, that is, the vertical period is set to ensure a distortion-free output. The second display controller can refresh the display device separately without the need to display a controller or a processor, so the display does not require a processing state for continuous operation. The first and second display controllers and the display device can be smashed under an extended period of time. Therefore, the system can save a lot of energy. The above-described embodiments of the present invention propose various applications that do not require expensive and complicated hardware and are more suitable for price-oriented or energy-consuming guidance.

The above description is only a detailed description of the specific embodiments of the present invention, but the features of the present invention are not intended to limit the present invention. The scope of the patent application is subject to the following patents, and the spirit of the scope of the patent application of the present invention and its similar variations are to be included in the fourth aspect of the present invention, and any one skilled in the art is in the present invention. Changes or modifications that can be easily considered in the field can be covered in the scope of the patents in this case below. 26 1344106 [Simplified description of the drawings] = a schematic diagram of the whole system of the embodiment of the invention; the second diagram is a schematic diagram of the display system of the embodiment of the invention; the third diagram shows the driving display of the embodiment of the invention (4) Figure of the present invention, a fourth embodiment of the present invention, a flowchart of the control of the switching display device of the display system;

The fifth figure is a flowchart of the control function of the display device of the display system of the embodiment of the present invention; the sixth figure is the startup of the display system of the embodiment of the present invention.

The seventh diagram is a relationship diagram of the control time corresponding to the control of the switching display device of the display system of the present invention; the eighth figure is the control time corresponding to the control of the switching display device of the display system according to the embodiment of the present invention Diagram of change; and

The figure is a relationship diagram of the second display control control corresponding time change of the activation of the touch system of the present invention. 27 1344106 [Description of main component symbols] 100 - full system 102 - processor 104 - first display controller 106 - second display controller - 108 - display device 200 - display system 202 - picture buffer • 204 - face buffer 206 - clock generator 208 - clock generator 210 - first terminal 212 - second terminal 214 - third terminal 216 - fourth terminal 218 - fifth terminal 28

Claims (1)

  1. Patent application scope · 99 years] February 3 曰 correction replacement page @ a display method with a display system with dual display controllers, wherein the ::: system includes a display device, a processor, a first display Control state - a second display controller, the driving method comprises: The first display controller receives the display data from the processor; the control of the replacement of the device is between the first display controller and the second controller 2 and the switching is followed by the vertical synchronization pulse The trailing edge executes; and = the second display controller refreshes the display device without relying on the first display controller and the processor. Please display the display with dual display controller as described in the first item of the patent scope: the first driving method 'where the control right of the display device in the (10) is one of the first steps / another new display picture gamma (four) is written Entering the first-display controller-picture buffer, the first terminal of the second display controller is set to a low-order state. The driving method of the display system with the dual display controller described in the second item, wherein the step of the second display controller is the first-lower state, including performing a display cycle (jlay1〇adcycle) And the step of executing a display loop includes the step of writing a - frame to the second display controller - a full buffer, the writing step is followed by a V-Sync pulse The trailing edge of the ).乂氏冲4 As described in the patent scope of item i, the double display (four) device, such as 29 1344106, the method of modifying the replacement page system on December 3, 1999, wherein the control of the display device is controlled ^ The step 'includes when a new frame of the main frame is written to the picture buffer of the first display controller, and sets the first terminal of one of the second display controllers to an intermediate type. The step of the intermediate high state, wherein the high-order state of the intermediate type is an intermediate high-energy write state. 5. The driving method of the display system with dual display controllers as claimed in claim 1, wherein the switching control of the display device is performed, including at least one of the first display controllers A modulation step between a video timing and at least one video timing of the 6th first display controller. 6. The driving method of a display system having a dual display controller according to claim 5, wherein the modulating step comprises at least one of simultaneously displaying the first display controller and the first display controller Video timmg re-initia immersing steps, and the image timings are re-triggered simultaneously during a blanking interval. The method of driving a system, wherein the step of controlling the control of the display device further comprises: temporarily The memory is switched from a write mode to a read mode. 8. The driving method of a display system having a dual display controller according to claim 5, wherein the step of controlling the control device further comprises connecting the image timing of the second display controller to The step of the processor, the step includes: 30 1344106. The correction of the replacement page is performed on the third page of the second display controller. The second terminal is a low-order state in a 'vertical sync pulse (v_sync Pulse). One of the previous predetermined time points; and setting the second terminal to a high-order state during a blanking interval, wherein the blanking period is a trailing edge of a vertical sync pulse (V-sync pulse) and a new start The time period between the scan lines. 9. The driving method of the display system with dual display controllers as described in claim 5, wherein the step of controlling the switching device comprises: providing at least one type of sweeping cat line a step of interrupting, wherein each type of sweeping cat line interrupt is provided with a timing 2 corresponding to a predetermined sweeping line and each type of scanning line interruption is provided by a third terminal of the second display controller, and The type of the broom line interruption is indicated by at least one fourth terminal of the second display controller. 10. The driving method of a display system having a dual display controller according to claim 9, wherein the step of providing at least one type of scanning line interruption further comprises: disabling dbling) the first display control The step of 'the step' and the disabling step is based on the type of the interrupting of the cat line: ., the display with the dual display controller as described in claim 9 of the patent application, the driving method of the system Providing at least one type of scan line interrupt step further comprises: aerating the processor to perform at least one image sequence with the re-triggering of the first display control H and at least one of the read and display controllers The image timing (vide〇Um(4) step 12 re-triggering step is performed based on the type of the sweeping (four) towel. / The driving method of the dual display controller _ 所述 system described in claim 5, wherein Step of switching control of the display device 31. The replacement page is modified on December 3, 1999, and further includes a step of driving the second display controller to the idle mode, and the step 疋 is based on the second display control Executing at least one value of the register. .13. The display having the dual display controller as described in the scope of the patent application, the driving method of the system, wherein the step of refreshing the display device further comprises - a step of initiating the second display controller in the inter-mode, and the second display controller is processed by the processor if the processor receives an input signal input by at least one of the input devices 14. The driving method of the display system with dual display controllers as described in the scope of claim 2, wherein the step of refreshing the display device further comprises the following steps: A fifth terminal is adjusted from a low-order state to a high-order state, when the processor receives an input signal input by at least one input device; and activates the second display controller in an idle mode. The method for driving a display with a dual display controller according to item 1 of the patent application of the first aspect of the invention, wherein the step of refreshing the display device includes the command ⑽manding) of the - display controller activating at least - a video output, V ί pounds was written eight picture is not the first picture of the display controller for each instrument. - The display having a dual display controller according to the first aspect of the patent, the driving method of the present invention, wherein the step of refreshing the display device comprises autonomously driving the display device by the f^ control state, although there is no new one The display screen is written to the first display controller's picture 32 1344106 _99 December 3 曰 corrected replacement page buffer. 17 display systems having dual display controllers, comprising: a processor; a first display controller that is electrically coupled to the processor and receives signals output by the processor; and a second display controller Connected to the processor, and switch control of the display device with the first display controller, and at the trailing edge of the two-way sync pulse; wherein, when the control of the display device is switched to the The second display controller=, the second display controller refreshes the display device without relying on the first display controller and the processor. 18 19 'A display system having a dual display controller as described in claim 17 (4), wherein the first display controller and the second display controller respectively include at least one video clock (vide〇timing), And the image clocks are synchronized in the control of the display device (10). The invention has the dual display controller as described in claim 17: the system: wherein the second display controller comprises: a terminal for controlling an input end of the display device, and according to at least one The new display surface is written into one of the first display controllers (10), and the fourth terminal is in a state (敝); the terminal is used to control the display timing of the second display controller. And for providing at least one type of sweeping fault (inte-〇33 1344106, December 3, 1999, the replacement page fourth terminal for indicating the interrupt of the sweeping cat line provided by the second display controller 20. A display system having a dual display controller as described in claim 4, wherein the second display controller further includes a fifth terminal for using the second display controller The inactive mode is changed to an active mode, and the processor receives at least one input signal from at least one input device. 2, as described in claim 17 of the patent having the dual display controller Not systematic The second display controller includes a buffer, and the buffer is written by the first buffer of the second display controller when the first terminal is set to a low-order state (I°WState). (write) mode cut right to read (read) mode. 23 material township (four) 17 items with the money show Qiuqiu system is not system 'the second remote display controller includes at least one temporary plug (egister) 4 At least one of the register and the first display controller may be initialized when the control of the display device is changed by the first display controller to the second display (four). A display system having a dual display controller, wherein the display system package includes a two-person display device, a first display controller, a second display controller, and a processor, the system comprising: means (meanS) Transmitting the display of the first display controller to the second display controller; = means "the means for controlling the display device to the "" page does not control H and the first Two display controllers switch between 'and the cut 34 1344106 99 December 3曰Correcting the replacement page changing action to follow the vertical sync pulse (the trailing edge of v_Syncpu (4); and a refreshing means for refreshing the display device, and the display device is driven by the second display controller without Relying on the first display controller and the processor. 24. A driving method for two display systems having dual display controllers, comprising a machine-readable storage medium comprising at least one state executable ( a processor_executable) program for controlling a processor of a display system, wherein the display system includes a display device, a display controller, a second display controller, and a processor, the method comprising: receiving display data ' wherein the display data is received by the first display controller from the processor; switching control of the display device between the first display controller and the second display controller, and the switching is followed by Performing a trailing edge of a vertical sync pulse (V-Sync pulse); and refreshing the display device 'where the display device is driven by the second display controller 'Without dependence of the first display controller and the processor. 35
TW96110222A 2006-03-23 2007-03-23 Artifact-free transitions between dual display controllers TWI344106B (en)

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