JP4868313B2 - Display sub-system power consumption reduction method - Google Patents

Display sub-system power consumption reduction method Download PDF

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JP4868313B2
JP4868313B2 JP2007077119A JP2007077119A JP4868313B2 JP 4868313 B2 JP4868313 B2 JP 4868313B2 JP 2007077119 A JP2007077119 A JP 2007077119A JP 2007077119 A JP2007077119 A JP 2007077119A JP 4868313 B2 JP4868313 B2 JP 4868313B2
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display
display controller
refresh data
bit
control device
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JP2007293296A (en
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マイケル ボブ ジュニア. ヴィクター
ゲッティズ ジェイムズ
ジェイ. フォスター マーク
ルー ジェプスン メアリー
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ワン ラップトップ パー チャイルド アソシエイション インク.
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/14Interconnection, or transfer of information or other signals between, memories, peripherals or central processing units
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/15Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon peripherals
    • Y02D10/151Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon peripherals the peripheral being a bus

Description

  The present invention relates generally to the field of display devices in computer-related units. More particularly, the present invention relates to a method and system for refreshing a display device of a computer related unit.

  The computer-related unit presents information to the user using a display device. The display device is an interface between the computer and the user. Examples of display devices include, but are not limited to, cathode ray tube (CRT) monitors, liquid crystal display (LCD) monitors, plasma screens, and organic light emitting diodes (OLEDs). The display controller in the computer related unit obtains an input signal from the processor. The display control device processes the input signal and provides refresh data for refreshing the display device.

  The refresh data is stored in the refresh memory of the display control device. In some systems, the display controller refresh memory is integrated with the processor RAM. This is known as a unified memory configuration (UMA). In some other systems, the display controller has its own RAM controller for refresh memory, separate from the processor RAM. The refresh data in the refresh memory includes a plurality of color values for each pixel in each line of the display device. The total amount of memory required to store the refresh data depends on the resolution of the display device. This resolution can be defined as the physical number of a matrix of pixels that form the display. In addition, the total amount of memory required to refresh the display device depends on the color depth. The color depth consists of the number of bits used to represent the color of a single pixel. In an integrated memory configuration, the display device obtains refresh data directly from the processor refresh memory. The processor drives a significant amount of memory to enable the basic input / output system (BIOS), operating system (OS), and various other application programs. The amount of memory required for multiple operations of the processor is typically greater than the memory required by the display controller and refreshes the display device in the integrated memory configuration.

  It can be said that the power required to drive the refresh memory is P = CV ^ 2F. Here, C indicates the capacity of the memory device, V indicates the voltage, and F indicates the frequency of the memory clock. The power consumed to refresh the memory is directly proportional to the memory size. Furthermore, additional power is required to run the memory allocation unit used to divide the processor's main storage resources between the processor and the display. As a result, power consumption increases while multiple display devices in an integrated memory configuration are refreshed.

  Moreover, in many computer-related units, multiple display controllers are integrated with the processor. Such computer-related units do not power off the processor when there is no user input and the display device no longer needs to be refreshed. This is caused by common electronics associated with the dual-use memory system. As a result, power consumption is further increased when multiple display devices are refreshed, even during periods when the processor is non-functional.

  In view of the above data, there is a need for a method and system that refreshes display devices and avoids the use of large memory. Such a method and system should also be able to refresh the display without requiring power to run the high speed memory allocation unit. Furthermore, such a method and system should power off the processor when the display device does not need to be refreshed. In addition, there is a need for a method and system that autonomously powers down the display device after an extended non-functional period and restarts the display device upon resumption of user activity, independent of the processor.

  It is an object of the present invention to provide a method and system for a display system that drives a display device.

  Another object of the present invention is to provide a method and system for driving a display device without the intervention of a processor.

  It is another object of the present invention to provide a method and system for saving power consumption while a display device is refreshed.

  Another object of the present invention is to provide a method for synchronizing the first and second display control devices.

  Yet another object of the present invention is to eliminate the need for expensive and dedicated hardware, thereby making the present invention ideal for use in multiple applications where cost and power are considered.

  To achieve the above objectives, as described broadly herein, various embodiments of the present invention provide a method and system for a display system for driving a display device. provide. The display system includes a processor, a first display control device, a second display control device, and a display device. The first display controller receives display data sent by the processor and drives the display device when the processor sends a new multiple display frame. When the same multiple display frames are sent sequentially by the processor, the display control is switched to a second display controller optimized for low power operation.

  This application claims the priority of US Provisional Patent Application No. 60/785066 entitled “Self-Refresh Display Control Device for Portable Computers” filed on March 23, 2006, which is , Is used here as it is.

  This application also includes US Provisional Patent Application No. US60 / 785065 entitled “Artifact-Free Transition Between Dual Display Controllers” filed Mar. 23, 2006 by Mark J. Foster and Mark The co-pending application of US provisional patent application number US 60/906122, filed March 9, 2007 by J. Foster and entitled “Artifact-free transition between dual display controllers” was incorporated. The

  Various embodiments of the present invention will now be described with reference to the accompanying drawings, which are provided to illustrate the same elements without limiting the invention and like designations.

  Embodiments of the present invention provide a method, system and computer program product for driving a display device in a display subsystem. The display subsystem is in a computer-related unit and includes a processor, a first display controller, a second display controller, a frame buffer for the second display controller, and a display device. The display device can be driven by either the first display control device or the second display control device. The first display controller drives the display device when the processor generates new refresh data. In addition, the first display control device provides display data to the second display control device. The second display control device can refresh the display device by reflecting the refresh data, or can operate the refresh data and then refresh the display device. When the processor generates the same refresh data for a predetermined period of time, the display device control is switched from the first display control device to the second display control device. Subsequently, the frame to be displayed is recorded in the frame buffer of the second display controller.

  FIG. 1 is a schematic diagram of a configuration capable of implementing various embodiments of the present invention. The configuration includes a display subsystem 100, which may be in a computer related unit. The computer-related unit can be, for example, a laptop computer, a palmtop computer, a desktop computer, a computer, a mobile phone or a personal digital assistant (PDA). The display subsystem 100 includes a processor 102, a first display control device 104, a second display control device 106, and a display device 108. Examples of display device 108 include, but are not limited to, a liquid crystal display (LCD) screen, a cathode ray tube (CRT) monitor, and a plasma screen. The processor 102 is a normal central processing unit (CPU) in a computer related unit. The first display controller 104 and the second display controller 106 can be a conventional video graphics array (VGA) or other type of controller or application specific integrated controller (ASIC). The processor 102 controls the first display control device 104 and the second display control device 106.

  FIG. 2 is a schematic diagram of various elements in the second display control device 106 according to an embodiment of the present invention. The second display control device 106 can use various interfaces. The first interface is the input port 202, which is designed to receive refresh data from the first display controller 104.

  In accordance with one embodiment of the present invention, the input port 202 is designed to be directly connected to a TTL compatible TFT display controller. This input-only port receives video data from a conventional VGA control device such as a video display output of AMD / GX2-533. This interface receives 19-bit RGB data in 6-7-6 format with 6-bit red, 7-bit green and 6-bit blue data per pixel.

  The second interface is an output port 204, which is directly connected to a multi-integrated circuit (IC) of a compatible thin-film transistor (TFT) panel matrix driver, which supports LCD display output on a suitable multi-TFT display. To do. The third interface is a synchronous dynamic read / write storage (SDRAM) interface port 220, which communicates with a low power synchronous dynamic RAM that stores one complete refresh data frame. The second display control device 106 autonomously refreshes the display device 108 by obtaining refresh data from the frame buffer 206. A frame buffer 206 is associated with the second display controller 106 and is used to store refresh data.

In accordance with one embodiment of the present invention, frame buffer 206 is a 512K × 16 SDRAM frame buffer containing 1,048,576 bytes, but as an example, one laptop per child (OLPC) A 1200 × 900 TFT includes 1,080,000 pixels. Therefore, the second display controller 106 has to fill the pixels, and each display pixel must be stored in 1 byte or less of the memory. The panel's multiple drivers and double edge transistor-transistor logic (DETTL) interface support 6 bits of information / pixel. Therefore, in order to improve memory efficiency, each group of 4 pixels (4 pixels × 6 bits / pixel = 24 bits) is stored as 3 bytes (3 bytes × 8 bits / byte = 24 bits) of the SDRAM frame buffer. Is done. Note that the SDRAM frame buffer is actually 16 bits wide. As a result, 8 pixels (8 pixels × 6 bits / pixel = 48 bits) are packed into 3 words (3 words × 16 bits / word = 48 bits) of SDRAM in 8 bits (8 pixels × 6 bits / pixel = 48 bits). Is to be. With this memory mechanism, the frame buffer occupies 405,000 words of 512K × 16 SDRAM, leaving 119,288 words unused.

  In accordance with another embodiment of the present invention, the frame buffer 206 is included in the second display controller 106.

  In accordance with yet another embodiment of the present invention, frame buffer 206 is external to the frame buffer.

The fourth interface is a clock 208. In accordance with one embodiment of the present invention, clock 208 is attached directly to a 14.31818 MHz lens supported by an on-chip oscillator and provides an independent pixel clock for display refresh regardless of the state of the display input port. Clock 208 also provides interface timing for attached frame buffer 206. The fifth interface includes one or more input / output pin interfaces that manage significant switching of timing between the first display controller 104 and the second display controller 106. The first pin 210 determines which of the two display control devices refreshes the display device 108. The first display control device 104 refreshes the display device 108 when the first pin 210 is in the functional state, whereas the second display control device 106 displays the display device when the first pin 210 is in the non-functional state. 108 is refreshed. Further, the second pin 212 is set to the functional state if the second display control device 106 is in the non-functional state. The third pin 214 indicates the state of the second display controller 106 by generating one or more interrupts. The fourth pin 216 enables communication between the processor 102 and the second display controller 106 .

  In accordance with one embodiment of the present invention, the second display controller 106 functions the second display controller 106 from a non-function when the processor 102 receives one or more inputs from one or more input devices. It includes a fifth pin 218 for driving to the state. These one or more input devices are connected to the processor 102.

  The second display control device 106 includes a processing module 220 and a determination module 222. The processing module 220 provides support for color swizzling and the display device 108 can be a conventional 24-bit panel. Color swizzling is a process for converting the data content of the first display controller 106 into a reduced bit format for better and more effective display. The implementation items of the color swizzling function will be described in conjunction with the detailed description of FIG. In addition, the processing module 220 allows the use of optional anti-aliasing capabilities and improves text display. The processing module 220 provides black and white mode support for automatic pixel address conversion from color to gray scale. The black and white display harmonizes with the human brightness feeling of the refresh data in the first display control device. This is described in detail in conjunction with FIGS. Decision module 222 assists processing module 220 in anti-aliasing.

  The second display control device 106 has a performance that is transparent to incoming refresh data in the passing mode. The pass mode can be activated by changing one or more bit values in the registers of the second display controller 106. It emulates a single LCD timing controller chip and automatic fly-by mode, prevents unnecessary multiple writes to the attached frame buffer 206 and minimizes power consumption. In addition, the second display controller 106 includes support for a conventional red green blue (RGB) DETTL panel for effective debugging and self-test performance for production line testing. Details relating to self-test performance for production line testing are described in detail in conjunction with FIGS.

  In accordance with one embodiment of the present invention, a single refresh data frame in the first display controller 104 is converted to a reduced bit format. This is performed immediately before instructing the second display controller 106 to refresh the display device 108. As a result, the efficiency of display processing is increased.

  FIG. 3 is a flow diagram of a method for conserving power consumption while the display device 108 is refreshed in a computer-related unit, according to one embodiment of the invention. At step 302, the first display controller 104 is switched from a functional to a non-functional state if no new refresh data is generated by the processor 102. In step 304, the second display controller 106 is instructed to refresh the display device 108 separately from the first display controller 104 and the processor 102. The second display control device 106 consumes substantially less power than the first display control device 104.

  4A and 4B are a flow diagram of a method for switching control of the display device 108 from the first display control device 104 to the second display control device 106 according to one embodiment of the invention. In step 402, the first display controller 104 refreshes the display device 108 when the processor 102 continuously generates new refresh data. In step 404, it is ascertained whether new refresh data has been generated by the processor. If the processor 102 is generating new refresh data, the first display controller 104 continues to refresh the display device 108 at step 402. However, if no new refresh data is generated by the processor 102, the first pin 210 of the second display controller 106 is switched to a non-functional state at step 406. Subsequently, the refresh data in the first display controller 104 is converted into a reduced bit format in step 408. The reduced bit format is visually indistinguishable from the refresh data in the first display controller 104. The step of converting the refresh data to reduced bit format includes one or more modifications made to the refresh data, such as changing the frequency of multiple display outputs, performing color swizzling, or color anti-aliasing functions. Including. At step 410, the reduced bit format is stored in the frame buffer 206. At step 412, the second display controller 106 is instructed to refresh the display device 108.

Thereafter, the second display controller 106 refreshes the display device 108 by obtaining refresh data from the frame buffer 206 . In step 414, the first display control device 104 is switched from the functional state to the non-functional state. At step 416, processor 102 is switched to a non-functional state. As a result, the processor 102 is rendered non-functional after an extended non-functional period. At step 418, display device 108 is powered off when the same refresh data is displayed for an extended period of time.

In accordance with one embodiment of the present invention, the second display controller 106 can modify the refresh data and refresh the display device 108 without storing the refresh data in the frame buffer 206 .

  In accordance with an embodiment of the present invention, the second display control device 106 can autonomously perform the role of refreshing the display device 108 in step 412.

  In accordance with an embodiment of the present invention, the second display controller 106 can be switched to a non-functional state if the display device 108 is refreshed a predetermined number of times with the same refresh data. The number of times, after which the second display controller 106 can be switched to a non-functional state, is stored in one or more registers of the second display controller 106.

FIG. 5 is a flowchart of a method for switching control of a display device from the second display control device 106 to the first display control device 104 according to an embodiment of the present invention. In step 502, the second display control device 106 drives the display device 108. At step 504, it is determined whether the processor 102 is generating new refresh data. If no new refresh data is generated by the processor 102, the second display controller 106 refreshes the display device 108. If new refresh data has been generated by the processor 102, the second display controller 106 is notified at step 506 that new refresh data has been generated. In step 508 , the first pin 210 is set to the functional state. The function state of the first pin 210 indicates the recording state of the intermediate function of the first display control device 104. In step 510, the first display controller 106 is switched from a function to a non-function state. In step 512, the first display controller 106 is instructed to refresh the display device 108. Thereafter, the first display control device 104 transmits the refresh data to the second display control device 106. The second display controller 106 can convert the refresh data to a reduced bit format, which is then used to refresh the display device 108.

  FIG. 6 is a flowchart of a method for activating the second display controller 106 from a non-functional state according to an embodiment of the present invention. In step 602, it is confirmed whether the second display control device 106 is in a non-functional state. In step 604, it is determined whether an input signal has been received by the second display controller 106 from one or more input devices connected to the display subsystem 100.

  In accordance with one embodiment of the present invention, input signals are received by the second display controller 106 from one or more input devices without the intervention of the processor 102.

  In accordance with another embodiment of the present invention, input signals are received from one or more input devices by the second display controller 106 via the processor 102. Examples of one or more input devices include, but are not limited to, a keyboard, touchpad, wireless event, cursor pad, or mouse.

  In step 606, the switching of the second display control device 106 is switched from the non-functional state to the functional state. Further, the fifth pin 218 is set from a non-functional state to a functional state each time an input signal is received from one or more input devices. If the fifth pin 218 is set to the functional status when the second display control device 106 is in the functional state, the second display control device 106 can rotate the second display control device 106 to the non-functional state. Set one or more registers to store numeric values.

  If the processor 102 does not generate new refresh data, the second display controller 106 begins to autonomously refresh the display device 108 with the refresh data in the frame buffer 204. When the processor 102 updates the frame buffer 202 with new refresh data, the second display controller 106 erases the display by turning on the display device 108 and resetting one or more display blanking registers. To do. The third pin 214 generates an interrupt that instructs the second display controller 106 to update the refresh data. In step 608, display device 108 is powered on if it was previously powered off.

  FIG. 7 is a flowchart of a method for converting data content of a first display controller to a reduced bit format according to an embodiment of the present invention. When the second display controller 106 is used in the transmission mode, the backlight is turned on. Each pixel in the reduced bit format represents a single color value-red, blue or green. The color value-swizzling enable bit, when set to 1, enables the second display controller 106 to automatically select the appropriate color field from the corresponding pixel of the reduced bit format input refresh data. . After delineating the physical panel structure in step 702 above, the second display controller 106 processes the red input field of the first pixel of the first line of refresh data to produce the first line in reduced bit form. The first pixel is formed. In step 704, the second display controller 106 processes the green input field of the second pixel of the first line of refresh data to form the second pixel of the first line in the reduced bit format.

  In step 706, the second display controller 106 processes the blue input field of the third pixel of the first line of refresh data to form the third pixel of the first line in reduced bit format. At step 708, the process is repeated for each pixel in the line. This regular process is repeated throughout the line. At step 710, the process is repeated for each line of refresh data. However, for each subsequent line in the refresh data, the second display controller 106 selects the color of the pixel so that it is offset by one color component in the previous line in reduced bit format. Accordingly, the first pixel of the second line of reduced bit format is green, the second pixel of the second line of reduced bit format is blue, and the third pixel of the second line of reduced bit format is red. . This regular process is repeated over the second line in reduced bit form. The first pixel of the third line of the reduced bit format is blue, the second pixel of the third line of the reduced bit format is red, and the third pixel of the third line of the reduced bit format is green. This regular process is repeated over the second line. The regular processing for the first three lines described above is then repeated for groups of three lines throughout the reduced bit format.

  According to one embodiment of the invention, each pixel in reduced bit format has a single 6-bit value. In accordance with another embodiment of the present invention, the red and blue pixels are written with trailing zeros so that each pixel has a 6-bit left justified value.

FIG. 8 is a schematic diagram of a method for color swizzling according to one embodiment of the present invention. The figure illustrates color swizzling using an example. The color swizzling is a process for converting the data content of the first display control device 106 into a reduced bit format. The multiple red bits R 11 in the first pixel of line 1 of the 16-bit input signal are selected as the first pixel R 11 ′ in the first line of reduced bits. The green multiple bit G 15 in the second pixel of line 1 of the 16-bit input signal is selected as the second pixel G 15 ′ in the first line of reduced bits. The third pixel blue bit B 19 in line 1 of the 16-bit input signal is selected as the third pixel B 19 ′ in the first line of reduced bits. This regular process is repeated over line 1. Each subsequent line is an offset of the previous line by one color component. The first pixel green bit G 22 in line 2 of the 16-bit input signal is selected as the first pixel G 22 ′ in line 2 of the reduced bit format. The multiple blue bits B 26 of the second pixel in line 2 of the 16-bit input signal are selected as the second pixels B 26 ′ in line 2 of the reduced bit format. The red multi-bit R 27 of the third pixel in line 2 of the 16-bit input signal is selected as the third pixel R 27 ′ in line 2 of the reduced bit format. This regular process is repeated over line 2. The first plurality of blue bits B 33 of the first pixel in line 3 of the 16-bit input signal is selected as the first pixel B 33 ′ in line 3 of the reduced bit format. The red multi-bit R 34 of the second pixel in line 3 of the 16-bit input signal is selected as the second pixel R 34 ′ in line 3 of the reduced bit format. The green multi-bit G 38 of the third pixel in line 3 of the 16-bit input signal is selected as the third pixel G 38 ′ in line 3 of the reduced bit. This regular process is repeated over line 3.

When the color swizzling mode is activated, the color anti-aliasing mode bit can be set to one. Color anti-aliasing mode is said to work when both bits are set. In this mode, the color swizzling process proceeds as described above, but the resulting output is filtered to prevent color aliasing. This is especially important when copying multiple text fonts. The filtering process works by combining the current color value of the pixel with, for example, a matching color field of multiple pixels above, below, left, and right of the current pixel. For example, considering B 26 ′ in FIG. 8, the top, bottom, left, and right are the second pixel in line 1, the second pixel in line 3, the first pixel in line 2, and the third pixel in line 2, respectively. The blue bits of these pixels are considered . This works by adding multiple values of the matching color field from four neighboring pixels that are the upper, lower, left and right pixels of the current pixel. After this, the right 3 bits of the result are shifted and added to the current pixel value shifted right by 1 bit. The resulting output truncated to 6 bits is equivalent to the filtered color swizzling process when color anti-aliasing was not activated. This 6-bit value is stored in the frame buffer 206 of the second display controller 106 for the current pixel.

  In accordance with another embodiment of the present invention, the input signal includes 19 bits in 6-7-6 format, where 6 bits are the red component of the input refresh data, 7 bits are the green component, and 6 bits are Indicates the blue component.

As long as the color swizzling and color anti-aliasing bits are 0, the second display controller 106 can switch to monochrome luminance mode by setting the color anti-aliasing bit to 1. In this mode, a 16-bit input color value in the 5-6-5 RGB format is converted to a 6-bit pixel display value via the following simple integer approximation to the standard NTSC luminance conversion equation, and pixel value = (R>> 2) + (R >> 4) + (G >> 1) + (G >> 4) + (B >> 3) .

  Note that when the color swizzling enable bit is zero, the second display controller 106 simply changes the green component of the refresh data in the first display controller 104 to another form. Another form is materially and visually equal to the green content of the refresh data in the first display controller 104. As a result, the second display control device 106 outputs the green color field value of the input pixel value of each pixel unless the monochrome luminance operation bit is set to 1.

  To ensure minimum power consumption, the second display controller 106 allows the use of a process that reduces the frequency of the panel interface dot clock. This field value specifies a division of the crystal oscillator of 1 or less, resulting in the frequency of the system dot clock. All video timing is derived from the dot clock. If this field contains 0, the dot clock is equal to the frequency of clock 208, whereas a value of 7 results in a dot clock of 1/8 of the lens frequency. Using a 54.06 MHz lens with multiple parameters of nominal program video timing that yields a 50 Hz panel refresh rate, and only changing the dot clock division, 50.00 Hz as the actual panel refresh rate, This results in 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz, 7.14 Hz or 6.25 Hz.

  FIG. 9 is a timeline diagram of method steps for activating the second display controller 106 from a non-functional state according to one embodiment of the present invention. The figure shows the state of the various elements of the display system 200 and the method steps performed by the elements in time order, with time being shown on the x axis and the elements of the system being shown on the y axis. The second display control device 106 can receive several inputs from a plurality of input devices. When receiving multiple inputs, the fifth pin 218 activates the second display controller 106. The third pin 214 generates an interrupt output after the second display controller 106 is started. Next, the second display control device 106 blanks the display device 108. Subsequently, the frame buffer 206 performs a frame loading cycle of display load. The second display controller 106 is responsible for controlling the display device 108 as soon as the frame buffer 206 completes the frame loading cycle.

  In view of the above description, industrial-based implementation details of the present invention (second display controller) according to one embodiment are included herein. These details include various hardware implementation details including construction level details for various processors, ICs, pins and registers. The description will be understood by one of ordinary skill in the art and will assist in practicing the invention without undue experimentation.

Second Display Controller 106 Direct I / O Pin Interface Some interface operations between the second display controller 106 and the processor 104 are particularly time critical. In particular, switching back and forth between the first controller 104 that manages display refresh and the second display controller 106 that manages display refresh must be carefully timed to prevent display artifacts. The second display controller 106 uses high-speed direct I / O pin connections for the CS5536 companion I / O device that enables the use of these functions. The CS5536 is a standard processor for I / O operations designed by Advanced Micro Devices. Details about the interconnection of the system are included and each pin is described.

  The DCONIRQ / pin is a negative logic scan line interrupt output from the chip of the second display controller 106, which can be programmed to be inserted on any particular scan line of the video output. The primary purpose of this pin is to automatically alert the processor 102 at a certain time before the start of the next displayed frame. By receiving an interrupt with a known timing associated with the display operation, the processor 102 is able to refresh the first display controller 104—control refresh or control the second display controller 106 without a “busy wait” or polling loop. The current display state for refresh can be reconstructed. See DCONLOAD below for further details.

  DCONBLANK is used to assist at times when it is desirable to start the display change in the display state asynchronously. If the second display controller 106 intends to pole, it will drive the DCONBLANK output under two circumstances. Under the first situation, the DCONBLANK output is driven low at the beginning of the first output scan line after multiple scan lines of active vertical resolution output and remains low until the falling edge (end) of the output Vsync timing period. Yes, it is driven high again at that time. Under the second condition, the DCONBLANK output remains high whenever the display of the output of the second display controller 106 is inactive.

  DCONSTAT is used to indicate whether the first display controller 104 or the second display controller 106 is managing the current display refresh. Since the display control for switching the second display controller 106 is synchronized with the display process, the status pin allows the processor 102 to accurately confirm when the display switch of the second display controller 106 has occurred.

  DCONLOAD is used to initiate a frame load cycle for display load. This signal is used to determine whether the multiple video timing output of the second display controller 106 follows the multiple video input, or whether the multiple timing registers within the second display controller 106 are driving the multiple video outputs. To decide. As described above in the description of the display mode register of the second display controller 106, in either case, the actual multiple data output made to the panel is usually corrected by the chip of the second display controller 106. Note that it is done.

DRAM configuration of the display controller ASIC Pinout-2M (1M × 16) of the second display controller 106 Geode (TM) display interface pin group Geode (TM) pixel clock GFDOTCLK 1
Geode (TM) red data GFRDAT0-4 5
Geode (TM) Green Data GFGDAT0-5 6
Geode (TM) Blue Data GFBDAT0-4 5
Geode (TM) Vsync GFVSYNC 1
Geode (TM) Hsync GFHSYNC 1
Geode (TM) display operation GFDISP_EN 1
Geode (TM) FP_LDE GFP_LDE 1
1M × 16 DRAM interface pin group FBRAM data FBD0-15 16
FBRAM address FBA0-11 12
FB column address strobe FBCAS / 1
FB row address strobe FBRAS / 1
FBRAM chip select FBCS / 1
FBRAM writing operation FBWE / 1
FBRAM clock FBCLK 1
FBRAM clock operation FBCLKE 1
Self-refreshing crystalline lens of the second display controller 106 Display crystalline lens in DCONXI 1
Display lens out DCONXO 1
System interface pin group System reset RESET 1
Interrupt output DCONIRQ / 1 of the second display controller 106
Display load command request DCONLOAD 1 of the second display controller 106
Second display controller 106 vs. Geode (TM) / Display function status DCONSTAT 1
Blanking state DCONBLNK 1 of the second display controller 106
Register I / O • SMB clock DCONSMBCLK 1 of the second display controller 106
Register I / O / SMB data DCONSMBDATA 1 of the second display controller 106
PPTTL / Panel Interface Pin Group Panel Pixel Data 1D1O0-2 3
Panel pixel data 2D2O0-2 3
SCLK SCLK1
DCLK DCLK1
GOE GOE1
GCK GCK1
GSP GSP1
DINT DINT1
SDRESET SDRESET 1
DBC DBC1
INV INV1
PWST PWST1
POL1 POL11
POL2 POL21
Self-test / boundary scan BIST0-1 2
General user I / O 84

Register definition:
Register 0: Second Display Controller 106 ID + Revision This 16-bit register is a read-only register and returns the ASIC identifier and revision number of the second display controller 106. The first pass of this silicon returns a hexadecimal value of 'DC01'H, and the next revision returns'DC02'H, etc.

Register 1: Display mode of second display controller 106 Bit 0: Pass not activated This bit controls which second display controller 106 performs any operation on the refresh data. At start-up, this bit is automatically initialized to 0 by the second display controller 106, which causes the multiple video output to directly follow the multiple video input, and the second display controller 106 is in pass mode. Said to be moving. In this mode, the second display control device 106 operates alone as a chip of an old-fashioned TFT timing control device (TCON), and in this case, a plurality of video outputs must obtain a display panel compatible DETTL output signal. Only converted when. For power reduction purposes, the SDRAM interface port 220 must be completely disabled during the pass mode, even if no SDRAM clock signal is generated. In the pass mode, all other registers and multiple control bits of the second display controller 106 are ignored except for the self-test activation bit that is handled preferentially over the pass mode.

  Writing a 1 to the pass inactive bit allows the normal second display controller 106 to function, such as SDRAM interface port 220, internal multiple video timing registers, multiple mode configuration bits, etc. Accompanying startup.

Bit 1: Sleep mode of the second display controller 106 An important factor related to the power efficiency of the second display controller 106 is its ability to enter a low power state, in which the display device 108 is fully Turned off and the frame buffer 206 is set to self-refresh mode. The self-refresh mode is understood as the sleep mode of the second display controller 106. Under normal circumstances, the second display controller 106 may, in particular, have the automatic sleep mode bit set and a multiple video output frame of display timeout value occurred without causing a display load cycle or input. If a signal is received from one or more input devices, the sleep mode is automatically entered as a result of an extended non-function of the system. The second display controller 106 then sets this bit and automatically enters sleep mode.

  Alternatively, it may be necessary for the processor 102 to begin switching the second display controller 106 to sleep mode. In particular, the processor 102 manually enters sleep mode when selecting “system off” with the power switch, when the laptop lid switch is closed, or when a very low battery level is detected. . To enter sleep mode, this bit should be written with '1'.

  While the second display controller 106 is in sleep mode, the frame buffer 206 is held in a low power self-refresh state so that the second display controller 106 processes incoming multiple display load cycles. I can't. However, the load pin of the second display controller 106 is not ignored. If the processor 102 makes a request for a display load cycle while the second display controller 106 is in sleep mode, an internal state known as LOAD_MISSED of the second display controller 106 is set. This state is used to inform the second display controller 106 that the data in the frame buffer 206 is no longer consistent with the final refresh data generated by the processor 102. When the second display controller 106 exits sleep mode after missing the second display controller 106 load, it automatically blanks the display device 108 and a second display control for one line of refresh data. By driving the IRQ active of the device 106, the LOAD_MISSED interrupt of the second display control device 106 is generated. This causes the final refresh data generated by the processor 102 to be written to the processor 102 and then clears the video blanking pin to cause the display device 108 to draw the latest information.

The process of exiting the sleep mode can be executed either manually or automatically. Under normal circumstances, this bit is automatically cleared on the occurrence of ECPWRRQST. ECPWRRQST appears when the second display controller 106 receives an input signal from one or more input devices. In other words, by hitting a key, separately recover the video display processor 102, whereby on the keyboard keys, "immediately" when the cursor buttons or touch pads are functional display device 108 To do. Alternatively, processor 102 can exit the sleep mode if necessary and resume the process of refreshing display device 108 by clearing this bit to zero.

Bit 2: Automatic sleep mode When this bit is set to 1, the second display controller 106 automatically stops the display process after a plurality of video frames having a display timeout value are output without the system function. . When either the LOAD of the second display controller 106 is high or an incoming ECPWRRQST occurs, the internal display timeout register is automatically reset to the value of the display timeout value register. If a display timeout occurs, the second display controller 106 automatically enters the sleep mode by setting the sleep mode bit of the second display controller 106 to 1. When the automatic sleep mode bit is 0, the second display controller 106 continues to refresh the display device 108 indefinitely. If a display load cycle or ECPWRRQST occurs, the sleep mode can be entered by simply writing to the sleep mode bit of the second display controller 106.

Bit 2: Backlight Activation Backlight activation is used to determine whether the display 108 backlight should be turned on while the display is activated. This bit is set to 1 to turn on the backlight whenever the second display controller 106 is not in the sleep mode of the second display controller 106. Note that setting this bit automatically activates and deactivates the backlight, so for screen savers it is necessary to turn the backlight activation on and off. If this bit remains clear, the backlight remains inactive regardless of whether the second display controller 106 is in the sleep mode of the second display controller 106 or not. When the backlight is activated, the BACKLIGHT pin is driven positive logic and the DBC pin is driven with a PWM wave with a duty cycle that matches the value of the backlight brightness register.

Bit 4: Video Blanking Video blanking is used to display the screen “black” without affecting the contents of the frame buffer 206 of the second display controller 106 or the power state of the display device 108. This feature is mainly related to whether the display device 108 displays refresh data, or the display device 108 should be masked off until the next display load cycle, so that the second display controller 106 should exit sleep mode. Used to determine This is used in particular by the second display controller 106. The second display controller 106 cannot record incoming display load cycles while in the sleep mode, so if the LOAD of the second display controller 106 is high while sleeping, the video blanking is automatically performed.・ Set the bit. This ensures that old refresh data is not displayed during wakeup. If this bit is written as “1”, the display device 108 displays “black”. If written as '0', the current contents of the frame buffer 206 are displayed on the display device 108.

Bit 5: Color Swizzling Operation According to one embodiment of the present invention, the selected display device 108 is a conventional mixed monochrome / color panel that does not utilize multiple RGB sub-pixels. Instead, each pixel contains only a single “subpixel value”. When used as a reflector, i.e. when the backlight is off, these pixel values represent a gray scale. The resulting image is in black and white display. When used in transmissive mode, i.e., when the backlight is on, each pixel exhibits a single color value from the set of red, green and blue.

  The first pixel of the first line of refresh data is red, the second pixel of this line is green, and the third pixel is blue. This regular arrangement is repeated across the line. Note, however, that each subsequent line is offset by one color component from the previous line. Thus, the first pixel of the second line is green, its second pixel is blue, and its third pixel is red. This regular arrangement is repeated over the second line. The first pixel in the third line is blue, its second pixel is red, and its third pixel is green. This regular arrangement is repeated over the third line. The above regular arrangement for the first three lines is then repeated in groups of three lines across the display panel.

  This regular arrangement of colors helps to eliminate display artifacts, but also complicates the system software. When the color swizzling enable bit is set, it enables the second display controller 106 to automatically select the appropriate color field from the refresh data at inputs 6-7-6. After the outline of the physical panel structure is drawn as described above, the second display controller 106 selects the red input field for the first pixel of the first line, the green input field, etc. for the next pixel of this line. . The net effect of the color swizzling activation function is that each output pixel written to the frame buffer 206 has a single 6-bit value, so that the second display controller 106 is one third of the input refresh data. 2 is to automatically discard.

  When the color swizzling activation bit is 0, the second display controller 106 outputs the most significant 6 bits of the green color field of each input pixel until the black and white luminance activation bit is set to 1. Please note that. Color swizzling alone does not require the use of multiple scan line ring buffers of the second display controller 106 as described below. Only the color anti-aliasing mode is active when both the color swizzling and color anti-aliasing mode bits are set to 1, requiring the use of multiple ring buffers on the chip.

  Whenever the color swizzling mode is functioning, the COLMODE output pin of the second display controller 106 is driven high. This pin allows the display device 108 to switch its internal panel bias to optimize display quality in either color or monochrome mode.

Bit 6: Color Antialiasing Operation When the color swizzling mode is activated, the color antialiasing mode bit can also be set to 1. When both bits are set, the color anti-aliasing mode is said to be working. In this mode, the color swizzling process proceeds as described above, but the resulting output is filtered to prevent color aliasing. This filtering process converts the current pixel color value at pixel coordinates (V, H) to the upper (V-1, H), lower (V + 1, H), left (V, H-1) of the current pixel. And combined with multiple matching color fields from multiple pixels on the right (V, H + 1). The procedure sums the matching color field values from these four neighboring pixels, shifts the result 3 bits to the right, and adds the current pixel value right shifted by 1 bit to it. Work by. The resulting output truncated to 6 bits corresponds to the filtered value of the color swizzling process when color anti-aliasing is not activated, and this 6-bit value is stored in the current pixel of frame buffer 206.

  It is particularly important to emphasize that color anti-aliasing works with 19-bit color values, rather than the 6-bit color values that are the output of the color swizzling process when color anti-aliasing is not activated. The above calculations are performed for a plurality of color fields that are particularly suitable for the current pixel. In other words, if the current pixel has a red filter, the calculation sums and combines multiple red fields of neighboring pixels with the red field of the current pixel. The next pixel to the right performs the same function for multiple green fields, such as the current and neighboring pixels.

  In order to obtain a plurality of color fields suitable for color anti-aliasing, two significances are immediately apparent. First, it is necessary to use a two-scan line length ring buffer to perform this process. Second, each element's ring buffer must hold 19-bit color data in the 6-7-6 output color format rather than in the 6-bit output format.

  Implementation Details: The multiple input line buffers are typically 2 × 1200 19-bit words. However, once the multiple buffers are executed, it is essential that they are updated on a pixel-by-pixel basis, similar to the ring buffer. Otherwise, three full scan lines are required to perform the color anti-aliasing function.

  Implementation Note: The above simplified calculations are used for ease of understanding and do not represent actual implementation. For example, the use of the right shift operator is intended to specify the alignment of multiple bits into various color components and does not imply that some bits are “lost” during anti-aliasing. For visual display quality, full 10-bit accuracy is maintained until a complete result is output. Only the final output of anti-aliasing can be truncated to 6 bits by discarding 4 LSBs. Implementations that discard the least significant bits during anti-aliasing operations before output truncation are unacceptable.

Bit 7: Monochrome Luminance Operation As long as the color swizzling and color anti-aliasing bits are 0, the second display controller 106 can be put into the monochromatic luminance mode by writing this bit to 1. In this mode, the 19-bit input color value is converted back to a 6-bit pixel display value via the following simple integer approximation to the standard NTSC luminance conversion equation, again in 6-7-6 RGB format: = (R >> 2) + (R >> 4) + (G >> 1) + (G >> 4) + (B >> 3).

  Note that unlike the color anti-aliasing mode, the black and white luminance function works alone for multiple color fields of the current pixel. As a result, the two-line ring buffer on the chip is not used in this mode.

  Implementation note: The above simplified calculation is used to facilitate understanding and does not represent an actual implementation.

Bit 8: Scan Line Interrupt Operation Setting this bit to 1 allows the output of the scan line interrupt of the second display controller 106 to be generated between video scan lines programmed into the scan line interrupt value register. To do. This interrupt becomes functional at the beginning of the programmed scan line and is in a functional state for one scan line period of each frame. This sequence continues as long as the scan line interrupt enable bit is one.

Bits 9-11: Dot clock division To allow the use of minimal power output, the second display controller 106 can use the ability to reduce the frequency of the dot clock of the panel interface. The value of this field specifies a division of the crystal oscillator of 1 or less, resulting in the system's dot clock frequency, and all video timing is derived from the dot clock. If this field contains 0, the dot clock is equal to the lens clock frequency, while a value of 7 results in a dot clock that is 1/8 of the lens frequency. Using a quadruple, 14.31818 MHz lens with a nominal program video timing parameter that yields a panel refresh rate of 50 Hz, and changing only the dot clock division, 50 as the actual panel refresh rate. Resulting in 0.000 Hz, 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz, 7.14 Hz or 6.25 Hz.

Bits 12-13: Reserved These read-only bits are reserved.

Bit 14: Debug mode operation When the debug mode bit is written high, two actions occur. First, the LCD panel interface changes to allow the use of a conventional color LCD with multiple color subpixels. Second, the SDRAM interface port 220 changes to allow the use of 4 MB SDRAM. This bit should be cleared to 0 when manufacturing multiple ASICs for the second display controller 106.

Bit 15: Self-test mode At start-up, the second display controller 106 samples the BIST pin and decides whether to enter normal operation (rather than BIST low or self-test operation, BIST high) . The state of the BIST pin is copied to the self test mode bit when exiting. Also, the software can start input to the BIST mode by writing this bit with 1 and can restore normal operation by writing this bit with 0. The second display controller 106 is placed in a self-test mode and automatically outputs its display output through multiple sequences of white, black, red, green and blue every 2 seconds when no input video clock is detected. It circulates to.

Register 2: Horizontal Resolution This 16-bit register contains the number of display pixels per horizontal line, which is typically 1200. Note that due to timing constraints in the first display controller 104, the second display controller 106 may receive more input pixel clocks than the number programmed in this register. When this happens, subsequent clocks exceeding the number of pixels programmed in this register should be ignored until the next HSync pulse is generated. As a result, the number programmed into this register matches the memory pitch after padding pixels from one line to the next as stored in the frame buffer 206.

Register 3: Total number of horizontal characters This 16-bit register contains the total number of dot clocks for each horizontal scan line.

Register 4: Horizontal Sync Start and Width This 16-bit register contains two 8-bit registers. The most important byte registers include the horizontal synchronization start register. After “horizontal resolution”, a dot clock occurs on each line. HSync is generated after multiple additional clocks of “Start HSync” occur. The least significant byte of this register contains the number of clocks that HSync remains functional once HSync is generated.

Register 5: Vertical Resolution This 16-bit register contains the total number of lines displayed per video frame. This typically includes a value of 900.

Register 6: Number of Vertical Display Lines This 16-bit register contains the total number of scan line periods that occur per video frame. For clarity, the refresh rate hertz of a TFT panel is equal to the value of its register.
Dot clock / (total number of horizontal characters x number of vertical display lines)

Register 7: Vertical Sync Start and Width This 16-bit register contains two 8-bit registers. The most important byte in the register contains the vertical synchronization start register. After multiple lines of vertical resolution are displayed, VSync is generated after a number of scan lines that are an additional multiple of “VSync start” are generated. The lowest importance byte of this register contains the number of scan lines that VSynce will remain functional once VSync is generated.

Register 8: Display Timeout Value To save power, the second display controller 106 has the ability to automatically power down the multiple display outputs and enter the sleep mode of the second display controller 106. This register contains the number of output video frames before automatic power down occurs.

Register 9: Scan Line Interrupt Value In order to properly synchronize the video output of the processor 102 with the video output of the second display controller 106, the second display controller 106 is the processor 102 on any given line of display. The system software can be synchronized with the display process by generating the interrupt. This register is written with the number of output video scanning lines, during which an interrupt is generated.

Register 10: Backlight brightness Only the upper 4 bits of this register are used, the lower 12 bits are undefined and should be ignored. The backlight brightness register is used to set the duty cycle of the DBC output pin. A value of 00H corresponds to a 0 percent duty cycle, while a value of 0FH corresponds to a 100 percent duty cycle. Multiple intermediate values can be used to set a specific brightness level. Note that if the backlight activation bit is set to 1 and the panel is currently activated, the DBC pin can only be driven with a PWM wave.

Registers 11-127: Reserved These registers are reserved.

  In view of the above, the industrial-based implementation details of the present invention (0.8 version of the second display controller) according to another embodiment are included with this.

Second Display Controller 106 Direct I / O Pin Interface Some interface operations between the second display controller 106 and the processor 102 are particularly time critical. In particular, the switching between the first display controller 104 that manages display refresh and the second display controller 106 that manages display refresh must be carefully timed to prevent display artifacts. To enable these operations, the second display controller 106 uses a high speed direct I / O pin connection to the CS5536 companion I / O device. At the description of each pin, continue the interconnection details of the system.

GPIO12 of DCONBLNK-CS5536
DCONBLNK subsidizes the processor 102 to synchronize its video timing with the video timing of the second display controller 106, and to make an unobstructed transition from the second display controller 106-control refresh to the processor 102-control refresh. Used to guarantee. If intended to pole, the second display controller 106 drives the DCONBLNK output under two circumstances. In the first, the DCONBLNK output is driven low at the beginning of the first output scan line following a functioning vertical resolution multiple output scan line and remains low until the falling edge (end) of the output VSync timing interval. At that time, it is driven high again. Secondly, the DCONBLNK output remains high whenever the second display controller 106 is in the sleep mode of the second display controller 106.

GPIO11 of DCONLOAD-CS5536
DCONLOAD controls the source of the video display refresh cycle. Whether this signal directly determines whether the multiple video timing output of the second display control device 106 follows the multiple video input while indicating that the control device of the first display control device 104 is managing display refresh. Alternatively, it is determined whether a plurality of timing registers inside the second display control device 106 are driving a plurality of video outputs. In either case, the actual data output to the panel will normally be modified by the chip of the second display controller 106, as described in the description of the display mode register of the second display controller 106. Please be careful. With this exception when the second display controller 106 is operating in the pass mode, the data output of the second display controller 106 is simply green video so that it is appropriately delayed for proper signal synchronization. Reflects 6-bit truncation of data input.

DCONIRQ / -CS5536 INTB #
The DCONIRQ / pin is a negative logic interrupt request output from the second display controller 106 chip. This signal is driven under three circumstances. First, at the completion of the display load cycle, DCONIRQ / is driven to inform the processor 102 that the first display controller 104 has now been safely deactivated. In addition, the second display controller 106 may be programmed to generate an interrupt on any particular scan line of the video output. The main purpose of this use is to automatically alert the processor 102 at a fixed time before the start of the next displayed frame. When an interrupt with a known timing associated with a display operation is received, the processor 102 can restart the video in synchronism with the current display of the second display controller 106 without display artifacts. The scanning line interrupt capability can be used for conventional purposes such as display animation.

  The last DCONIRQ interrupt source occurs when the processor 102 has updated the screen and executed the display load sequence, but the second display controller 106 is now in sleep mode. When the second display controller 106 is later woken up by ECPWRRQST, it normally starts the panel and autonomously resumes the display refresh. In this case, the second display control device 106 instead starts the panel while holding the video blank by setting the video blanking bit, and generates a DCONLOAD_MISSED interrupt to display the video. Informs processor 102 that it must be updated. Note that it is the responsibility of the processor 102 to clear the video blanking bit after updating the display. (The internal DCONLOAD_MISSED status flag is cleared by writing the video blanking bit.)

GPCON5 and GPIO6 of DCONSTAT0..1-CS5536
The DCONSTAT pins are used to communicate with the processor 102 in high speed, especially for the purpose of identifying the cause behind the DCONIRG interrupt. The multiple pins of DCONSTAT0..1 are encoded as follows:

00: Scan line interrupt generated while the processor 102 was performing refresh control, that is, the always-on mode. This state is used to indicate that any incoming multiple interrupts indicate a conventional multiple scan line interrupt, i.e. an interrupt associated with an animation or the like.
01: Scan line interrupt generated in state 2 (second display control device 106 mode). This state is used together with the re-initialization of the multiple video output of the processor 102, and starts the synchronization of the multiple video timing of the processor 102 with the multiple video timing of the second display control device 106. After this interrupt, the processor 102 checks the state of the DCONBLNK pin and performs elaborate timing synchronization.
10: Generated display load completion interrupt. In this state, the processor 102 indicates that the second display control device 106 has finished recording the video frame, and therefore the clock of the control device of the on-chip first display control device 104 is deactivated and output with maximum power saving. To the processor 102 that it is safe for the user.
11: DCONLOAD_MISSED interrupt generated while exiting sleep mode. As stated earlier, if the processor 102 draws a picture on the screen while the second display controller 106 is in the sleep mode, the screen will be delayed when it wakes up. This interrupt signals the second display controller 106 that a display load cycle must be executed to clear the video blanking bit in the mode register of the second display controller 106 and the display must be activated. .

  While this encoding may seem a little difficult to understand, it is an indication of the need to put state information in the most effective pinout.

ECPWRRQST-System function monitoring
The ECPWRRQST pin is used to “wake up” the second display controller 106 from sleep mode. Each time a keyboard, touchpad or cursor key event occurs, the system's built-in controller will pulse this pin high. The rising edge of ECPWRRQST causes the second display controller 106 to automatically initiate a display and autonomously initiate a display refresh (see above description for significant exceptions to the DCONLOAD MISSED interrupt). If the second display controller 106 enters sleep mode, either automatically or manually, the sleep mode bit of the second display controller 106 is cleared to 0 or the ECPWRRQST pin goes high. It is toggled and remains in sleep mode until the sleep mode bit of the second display controller 106 is cleared.

  Note that ECPWRRQST that arrives while the display is functioning has only one effect. It resets the internal display timeout register to the value of the display timeout value register.

  The minimum duty cycle during ECPWRRQST function is less than 100nS. (This pin does not need to be debounced or filtered.)

Register definition of the second display controller 106 Register Index Default ID and revision of the second display controller 106 DC01H
Display mode of second display controller 106 1 0012H
Horizontal resolution 2 0458H (1200 decimal)
Total number of horizontal characters 3 04E8H (1256 decimal)
Horizontal synchronization 4 1808H (24, 8 decimal)
Vertical resolution 5 0340H (900 decimal)
Number of vertical display lines 6 0390H (912 decimal)
Vertical synchronization 7 0403H (4, 3 decimal)
Display timeout 8 FFFFH
Scan line interrupt 9 0000H
Backlight brightness 10 XXXFH
Spare 11-127

User I / O Pin Definition of Second Display Controller 106 ASIC Pinout-1M (512K × 16) SDRAM Configuration of Second Display Controller 106 Geode (TM) Display Interface Pin Group Geode (TM) Pixel Clock GFDOTCLK 1
Geode (TM) red data GFRDAT0-5 6
Geode (TM) Green Data GFGDAT0-6 7
Geode (TM) Blue Data GFBDAT0-5 6
Geode (TM) VSync GFVSYNC 1
Geode (TM) HSync GFHSYNC 1
Geode (TM) FP_LDE GFP_LDE 1

512K × 16 SDRAM interface pin group FBRAM data FBD0-15 16
FBRAM address FBDA0-10 11
FB column address strobe FBCAS / 1
FB row address strobe FBRAS / 1
FB data mask FBDM0-1 2
FBRAM chip select FBCS / 1
RBRAM writing operation FBWE / 1
FBRAM clock FBCLK 1
FBRAM clock operation FBCLKE 1

Crystal for self-refresh of the second display controller 106 Display XTAL in DCONXI 1
Display XTAL out DCONXO 1

System interface pin group System reset RESET 1
EC power on request ECPWRRQST 1
Interrupt output of second display controller 106 DCONIRG / 1
Display load command request of second display controller 106 DCONLOAD 1
State pin group DCONSTAT 2 of the second display control device 106
Blanking state of the second display controller 106 DCONBLNK 1
Register I / O • SMB clock DCONSMBCLK 1 of the second display controller 106
Register I / O / SMB data of the second display controller 106 DCONSMBDATA 1

DETTL / Panel interface pin group Panel pixel data 0 DO00-DO01 3
Panel pixel data 1 DO10-DO11 3
Panel pixel data 2 DO20-DO21 3
Source dot clock SCLK 1
Data interface polarity control REV1-2 2
Graphic output operation (gate driver operation) GOE 1
-INV 1
-CPV 1
-STV 1
-FSTH 1
-BSTH 1
-TP 1
LCD backlight operation BACKLIGHT 1
Display backlight control (PWM) DBC 1
Driver polarity signal 1 POL1 1
LCD VDD operation VDDEN 1
Run-in / Test mode AGMODE 1
Color / monochrome panel bias ・ Select COLMODE 1
General user I / O 94

Second Display Controller 106 Register Definition The primary programming interface to the second display controller 106 chip is the 100 KHz serial SMBUS interface, which provides read and write access to multiple configuration registers within the chip. Is acceptable. These registers are all 16 bits long, and access can only be used as 16-bit registers. Accessing these registers in any mode is undefined and may have undefined results. In particular, a 32-bit SMBUS cycle is used to properly communicate with the second display controller 106 and the first 8 bits specify an SMBUS address that is always 0DH in this execution and read / write mode bits. . The next 8 bits provide the register number to communicate with, and the remaining 16 bits contain the contents of the desired register. Note that in order to understand the communication of the second display controller 106 with the system, the second display controller 106 is connected to the SMBUS port of the AMD CS 5536 I / O chip with the SMBUS address 0DH.

Register 0: Second Display Controller 106 ID + Revision This 16-bit register is a read-only register and returns the ASIC identifier and revision number of the second display controller 106. The first pass of this silicon should return a hexadecimal value of 'DC01'H, the next revision should return'DC02'H, etc.

Register 1: Display mode of the second display controller 106 Bit 0: Pass through disabled This bit controls whether the second display controller 106 performs any operation on the refresh data. At start-up, this bit is automatically initialized to 0 by the second display controller 106, which causes multiple video outputs to directly follow multiple video inputs, and the second display controller 106 operates in pass mode. It is said that In this mode, the second display controller 106 operates alone as an old TFT timing controller (TCON) chip, where multiple video outputs need to drive a DETTL compatible multiple output signal for the display panel. Converted only when there is. For power reduction purposes, the SDRAM interface port 220 must be completely deactivated while in the pass mode, and even no SDRAM clock signal is generated. In the pass mode, all other registers and control bits of the second display controller 106 are ignored except for the self-test activation bit which takes precedence over the pass mode.

  Writing a 1 to the pass inactive bit allows the normal secondary display controller 106 to function and functions of the SDRAM interface port 220 as well as functions such as the internal video timing register, mode configuration bits, etc. Including.

Bit 1: Display operation of the second display control device 106 The display operation bit is initialized to 1 when the reset processing by the second display control device 106 is completed. This normal state allows the multiple outputs of the panel interface of the second display controller 106 to be driven as determined by the current chip mode. By immediately writing this bit to 0 in synchronization, multiple video outputs are driven to a low power blank state. As a result, setting this bit activates multiple video outputs, but the reactivation process is synchronous and the panel remains in a low power state until the next falling edge of the Vsync output timing interval. It is. At that time, the video drivers are turned on and remain on until the display operation of the second display controller 106 is cleared again.

  Note that the second display controller 106 automatically clears this bit and the display is erased.

  If the display timeout activation bit is set, multiple video output frames with a display timeout value are generated without causing a display load cycle.

Bit 2: Color Swizzling Operation According to one embodiment of the present invention, the selected display device 108 is a hybrid black / white / color panel, which does not use conventional RGB sub-pixels. Instead, each pixel contains only a single “subpixel value”. When used as a reflector, when the backlight is inactive, these pixel values represent a gray scale so that the image is a black and white display. When used in transmissive mode, each pixel represents a single color value from the red, green and blue set when the backlight is on.

  The first pixel of the first line of refresh data is red, the second pixel is green, and the third pixel is blue. This regular arrangement is repeated across the line. Note, however, that each subsequent line is offset by one color component from the previous line. Thus, the first pixel in the second line is green, the second pixel is blue, and the third pixel is red. This regular arrangement is repeated over the second line. The first pixel in the third line is blue, the second pixel is red, and the third pixel is green. The regular arrangement of the first pixels is repeated over the third line. Subsequently, the above described regular arrangement of the first three lines is repeated in groups of three lines over the entire display panel.

  This regular arrangement of colors helps eliminate display artifacts, but complicates system software. The color swizzling enable bit, when set to 1, enables the second display controller 106 to automatically select the appropriate color field from the input 6-7-6 refresh data. After the physical panel structure outlined above, the second display controller 106 selects the red input field for the first pixel of the first line and the green input field for the next pixel of this line. To do. The net effect of the color swizzling activation function is that each output pixel written to the frame buffer 206 has a single 6-bit value, so that the second display controller 106 is one third of the input refresh data. 2 is to automatically discard.

  Note that when the color swizzling enable bit is set to 0, the second display controller 106 simply outputs the green field value of the input pixel until the monochrome brightness enable bit is set to 1. Since the color swizzling and color anti-aliasing mode bits work and require the use of the chip's multiple ring buffer only in color anti-aliasing mode, color swizzling mode is turned on. In some cases, it is not necessary to use a plurality of scanning line ring buffers of the second display controller 106.

Bit 3: Color Anti-aliasing Operation When color swizzling mode is activated, the color anti-aliasing mode bit can also be set to 1. The color antialiasing mode is said to be working when both of its bits are set. In this mode, the color swizzling process proceeds as described above, but the resulting output is filtered to prevent color aliasing. This filtering process changes the color value of the current pixel at the pixel coordinates (V, H) above the current pixel (V-1, H), below (V + 1, H), left (V, H-1) and right ( Works by combining multiple color fields that match the multiple pixels in V, H + 1). This adds multiple values of the matching color field to those of the four neighboring pixels, shifts the result to the right by 3 bits, and converts it to the value of the current pixel shifted to the right by 1 bit. Including adding. The resulting output, truncated to 6 bits, corresponds to the filtered value of the color swizzling process when color anti-aliasing is not activated. This 6-bit value is stored in the current pixel of the frame buffer 206.

  It is particularly important to emphasize that color anti-aliasing works with 16-bit color values rather than the 6-bit color values that are the output of the color swizzling process when color anti-aliasing is not activated. The above calculations are performed for a plurality of color fields that are particularly suitable for the current pixel. In other words, if the current pixel has a red filter, the calculation sums and combines multiple red fields of neighboring pixels with the red field of the current pixel. The next pixel to the right performs the same function for multiple green fields, such as the current and neighboring pixels.

  In order to obtain multiple color fields suitable for color anti-aliasing, two important things will be immediately apparent. First, a two scan line length ring buffer must be used to perform the processing. Second, each element's ring buffer must hold 16 bits of color data in a 5-6-5 input color format rather than in a 6 bit output format.

  Implementation Details: The multiple input line buffers are typically 2 × 1110 words or 2 × 830 words long, depending on whether the display is driven in portrait or landscape mode. However, it is essential that the buffers are updated on a pixel-by-pixel ring buffer basis once executed. Otherwise, three full scan lines are required to perform the color anti-aliasing function.

  Implementation Note: The above simplified calculations are used for ease of understanding and do not represent actual implementation. For example, the use of left shift and right shift operators is intended to specify alignment of multiple bits from various color components and does not imply that any multiple bits are “lost” during anti-aliasing. . In order to achieve visual display quality, it is essential that full 10-bit accuracy is maintained until a complete result is output. Only the final output of anti-aliasing can be truncated to 6 bits.

  Implementations that discard the least significant bits during anti-aliasing operations before output truncation are unacceptable.

Bit 4: Monochrome Luminance Operation As long as the color swizzling and color anti-aliasing bits are 0, the second display controller 106 can be put into the monochromatic luminance mode by writing this bit to 1. In this mode, 16-bit input color values in the 5-6-5 RGB format are converted to 6-bit pixel display values via the following simple integer approximation to the standard NTSC luminance conversion equation.
Pixel value = (R >> 2) + (R >> 4) + (G >> 1) + (G >> 4) + (B >> 3)

  Note that unlike the color anti-aliasing mode, the black and white luminance function works alone for multiple color fields of the current pixel. As a result, the two-line ring buffer on the chip is not used in this mode.

  Implementation note: The above simplified calculation is used to facilitate understanding and does not represent an actual implementation. For example, the use of the left shift and right shift operators is intended to specify the alignment of multiple bits from various color components and implies that any multiple bits are “lost” during the luminance conversion process. do not do. For visual display quality, it is essential that full 10-bit accuracy is maintained until a complete result is output. Only the final output of the luminance conversion process can be truncated to 6 bits. Implementations that discard the least significant bits during the luminance calculation before output truncation are unacceptable.

Bits 5-7: Dot clock division To allow the use of minimal power output, the second display controller 106 can use the ability to reduce the frequency of the dot clock of the panel interface. This field value specifies a division of the crystal oscillator of 1 or less, resulting in the frequency of the system dot clock. All video timing is derived from the dot clock. If this field contains 0, the dot clock is equal to the lens clock frequency, while a value of 7 results in a dot clock that is 1/8 of the lens frequency. Using a 54.06 MHz lens with multiple video timing parameters of a nominal program that yields a panel refresh rate of 50 Hz, and changing only the dot clock division, an actual panel refresh rate of 50.00 Hz , 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz, 7.14 Hz or 6.25 Hz.

  Implementation Details: Using a double memory clock PLL as an input clock source for dot clock division simplifies the generation of a 50 percent duty cycle dot clock with all dividers One possible method.

Bit 8: Automatic video synchronization mode If this bit is set, the second display controller 106 will have all of its display load sequences started each time it hits the falling edge of the first VsyncIn pulse. Reset the internal video timing counter. This mode is intended for use when programmed to have the same frequency of VsyncIn and VsyncOut. If not, this mode should be used with caution.

  For example, the dot clock divider of the second display controller 106 is programmed to allow the use of a panel refresh rate of 25 Hz, but the first display controller 104 of the system is built with an output rate of 50 Hz. If so, only the first half or less of that panel is re-refreshed before the multiple video timer of the second display controller 106 is reset. By running the input / output frequencies at the same rate, the above artifacts can be avoided. In advanced applications, it can be tried to use the scanning line interrupt capability of the second display controller 106 to allow the use of mixed frame rates.

  Note that automatic video synchronization only works when the second display controller 106 follows the video input port, i.e., when the display load sequence is in process. This prevents display problems that may occur when multiple outputs that reinitialize the first display controller 106 interfere inadvertently with the video refresh of the second display controller 106.

Bit 9: Display timeout operation When this bit is set to 1, the second display controller 106 automatically stops the display process.

  When multiple video frames with a display timeout value are output without causing a display load sequence, automatic execution of display load resets the internal timeout counter to the value of the display timeout value register. When this bit is set to 0, the second display controller 106 continues the display output refresh unrelated to the display load cycle.

Bit 10: Scan Line Interrupt Operation Setting this bit to 1 allows the scan line interrupt output of the second display controller 106 to be generated during the video scan line and is programmed into the scan line interrupt value register. The This interrupt will function at the beginning of the programmed line and will remain functional for one line period of each frame. This sequence continues as long as the scan line interrupt enable bit is one.

Bits 11-14: Reserved These read-only bits are reserved and always return a value of 0 when read.

Bit 15: Self Test Mode Upon start-up, the second display controller 106 samples the BIST0 pin and determines whether to enter normal operation, ie, BIST0 low, self test operation or BIST0 high. The state of the BIST pin is copied to the self test mode pin when exiting reset. Also, the software can start input to the BIST mode by writing this bit with 1, and can restore normal operation by writing this bit with 0.

  Various embodiments of the present invention ensure that power consumption is reduced while the display subsystem is driven. The second display control device can autonomously refresh the display device separately from the processor and the first display control device, thereby eliminating the continuous processor intervention. The first and second display controllers and the display device can be turned off for extended periods of non-functionality, resulting in significant savings in display system power consumption.

  Various embodiments of the present invention do not require dedicated and expensive hardware, and provide an ideal system for use of electronic devices in applications that are cost and power-sensitive.

  The system may be implemented in the form of a computer system as described in the present invention or any of its components. Typical examples of computer systems include general purpose computers, program microprocessors, microcontrollers, peripheral integrated circuit elements, and other devices or device strategies capable of performing the multiple steps of the method of the present invention. Is included.

  The computer system includes a computer, an input device, a display unit, and the Internet. The computer consists of a microprocessor, which is connected to a communication bus. The computer also includes memory, which can include read-write storage (RAM) and read-only storage (ROM). Further, the computer system includes a storage device, which can be a hard disk drive or a removable storage drive such as a floppy disk drive and optical disk drive. The storage device may also include other similar means for loading a plurality of computer programs or other plurality of instructions into the computer system.

  The computer system executes a set of instructions stored in one or more storage elements to process input data. The storage element may also hold desired data or other information, and may be an information source or physical storage element in the processor.

  The instruction set can include various commands that direct the processor to perform specific tasks, such as the multiple steps that make up the method of the present invention. The instruction set may be in the form of a software program. The software may be in various forms such as system software or application software. Furthermore, the software may be in the form of a collection of individual programs, a program module with a larger program, or a part of a program module. The software can also include modular programming in the form of object-oriented programming. The processing of input data by the processor may be in response to a user command, a previous processing result, or a request made by another processor.

  While embodiments of the invention have been discussed and described, the invention is not limited to only these embodiments. Several changes and modifications can be envisaged as set forth in the claims without departing from the scope of the invention.

It is a schematic diagram of the composition which can carry out various embodiments of the present invention. It is a schematic diagram of various elements in the 2nd display control device by an embodiment of the present invention. 4 is a flowchart of a method for saving power consumption while a display device is refreshed in a computer-related unit, according to an embodiment of the present invention. 4 is a flowchart of a method for switching control of a display device from a first display control device to a second display control device according to an embodiment of the present invention. 4 is a flowchart of a method for switching control of a display device from a first display control device to a second display control device according to an embodiment of the present invention. 3 is a flowchart of a method for switching control of a display device from a second display control device to a first display control device according to an embodiment of the present invention. 3 is a flowchart of a method for activating a second display control device from a non-functional state according to an embodiment of the present invention; 4 is a flowchart of method steps for converting data content of a first display controller to reduced bit format, in accordance with an embodiment of the present invention. FIG. 2 is a schematic diagram of a method for color swizzling according to an embodiment of the present invention. 4 is a timing flowchart for starting a second display control device from a non-functional state according to an embodiment of the present invention;

Explanation of symbols

100 Display Subsystem 102 Processor 104 First Display Controller 106 Second Display Controller 108 Display Device 202 Input Port 204 Output Port 206 Frame Buffer 208 Clock 220 Processing Module 222 Decision Module

Claims (7)

  1. A method for reducing power consumption of the display sub-system in the computer-related units,
    The display subsystem includes a display device, a processor, a first display control device, and a second display control device,
    A method for reducing the power consumption of the display subsystem is:
    Refreshing the display device by the first display control device when the second display control device is in a non-functional state;
    If no new refresh data is generated by the processor, switching the first display controller from a functional state to a non-functional state;
    Converting the refresh data of the first display control device into second refresh data used by the second display control device to refresh the display device;
    Instructing the second display controller to refresh the display device in the display subsystem with the second refresh data separately from the first display controller and the processor ;
    The second display control device refreshing the display device with the second refresh data ;
    The step of converting the refresh data of the first display control device into the second refresh data comprises the step of converting the refresh data in the first display control device into a reduced bit format. Power consumption reduction method for the display subsystem.
  2. The reduction bits format, power consumption reduction method of a display sub-system of claim 1, wherein that will be stored in the frame buffer that is connected to the second display control unit.
  3. Converting the refresh data in the first display control device in the reduced bit form,
    a) processing a plurality of red bits of refresh data in the first display controller to form a reduced bit format, wherein the plurality of red bits and the reduced bit format of the refresh data of the first display controller are: Corresponding to the first pixel of the first line of the display device;
    b) processing a plurality of green bits of refresh data in the first display controller to form a reduced bit format, wherein the plurality of green bits and the reduced bit format of the refresh data of the first display controller are: Corresponding to the second pixel of the first line of the display device;
    c) processing a plurality of blue bits of refresh data in the first display controller to form a reduced bit format, wherein the plurality of blue bits and the reduced bit format of the refresh data of the first display controller are: Corresponding to the third pixel of the first line of the display device; and
    Power consumption reduction method of a display sub-system of claim 1, wherein the Ru with the.
  4. 4. The display sub-system power consumption reduction method according to claim 3 , further comprising the step of processing refresh data in the first display control device for each pixel of each line of the display device .
  5. Power consumption reduction method of a display sub-system of claim 1, further comprising the step of antialiased the reduction bit form.
  6. Processing the refresh data in the first display controller to form a reduced bit format comprises converting the input color information of the refresh data in the first display controller into a black and white representation. Item 4. A method for reducing power consumption of a display sub-system according to Item 1 .
  7. Step, the power consumption reducing method of a display sub-system of claim 1, wherein changing the green component of the refresh data in the first display control device into another format for processing the refresh data in the first display control unit .
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