KR100890841B1 - Self-refreshing display controller for display device in a computational unit - Google Patents

Abstract

The present invention provides a method, system and computer program product for a display system for driving a display device. The display system includes a processor, a primary display controller, a secondary display controller and a display device. The primary display controller receives the display data sent by the processor. The primary display controller also drives the display device when the processor sends a new display frame. When these display frames are transmitted continuously by the processor, the control of the display device is switched to a secondary display controller that is optimized for low power operation.

Description

Self-refreshing display controller for display unit of computer unit {SELF-REFRESHING DISPLAY CONTROLLER FOR DISPLAY DEVICE IN A COMPUTATIONAL UNIT}

1 is a schematic diagram illustrating an environment in which various embodiments of the present invention will be practiced;

2 is a schematic diagram illustrating various components present in a secondary display controller in accordance with an embodiment of the invention;

3 is a flowchart of a method for reducing power consumption while a display device is refreshed in a computer unit in accordance with an embodiment of the present invention;

4A and 4B are flowcharts of a method of switching control of a display device from a primary display controller to a secondary display controller according to an embodiment of the present invention;

5 is a flowchart of a method of switching control of a display device from a secondary display controller to a primary display controller according to an embodiment of the present invention;

6 is a flowchart of a method of activating a secondary display controller from an inactive state in accordance with an embodiment of the present invention;

7 is a flowchart of a method of converting data content of a primary display controller into a reduced bit form according to an embodiment of the present invention;

8 is a schematic diagram illustrating a method of color-swizzling according to an embodiment of the present invention.

9 is a time flow diagram for activating a secondary display controller from an inactive state in accordance with an embodiment of the present invention.

The present invention relates generally to the field of display devices of computer units. More particularly, the present invention relates to a method and system for refreshing a display device of a computer unit.

The computer unit uses the display device to present the information to the user. The display device is the interface between the computer and the user. Examples of display devices include, but are not limited to, Cathode Ray Tube (CRT) monitors, Liquid Crystal Display (LCD) monitors, Plasma screens, and Organic Light Emitting Diodes (OLEDs). The display controller present in the computer unit acquires an input signal from the processor. The display controller processes the input signal and provides refresh data for refreshing the display device.

The refresh data is stored in the refresh memory of the display controller. In some systems, the refresh memory of the display controller is integrated with the processor RAM. This is known as the Unified Memory Architecture (UMA). In other systems, the display controller has its own RAM controller for the refresh memory independent of the processor RAM. The refresh data present in the refresh memory includes the color value of each pixel present in each line of the display device. The total amount of memory needed to store the refresh data depends on the resolution of the display device. This resolution can be defined as the physical number of columns and rows of pixels forming the display. In addition, the total amount of memory required to refresh the display device depends on the color depth. The color depth includes the number of bits used to represent the color of a single pixel. In the integrated memory structure, the display device directly accesses the refresh data from the processor's refresh memory. The processor runs very large memory to support Basic Input / Output System (BIOS), Operating System (OS) and various other application programs. The total amount of memory required for the operation of the processor is generally larger than the memory required by the display controller to refresh the display device in the UMA.

The power required to drive the refresh memory can be expressed as P = CV ^ 2F. Where C is the capacity of the memory capacitor, V is the voltage, and F is the frequency of the memory clock. The power consumed to refresh the memory is directly proportional to the memory size. In addition, additional power is needed to drive the memory arbitration unit that is used to share the processor's main memory resources between the processor and the display device. As a result, the power consumption increases while the display device in the UMA is refreshed.

Moreover, in many computer units, the display controller is integrated with the processor. This computer unit does not allow the processor to power off even when the display device no longer needs to be refreshed due to the absence of user input. This is due to the common electronics associated with dual-use memory systems. As a result, the power consumption is further increased if the display device is refreshed even while the processor is inactive.

In view of the above data, there is a need for a method and system that avoids the use of large memory in order to refresh the display device. Such a method and system should be able to refresh the display device without requiring power to drive the high speed memory arbitration unit. In addition, such methods and systems should allow the processor to be powered off if the display does not need to be refreshed. In addition, the methods and systems require a function that can automatically power down the display device after a long period of inactivity, in addition to the ability to reactivate the display device upon resumption of user operation independent of the processor.

It is an object of the present invention to provide a method and system for a display system for driving a display device.

Another object of the present invention is to provide a method and system for driving a display device without processor interference.

It is another object of the present invention to provide a method and system that can reduce power consumption while a display device is refreshed.

Another object of the present invention is to provide a method for synchronizing primary and secondary display controllers.

It is yet another object of the present invention to obviate the need for expensive dedicated hardware and to allow the concepts of the present invention to be used in cost and power sensitive applications.

In order to achieve the above object, and in accordance with various embodiments of the present invention, various embodiments of the present invention provide a method and system for a display system for driving a display device. The display system includes a processor, a primary display controller, a secondary display controller and a display device. The primary display controller receives the display data sent by the processor and drives the display device when the processor sends a new display frame. When the same display frame is transmitted continuously by the processor, control of the display device is switched to the secondary display controller, which is optimized for low power operation.

Embodiments of the present invention provide a method, system and computer program product for driving a display device in a display subsystem. The display subsystem resides within the computer unit and includes a processor, a primary display controller, a secondary display controller, a frame buffer for the secondary display controller, and a display device. The display device may be driven by either the primary display controller or the secondary display controller. The primary display controller drives the display device when the processor generates new refresh data. The primary display controller also delivers display data to the secondary display controller. The secondary display controller may reflect the refresh data, refresh the display data, or perform an operation on the refresh data to refresh the display device. When the processor generates the same refresh data for a predetermined time, control of the display device is switched from the primary display controller to the secondary display controller. The frame to be displayed next is written into the frame buffer of the secondary display controller.

1 is a schematic diagram illustrating an environment in which various embodiments of the present invention will be practiced. The environment includes a display subsystem 100 that can reside in a computer unit. Computer units include, for example, laptop computers, palmtop computers, desktop computers, calculators, mobile phones or PDAs. The display system 100 includes a processor 102, a primary display controller 104, a secondary display controller 106, and a display device 108. Examples of display device 108 include, but are not limited to, LCD screens, CRT monitors, and plasma screens. Processor 102 is generally a CPU present in a computer unit. The primary display controller 104 and the secondary display controller 106 may be a conventional video graphics array (VGA) or other type of controller or application-specific integrated controller (ASIC). Processor 102 controls primary display controller 104 and secondary display controller 106.

2 is a schematic diagram illustrating various components present in the secondary display controller 106 in accordance with an embodiment of the present invention. The secondary display controller 106 supports various interfaces. The first interface is an input port 202 designed to receive refresh data from the primary display controller 104.

According to an embodiment of the present invention, the input port 202 is designed to connect directly to a TTL-compatible TFT display controller. This input-only port accepts video data such as the AMD GX2-533 video display output from a prior art VGA controller. This interface accepts 19 bits of RGB data in 6-7-6 format, i.e. 6 bits of red, 7 bits of green, and 6 bits of blue data per pixel.

The second interface is an output port 204 that connects directly to a compatible TFT panel row and column drive integrated circuit that supports LCD display output for a suitable TFT display device. The third interface is a Synchronous Dynamic Random Access Memory (SDRAM) interface port 220 that communicates with a low power synchronous dynamic RAM to store one complete refresh data frame. The secondary display controller 106 automatically refreshes the display device 108 by acquiring refresh data from the frame buffer 206. The frame buffer 206 is associated with the secondary display controller 106 and used to store refresh data.

According to an embodiment of the present invention, the frame buffer 206 is a 512K × 16 SDRAM frame buffer with 1,048,576 bytes, for example a 1200 × 900 One Laptop Per Child (OLPC) TFT panel having 1,080,000 pixels. As a result, the secondary display controller 106 must perform pixel packing, where each display pixel must occupy less than one byte of memory. The driver in the panel and the Double Edged Transistor-Transistor Logic (DETTL) interface support 6 bits of information / pixel. Therefore, to improve memory efficiency, each group of 4 pixels (4 pixels x 6 bits / pixel = 24 bits) is stored as 3 bytes (3 bytes x 8 bits / byte = 24 bits) in the SDRAM frame buffer. However, the SDRAM frame buffer is actually 16 bits wide. As a result, the actual addressable packing of pixels into the frame buffer is that 8 pixels (8 pixels * 6 bits / pixel = 48 bits) are packed into 3 words (3 words * 16 bits / word = 48 bits) of SDRAM. With this memory configuration, the frame buffer occupies 405,000 words of 512K x 16 SD-RAM, leaving 119,288 words unused.

According to another embodiment of the present invention, the frame buffer 206 is included in the secondary display controller 106.

According to another embodiment of the invention, the frame buffer 206 is outside the frame buffer.

The fourth interface is clock 208. According to an embodiment of the present invention, clock 208 is a directly attached 14.31818 MHz crystal supported by an on-chip oscillator, providing an independent pixel clock for display refresh regardless of the state of the display input port. Clock 208 also provides interface timing for attached frame buffer 206. The fifth interface includes one or more input / output pin interfaces that manage timing-critical transitions between the primary display controller 104 and the secondary display controller 106. The first pin 210 determines which of the two display controllers refreshes the display device 108. The primary display controller 104 refreshes the display device 108 when the first pin 210 is active, and the secondary display controller 106 displays the display device when the first pin 210 is inactive. Refresh 108. In addition, when the secondary display controller 106 is in an inactive state, the second pin 212 is set to an active state. The third pin 214 generates one or more interrupts to indicate the state of the secondary display controller 106. The fourth pin 216 facilitates communication between the processor 102 and the secondary display controller 106.

According to an embodiment of the invention, the secondary display controller 106 is configured to drive the secondary display controller 106 from inactive to active when the processor 102 receives one or more inputs from the input device. A fifth pin 218. One or more such input devices are connected to the processor 102.

The secondary display controller 106 includes a processing module 220 and a determination module 222. Processing module 220 provides color mixing support so that display device 108 appears as a 24-bit panel of the prior art. Color mixing is a process for converting the data content of the primary display controller 106 into reduced bit form for better and more efficient display. Implementation details of the color mixing function are described in conjunction with the detailed description in FIG. 8. The processing module 220 also supports optional antialiasing capabilities to improve text display. Processing module 220 provides a monochrome mode to support automatic pixel-addressable conversion from color to gray scale. The monochrome representation matches the human brightness detection of the refresh data present in the primary display controller. This is explained in detail in conjunction with FIGS. 7 and 8. The determination module 222 assists the processing module 220 in antialiasing.

The secondary display controller 106 also provides the ability to be transparent to input refresh data in pass-through mode. Pass-through mode may be enabled by changing one or more bit values in the registers of the secondary display controller 106. This emulates a simple LCD timing controller chip and automatic fly-by mode, preventing unnecessary writing to the attached frame buffer 206 and also minimizing power consumption. Secondary display controller 106 also includes support for prior art RGB DETTL panels for efficient debugging in addition to self-inspection capabilities for production line inspection. Details of the self-test capability for production line inspection have been described in conjunction with FIGS. 7 and 9.

According to an embodiment of the present invention, a single refresh data frame present in the primary display controller 104 is converted into a reduced bit form. This is done just before instructing the secondary display controller 106 to refresh the display device 108. As a result, the efficiency of the display process is improved.

3 is a flowchart of a method for reducing power consumption while display device 108 is refreshed within a computer unit, in accordance with an embodiment of the present invention. In step 302, if no new refresh data is generated by the processor 102, the primary display controller 104 transitions from active to inactive. In step 304, the secondary display controller 106 is instructed to refresh the display device 108 independently of the primary display controller 104 and the processor 102. The secondary display controller 106 consumes substantially less power than the primary display controller 104.

4A and 4B are flowcharts of a method of switching control of a display device from a primary display controller to a secondary display controller according to an embodiment of the present invention. In step 402, the primary display controller 104 refreshes the display device 108 when the processor 102 continuously generates new refresh data. At step 404, it is checked whether new refresh data is generated by the processor 102. When the processor 102 generates new refresh data, the primary display controller 104 continues to refresh the display device 108 at step 402. However, if no new refresh data is generated by the processor 102, the first pin 210 of the secondary display controller 106 is transitioned to an inactive state in step 406. Next, the refresh data present in the primary display controller 104 is converted into a reduced bit form in step 408. The reduced bit form cannot be visually distinguished from the refresh data present in the primary display controller 104. Converting the refresh data into a reduced bit form includes one or more modifications to the refresh data, such as changing the frequency of the display output or performing color mixing or color antialiasing functions. In operation 410, when the same refresh data is displayed for a long time, the display device 108 is powered off.

According to an embodiment of the present invention, the secondary display controller 106 can modify the refresh data and refresh the display device 108 without storing the refresh data in the frame buffer 206.

According to another embodiment of the present invention, the secondary display controller 106 may automatically assume the responsibility of refreshing the display device 108 at step 412.

According to an exemplary embodiment of the present disclosure, when the display apparatus 108 is refreshed a predetermined number of times with the same refresh data, the secondary display controller 106 may be switched to an inactive state. The number of times the secondary display controller 106 can be switched to an inactive state is stored in one or more registers in the secondary display controller 106.

5 is a flowchart of a method of switching control of a display device from a secondary display controller 106 to a primary display controller 104 in accordance with an embodiment of the present invention. In step 502, the secondary display controller 106 drives the display device 108. In step 504, it is determined whether the processor 102 generates new refresh data. If new refresh data is not generated by the processor 102, the secondary display controller 106 refreshes the display device 108. When new refresh data is generated by the processor 102, the secondary display controller 106 is instructed at step 504 that new refresh data has been created. In step 506, the first pin 210 is set to an active state. The active state of the first pin 210 represents an intermediate active write state of the primary display controller 104. In step 510, the primary display controller 106 is instructed to refresh the display device 108. In step 512, the primary display controller 106 is commanded to refresh the display device 108. Next, the primary display controller 104 transmits the refresh data to the secondary display controller 106. The secondary display controller 106 may convert the refresh data into a reduced bit form, which is then used to refresh the display device 108.

6 is a flowchart of a method of activating a secondary display controller from an inactive state in accordance with an embodiment of the present invention. In step 602, it is checked whether the secondary display controller 106 is inactive. In step 604, it is determined whether an input signal has been received by the secondary display controller 106 from one or more input devices associated with the display subsystem 100.

In accordance with an embodiment of the present invention, an input signal is received by the secondary display controller 106 from one or more input devices without intervention of the processor 102.

According to an embodiment of the present invention, an input signal is received by the secondary display controller 106 from one or more input devices via the processor 102. Examples of one or more input devices include, but are not limited to, a keyboard, touch pad, wireless event, cursor pad or mouse.

In step 606, the secondary display controller 106 is transitioned from inactive to active. In addition, the fifth pin 218 is set from inactive to active whenever receiving an input signal from one or more input devices. If the fifth pin 218 is set to the active state when the secondary display controller 106 is active, then the secondary display controller 106 is the number of times that the secondary display controller 106 can be inactive. Set one or more registers to store the values.

If the processor 102 does not generate new refresh data, the secondary display controller 106 automatically begins to refresh the display device 108 with the refresh data present in the frame buffer 206. When processor 102 updates frame buffer 202 with new refresh data, secondary display controller 106 powers up display device 108 and resets the display by resetting one or more deep-blanking registers. Blank. The third pin 214 generates an interrupt to instruct the secondary display controller 106 to update the refresh data. In step 608, the display device 108 is powered up if it is previously powered off.

7 is a flowchart of a method of converting data contents of a primary display controller into a reduced bit form according to an embodiment of the present invention. The backlight is turned on when the secondary display controller 106 is used in the transfer mode. Each pixel in the reduced bit form represents a single color value-red, blue or green. When the color mixing enable bit is set to 1, the secondary display controller 106 is enabled to automatically select the appropriate color field from the input refresh data of the corresponding pixel in the form of a reduced bit. After the physical panel structure is outlined in step 702, the secondary display controller 106 processes the red input field of the first pixel of the first line of refresh data, thereby reducing the first of the first line in the form of a reduced bit. Form a pixel. In step 704, the secondary display controller 106 processes the green input field of the second pixel of the first line of refresh data to form a second pixel of the first line in the form of a reduced bit.

In step 706, the secondary display controller 106 processes the blue input field of the third pixel of the first line of refresh data to form the third pixel of the first line in the form of a reduced bit. At step 708, the process is repeated for each pixel in the line. This pattern is repeated over the entire line. At step 710, the process is repeated at each line of refresh data. However, for each continuous line in the refresh data, the secondary display controller 106 selects the pixel color and is offset by one color component in the pre-line in the form of a reduced bit. The first pixel in the reduced bit form second line is therefore green, the second pixel in the reduced bit form second line is blue, and the third pixel in the reduced bit form second line is red. This pattern is repeated over the second line in the form of a reduced bit. The first pixel in the reduced bit form third line is blue, the second pixel in the reduced bit form third line is red, and the third pixel in the reduced bit form third line is green. This pattern is repeated over the second line. The above-described pattern for the first three lines is repeated in groups of three lines through the whole reduced bit form.

According to an embodiment of the invention, each pixel in the form of a reduced bit has a single 6-bit value. According to another embodiment of the invention, the red and blue pixels are written with trailing zeros, so each pixel has a 6-bit left justified value.

8 is a schematic diagram illustrating a method of color-swizzling according to an embodiment of the present invention. The drawings illustrate color mixing by way of example. Color mixing is a process of converting the data content of the primary display controller 104 into a reduced bit form. Red bits of the first pixel in line 16 of 1-bit input signal is referred to as R _11, it is selected for the first pixel in the first line of the reduced bit referred to as R _{11 '.} The green bit of the second pixel in line 1 of the 16 bit input signal is called G ₁₅ and is selected for the second pixel in the first line of reduced bits called G _{15 ′} . 16-bit input pixel in the third line of the first signal, the blue bit is referred to as B ₁₉ is selected for the third pixel in the first line of the reduced bit referred to as B _{19 '.} This pattern is repeated over line 1. Each continuous line is an offset by one color component of the previous line. 16-bit input line green bits of the first pixel in the second of the signal is referred to as a G ₂₂ is selected for the first pixel of the reduced bit form of the line 2 referred to as a G _{22 '.} The second bit of the blue pixels in the second line the 16-bit input signal is referred to as B _26, it is selected for the second pixel in the line of the reduced bit form two calls to B _{26 '.} 16. The red bits of the third pixel in line 2 of the input bit signal is referred to as R _27, is selected for the third pixel in the R _{27 'in} the form of a reduced bit line referred to two. This pattern is repeated over line 2. The first bit of the blue pixel in the line 3 of the 16-bit input signal is referred to as B _33, is selected for the first pixel in the line of the 16-bit input signal is referred to as B _{33 '3.} The second bit of the red pixel in the line 3 of the 16-bit input signal is referred to as R _34, it is selected for the second pixel in the call to R _{34 'of} the line 16-bit input signal 3. The green bits of the third pixel in the line of the 16-bit input signal 3 is referred to as a G _38, is selected for the third pixel in the line of the 16-bit input signal is referred to as a G _{38 '3.} This pattern is repeated over line 3.

When the color mixing mode is enabled, the color antialiasing mode bit may be set to one. The color antialiasing mode is said to be set active if all bits are set. In this mode, the color mixing process proceeds as described above, but the resulting output is filtered to prevent color aliasing. This is especially important when text fonts are shown. The filtering process works by combining the color values of the current pixel with, for example, the color fields of the matching pixels above and below the left and right of the current pixel. For example, considering B _{26 '} in FIG. 8, the pixels above and below to the left and right thereof are respectively the second pixel in line 1, the second pixel in line 3, the first pixel in line 2 and the line 2 Will be the third pixel in the. The blue bits of these pixels are considered.

In another embodiment of the present invention, the input signal comprises 19 bits of the 6-7-6 format, where 6 bits represent the red component of the input refresh data, 7 bits the green component, and 6 bits the blue component.

While the color mixing and color antialiasing bits are zero, the secondary display controller 106 switches to the monochrome luminance mode by setting the color-antialiasing bits to one. In this mode, 16-bit input color values in the 5-6-5 RGB format are converted to 6-bit pixel display values through the following brief integer approximation to the standard NTSC luminance-conversion formula, and pixel values = (R >> 2) + (R >> 4) + (G >> 1) + (G >> 4) + (B >> 3). This works by adding values of matching color fields from four neighboring pixels, the neighboring pixels being the top pixel, the bottom pixel, the left pixel and the right pixel of the current pixel. After that, the last right 3 bits are shifted and added to the value of the current pixel shifted by 1 bit. The final output, reduced to 6 bits, is the filtered equivalent of the color mixing process when color anti-aliasing is not enabled. This 6 bit value is stored in the frame buffer 204 of the secondary display controller 106 of the current pixel.

When the color mixing enable bit is zero, the secondary display controller 106 passes the green component of the refresh data present in the other type of primary display controller 104. The other form is materially and visually identical to the green content of the refresh data present in the primary display controller 104. As a result, the secondary display controller 106 outputs the green color field value of the input pixel value of each pixel, unless the monochrome luminance enable bit is set to one.

To ensure minimum power consumption, the secondary display controller 106 supports a process of reducing the frequency of the panel interface Dot clock. The value in this field defines the crystal oscillator divisor minus one, yielding the system Dot clock frequency. The overall video timing is derived from the dot clock. If this field contains zero, the dot clock is equal to the clock 208 frequency, where a value of 7 yields a dot clock of one eighth of the crystal frequency. Using a 54.06 MHz crystal that yields a 50 Hz panel refresh rate with nominally programmed video timing parameters and varying the Dot clock divider alone, the actual panel refresh rate is 50.00 Hz, 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz, 7.14 Hz or 6.25 Hz.

 9 is a time flow diagram for activating secondary display controller 106 from an inactive state in accordance with an embodiment of the present invention. The figure illustrates the method steps performed by the components in chronological order when the status and time of the different components of the display system 200 are the x-axis and the system components are the y-axis. The secondary display controller 106 can receive multiple inputs from the input device. When receiving the input, the fifth pin 218 powers up the secondary display controller 106. The third pin 214 generates an interrupt output after the second display controller 106 is powered up. The secondary display controller 106 then blanks the display device 108. Next, frame buffer 206 performs a display load frame-loading cycle. The secondary display controller 106 begins control of the display device 108 once the frame buffer 206 completes a frame-loading cycle.

In view of the description given above, industry-based implementation details of the invention are included herein, depending on the embodiment. These details include various hardware implementation details including schematic details of various processors, ICs, pins, and registers. The above description will be appreciated by those skilled in the art and will help to implement the invention without undue experimentation.

Secondary Display Controllers 106 DIRECT I / O PIN INTERFACE

Some of the interface operation between the secondary display controller 106 and the processor 104 is inherently time sensitive. In particular, the transition between the primary controller 104 that manages display refresh and the secondary display controller 106 that manages display refresh must be carefully timed in order to prevent display artifacts. The secondary display controller 106 uses fast and direct I / O pin connections to the CS5536 companion I / O device to support them. The CS5536 is a standard processor for I / O operation designed by advanced microdevices. Details describing each pin are included for system interconnection.

DCONIRQ / pin is a low activity scanline interrupt output of the secondary display controller 106 chip, which may be programmed to be inserted into any particular scanline of the video output. The main purpose of this pin is to automatically alert the processor 102 at a fixed time before the start of the next displayed frame. By receiving an interrupt at a known timing that is proportional to the display operation, the primary display controller 104 controlled refresh or secondary display controller 106, without “busy-wait” or polling loops. It is possible to reconfigure the current display state for controlled refresh. See DCONLOAD below for more details.

DCONBLNK is used to help when it is desirable to start a display change asynchronously in the display state. The secondary display controller 106 to be polled will drive the DCONBLNK output under two circumstances. Under the first environment, the DCONBLNK output is low to the tailing edge (end) of the output Vsync timing interval, in that it is driven low at the start of the first output scan line after the active vertical resolution output scan line and driven high again. Keep it. In the second environment, the DCONBLNK output remains high whenever the display of the output of the secondary display controller 106 is disabled.

DCONSTAT is used to indicate whether the primary display controller 104 or secondary display controller 106 is currently managing display refresh. Since display control switching of the secondary display controller 106 is synchronized with display processing, the status pin allows the processor 102 to precisely identify when display switching of the secondary display controller 106 occurs.

DCONLOAD is used to initiate a display load frame loading cycle. This signal directly determines whether the video timing output of the secondary display controller 106 follows the video input, or whether the internal timing register of the secondary display controller 106 is driving the video output. Note that as discussed in the secondary display controller 106 display mode register description above, the actual data output made for the panel in all cases will typically be modified by the secondary display controller 106 chip.

Secondary Display Controller (106) Display Controller ASIC Pinout-2M (1M × 16) DRAM Configuration

Geode display interface pin

Geode pixel clock GFDOTCLK 1

Geode red data GFRDAT0-4 5

Geode Green Data GFGDAT0-5 6

Geode blue data GFBDAT0-4 5

Geode Vsync GFVSYNC 1

Geode Hsync GFHSYNC 1

Geode Display Enable GFDISP_EN1

Geode FP_LDE GFP_LDE 1

Interface Pins for 1M × 16 DRAM

FBRAM Data FBD0-15 16

FBRAM Address FBA0-11 12

FB column address strobe FBCAS / 1

FB Low Address Strobe FBRAS / 1

FBRAM Chip Select FBCS / 1

FBRAM light enable FBWE / 1

FBRAM Clock FBCLK 1

FBRAM Clock Enable FBCLKE 1

Crystal for Secondary Display Controller (106) Self Refresh

Display XTAL In DCONXI 1

Display XTAL Out DCONXO 1

System interface pins

System Reset RESET 1

Secondary Display Controller (106) Interrupt Output DCONIRQ / 1

Request display load command for secondary display controller 106 DCONLOAD 1

Secondary display controller (106) vs. geode / display active DCONLOAD 1

Secondary display controller 106 blanking state DCONBLNK 1

Secondary Display Controller (106) Register I / O SMB Clock DCONSMBCLK 1

Secondary Display Controller 106 Register I / O SMB Data DCONSMBDATA 1

PPTTL / Panel Interface Pins

Panel pixel data 1 D1O0-2 3

Panel pixel data 2 D2O0-2 3

SCLK SCLK 1

DCLK DCLK 1

GOE GOE 1

GCK GCK 1

GSP GSP 1

DINT DINT 1

SDRESET SDRESET 1

DBC DBC 1

INV INV 1

PWST PWST 1

POL1 POL1 1

POL2 POL2 1

Self Test / Boundary Scan BIST0-1 2

Total User I / Os 84

Register Definition:

Register 0: Secondary Display Controller (106) ID + Revision

This 16-bit register is a read-only register that returns the secondary display controller 106 ASIC identifier and calibration number. The first pass of this silicon must return the hexadecimal value of 'DC01'H, and the next calibration must return' DC02'H, etc.

Register 1: Secondary Display Controller 106 Display Mode

Bit 0: pass-through disable

This bit controls whether the secondary display controller 106 will perform any operation on the refresh data. When powered on, this bit is automatically cleared to zero by the secondary display controller 106, which causes the video output to follow the video input directly, and the secondary display controller 106 runs in passthrough mode. do. In this mode, the secondary display controller 106 alone operates as a conventional TFT timing controller (TCON) chip, where the video output is only converted when it is necessary to derive a DETTL compatible output signal for the display panel. To save power, the SDRAM interface port 220 must be completely disabled without even generating the SDRAM clock signal in passthrough mode. In passthrough mode, all other secondary display controller 106 registers and control bits are ignored except for the self test enable bit, which overrides the padthrough mode.

Writing a 1 to the passthrough disable bit enables the general purpose secondary display controller 106 to function, including activation of the SDRAM interface port 220, internal video timing registers, mode configuration bits, and the like.

Bit 1: Secondary display controller 106 sleep mode

A key factor in power efficiency of the secondary display controller 106 is the ability to enter a low power state in which the display device 108 is completely turned off and the frame buffer 206 is set to self-refresh mode. The self refresh mode is known as the secondary display controller 106 sleep mode. Under normal circumstances, the secondary display controller 106 is particularly configured when the auto sleep mode bit is set and the display timeout value video output frame occurs without the occurrence of a display load cycle or when an input signal is received from one or more input devices. The system automatically enters sleep mode as a result of extended inactivity of the system. The secondary display controller 106 then sets this bit and automatically enters the sleep mode.

Alternatively, the processor 102 may need to initialize the switch to the secondary display controller 106 sleep mode. In particular, the processor 102 must manually enter sleep mode when the power switch selects “system off”, when the laptop reed switch is closed, or when a critical low battery level is detected. To enter sleep mode, this bit must be written as '1'.

Since the frame buffer 206 remains in the low power self refresh state and the secondary display controller 106 is in sleep mode, the secondary display controller 106 cannot handle the incoming display load cycle. However, the load pin of the secondary display controller 106 is not ignored. When processor 102 requests a display load cycle and secondary display controller 106 is in sleep mode, an internal state, known as secondary display controller 106 LOAD_MISSED, is set. This state is used to inform the secondary display controller 106 that the data in the frame buffer 206 no longer matches the latest refresh data generated by the processor 102. If the secondary display controller 106 goes out of sleep mode after loading the secondary display controller 106, the display device 108 is automatically emptied and the secondary display controller 106 IRQ for one line of refresh data. Will be driven to generate a secondary display controller 106 LOAD_MISSED interrupt. This allows the processor 102 to rewrite the latest refresh data generated by the processor 102 and then clear the video blanking pin to draw the latest information to the display device 108.

Processing out of the sleep mode may be performed manually or automatically. Under normal circumstances, this bit is automatically cleared upon arrival of ECPWRRQST. In the ECPWRRQST, the secondary display controller 106 receives an input signal from one or more input devices. That is, the video display is restored by pressing a key irrespective of the processor 102, and when the keyboard key, cursor button, or touch pad is activated, the display device 198 is turned on "on the fly". Alternatively, if necessary, the processor 102 may exit the sleep mode or clear the bit to 0 to reinitialize the process of refreshing the display device 108.

Bit 2: auto sleep mode

If this bit is set to 1, the secondary display controller 106 automatically stops display processing after the Display Timeout Value video frame is output without system activity. Whenever the secondary display controller 106 LOAD is high, or when an incoming ECPWRRQST occurs, the internal display timeout register is automatically reset to the value of the display timeout value register. When a display timeout occurs, the secondary display controller 106 automatically sets the secondary display controller 106 sleep mode bit to 1 to enter the sleep mode. If the auto sleep mode bit is zero, the secondary display controller 106 continues to refresh the display device 108 indefinitely. When a display load cycle or ECPWRRQST occurs, the sleep mode can only be entered by writing the secondary display controller 106 sleep mode bit.

Bit 3: Backlight Enable

The backlight enable is used to determine whether the backlight of the display device 108 should be turned on while the display is enabled. This bit is set to 1 to turn on the backlight at any time when the secondary display controller 106 is not in the secondary display controller 106 sleep mode. Note that by setting this bit the backlight can be automatically enabled or disabled, so that the screen saver does not need to turn the backlight enable on or off. If this bit is cleared, the backlight remains disabled whether or not the secondary display controller 106 is in the secondary display controller 106 sleep mode. When the backlight is enabled, with a duty cycle that matches the value of the backlight brightness register, the BACKLIGHT pin is driven high and the DBC pin is driven by a PWM waveform.

Bit 4: video blanking

Video blanking is used to display “black” on the screen without affecting the content of the secondary display controller 106 flame buffer 206, or the power state of the display device 108. This feature is mainly used to determine whether the secondary display controller 106 should exit the sleep mode with the display device 108 displaying the refresh data or with the display device 108 masked off until the next display load cycle. This is markedly used by the secondary display controller 106. Since the secondary display controller 106 cannot record the display load cycles that arrive during the sleep mode, it will automatically set the VIDEO_BLANKING bit when the secondary display controller 106 LOAD goes high during sleep. This ensures that the previous refresh data is not displayed upon wake up. If this bit is written as '1', display device 108 displays "black." If written as '0', the current content of the frame buffer 206 is displayed on the display device 108.

Bit 5: Color-swizzling enable

According to a preferred embodiment of the present invention, the selected display device 108 is a hybrid monochrome / color panel that does not utilize conventional RGB subpixels. Instead, each pixel contains only a single "subpixel value". When used as a reflective panel, ie when the backlight is off, these pixel values represent a gray scale. The resulting image is a monochrome display. When used in the transfer mode, ie when the backlight is on, each pixel represents a single color value from a set of red, green and blue.

The first pixel of the first line of refresh data is red, the second pixel of this line is green, and the third pixel is blue. This pattern repeats along the line. However, note that each successive line is offset from the previous line by one color component. Thus, the first pixel of the second line is green, the second pixel is blue, and the third pixel is red. This pattern repeats along the second line. The first pixel of the third line is blue, the second pixel is red, and the third pixel is green. This pattern repeats along the third line. The above patterns for the first three lines are then repeated in groups of three lines across the entire display panel.

This color pattern helps to eliminate display artifacts, but complicates the system software. The color mixing enable bit, when set to 1, allows the secondary display controller 106 to automatically select the appropriate color field from the input 6-7-6 refresh data. According to the physical panel structure described above, the secondary display controller 106 selects a red input field for the first pixel on the first line, a green input field for the next pixel on this line, and the like. The net effect of color mixing enable is that the secondary display controller 106 automatically takes two thirds of the input refresh data as a result of each output pixel written to the frame buffer 206 having a single six-bit value. To discard it.

If the color mixing enable bit is zero, the secondary display controller 106 simply outputs the six most significant bits of the green color field of each input pixel, unless the monochrome luminance enable bit is set to one. The color mixing mode alone does not require the use of the secondary display controller 106 scanline ring buffer as described below; When both the color mixing and color antialiasing mode bits are set to 1 and active, only the color antialiasing mode requires the use of the chip's ring buffer.

Whenever color mixing mode is active, the secondary display controller 106 COLMODE output pin is driven high. This pin allows the display device 108 to switch its internal panel bias to optimize the display quality to either color or monochrome mode.

Bit 6: Enable color antialiasing

When the color mixing mode is enabled, the color antialiasing mode bit may be set to one. If both bits are set, the color antialiasing mode is activated. In this mode, the color mixing process proceeds as described above, but the resulting output is filtered to prevent color aliasing. This filtering process converts the color values of the current pixel at pixel coordinates (V, H) to the top (V-1, H), bottom (V + 1, H), left (V, H-1), right of the current pixel. In combination with the matching color field from the pixels at (V, H + 1). The process is done by summing the values of the matching color fields from these four neighboring pixels, shifting the result three bits to the right, and adding it to the current value of the pixel, shifted to the right by one bit. . The resulting output, truncated to 6 bits, is the filtered equivalent of the color mixing process when color antialiasing is not enabled. This 6-bit value is stored in the frame buffer 206 of the current pixel.

It is particularly important to emphasize that the color antialiasing process is performed with a 19 bit color value rather than the 6 bit color value which is the output of the color mixing process when the color antialiasing is not enabled. The mathematical process described above is specifically calculated for the color field that is appropriate for the current pixel. That is, if the current pixel has a red color filter, the mathematical processing is summed to combine the red field of the current pixel with the red field of neighboring pixels. The next pixel to the right performs the same function for green color fields, such as the current and neighboring pixels.

To get the proper color field for color antialiasing, two results are immediately apparent. First, it is necessary to use a long ring buffer of two scan lines to perform this process. Second, each element of the ring buffer must hold 19 bits of color data in the 6-7-6 input color format rather than the 6-bit output format.

Implementation Details: The input line buffer is typically a 2x1200 19-bit word. However, once the buffers are implemented, it is very important that they are updated pixel by pixel in the same way as the ring buffers. Otherwise, three full screen lines are needed to perform the color antialiasing function.

Implementation Warning: The above simplified mathematical process is not meant to be an actual implementation but is used to make it easier to understand. For example, in the above, the use of the right shift operator does not mean that any bits are "lost" during the antialiasing process, but rather to specify the alignment of the bits with different color components. For visual display quality, it is essential that the full 10-bit precision be maintained until a complete result is output. Only the final output of the antialiasing process can be truncated to 6 bits by discarding four LBSs. Before truncating the output, the implementation of discarding the least significant bits during the antialiasing calculation is unacceptable.

Bit 7: Solid Color Luminance Enable

As long as the color mixing and color antialiasing bits are zero, the secondary display controller 106 may be placed in the monochrome luminance mode by writing this bit to one. In this mode, again in 6-7-6 RGB format, 19-bit input color values are converted to 6-bit pixel display values through the following simple integer approximation to the standard NTSC luminance conversion equation: pixel value = (R >> 2 ) + (R >> 4) + (G >> 1) + (G >> 4) + (B >> 3)

Unlike the color antialiasing mode, the monochrome luminance function is done solely for the color field of the current pixel. As a result, an on-chip 2-line ring buffer is not used in this mode.

Implementation Warning: The simplified mathematical processing given above is used for ease of understanding and does not imply an actual implementation.

Bit 8: Enable scan line interrupt

Setting this bit to 1 allows the output of the secondary display controller 106 scan line interrupt to be generated during the video scan line programmed into the scan line interrupt value register. This interrupt is activated at the start of the programmed scan line and remains active for one scan line duration in each frame. This sequence continues as long as the scan line interrupt enable bit is one.

Bits 9-11: Dot Clock Dividers

To support the minimum power consumption, the secondary display controller 106 supports the ability to reduce the frequency of the panel interface dot clock. The value in this field specifies the crystal oscillator as the divisor subtractive to yield the system dot clock frequency. All video timings are derived from dot clocks. If this field contains zero, the dot clock is equal to the clock frequency of the crystal, whereas a value of 7 yields a dot clock of one eighth the crystal frequency. By using 4X, 14.31818 MHz crystals and changing only the dot clock divider with the conventionally programmed video timing parameters that yield 50Hz panel refresh rate, 50.00Hz, 25.00Hz, 16.67Hz, 12.50Hz, 10.00Hz, 8.33Hz, The actual panel refresh rate is 7.14Hz or 6.25Hz.

Bit 12-13: Reserved

These read-only bits are reserved.

Bit 14: enable debug mode

If the debug mode bit is written high, two actions take place. First, the LCD panel interface changes to support conventional color LCDs with color subpixels. Second, the SDRAM interface port 220 changes to support 4 MB of SDRAM. In the manufacture of the secondary display controller 106 ASICs, this bit remains cleared to zero.

Bit 15: self test mode

When the power is turned on, the secondary display controller 106 samples the BIST pin to determine if it should enter normal operation, BIST low or self test operation, and BIST high. The state of the BIST pin is copied to self-test mode upon exiting reset. The software may write this bit to 1 to initiate entry into the BIST mode, and write this bit to 0 to restore normal operation. When the secondary display controller 106 is in self test mode and no input video clock is detected, the secondary display controller 106 automatically passes through the white, black, red, green and blue sequences every two seconds. Cycles display output.

Register 2: horizontal resolution

This 16-bit register contains the number of pixels displayed per horizontal line, typically 1200. Due to timing constraints in the primary display controller 104, the secondary display controller 106 may receive more input pixel clocks than the number programmed in this register. If this happens, successive clocks beyond the number of pixels programmed into this register must be ignored until the next HSync pulse occurs. As a result, the number programmed into this register must match the memory pitch after pixel packing, from one line to the next, as stored in frame buffer 206.

Register 3: Horizontal Full

This 16-bit register contains the total number of dot clocks per horizontal scan line.

Register 4: Horizontal Sync Start and Width

This 16-bit register contains two 8-bit registers. The most significant byte in the register contains the horizontal sync start register. After the "horizontal resolution", a dot clock occurs on each line. HSync is generated after the “HSync Start” additional clock is generated. The least significant byte in this register contains the number of clocks that will keep HSync active once the HSync is created.

Register 5: vertical resolution

This 16-bit register contains the total number of lines displayed per video frame. This typically includes the value 900.

Register 6: vertical full

This 16-bit register contains the total number of scan line durations that occur per video frame. Clearly, the TFT panel refresh rate at Hz is equal to the value of the register.

Dot Clock / (Horizontal Full * Vertical Full)

Register 7: vertical sync start and width

This 16-bit register contains two 8-bit registers. The most significant byte in the register contains the vertical sync start register. After the vertical resolution line is displayed, a “VSync Start” VSync is generated after an additional number of scan lines are generated. The least significant byte in this register is a scan in which VSync must remain active once the VSync is created. Contains the number of lines.

Register 8: Display Timeout Value

To reduce power consumption, the secondary display controller 106 has the ability to automatically power off the display output to enter the secondary display controller 106 sleep mode. This register contains the number of output video frames before automatic power off occurs.

Register 9: Scan Line Interrupt Value

In order to properly synchronize the processor 102 video output with the secondary display controller 106 video output, the secondary display controller 106 may cause display processing by causing the system software to generate a processor 102 interrupt on any given line of display. Have the ability to be motivated. This register records the number of output video scan lines while an interrupt must be generated.

Register 10: Backlight Brightness

Only the top four bits of this register are used. The lower 12 bits are undefined and must be ignored. The backlight brightness register is used to set the duty cycle of the DBC output pin. A value of 00H corresponds to a duty cycle of 0 percent and a value of 0FH corresponds to a duty cycle of 100 percent. The median value can be used to set a specific brightness level. Note that if the backlight enable bit is set to 1 and the panel is currently enabled, the DBC pin can only be driven by a PWM waveform.

Register 11-127: Reserved

These registers are reserved.

In view of the above, according to another embodiment, the industry-based implementation details (secondary display controller version 0.8) of the present invention are included here.

Secondary Display Controller (106) DIRECT I / O PIN INTERFACE

Some of the interface operations between the secondary display controller 106 and the processor 102 are, in fact, executed first. In particular, the transition between the primary display controller 104 management display refresh and the secondary display controller 106 management display refresh should be carefully timed out to prevent display artifacts. In supporting these activities, the secondary display controller 106 uses a fast direct I / O pin connection to the CS5536 Companion I / O device. Details of the interconnections in the system are described in the following pin descriptions.

DCONBLNK-CS5536 GPIO12

DCONBLNK is used to assist the processor 102 in synchronizing its video timing with the secondary display controller 106 video so that there is no problem from the secondary display controller 106 control refresh to the processor 102 control refresh. You can certainly transition. To be polled, the secondary display controller 106 drives the DCONBLNK output in two environments. First, the DCONBLNK output is driven low at the beginning of the first output scan line following the active vertical resolution output scan line, held low to the end edge (end) of the output VSync timing interval, and driven high again there. Second, whenever the secondary display controller 106 is in the secondary display controller 106 sleep mode, the DCONBLNK output remains high.

DCONLOAD-CS5536 GPIO11

DCONLOAD controls the source of the refresh cycle of the video display. This signal indicates whether the primary display controller 104 is managing display refresh or the interior of the secondary display controller 106 with the video timing output of the secondary display controller 106 following the video input. Indirectly determines whether the timing register is driving the video output. In each case, as discussed in the description of the secondary display controller 106 display mode register, the actual data output to the panel is normally changed by the secondary display controller 106 chip. This is excluded when the secondary display controller 106 proceeds in pass-through mode, in which case the data output of the secondary display controller 106 may be reduced to 6 of the green video data input, as is appropriately delayed for proper signal paging. Simply reflect the bit cut.

DCONIRQ / -CS5536 INTB #

The DCONIRQ / pin is a low active interrupt request output from the secondary display controller 106 chip. This signal is driven in three environments. First, upon completion of the display load period, DCONIRQ / is driven to notify the current secure processor 102 to disable the primary display controller 104. In addition, the secondary display controller 106 may be programmed to generate an interrupt on any particular scan line of the video output. The primary purpose of this use is to automatically warn the processor 102 at a given time before the start of the next displayed frame. Upon receiving an interrupt at a known timing for the display operation, processor 102 may restart its video in synchronization with the current display of secondary display controller 106 without display artifacts. Scan-line interrupt capability can be used for conventional purposes such as display animation.

When processor 102 updates the screen and executes the display load sequence, the final DCONIRQ / interrupt source occurs, but then the secondary display controller 106 is in sleep mode. The secondary display controller 106 is later woken up by ECPWRRQST to start up the panel normally and automatically restart the display refresh. However, in this case, instead of activating the panel, the secondary display controller 106 maintains the video in a blank state by setting the video blanking bit to generate a DCONLOAD_MISSED interrupt and update it for display. Notify 102. Note that after updating the display, the processor 102 has an obligation to clear the video blanking bit (writing the video blanking bit clears the internal DCONLOAD_MISSED status flag).

DCONSTAT0..1-CS5536 GPIO5 & GPIO6

The DCONSTAT pin is used to inform the processor 102 of the fast state and, in particular, to identify the cause of the DCONIRQ interrupt. The DCONSTAT0..1 pin is encoded as follows:

00: Scan-line interrupt generated while processor 102 is in refresh control, i.e., in full-on mode. This state is used to indicate that any interrupts reached are related to conventional scan-line interrupts, i.e. animations and the like.

01: Scan-line interrupt generated in state 2 (secondary display controller 106 mode). This state is used in conjunction with the reinitialization of the processor 102 video output to begin synchronizing the video timing of the processor 102 with the video timing of the secondary display controller 106. After this interrupt, processor 102 is expected to poll the DCONBLNK pin to perform fine timing synchronization.

10: Interrupt generated DisplayLoad completed. This condition indicates that the secondary display controller 106 has finished recording the video frame, and therefore the processor 102 disables the clock and output of the on-chip primary display controller 104 for maximum power saving. Notifies processor 102 that it is safe.

11: DCONLOAD_MISSED interrupt generated while excited from sleep mode. As described above, if the processor 102 is dragged to the screen while the secondary display controller 106 is in the sleep mode, the screen is delayed in waking up. This interrupt executes the display load period and then signals the secondary display controller 106 to clear the video blanking bit in the secondary display controller 106 mode register to enable display.

This encoding may seem a bit unclear but reflects what is needed to put the maximum state information on the available pin outputs.

ECPWRRQST-System Activity Monitor

The ECPWRRQST pin is used to "wake up" the secondary display controller 106 from sleep mode. Whenever a keyboard, touch pad, or cursor key event occurs, the system's built-in controller pulses this pin "high." The rising edge of ECPWRRQST causes the secondary display controller 106 to automatically activate the display to automatically initialize the display refresh (see the description given above in the DCONLOAD_MISSED interrupt of the critical exception). When the secondary display controller 106 enters sleep mode automatically or manually, it remains in sleep mode until the sleep mode bit of the secondary display controller 106 is cleared to zero or until the ECPWRRQST pin is toggled high. , The sleep mode bit of the secondary display controller 106 is cleared.

Note that the ECPWRRQST reached while the display is active has only one effect-to reset the internal display timeout register to the value of the display timeout value register.

The minimum duty cycle for ECPWRRQST activation is ~ 100nS (this pin does not need to be debounced or filtered).

Secondary Display Controller (106) Register Definition

Register index default

Secondary Display Controllers 106 1D & RevisionO DCO1H

Secondary Display Controller 106 Display Mode 1 0012H

Horizontal resolution 2 0458H (120O decimal)

Horizontal Full 3 04E8H (1256 Decimal)

Horizontal Sync 4 1808H (24, 8 decimal)

Vertical resolution 5 0340H (900 decimal)

Vertical Full 6 O390H (912 decimal)

Vertical Sync 7 0403H (4, 3 decimal)

Display timeout 8 FFFFH

Scanline Interrupt 9 000H

Backlight Luminance 10 XXXFH

Reserve 11-127

Secondary Display Controller (106) User I / O Pin Definitions

Secondary Display Controllers (106) ASIC Pinout-1M (512K x 16)

SDRAM Configuration

Geode display interface pin

Geode Pixel Clock GFDOTCLK 1

Geode Red Data GFRDAT0-5 6

Geode Green Data GFGDAT0-6 7

Geode blue data GFBDAT0-5 6

Geode VSync GFVSYNC 1

Geode HSync GFHSYNC 1

Geode FP LDE GFP_LDE 1

Interface Pins for 512K x 16 SDRAM

FBRAM Data FBDO-15 16

FBRAM address FBDA0-10 11

FB column address strobe FBCAS / 1

FB Low Address Strobe FBRAS / 1

FB data mask FBDM0-1 2

FBRAM Chip Select FBCS / 1

FBRAM light enable FBWE / 1

FBRAM Clock FBCLK 1

FBRAM Clock Enable FBCLKE 1

Modifications for Secondary Display Controller

106 Self Refresh

Display XTAL In DCONXI 1

Display XTAL Out DCONXO 1

System interface pins

System Reset RESET 1

EC Power On Request ECPWRRQST 1

Secondary Display Controller 106

Interrupt output DCONIRQ / 1

Secondary Display Controller 106

Display Load Command Request DCONLOAD 1

Secondary Display Controller 106 Status

Pin DCONSTAT 2

Secondary Display Controller 106

Blanking State DCONBLNK 1

Secondary Display Controller 106

Register I / O SMB Clock DCONSMBCLK 1

Secondary Display Controller 106

Register I / O SMB Data DCONSMBDATA 1

DETTL / Panel Interface Pins

Panel Pixel Data 0 DO00-DO01 3

Panel pixel data 1 DO10-DO11 3

Panel pixel data 2 DO20-DO21 3

Source Dot Clock SCLK 1

Data Interface Polarity Control REV1-2 2

Graphic Output Enable (Gate

Driver Enabled) GOE 1

-INV 1

CPV 1

-STV 1

-FSTH 1

-BSTH 1

TP 1

LCD Backlight Enable BACKLIGHT 1

Display Backlight Control (PWM) DBC 1

Driver Polarity Signal 1 POL1 1

LCD VDD Enable VDDEN 1

Burn-In / Test Mode AGMODE 1

Color / Monochrome Panel Bias Select COLMOD 1

Total User I / O 94

Secondary Display Controller (106) Register Definition

The primary programming interface to the secondary display controller 106 chip is a 100KHz serial SMBUS interface, which allows read & write access to the chip's internal configuration registers. All of these registers are 16 bits long and access is only supported as 16 bit registers. Accessing these registers in any other mode is undefined and can produce unexpected results. In particular, a 32-bit SMBUS cycle is used to accurately communicate with the secondary display controller 106, the first 8 bits specifying the read / write mode bits as well as the SMBUS address that is always 0DH in this implementation. The next 8 bits supply the register number being communicated with, and the remaining 16 bits contain the contents of the desired register. To understand the communication between the secondary display controller 106 and the system, the secondary display controller 106 is connected to the SMBUS port of the AMD CS5536 I / O chip at SMBUS address 0DH.

Register 0: Secondary Display Controller (106) ID + Revision

This 16-bit register is a read / only register and returns the secondary display controller 106 ASIC identifier and revision number. The first pass of this silicon should return the hexadecimal number of 'DC01'H, the next revision should return' DC02'H, and so on.

Register 1: Secondary Display Controller (106) Display Mode

Bit 0: Pass-Through Disable

This bit controls whether the secondary display controller 106 performs any operation on the refresh data. At startup, this bit is automatically initialized to zero by the secondary display controller 106, causing the video output to come immediately after the video input, and the secondary display controller 106 is to proceed in pass-through mode. In this mode, the secondary display controller 106 operates solely as a conventional TFT timing controller (TCON) chip, and the video output is only converted when needed to drive a DETTL-compatible output signal for the display panel. For power-saving purposes, the SDRAM interface port 220 must be completely disabled during pass-through mode, even when no SDRAM clock signal is generated. In pass-through mode, all other secondary display controller 106 registers and control bits are ignored except for the self-test enable bit, giving priority to pass-through mode.

Writing a 1 to the pass-through disable bit enables the normal secondary display controller 106 to function and activates the SDRAM interface port 220 as well as the active, mode-configured bits, etc. of the internal video timing registers. Activity.

Bit 1: Secondary Display Controller 106 Display Enable

When the reset process is completed by the secondary display controller 106, the display enable bit is initialized to one. This steady state enables the output of the panel interface of the secondary display controller 106 to be driven, as defined by the current chip mode. By writing zeros to this bit, the video output is immediately driven asynchronously with a low power blank. Thus, setting this bit enables video output, but the re-enable process is synchronized to keep the panel driver in a low power state until the end edge of the next Vsync output-timing interval. At this point, the video driver is turned on and remains on until the secondary display controller 106, display enable, is cleared again.

Note that the secondary display controller 106 automatically clears this bit so that the display is blanked.

If the display timeout enable bit is set, a display timeout value video output frame occurs without display load cycle occurrences.

Bit 2: Enable color mixing

According to an embodiment of the present invention, the selected display device 108 is a hybrid monochrome / color panel that does not use conventional RGB subpixels. Instead, each pixel contains only a single "sub-pixel value". When used as a reflective panel, when the backlight is disabled, these pixel values represent gray scales and the resulting image is a monochrome display. When used in transmissive mode, when the backlight is on, each pixel represents a single color value among a set of red, green, and blue.

If the first pixel of the first line of refresh data is red, the second pixel is green and the third pixel is blue. This pattern is repeated over that line. However, note that each subsequent line is offset from the preceding line by one color component. Therefore, the first pixel of the second line is green, the second pixel is blue, and the third pixel is red. This pattern is repeated over the second line. The first pixel of the third line is blue, the second pixel is red, and the third pixel is green. The pattern of the first pixel is repeated over the third line. The patterns described above for the first three lines are repeated in groups of three lines over the entire display pattern.

This color pattern helps to eliminate display artifacts, but complicates the system software. The color mixing enable bit, when set to 1, enables the secondary display controller 106 to automatically select the appropriate color field from the input 6-7-6 refresh data. After the physical panel outlined above, the secondary display controller 106 selects a red input color for the first pixel of the first line, a green input color, etc. for the next pixel of the line. The net effect of the color mixing enable function is that the secondary display controller 106 automatically discards two thirds of the input refresh data, resulting in each output pixel written to the frame buffer 206 having a single 6-bit value. Have

When the color mixing enable bit is zero, if the monochrome luminance enable bit is not set to zero, the secondary display controller 106 simply outputs the green color field value of the input pixel for each pixel. Mixed color mode is itself a secondary display controller 106 scan-line ring buffer, because the mixed color as well as the color antialiasing mode bits are enabled only when in the color antialiasing mode, requiring the use of the chip's ring buffer. Note that it does not require the use of.

Bit 3: Enable color antialiasing

When the mixed color mode is enabled, the color antialiasing enable mode bit can also be set to one. When both bits are set, the color antialiasing mode is said to be activated. In this mode, mixed color processing proceeds as described above, but the output of the result is filtered to prevent color antialiasing. This filtering process changes the color values of the current pixel in pixel coordinates (V, H), above (V-1, H), below (V + 1, H), left (V, H-1). , By combining with the matching color field from the pixels on the right (V, H + 1). This involves adding a matching color field to the value of four adjacent pixels, shifting the result to the right by three bits, and adding it to the value of the current pixel shifted to the right by one bit. The resulting output, truncated to 6 bits, is filtered to be equivalent to the blending process when color antialiasing is not enabled. This 6-bit value is stored in the frame buffer 206 of the current pixel.

When color antialiasing is not enabled, it is particularly important to emphasize that the color antialiasing process is performed with a 16-bit color value rather than the 6-bit color value that is the output of the mixed color process. The calculation described above is calculated in particular on the color field suitable for the current pixel. That is, if the current pixel has a red color filter, the equation combines the red fields of adjacent pixels with the red fields of the current pixel. The next pixel performs the same function to the right on a green color field, such as the current and neighboring pixels.

In order to obtain a color field suitable for color antialiasing, two facts are evident. First, it is necessary to utilize a two scan line length ring buffer to perform the processing. Second, each element of the ring buffer must maintain 16-bit color bit data in the 5-6-5 input color format, not the 6-bit output format.

Implementation Details: The input line buffer is typically 2 x 1110 words long or 2 x 830 words long, depending on whether the display is driven in longitudinal or lateral mode. However, once the buffer is executed, it is important to update based on the pixel ring buffer. Or, to run the color antialiasing function, three full screen lines are required.

Execution Warning: The simplified calculations given above are used for ease of understanding and are not intended to convey actual execution. For example, the use of the left shift and right shift operators is intended to specify the alignment of bits from other color components and does not mean that any bits are "lost" during the antialiasing process.

Prior to output truncation, the execution of discarding the least significant bit during antialiasing calculations is not acceptable.

Bit 4: monochrome luminance enable

If the mixed color and color antialiasing bit is 0, by writing 1 to this bit, the secondary display controller 106 can be placed in monochrome luminance mode, and the 16-bit input color value in the 5-6-5 RGB format is standard NTSC. It is converted to a 6-bit pixel display value by the following simple integer that approximates the luminance conversion equation.

Pixel value = (R >> 2) + (R >> 4) + (G >> 1) + (G >> 4) + (B >> 3)

Note that unlike in color antialiasing mode, the monochrome luminance function can only work in the color field of the current pixel. As a result, the on-chip two-line ring buffer is not used in this mode.

Execution Warning: The simplified calculations given above are used for ease of understanding and are not intended to convey actual execution. For example, the use of the left shift and right shift operators is intended to specify the alignment of bits from other color components and does not mean that any bits are "lost" during the luminance conversion process. For visual display quality, it is essential that the overall 10-bit accuracy be maintained until the finished result is output. Only the final output of the luminance transform can be truncated to 6 bits. Before output truncation, the execution of discarding the least significant bit during the luminance conversion is not acceptable.

Bits 5-7: Dot Clock Dividers

To support the minimum power drain, the secondary display controller 106 supports the ability to reduce the frequency of the panel interface dot clock. To calculate the system dot clock frequency, the value of this field specifies a crystal oscillator divisor minus one. All video timings are driven from dot clocks. If this field contains zero, the dot clock is equivalent to the clock frequency of the crystal, while a value of 7 yields a dot clock of frequency 1/8 of the crystal. By changing only the dot clock divider using a 54.06 MHz correction with a normal programmed video timing parameter that yields a 50 Hz panel refresh rate, the result is 50.00 Hz, 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz. The actual panel refresh rates of 7.14 Hz and 6.25 Hz are obtained.

Implementation Details: Using a 2X memory clock PLL as the input clock source for the dot clock divider is one possible way to simply generate a 50 percent duty cycle dot clock with all divisors.

Bit 8: Video autosync mode

If this bit is set, the secondary display controller 106 automatically resets all internal video timing counters every time the display load sequence is initialized, i.e., when it encounters the end edge of the first Vsyncln pulse. This mode is for use when the Vsyncln and VsyncOut frequencies are programmed to be the same. Otherwise, this mode should be used with caution.

For example, if the dot clock divisor of the secondary display controller 106 is programmed to support a 25 Hz panel refresh rate, but the system's primary display controller 104 is configured for a 50 Hz output rate, then the secondary display controller Before the video timer of 106 is reset, only the first ½ panels are refreshed. By driving the input and output frequencies at the same rate, such artifacts can be avoided. However, to support the use of mixed frame rates, one can further apply to use the scan line interrupt capability of the secondary display controller 106.

When the secondary display controller 106 pays attention to the video input port, that is, when the display load sequence is being processed, only video auto sync can function. This prevents display problems that may occur when the output of the re-initializing secondary display controller 106 suddenly interferes with the video refresh of the secondary display controller 106.

Bit 9: Enable display timeout

When this bit is set to 1, the secondary display controller 106 automatically stops display processing.

Display Timeout Value When a video frame is output without the display load sequence occurring, display load is executed to automatically reset the internal timeout counter to the value of the display timeout value register. When this bit is set to 0, the secondary display controller 106 continues the display output refresh separate from the display load period.

Bit 10: enable scanline interrupt

Setting this bit to 1 enables the secondary display controller 106 scanline interrupt output to be generated during the video scan line and is programmed into the scanline interrupt value register. This interrupt is active at the beginning of the programmed line and active for one line of each frame. This sequence continues while the scan line interrupt enable bit is one.

Bit 11-14: Spare

This read only bit is reserved and always returns to a value of zero upon reading.

Bit 15: self-test mode

At startup, the secondary display controller 106 samples the BIST0 pin to determine whether it has entered normal operation, whether BIST0 is low, self-test operation or BIST0 is high. The state of the BIST pin is copied to the self-test mode pin when excited by reset. The software can also initialize the input to the BIST mode by writing this bit to 1, and return to normal operation by writing this bit to zero.

Various embodiments of the present invention ensure that power consumption is reduced while the display system is running. The secondary display controller can automatically refresh the display device regardless of the processor and primary display controller, thus eliminating the need for continuous processor intervention. The primary and secondary display controllers and display devices can be turned off for extended periods of inactivity, resulting in significant savings in power consumption of the display system.

Various embodiments of the present invention provide an ideal system for using electronic devices in cost and power sensitive applications without requiring expensive dedicated hardware.

As described herein, any of the systems or components thereof may be embedded in the form of a computer system. Typical examples of computer systems include general purpose computers, programmed microprocessors, micro-controllers, peripheral integrated circuit devices and other devices or an arrangement of such devices capable of carrying out the steps constituting the method of the present invention.

Computer systems include computers, input devices, display units and the Internet. The computer includes a microprocessor and is connected to a communication bus. The computer also includes memory, and may include random access memory (RAM) and read only memory (ROM). The computer system also includes a storage device, which may be a removable storage device such as a hard disk drive or a floppy disk drive, an optical disk drive, or the like. The storage device may also be other similar means of loading a computer program or instruction into the computer system.

The computer system executes a set of instructions stored in one or more storage devices to process input data. The storage device may also hold desired data or other information, and may be an information source or physical memory device residing in the processor.

The instruction set may include various instructions that direct the processor to execute a particular task, such as the steps that make up the method of the present invention. The instruction set may be in the form of a software program. The software may be in various forms such as system software or application software. In addition, software may be in the form of a set of separate programs, program modules having larger programs, and portions of program modules. The software may include modular programming in the form of object-oriented programs. Processing of input data by the processor may be based on user instructions, the results of preprocessing, or requests generated by other processors.

While embodiments of the invention have been discussed and described, the invention is not limited to these embodiments. Many variations and modifications may be considered without departing from the scope of the invention as set forth in the claims.

As described above, according to the present invention, a method and system for a display system for driving a display device can be obtained, and a method and system for driving a display device without processor interference can be obtained. A method and system can be obtained that can reduce power consumption while being refreshed, as well as a method for synchronizing primary and secondary display controllers, as well as eliminating the need for expensive dedicated hardware. Can be used for price and power sensitive applications.

Claims (28)

A method of reducing power consumption of a display subsystem in a computer unit including a processor, a primary display controller, and a secondary display controller, the method comprising: a. If the new refresh data is not generated by the processor, switching the primary display controller from an active state to an inactive state; And b. Instructing the secondary display controller to consume substantially less power than the primary display controller to refresh a display device within the display subsystem, independent of the primary display controller and the processor. , A method of reducing power consumption of a display subsystem. The method of claim 1, further comprising converting refresh data in the primary display controller into a reduced bit form, wherein the reduced bit form is visually indistinguishable from the refresh data in the primary display controller. A method of reducing power consumption of a display subsystem. The method of claim 2, wherein the reduced bit form is stored in a frame buffer, and the frame buffer is connected to the secondary display controller. The method of claim 2, wherein converting the refresh data in the primary display controller into a reduced bit form: a) processing a red bit of refresh data in the primary display controller to form a reduced bit shape, wherein the red bit and the reduced bit shape of the refresh data of the primary display controller are formed in the display device; Corresponds to the first pixel of the first line; b) processing the green bits of the refresh data in the primary display controller to form a reduced bit form, wherein the green bits and the reduced bit forms of the refresh data of the primary display controller are formed in the display device. Corresponds to the second pixel of the first line; c) processing the blue bits of the refresh data in the primary display controller to form a reduced bit form, wherein the blue bits and the reduced bit forms of the refresh data of the primary display controller are formed in the display device. Corresponding to the third pixel of the first line. The display of claim 4, further comprising processing the refresh data in the primary display controller for each pixel of each line of the display device, wherein the color specification for each horizontal offset is different from the immediately adjacent line. A method of reducing power consumption of a subsystem. The method of claim 2, further comprising anti-aliasing the reduced bit shape, wherein the anti-aliasing of the reduced bit shape comprises determining a value of each pixel of each line of the display device. And the anti-aliased value of each said pixel is determined by calculating a value of a pixel adjacent to a value of a current pixel. The method of claim 2, wherein processing the refresh data in the primary display controller to form a reduced bit form includes converting input color information of the refresh data in the primary display controller into a monochrome display. And wherein the monochrome display is consistent with a person's brightness perception of the refresh data in the primary display controller. 3. The method of claim 2, wherein processing the refresh data in the primary display controller to form a reduced bit shape comprises transferring the green component of the refresh data in the primary display controller to another form. And wherein said other form is substantially visually identical to the green content of said refresh data in said primary display controller. The method according to claim 1, a. Instructing the primary display controller to enter an active state from an inactive state when the processor generates new refresh data; b. Instructing the secondary display controller that new refresh data has been generated by the processor; And c. Instructing the primary display controller to refresh the display device. 10. The method of claim 9, further comprising converting a single refresh data frame in the primary display controller into reduced bit form, wherein the converting step is immediately before instructing the secondary display controller to refresh the display device. And wherein said converting step thereby improves the efficiency of said display processing. The method of claim 1, wherein the secondary display controller can enter an inactive state, wherein the inactive state is entered by disabling the refresh of the display device without the processor interference. . The method of claim 11, wherein the secondary display controller is able to completely turn off the display device. The method of claim 11, wherein the secondary display controller is capable of autonomously switching from inactive to active when receiving input signals from one or more input devices, wherein the one or more input devices are connected to the computer unit, and the input And a signal is received by the secondary display controller without the processor interference. The method of claim 13, wherein the input signal from the one or more input devices connected to the computer unit is received by a pin in the secondary display controller. The method of claim 11, wherein the secondary display controller is capable of autonomously switching from inactive to active when receiving input signals from one or more input devices, wherein the one or more input devices are connected to the computer unit, and the input And a signal is received by the secondary display controller via the processor interference. The method of claim 1, wherein the method of reducing power consumption of a display subsystem within a computer unit is implemented by a data processor in accordance with computer-executable instructions stored on a computer readable medium. Way. A system for reducing power consumption of a display subsystem within a computer unit, a) a processor for generating refresh data to be displayed by a display device in the display subsystem; b) a primary display controller for refreshing the display device with the refresh data; And c) a secondary display controller for refreshing the display device with the refresh data independent of the primary display controller and the processor, wherein the secondary display controller comprises: i. And a frame buffer to store a refresh frame for refreshing the display device independent of the primary display controller and the processor. 18. The apparatus of claim 17, wherein the secondary display controller further comprises an input port for receiving the refresh data in the primary display controller for each pixel of each line in the display device, wherein the refresh data is provided to the processor. Generated by the system to reduce power consumption of the display subsystem. 18. The method of claim 17, wherein the secondary display controller further comprises an output port connected to a compatible thin film transistor (TFT) panel row and column driver integrated circuit (IC) in the computer unit, wherein the TFT panel row and column driver IC Provides a reduced bit form to the display device through an output port, wherein the reduced bit form is not visually indistinguishable from the refresh data even though fewer than 1/3 bits are used to represent refresh data. And a form is used to refresh the display device independent of the processor. 18. The system of claim 17, wherein the secondary display controller further comprises one or more clocks running in synchronization with one or more clocks of the primary display controller. The method of claim 17, wherein the secondary display controller, a. A first pin that determines which of the two display controllers to refresh the display device, wherein the primary display controller refreshes the display device when the first pin is active, and the secondary display controller is configured to refresh the display device. Refresh the display device when one pin is inactive; b. A second pin set to an active state when the secondary display controller is in an inactive state; c. A third pin for driving the secondary display controller from the inactive state to an active state when the processor receives one or more inputs from one or more input devices connected to the processor; And d. And a fourth pin for facilitating communication of the secondary display controller to the processor. The system of claim 21, wherein the secondary display controller further comprises a fifth pin for receiving an input signal from the one or more input devices. The method of claim 17, wherein the secondary display controller, a. And a processing module for processing the refresh data in the first display controller to form a reduced bit shape. Iii. And a determination module for determining the value of each pixel of each line of the display device. A system for reducing power consumption of a display subsystem within a computer unit, a. A processor for generating refresh data to be displayed by a display device in the display subsystem; b. A primary display controller for refreshing the display device with the refresh data; c. A frame buffer for storing a refresh frame for refreshing the display device; And d. And a secondary display controller for refreshing the display device with the refresh data irrespective of the primary display controller and the processor, wherein either the primary or secondary display controller is dynamically commanded to refresh the display device. , A method of reducing power consumption of a display subsystem. a. An input port for receiving refresh data in the primary display controller for each pixel of each line in the display device connected to a transistor-transistor logic (TTL) compatible thin film transistor (TFT) display controller; b. An output port connected to the compatible TFT panel row and column driver integrated circuit (IC) to support a display output to the compatible TFT display; c. A frame buffer for storing a refresh frame for refreshing the display device regardless of the primary display controller and the processor; d. A synchronous dynamic random access memory (SDRAM) interface port connected to the frame buffer; And e. And one or more clocks for refreshing the display device. The method according to claim 25, a. A first pin that determines which of the two display controllers to refresh the display device, wherein the primary display controller refreshes the display device when the first pin is active, and the secondary display controller is configured to refresh the display device. Refresh the display device when one pin is inactive; b. A second pin set to an active state when the secondary display controller is in an inactive state; c. A third pin for driving the secondary display controller from the inactive state to an active state when the processor receives one or more inputs from one or more input devices connected to the processor; And d. And a fourth pin for facilitating communication of the secondary display controller to the processor. 27. The secondary display controller of claim 26, further comprising a fifth pin for receiving an input signal from the one or more input devices. The method of claim 26, a. And a processing module for processing the refresh data in the first display controller to form a reduced bit shape. Iii. And a determination module for determining a value of each pixel of each line of the display device.

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