TWI437433B - Self-refreshing display controller for display devices in a computational unit - Google Patents

Description

Self-renewing display controller for display devices in a computing unit

The present invention relates to the field of display devices within computing units. More specifically, the present invention relates to a method and system for updating a display device within a computing unit.

The present invention claims US Provisional Patent Application No. 60/785,066, entitled "Self-Updating Display Controller for Laptops", the application date is March 23, 2006, the contents of which are hereby incorporated by reference. Incorporate into the case.

The present application is also incorporated by reference in its co-pending application, US Provisional Patent Application No. US 60/785, 065, filed Jan. 23, 2006, Mark J. Foster, entitled 'Dual Display Control Artifact-Free Transitions Between Duel Display Controller and US Provisional Patent Application US 60/906,122 (Application date is March 9, 2007, Mark F. Foster ), the name is "Artifact-Free Transitions Between Duel Display Controller" and other content is incorporated into the case.

The computing unit utilizes a display device to present the data to the user. The display device is an interface between the computer and the user. Display devices include, for example, but are not limited to, cathode ray tube (CRT) display screens, liquid crystal display (LCD) screens, plasma screens, and organic light emitting diodes (OLEDs). The display controller located within the computing unit includes an input signal from the processor. The display controller processes the input signals and provides updated data for updating the display device.

The update data is an update memory stored in the display controller. In some systems, the display controller's update memory is integrated with the processor RAM. This is a known Unified Memory Architecture. In other systems, the display controller has an update memory RAM controller that is proprietary but separate from the processor RAM. The update data in the update memory includes the color values of each pixel present in each line of the display device. The total amount of memory required to store updated data depends on the resolution of the display device. This resolution can be defined as the physical value that forms the rank of the displayed image. In addition, the total number of memory required to update the display device depends on the color depth. The color depth includes the number of bits needed to represent the color of a single pixel. In the joint memory structure, the display device accesses the update data directly from the update memory of the processor. The processor drives a much larger amount of memory to support the basic input/output system (BIOS), operating system (OS) and various applications. The amount of memory required to operate the processor is typically greater than the amount of memory required by the display controller to update the display device within the joint memory structure.

The amount of power required to drive the update memory can be represented by P = CV^2F. Here, C denotes the capacitance of the memory capacitor, and V denotes a voltage, and F denotes a memory clock calculation frequency. The amount of power consumed to update memory is directly proportional to the size of the memory. In addition, additional power is required to operate a memory computing unit for sharing the processor's primary memory resources between the processor and the display device. As a result, the display device is updated in the joint memory structure, and the electric consumption is more and more increased.

Moreover, in many computing units, the display controller is integrated with the processor. These computing units do not allow the processor to shut down when the display device no longer needs to be updated because there is no user input action. This is due to the general electronic products associated with dual-purpose memory systems. As a result, the display device consumes more power when updated, even if the processor is inactive.

From the viewpoint of the above data, there is a need for a method and system for avoiding the use of a large amount of memory for updating a display device. These methods and systems should also be able to update the display device without the power required to operate the high speed memory architecture unit. In addition, such methods and systems should cause the processor to shut down when the display results do not need to be updated. In addition, there is a need for a method and system that can automatically turn off the display device power when it is not operating for a long period of time, and can also restart the display device when the user operates again in addition to the operation of the processor.

Accordingly, it is a primary object of the present invention to provide a method and system for a display system to drive a display device.

Another object of the present invention is to provide a method and system for driving a display device without the intervention of a processor.

It is still another object of the present invention to provide a method and system for achieving power saving purposes when a display device is updated.

Yet another object of the present invention is to provide a method of synchronizing primary and secondary display controllers.

Yet another object of the present invention is to eliminate the need for expensive and complex hardware, thereby making the invention applicable to applications that are cost sensitive and power consuming.

To achieve the above and other objects, the present invention provides a method and system for a display system to drive a display device. The display system includes a processor, a primary display controller, a primary display controller, and a display device. The primary display controller receives display data sent from the processor and drives the display device when the processor sends a new display. When the same display screen is continuously sent by the processor, the control of the display device is taken over by the secondary display controller, so that the low-power operation is optimized.

The present invention provides a method, system and computer program product for driving a display device in a display sub-system. The display subsystem is located in a computing unit and includes a processor, a primary display controller, a primary display controller, a picture buffer for the primary display controller, and a display device. The display device can be driven by a primary display controller or a secondary display controller. The primary display controller drives the display device when the processor generates new update data, and in addition the primary display controller transmits the display data to the secondary display controller. The secondary display controller may reflect the updated data and update the display device display content, or may perform an operation of updating the data, and then update the display device display content. When the processor generates the same update data for a predetermined time interval, the control of the display device changes from the primary display controller to the secondary display controller. The screen to be displayed is then recorded in the secondary display controller screen buffer.

The first figure is a schematic diagram of the architecture described in the specific embodiments of the present invention. The architecture includes a display subsystem 100 that can be located within the computing unit. The computing unit is, for example, a laptop, a palmtop, a desktop, a computer, a mobile phone or a personal digital assistant (PDA). The display subsystem 100 includes a processor 102, a primary display controller 104, a primary display controller 106, and a display device 108. Display device 108 includes, but is not limited to, a liquid crystal display (LCD) screen, a cathode ray tube (CRT) display screen, and a plasma screen. Processor 102 is a typical central processing unit (CPU) located within a computing unit. The primary display controller 104 and the secondary display controller 106 can be a conventional Video Graphics Array (VGA) or other type of controller or an application specific integrated circuit controller (ASIC). The processor 102 controls the primary display controller 104 and the secondary display controller 106.

The second figure is a schematic illustration of the various components within the secondary display controller 106 in accordance with an embodiment of the present invention. The secondary display controller 106 supports various interfaces. The first interface is an input port 202 for receiving update data from the primary display controller 104.

According to one embodiment of the invention, the input port 202 is used to directly connect to a TTL-compatible TFT display controller. The input port receives image data such as image display output values from the conventional VGA controller AMD GX2-533'. The interface receives 19-bits of RGB data in 6-7-6 format, where 6 bits in each pixel are red, 7 bits are green, and 6 bits are blue data.

The second interface is an output port 204 that directly connects compatible thin film transistor (TFT) panel row and column driver integrated circuits (ICs) that support LCD display output to a suitable TFT display device. The third interface is a Synchronous Dynamic Random Access Memory (SDRAM) interface 224, which communicates with the low-power synchronous dynamic RAM to store a complete updated data picture. The secondary display controller 106 automatically updates the display content of the display device 108 by obtaining updated data from the screen buffer 206. The picture buffer 206 is associated with the secondary display controller 106 and is used to store updated data.

According to an embodiment of the invention, the picture buffer 206 is a 512Kx16 SDRAM picture buffer comprising 1,048,576 bytes, however, for example, 1200x900 One Laptop Per Child (OLPC) TFT panel contains 1,080,000 Pixels. As a result, the secondary display controller 106 must perform pixel packing in which each display pixel must occupy less than one tuple of memory space. The driver in the panel and the Double Edged Transistor-Transistor Logic (DETTL) interface support six bits in the data/pixel. Therefore, in order to improve memory efficiency, a group of four pixels (4 pixels x 6 bits/pixel = 24 bits) is stored into a byte in the SDRAM picture buffer (3 bytes *8) Units/bytes = 24 bits). However, the SDRAM picture buffer is actually 16 bits wide. As a result, the pixels that are actually addressable in the picture buffer are eight pixels (8 pixels * 6 bits / pixels = 48 bits) packed into three characters of SDRAM (3 characters * 16 One bit/character = 48 bits), with this memory operation, the picture buffer will occupy 405,000 characters of 512Kx16 SD-RAM, leaving 119,288 characters unused.

In accordance with an embodiment of the present invention, picture buffer 206 is included in secondary display controller 106.

In accordance with another embodiment of the present invention, picture buffer 206 is located outside of the picture buffer.

The fourth interface is a clock 208. According to an embodiment of the invention, the clock 208 is a directly attached 14.31818 MHz quartz supported by an on-wafer oscillator to provide an independent pixel clock for displaying content updates, regardless of the mode in which the input port is displayed. Why? Clock 208 also provides an interface timing for attaching picture buffer 206. The fifth interface includes one or more input/output pin interfaces for managing timing-critical switching between the primary display controller 104 and the secondary display controller 106. The first pin 210 determines which of the two display controllers updates the display device 108 to display the content. If the first pin 210 is in the active mode, the primary display controller 104 updates the display device 108 display content, however if the first pin 210 is in the inactive mode, the secondary display controller 106 updates the display device 108 to display the content. Additionally, if the secondary display controller 106 is in the inactive mode, the second pin 212 is set to the active mode. The third pin 214 generates one or more interrupt values for indicating the secondary display controller 106. The fourth pin 216 facilitates communication between the processor 102 and the secondary display controller 106.

In accordance with an embodiment of the present invention, the secondary display controller 106 includes a fifth pin 218 for controlling secondary display when the processor 102 receives one or more input values from one or more input devices. The device 106 is driven from the inactive mode to the active mode. These one or more input devices are coupled to the processor 102.

The secondary display controller 106 includes a processing module 220 and a decision module 222. Processing module 220 provides color vector-swizzling support to make display device 108 a conventional 24-bit panel. The color vector channel reading converts the data content of the primary display controller 106 into a smaller bit pattern for better and more efficient display functionality. The details of the operation of the color vector channel read are detailed in the eighth figure. In addition, the processing module 220 supports an optional anti-aliasing capability to improve the content display results. The processing module 220 provides a monochrome mode to support automatic pixel-addressable conversion, converting from colorful to monochrome. The monochrome rendering is consistent with human luminosity perception of updated data within the primary display controller. This will be described in detail in the seventh and eighth figures. The decision module 222 assists the processing module 220 in performing anti-aliasing.

The secondary display controller 106 can easily input update data in a pass-through mode. The pass mode can change the value of one or more bits within a register of one of the secondary display controllers 106. Thereby, the simple LCD timing controller chip and the automatic fly-by mode are emulated to avoid unnecessary writing of the attached picture buffer 206 and to minimize power consumption. In addition, the secondary display controller 106 includes self-testing capabilities that support traditional Red Green Blue (RGB) DETTL panels for full debug and production line testing. For a detailed description of the test of the self-test capability of the production line test, please refer to the detailed description of the seventh and ninth figures.

In accordance with an embodiment of the present invention, a single updated data picture located within primary display controller 104 is converted to a reduced bit pattern. This action is performed just prior to commanding the secondary display controller 106 to update the display content of the display device 108. Therefore, the efficiency of the display method is improved.

The third figure is a flow diagram of a power saving method in accordance with an embodiment of the present invention in which display device 108 is being updated within a computing unit. In step 302, if the processor 102 does not generate new update data, the primary display controller 104 switches from the active mode to the inactive mode. In step 304, the secondary display controller 106, regardless of the primary display controller 104 and the processor 102, is commanded to update the display device 108 to display the content. The secondary display controller 106 consumes substantially less power than the primary display controller 104.

4A and 4B include a flow diagram for switching display device 108 from primary display controller 104 to secondary display controller 106, in accordance with an embodiment of the present invention. In step 402, when the processor 102 continuously generates new update data, the primary display controller 104 updates the display device 108 to display the content. In step 404, it is checked if the processor 102 is generating update data. If the update data is generated, then in step 402 the primary display controller 104 continuously updates the display device 108 to display the content. However, if the processor 102 does not generate new update data, then in step 406 the first pin 210 of the secondary display controller 106 switches to the inactive mode. Next, in step 408, the existing update data is converted to a reduced bit pattern. The reduced bit pattern is visually indistinguishable from the updated data present in the primary display controller 104. The step of converting the update data to the reduced bit pattern includes one or more embodiments of updating the data, such as changing the display output frequency, performing color-swizzling or color-correcting anti-aliasing functions. . In step 410, the reduced bit pattern is stored in the picture buffer 206. In step 412, the secondary display controller 106 is instructed to update the display device 108.

Thereafter, the secondary display controller 106 updates the display content of the display device 108 by obtaining the update data from the screen buffer 204. In step 414, primary display controller 104 switches from active mode to inactive mode. In step 416, the processor 102 switches to the inactive mode. As a result, the processor 102 stops operating after a long period of inactivity. In step 418, if the same update data has been displayed for a long period of time, display device 108 is turned off.

In accordance with an embodiment of the present invention, the secondary display controller 106 converts the updated data mode and updates the display device 108 to display the content without storing the updated data in the screen buffer 204.

In accordance with another embodiment of the present invention, in step 412, secondary display controller 106 can automatically set the task of updating display device 108 to display content.

In accordance with an embodiment of the present invention, if the display device 108 is used to display the content a predetermined number of times using the same update data, the secondary display controller 106 can switch to the inactive mode. The number of times the secondary display controller 106 can switch to the inactive mode is stored in one or more registers in the secondary display controller 106.

The fifth figure is a flow diagram of a method of controlling a display device to switch from the secondary display controller 106 to the primary display controller 104 in accordance with a particular embodiment of the present invention. In step 502, the secondary display controller 106 drives the display device 108. In step 504, it is determined if processor 102 generates new update data. If the processor 102 does not generate new update data, the secondary display controller 106 updates the display device 108 to display the content. If the processor 102 is generating new update data, the secondary display controller 106 commands the generation of new update data in step 506. In step 508, the first pin 210 is set to the active mode. The active mode display of the first pin 210 mainly displays the intermediate active recording state of the controller 104. In step 510, primary display controller 106 switches from the inactive mode to the active mode. In step 512, the primary display controller 106 is instructed to update the display device 108 to display the content. Thereafter, primary display controller 104 transmits the updated data to secondary display controller 106. The secondary display controller 106 can convert the updated data into a reduced bit pattern, and then reduce the bit pattern to update the display device 108 to display the content.

The sixth drawing is a flow diagram of a method of activating the secondary display controller 106 from an inactive mode in accordance with an embodiment of the present invention. In step 602, it is checked if the secondary display controller 106 is in an inactive mode. In step 604, it is determined whether the input signal has been received by the secondary display controller 106 from one or more input devices associated with the display subsystem 100.

In accordance with an embodiment of the present invention, the input signal is received by the secondary display controller 106 from one or more input devices without requiring the processor 102 to intervene.

In accordance with another embodiment of the present invention, the input signal is received by the secondary display controller 106 from the one or more input devices via the processor 102. The one or more input devices include, for example, but are not limited to, a keyboard, a touch pad, a wireless device, a vernier pad or a mouse.

In step 606, the secondary display controller 106 switches from inactive to active mode. In addition, the fifth pin 218 is inactively set to the active mode regardless of whether an input signal is received from one or more input devices. If the fifth pin 218 is set to the active mode when the secondary display controller 106 is in the active mode, the secondary display controller 106 sets one or more registers that store the secondary display controller 106. The number of times you can switch to inactive mode.

If the processor 102 does not generate new update data, the secondary display controller 106 automatically updates the display device 108 to display the content using the update data in the screen buffer 204. If the processor 102 has been updated with the update data of the picture buffer 202, the secondary display controller 106 turns on the display device 108 and blanks the display content by resetting one or more blank display registers. The third pin 214 generates an interrupt action indicating that the secondary display controller 106 updates the update data. In step 608, the display device 108 is restarted if it has been previously turned off.

The seventh diagram is a flow diagram of a method of converting data content of a primary display controller into a reduced bit pattern in accordance with an embodiment of the present invention. The backlight is turned on when the secondary display controller 106 is in the transfer mode. Each reduced bit pattern pixel presents a single color value - red, blue or green. The color-swizzling actuation bit, when set to 1, causes the secondary display controller 106 to act to automatically select the appropriate color gamut from the input update data corresponding to the reduced bit pattern pixel. In the physical panel structure as described above, in step 702, the secondary display controller 106 processes the red input color gamut of the first pixel of the first line of updated data to form the first line of the reduced bit pattern. The first pixel. In step 704, the secondary display controller 106 processes the green input color gamut of the second pixel of the first line of updated data to form a second pixel that reduces the first line of the bit pattern.

In step 706, the secondary display controller 106 processes the blue input color gamut of the third pixel of the first line of the updated data to form a third pixel that reduces the first line of the bit pattern. In step 708, the above steps are repeated for each pixel in each line. This pattern repeats throughout the line. In step 710, the above actions are repeated on each line of the updated data. However, for each subsequent line of updated data, the secondary display controller 106 selects the pixel color such that it can be compensated by a color component of a line before the reduced bit pattern. The first pixel in the second line of the reduced bit pattern is therefore green, the second pixel in the second line of the reduced bit pattern is blue, and the third line in the second line of the bit pattern is reduced. The pixels are red. This pattern is repeated on the second line of the reduced bit pattern. The first pixel in the third line of the reduced bit pattern is blue, the second pixel in the third line of the reduced bit pattern is red, and the third pixel in the third line of the bit type is reduced. It is green. This pattern repeats on the second line. The patterns of the first three strips mentioned above are one set, and the same pattern is repeated every three lines of the entire reduced bit pattern.

In accordance with an embodiment of the present invention, a pixel of reduced bit pattern has a single 6-bit value. In accordance with another embodiment of the present invention, the red and blue pixels have a tail 0 such that each pixel has a remaining 6-bit verification value.

The eighth figure is a schematic diagram of a color vector-swizzling method in accordance with an embodiment of the present invention. The figure shown in the figure is an example of color-swizzling. Color-swizzling is a method of converting the data content of the primary display controller 106 into a reduced bit pattern. The first pixel in the first line of the first pixel in the first line of the 16-bit input signal (referred to as R _11, ) is selected to reduce the first pixel in the first line of the bit pattern (R ₁₁ ') Used. The green bit of the second pixel (called G _15, ) in the first line of the 16-bit input signal is selected to reduce the second pixel in the first line of the bit pattern (referred to as G ₁₅ ') use. The blue bit of the third pixel (referred to as B _19, ) in the first line of the 16-bit input signal is selected to reduce the third pixel in the first line of the bit pattern (referred to as using B ₁₉ '). This pattern repeats on the entire first line. Each subsequent line is the compensation result of the compensation of the color of the previous line. The green bit of the first pixel (referred to as G ₂₂ ) in the second line of the 16-bit input signal is selected to reduce the green bit of the first pixel in the second line of the bit pattern (referred to as G ₂₂ ') Use. The blue bit of the second pixel (referred to as B ₂₆ ) in the second line of the 16-bit input signal is selected to reduce the second pixel (referred to as B ₂₆ ') in the second line of the bit pattern. . The red bit of the third pixel (called R _27, ) in the second line of the 16-bit input signal is selected to reduce the red bit of the third pixel in the second line of the bit pattern (R ₂₇ ' )use. This pattern repeats on the entire second line. The blue bit of the first pixel (referred to as B ₃₃ ) in the third line of the 16-bit input signal is selected for use by the first pixel (B ₃₃ ') in the third line of the reduced bit pattern. The red bit of the second pixel (referred to as R _34, ) in the third line of the 16-bit input signal is selected to reduce the second pixel in the third line of the bit pattern (referred to as R ₃₄ ') use. The green bit of the third pixel (called G ₃₈ ) in the third line of the 16-bit input signal is selected to reduce the third pixel (called G ₃₈ ') in the third line of the bit pattern. . This pattern appears repeatedly on the entire third line.

The color correction anti-aliasing mode bit can be set to 1 when the color vector-swizzling mode is activated. The color correction anti-aliasing mode is set to the active mode when the bits are set. In this mode, color-swizzling is performed as described above, except that the resulting output values are filtered to avoid color aliasing. This is especially important when looking at text fonts. The filtering method is performed by combining the color values of the current pixel with the matching color gamut of the pixels located above, below, and to the right of the current pixel. For example, if we consider B ₂₆ in the eighth figure, the pixels above and below the current pixel will be treated as the second pixel of the first line, the second pixel of the third line, and the first pixel of the second line, And the third pixel of the second line. The blue bits of these pixels are considered.

According to another embodiment of the present invention, the input signal comprises 19 bits in the 6-7-6 format, wherein the 6-bit element into which the update data has been input represents a red component, the 7-bit component represents a green component, and the 6-bit component represents a 6-bit representation. Blue composition.

As long as the color-swizzling and the anti-aliasing bit are 0, the secondary display controller 106 can switch to 1 by setting the modified anti-aliasing bit to 1. Monochrome lighting mode. In this mode, the 16-bit input color value of the 5-6-5 RGB format is approximately equal to the standard NTSC illumination value-conversion formula and pixel value =(R>>2)+(R>>4)+(G) >>1) +(G>>4)+(B>>3) is converted into a 6-bit pixel display value. This action is performed by summing the corresponding color gamut values from four adjacent pixels, wherein the adjacent pixels are the upper pixel, the lower pixel, the right pixel, and the left image of the current pixel. After that, the resulting right 3 bits are moved to and added to the value of the current pixel, and a bit is added to the right. The resulting output value, as short as 6 bits, is the filtered equivalent of the color-swizzling method when the color correction anti-aliasing has become inoperable. The 6-bit value is stored in the picture buffer 204 of the secondary display controller 106 of the current pixel.

Note that when the color-swizzling actuation bit is 0, the secondary display controller 106 transmits a green component of the update data that is present in the primary display controller 104 in another version. Another version refers to a visual judgment equal to the green content present in the primary display controller 104 to update the data. As a result, the secondary display controller 106 outputs the green gamut value of the input pixel value for each pixel unless the monochrome illumination actuation bit has been set to one.

To determine that power consumption is minimal, the secondary display controller 106 supports processing to reduce the dot matrix (point) clock frequency of the panel interface. This gamut value specifically reduces the quartz oscillator divider by one, resulting in a system lattice clock frequency. All image timings are derived from the lattice clock. If this gamut contains 0, the frequency of the lattice clock is 208, however one of the 7 gamuts produces a clock of the eighth quarter of the lattice. Using 54.06 MHz quartz, a nominally programmed image-timing parameter for a 50-Hz panel update rate is generated and the dot matrix clock splitter is individually changed, resulting in an actual panel update rate of 50.00 Hz, 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz, 7.14 Hz or 6.25 Hz.

The ninth diagram is a timing diagram of method steps for activating secondary display controller 106 from an inactive mode in accordance with an embodiment of the present invention. The figure depicts the state of the various components of display system 200, and the method steps performed by the components before and after the time, where the x-axis is time and the y-axis is the system component. The secondary display controller 106 can receive a number of input values from the input device. The fifth pin 218 turns on the secondary display controller 106 upon receiving the input value. The third pin 214 generates an interrupt output value after the secondary display controller 106 is turned "on". The secondary display controller 106 then causes the display device 108 to display a blank of content. Then, the picture buffer 206 performs a display load picture duty cycle. Once the picture buffer 206 completes the picture load cycle, the secondary display controller 106 sets the control of the display device 108.

From the above, details of the execution technique (secondary display controller) according to an embodiment of the present invention can be referred to below. The following description includes detailed descriptions of each hardware implementation, such as the structural relationship of each processor, IC, pin, and scratchpad. Those skilled in the art will recognize that the invention can be practiced without undue experimentation.

Secondary display controller 106 and direct I/O pin interface

For some interfaces operating between the secondary display controller 106 and the processor 104, time is essentially time-critical. In particular, switching between the primary controller 104 managing the display content update and the secondary display controller 106 managing the display of the content update must be carefully timed to avoid displaying artifacts. The secondary display controller 106 is connected to the CS5536 compare I/O device using fast direct I/O pins to support these operations. The CS5536 is a standard processor for I/O operation and is designed by Advanced Micro Devices. Details are included in the system interconnection job for each pin description.

The DCONIRQ/pin is a low active scan line interrupt (ScanLine Interrupt) output from the secondary display controller 106 chip, which can be programmed to be inserted into the image output at a fixed timing point before the next display is started. The processor 102 is changed. By receiving an interrupt value, along with known timing operations associated with the display operation, the processor 102 can reconstruct the current display state in which the primary display controller 104 has been controlled to update the content, or the secondary display controller 106 has been controlled to update. The content is currently displayed in a state without the need for a "busy-waiting" or polling loop. Please see the following for further explanation of DCONLOAD.

DCONBLNK is used to assist in the need to display changes in the display state asynchronously. The secondary display controller 106 to be polled will drive the DCONBLNK output in two cases. The first case is: DCONBLNK drives to a low voltage at the beginning of the first output scan line, then the active vertical resolution output scan line is maintained at a low voltage until the trailing edge of the Vsync timing interval is output. At this point it is driven again to a high voltage. In the second case, the DCONBLNK output is maintained at a high voltage regardless of whether the display content of the secondary display controller 106 output value cannot be displayed.

DCONSTAT is used to indicate whether the primary display controller 104 or the secondary display controller 106 currently manages updates to the displayed content. Because the display control switching of the secondary display controller 106 is synchronized with the display process, the status pins enable the processor 102 to accurately confirm when the secondary display controller 106 switches display content. DCONLOAD is used to start displaying the load picture - load cycle. The signal indirectly determines whether the secondary display controller 106 image timing output is output based on the image input value, or whether the internal timing register of the secondary display controller 106 drives the image output. Note that the actual data output to the panel will normally be corrected by the secondary display controller 106 wafer as described above with respect to the display mode register of the secondary display controller 106.

Secondary display controller 106 display controller ASIC pin (output) - 2M (1M x 16) DRAM structure Geode display interface pin Geode pixel clock GFDCLK 1 Geode red data GFRDAT0-4 5 Geode green data GFGDAT0-5 6 Geode Blue Data GFBDAT0-4 5 Geode Vsync GFVSYNC 1 Geode Hsync GFHSYNC 1 Geode Display Actuation GFDISP_EN 1 Geode FP_LDE GFP_LDE 1 1Mx16 DRAM Interface Pin FBRAM Data FBD0-15 16 FBRAM Address FBA0-11 12 FB Field Address Strobe pulse FBCAS/1 FB column address strobe pulse FBRAS/1 FBRAM chip selection FBCS/1 FBRAM write actuation FBWE/1 FBRAM clock FBCLK 1 FBRAM clock actuation FBCLKE 1 secondary display controller 106 self-updating Quartz display XTAL (input) InDCONXI 1 display XTAL (output) DCONXO 1 system interface pin system reset 1 time display controller 106 interrupt output DCONIRQ / 1 secondary display controller 106 display load command request DCONLOAD 1 secondary display Controller 106 vs. Geode/Display Active Status DCONSTAT 1 Secondary Display Controller 106 Blank Status DCONBLNK 1 Secondary Display Controller 106 Register I/O SMB Clock DCONSMBCLK 1 Secondary Display Controller 106 Register I/ O SMB data D CONSMBDATA 1 PPTTL/Panel Interface Pin Panel Pixel Data 1 D1O0-2 3 Panel Pixel Data 2 D2O0-2 3 SCLK SCLK 1 DCLK DCLK 1 GOE GOE 1 GCK GCK 1 GSP GSP 1 DINT DINT 1 SDRESET SDRESET 1 DBC DBC 1 INV INV 1 PWST PWST 1 POL1 POL1 1 POL2 POL2 1 Self Test / Edge Scan BIST0-1 2 Total User I/Os 84

Register definition: register 0: secondary display controller 106 ID + correction 16-bit register is a read-only register, restores the secondary display controller 106 ASIC recognizer and the number of corrections. When the cockroach passes for the first time, the hexadecimal value of ‘DC01’H should be restored, and the next correction should restore ‘DC02’H.

Register 1: Secondary display controller 106 display mode bit 0: Pass-through Disable This bit system controls whether the secondary display controller 106 performs an update of data. When the power is turned on, the bit is automatically initiated to 0 by the secondary display controller 106 such that the image output value is directly in accordance with the image input value and the secondary display controller 106 operates in the pass mode. In this mode, the secondary display controller 106 acts only as a conventional TFT timing controller (TCON) chip in which the image output values are converted only when a DETTL-compatible output signal from the display panel needs to be derived. For the purpose of reducing power, the SDRAM interface 224 must be completely inoperable in the pass mode, even if there is no SDRAM clock signal. In the pass mode, all other secondary display controllers 106 registers and control bits are ignored, except that the priority order is better than the self-test actuation of the pass mode.

Writing 1 through the unactuable bit activates the normal secondary display controller 106 to turn on and includes the SDRAM interface 埠 224, the internal image timing register, the mode construction bit, and the like.

Bit 1: Secondary Sleep Controller Mode 106 The key factor in the power efficiency of the secondary display controller 106 is its low power consumption when the display device 108 is fully turned off and the picture buffer 206 is set to the self-updating mode. The ability to measure state. The self-updating mode is known as the sleep mode of the secondary display controller 106. Under normal circumstances, the secondary display controller 106 automatically enters the sleep mode as a result of the long-term system inactivity, especially if the automatic sleep mode bit has been set and displayed, the timeout value has been outputted. There is no need to activate the Display Load Cycle or receive input signals from one or more input devices. Thereafter, the secondary display controller 106 sets the bit and automatically enters the sleep mode.

Alternatively, sometimes the processor 102 needs to begin switching the sleep mode of the secondary display controller 106. In particular, when the power source is switched to select "system off", when the laptop is closed, when the critical low battery level is detected, the processor 102 should manually enter the sleep mode. In order to enter sleep mode, the bit should be written as '1'.

Because the picture buffer 206 remains in the low battery self-updating state and the secondary display controller 106 is in the sleep mode, the secondary display controller 106 is unable to process the incoming display duty cycle. However, the load pins of the secondary display controller 106 are not ignored. If the processor 102 makes a request to display a duty cycle, but the secondary display controller 106 is in a sleep mode, it is set to an internal state known as the secondary display controller 106 LOAD_MISSED. This state is used to inform the secondary display controller 106 that the data in the picture buffer 206 is no longer the same as the update data generated by the processor 102. When the secondary display controller 106 changes to the sleep mode after losing the load of the secondary display controller 106, the display content of the display device 108 is automatically blanked, and the IRQ active bit of the secondary display controller 106 is driven by driving an update data line. The element is generated once to display the controller 106 LOAD_MISSED interrupt value. This causes processor 102 to rewrite the latest update data generated by processor 102 and then clear the image blanking pin to display the most recent data on display device 108.

The method of changing to sleep mode can be performed manually or automatically. Under normal circumstances, the bit is automatically cleared as soon as it reaches ECPWRRQST. The ECPWRRQST is reached when the secondary display controller 106 receives input signals from one or more input devices. In other words, pressing a button to store image display content is independent of which processor 102, thereby turning the display device 198 "on the fly" when the keyboard button, cursor button or touch pad has been activated. Alternatively, processor 102 can exit sleep mode and, if necessary, re-start updating display device 108 to display content by clearing the bit to zero.

Bit 2: Automatic Sleep Mode When this bit is set to 1, the secondary display controller 106 automatically stops the display method after the display timeout value image screen has been output without system operation. Whenever the secondary display controller 106 LOAD is at a high override value, or when an incoming ECPWRRQST occurs, the internal display timeout register is automatically set to display the value in the timeout value register. . If the timeout is displayed, the secondary display controller 106 automatically enters the sleep mode by setting the secondary display controller 106 sleep mode bit to one. When the automatic sleep mode bit is 0, the secondary display controller 106 determines to continuously update the display device 108 to display the content. If the display duty cycle or ECPWRRQST occurs, the sleep mode can be entered only by writing to the sleep mode bit of the secondary display controller 106.

Bit 3: Backlight actuated backlight actuation is used to determine that the backlight of display device 108 should be turned on, however the display function is activated. The bit is set to 1 and the backlight is turned on whenever the secondary display controller 106 is not in the sleep mode of the secondary display controller 106. Please note that it is not necessary for the screen saver to turn the backlight on and off, because setting the bit will cause the backlight to be automatically activated and unable to actuate. If the bit has been cleared, the backlight remains unactuable regardless of whether the secondary display controller 106 is the secondary display controller 106 sleep mode or not. When the backlight is actuated, the backlight pin is actively driven to a high voltage, and the DBC pin is driven by the PWM waveform, and its duty cycle is consistent with the value of the backlight luminance register.

Bit 4: Image blanking image blanking displays "blank" on the screen without affecting the content of the secondary display controller 106 picture buffer 206, or the state of charge of the display device 108. This feature is primarily used to determine whether the secondary display controller 106 should exit the sleep mode, wherein the display device 108 displays the update data, or wherein the display device 108 is masked until the next display of the duty cycle. This feature is clearly utilized by the secondary display controller 106. Since the secondary display controller 106 cannot record the incoming display duty cycle while in the sleep mode, the VIDEO_BLANKING bit is automatically set if the secondary display controller 106 becomes high voltage when the load is in the sleep mode. This action determines that the old update data does not show wake up. If the bit is written with '1', the display device 108 displays "black". If "0" is written, the current content of the picture buffer 206 is displayed on the display device 108.

Bit 5: Color Vector Swizzling Actuation In accordance with an embodiment of the present invention, the selected display device 108 is a hybrid monochrome/color panel that does not utilize conventional RGB sub-pixels. Instead, each pixel contains only a single "sub-pixel value." When used as a reflective panel, that is, when the backlight is off, these pixel values represent grayscale. The resulting image is a monochrome display. When in the transmission mode, that is, when the backlight is turned on, each pixel represents one of the single color values of the red, green and blue combination.

The first pixel of the first line of the update data is red, the second pixel of the line is green, and the third pixel is blue. This pattern appears repeatedly on the entire line. Note that each successive line compensates for a color element from the previous line. The first pixel of the second line is therefore green, the second pixel is blue, and the third pixel is red. This pattern appears repeatedly on the entire second line. The first pixel of the third line is blue, the second pixel is red, and the third pixel is green. This pattern repeats on the entire third line. The patterns of the first three lines mentioned above are a group and are repeated on the entire display panel.

This color pattern helps to remove display artifacts, but also complicates the system software. A color vector-swizzling actuating bit, when set to 1, activates the secondary display controller 106 to automatically select the appropriate color gamut from the input 6-7-6 update data. Next, the physical panel structure is as described above, and the secondary display controller 106 selects the first pixel of the first line as the red input color gamut, and the next pixel on the line is the green input color gamut or the like. The net effect of the color-swizzling actuation function is that the secondary display controller 106 automatically discards two-thirds of the input update data, with the result that each output pixel of the write picture buffer 206 has a single 6- Bit value.

Note that when the color-swizzling actuation bit is 0, the secondary display controller 106 simply outputs the six most significant bits in the green gamut of each input pixel, unless monochromatic illumination occurs. The move bit is set to 1. The color vector-swizzling mode itself does not require the use of the following secondary display controller 106 to scan the line buffer ring; only the secondary display controller 106 mode is in color-swizzling and color correction. When the anti-aliasing mode bit is set to 1, it is active, and it is necessary to use the buffer ring of the wafer.

Whenever the color vector-swizzling mode is active, the secondary display controller 106 COL mode output pin is driven to a high voltage. The pin actuates the display device 108 and switches its inner panel bias to optimize the display quality in color or monochrome mode.

Bit 6: Color Secondary Display Controller 106 Actuation The color correction anti-aliasing mode bit can also be set to one when the color-swizzling mode is activated. When both bits are timed, the color correction anti-aliasing mode is active. In this mode, color-swizzling is performed as above, but the resulting output values are filtered to avoid color-corrected anti-aliasing. The filtering method can be performed by combining the color values of the current pixels of the pixel coordinates (V, H), corresponding to the pixels above the current pixel (V-1, H), the lower pixels (V+1, H), and the left pixel (V, H-1) and the color gamut of the right pixel (V, H+1). The program is performed by summing the values corresponding to the gamut of the four adjacent pixels, shifting the resulting three bits, and adding the result to the current pixel value. Shifts the resulting 3 bits to the right and adds it to the current pixel value, shifting one bit to the right. The resulting output value (cut into six bits) is filtered by the color-swizzling filter when the color correction anti-aliasing is not actuated, the six-bit value is stored In the picture buffer 206 of the current pixel.

It is especially important to emphasize that color-corrected anti-aliasing operates with 19-bit color values, rather than color-swizzling with anti-aliasing without actuating color correction. The six bits of the output value. The above mathematics is specifically calculated on the color gamut suitable for the current pixel. In other words, if the current pixel has a red color filter, the mathematical operation sums up and combines the red color gamut of adjacent pixels of the red color gamut of the current pixel. The next pixel to the right performs the same function on the green gamut of the current and adjacent pixels.

In order to obtain the appropriate color gamut of the color correction anti-aliasing, two results are immediately apparent. First, the process must be performed using a buffer ring of two scan line lengths. Second, each component of the buffer ring must have a 6-7-6 input color version instead of a 6-bit output version, with 19 bits of color data. Execution details: The input buffer line is typically 2x1200 19-bit characters. However, once the buffer is executed, the point is that each pixel is updated with the latest value, in the same way as a buffer ring. Otherwise, three full scan lines are required to perform the color correction anti-aliasing function.

Implementation warning: The above simplified mathematical calculation formula is intended to be easy to understand, not actual implementation. For example, using a right-shift operation, the purpose is to explicitly align the bits to different color compositions, rather than implying that any bit is "lost" in the color correction anti-aliasing process. In order to visually display quality, it is necessary to maintain full 10-bit accuracy until the output is complete. Only the final output value of the modified anti-aliasing process can be reduced to six bits by abandoning the four LSBs. The operation of correcting the operation of discarding the least significant bit before outputting the pruning value during the anti-aliasing operation is not accepted.

Bit 7: Monochrome Illumination Actuation As long as the color-swizzling and color-corrected anti-aliasing bits are zero, the secondary display controller 106 can write the bit as The way of 1 is placed in the monochrome illumination mode. In this mode, the 19-bit input color value (again 6-7-6 RGB pattern) is reduced to the standard NTSC luminescence conversion formula via the following simple integer: pixel value = (R>>2) + (R>>4) + (G>>1)+(G>>4)+(B>>3), converted to a 6-bit pixel display value.

Note that unlike in the color correction anti-aliasing mode, the monochrome illumination function works only on the color gamut of the current pixel. As a result, the two line ring buffers on the wafer are not used in this mode.

Implementation warning: The above simplified mathematical calculation formula is intended to be easy to understand, not actual implementation.

Bit 8: Scan Line Interrupt Actuation Setting This bit is 1, driving the secondary display controller 106 to output a scan line interrupt generated during the image scan, wherein the image scan is programmed into a scan line interrupt value. Save. This interrupt action becomes active at the beginning of the programmed scan line and maintains the length of time that a scan line is active for each screen. This action is continued as long as the scan line interrupt actuating bit is one.

Bits 9-11: Point Clock Cutter To support minimal power supply, the secondary display controller 106 supports the ability to reduce the clock frequency of the panel interface point. The value in this color gamut causes the quartz oscillator cutter to be decremented by one, resulting in a system point clock frequency - all image timing is derived from the point clock. If the field contains 0, the point clock is equal to the quartz frequency clock, however one of the 7 gamuts produces a point clock of one-eighth of the quartz frequency, using 4X, 14.31818 MHz quartz 1 to produce a 50 Hz panel update. Rate and only change the nominal (nominal) stylized image timing parameter of the point clock cutter to get the actual panel update rate of 50.00 Hz, 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz, 7.14 Hz, or 6.25 Hz.

Bits 12-13: Reserved to retain these read-only bits.

Bit 14: Debug Mode Actuation Two cases occur when the debug mode bit is written to a high level. First, the LCD panel interface becomes a color LCD that supports traditional color sub-pixels. Second, the SDRAM interface 埠 224 becomes 4MB of the SDRAM. This bit remains completely at 0 when the secondary display controller 106 ASICs are fabricated.

Bit 15: When the self test mode is initiated, the secondary display controller 106 samples the BIST pin to determine if it should enter normal operation - BIST low level or self test operation - BIST High. Once the reset is left, the state of the BIST pin is copied to the self test mode bit. The software can also initialize the entry mode to the BIST mode by writing the bit to 1, and can resume the normal mode of operation by writing the bit to zero. When the secondary display controller 106 is in the self test mode and no input image clock has been detected, the secondary display controller 106 automatically cycles through its display output in white, black, red, green, and blue intervals every two seconds. value.

Scratchpad 2: Horizontal Resolution The 16-bit scratchpad contains the number of pixels displayed per horizontal line, normally 1200. Note that due to timing constraints in the primary display controller 104, the secondary display controller 106 can receive more input pixel clocks than is programmed in the scratchpad. When this occurs, the continuation clock within the range of programmed pixels in the scratchpad should be ignored until the next HSync pulse has occurred. Then, after the pixel is packed, the number of programs in the register, one after the other, should match the memory spacing, as in the picture buffer 206.

Scratchpad 3: Total number of levels The 16-bit scratchpad contains the total number of point clocks for each horizontal scan line

Scratchpad 4: Horizontal Sync Start and Width The 16-bit scratchpad contains two 8-bit scratchpads. The most obvious byte of the scratchpad contains the horizontal Sync start register. After "horizontal resolution", each line has a point clock. HSync is generated after the HSync Start" extra clock has occurred. The least obvious byte in the scratchpad contains the number of clocks so that HSync remains active as soon as HSync has been generated.

Scratchpad 5: Vertical Resolution The 16-bit scratchpad contains the total number of lines that are displayed for each image frame. This total contains a value of 900.

Scratchpad 6: Vertical Total The 16-bit scratchpad contains the total number of scan lines that occurred during each image frame. For clarity, the TFT panel update rate (in Hz) is equal to the value in the scratchpad.

Point clock / (horizontal total * vertical total)

Scratchpad 7: Vertical Sync Start and Width The 16-bit scratchpad contains two 8-bit scratchpads. The most obvious byte in the scratchpad contains the vertical sync start register. When the vertical resolution line is displayed, VSync is generated after an additional number of times "VSync Start" has occurred. The least obvious byte in the scratchpad contains the number of scan lines that VSync should keep active, once VSync has been generated.

Register 8: The display timeout value is a power save, and the secondary display controller 106 can automatically turn off the display output value and enter the sleep mode of the secondary display controller 106. The register contains the number of output image frames before the power is automatically turned off.

The scratchpad 9: scan line interrupt value properly synchronizes the processor 102 image output value with the secondary display controller 106 image output value, and the secondary display controller 106 can actuate the system software for display at any designated A processor 102 interrupt value is generated at the line in synchronization with the display processing. The register writes the number of output image scan lines during the generation of the interrupt value.

Scratchpad 10: Backlight Brightness Only the top four bits of the scratchpad are used - the lower 12 bits are undefined and should be ignored. The backlight brightness register is used to set the duty cycle of the DBC output pin. The value of 00H corresponds to a 0% duty cycle, whereas the value of 0FH corresponds to a 100% duty cycle. The transition value can be used to set a specific brightness value. Note that if the backlight actuation bit is set to 1 and the panel is currently rendered active, the DBC pin can only be driven by the PWM waveform.

Register 11-127: Reserved to keep these registers.

In summary, according to another embodiment, the industrial scale implementation details of the present invention (secondary display controller Version 0.8) include the following.

The secondary display controller 106 DIRECT I/O pin interface displays the interface operations between the controller 106 and the processor 102, some of which are inherently time dependent. In particular, the switching between the primary display controller 104 managing the display updates and the secondary display controller 106 managing the display updates must be carefully timed to avoid displaying artifacts. To support these activities, the secondary display controller 106 is connected to the CS5536 Companion I/O device using a fast direct I/O pin. For details on the internal connections in the system, please refer to the description of each pin.

DCONBLNK-CS5536 GPIO12 DCONBLNK is used to assist processor 102 in synchronizing its image timing and secondary display controller 106 image timing to confirm updates from the secondary display controller 106 to the processor 102-controlled updates. There is no missing transmission. To confirm, the secondary display controller 106 is enabled to drive the DCONBLNK output value in two cases. First, the DCONBLNK output value is driven low at the beginning of the first output value scan line followed by the active vertical resolution output value scan line, and then remains low until the end of the output VSync timing cell, where DCONBLNK is made The output value again becomes a high level. Second, the DCONBLNK output value remains high, regardless of when the secondary display controller 106 is the secondary display controller 106 sleep mode.

DCONLOAD-CS5536 GPIO11 DCONLOAD is the source that controls the update cycle of the image display. The signal indirectly determines whether the image-timing output value of the secondary display controller 106 follows the image input value, indicating that the primary display controller 104 controller is managing the display update, or the internal timing register of the secondary display controller 106. The image output value is being driven. Note that in either case, the actual data output to the panel is normally corrected by the secondary display controller 106 wafer, as described in the description of the secondary display controller 106 displaying the mode register. The difference is that the secondary display controller 106 is in the pass mode, wherein the data output value of the secondary display controller 106 only reflects the green image data input value by six bits, such as the appropriate signal phase shifting effect (phasing) The appropriate delay.

The DCONIRQ/-CS5536 INTB# DCONIRQ/ pin is the low-active interrupt request output value from the secondary display controller 106 chip. This signal is driven in three cases. First, when the Display Load cycle is complete, DCONIRQ is driven to inform processor 102 that it is now safe to actuate primary display controller 104. Additionally, the secondary display controller 106 can be programmed to generate an interrupt value on a particular scan line of the image output value. The primary purpose of this use is to automatically change the processor 102 at a fixed time before starting the next display. When a break in the known timing associated with the display operation is received, the processor 102 can resume its image with the current display content, within the sync. The scan line interrupt capability can also be used for traditional purposes, such as displaying a timeout.

The last DCONIRQ interrupt value source occurs when the processor 102 has updated the screen content and executed a Display Load sequence, but the secondary display controller 106 is simultaneously in sleep mode. When the secondary display controller 106 is later woken up by the ECPWRRQST, the panel power is normally activated and the automatic display update is resumed. However, in this case, the secondary display controller 106 instead activates the panel power by setting the Video Blanking bit. The way to keep its image in a blank state and generate a DCONLOAD_MISSED interrupt value to inform the processor 102 that the display content must be updated. Note that clearing the Video Blanking bit after updating the display content is a task of the processor 102. (Writing to the Video Blanking bit clears the internal DCONLOAD_MISSED status flag)

DCONSTAT0...1-CS5536 GPIO5 & GPIO6 The DCONSTAT pin is used to pass the fast state to the processor 102, especially to confirm the cause after a DCONIRQ interrupt value. The DCONSTAT0...1 pin code is as follows: 00: A scan line interrupt value occurs when the processor 102 is controlled to update, that is, Full-on mode. This state is used to indicate that the incoming interrupt value is a value related to the conventional scan line interrupt value and the image pause.

01: A scan line interrupt value occurs in state 2 (secondary display controller 106 mode). This state is used to re-start the processor 102 image output value to synchronize the initial image timing with the image timing of the secondary display controller 106. After this interrupt value, processor 102 is expected to accumulate the DCONBLNK pin to perform good timing synchronization.

10: An already occurring display load (Display Load) has completed the interrupt value. This state informs the processor 102 that the secondary display controller 106 has completed recording an image frame, and thus is safe for the processor 102 because the main display controller 104 controller clock on the wafer cannot be actuated and power is saved. The most output value.

11: A DCONLOAD_MISSED interrupt value occurs when jumping out of sleep mode. As previously discussed, if the processor 102 processes the picture while the secondary display controller 106 is still in the sleep mode, the screen lacks data upon waking up. The interrupt value tells the secondary display controller 106 that a display load cycle must be performed and then the Video Blanking bit within the secondary display controller 106 mode register is cleared to actuate the display content.

This encoding action may be a bit unclear, but it reflects the need to put the maximum state data into the available external pins.

The ECPWRRQST-System Activity Display Screen ECPWRRQST pin is used to "wake up" the secondary display controller 106 to wake up from sleep mode. Whenever the keyboard, touch panel or cursor key activates the controller embedded in the system, the pin is raised to a high level. The rising edge of ECPWRRQST causes the secondary display controller 106 to automatically power up the display and initiate an automatic display update (refer to the exception description of the DCONLOAD_MISSED interrupt value above). If the secondary display controller 106 has entered the sleep mode, it remains in the sleep mode either automatically or manually until the sleep mode bit of the secondary display controller 106 is cleared to zero or the ECPWRRQST pin becomes a high level and the secondary is cleared. The sleep mode bit of controller 106 is displayed.

Note that ECPWRRQST, which is communicated when the display is active, has only one effect - reset the internal display timeout (Timeout) register to the value in the display timeout value register.

The minimum working cycle for ECPWRRQST is ~100 nS. (The pin does not require switch bounce or filtering)

Secondary display controller 106 register definition

Secondary display controller 106 user I/O pin DEFINITIONS secondary display controller 106 ASIC external pin-1M (512K x 16) SDRAM architecture Geode display interface pin s

512Kx16 SDRAM interface pin

Secondary display controller 106 self-updating quartz

The primary display controller 106 registers the primary programmed interface of the secondary display controller 106 to the 100 KHz sequence SMBUS interface to enable the internal architecture register of the read and write chips. These registers are 16-bits long and support access by the 16-bit scratchpad. These registers have not been defined to be accessed in any other mode, so this access action may have unpredictable results. The 32-bit SMBUS cycle is used to properly communicate with the secondary display controller 106. The first octet previously specifies the SMBUS address, typically the 0DH and read/write mode bits at the time of execution. The next octet supports the number of scratchpads to communicate, and the remaining 16 bits contain the contents of the desired scratchpad. In order to understand the communication between the secondary display controller 106 and the system, please note that the secondary display controller 106 is connected to the SMBUS port of the AMD CS5536 I/O chip at the SMBUS address 0DH.

Register 0: Secondary Display Controller 106 ID+Revision The 16-bit register is a read-only register that returns the secondary display controller 106 ASIC identification value and correction value.矽 The first pass should make the value of 'DCO1'H hexadecimal return, the next correction will return 'DC02'H, and so on.

Scratchpad 1: Secondary Display Controller 106 displays mode bit 0: Pass-through can't actuate the bitstream to control whether the secondary display controller 106 will perform any copying of the update data. When the power is turned on, the bit automatically starts to 0 by the secondary display controller 106, causing the image output value to directly follow the image input value, and the secondary display controller 106 operates in the pass mode. In this mode, the secondary display controller 106 acts only as a conventional TFT timing controller (TCON) chip where the output value is only converted when it needs to drive a DETTL compatible output signal for the display panel. In order to save power, the SDRAM interface 埠 224 does not need to be fully activated even if the SDRAM clock signal is generated in the pass mode. In pass mode, all other secondary display controllers 106 registers and control bits are ignored, except for the self-test actuation of the bit in preference to the pass mode.

The write of 1 through the unactuable bit system causes the normal secondary display controller 106 to begin operation, and includes the activation of the SDRAM interface 224 and the initialization of the internal image timing register, mode-architecture bits, and the like.

Bit 1: Secondary Display Controller 106 Displays the Enable Display Enable bit to be initialized to 1 by the secondary display controller 106 upon completion of the reset action. This normal state allows the secondary display controller 106 to output the output value of the panel interface to be driven as defined by the current wafer mode. The bit is immediately written as 0 and the image output value is driven asynchronously to a low power blank state. Next, the bit is set to actuate the image output value, but the re-actuation process is performed synchronously - the panel driver remains in the low power state until the next Vsync output value - the tail of the timing interval. At this time, the image driver is turned on and turned on until the secondary display controller 106 displays the activated state (Enbale) is cleared again.

Note that the secondary display controller 106 automatically clears the bit and blanks the display.

If the display timeout (Timeout) actuating bit is set, the display time-out value (Timeout) image output value screen can be generated without a display load cycle.

Bit 2: Color Vector Swizzling Actuation In accordance with an embodiment of the present invention, the selected display device 108 is a hybrid monochrome/color panel that does not utilize conventional RGB sub-pixels. Instead, each pixel contains only a single "sub-pixel value." When used as a reflective panel and the backlight cannot be actuated, these pixel values represent grayscale and the resulting pattern is a monochrome display. When used in transfer mode and the backlight is on, each pixel represents a single color value in a combination of red, green, and blue.

The first pixel of the first line of the update data is red, the second pixel is green, and the third pixel is blue. The pattern is repeated over the entire line. However, please note that each successive line compensates for the previous line consisting of one color. The first pixel of the second line is therefore green, the second pixel is blue, and the third pixel is red. The pattern is repeated over the entire second line. The first pixel of the third line is blue, the second pixel is red, and the third pixel is green. The first pixel pattern is continuously repeated on the entire third line. The patterns of the first three lines mentioned above are a group and are repeated in the entire display panel.

This color pattern helps to eliminate display artifacts, but also complicates the system software. The color-swizzling actuation bit activates the secondary display controller 106 when set to 1, causing the secondary display controller 106 to automatically select the appropriate color gamut from the input 6-7-6 update data. . After the physical panel structure described above, the secondary display controller 106 selects a red input color gamut for the first pixel on the first line and a green input color gamut for the next pixel on the line. The net effect of the color-swizzling actuation function is that the secondary display controller 106 automatically discards two-thirds of the input update data, with the result that each output pixel written to the picture buffer 206 has a single 6-bit. Meta value.

Note that when the color-swizzling actuation bit is 0, the secondary display controller 106 simply inputs the green gamut value of the input pixel to each pixel unless monochromatic illumination is actuated. The bit is set to 1. Note that the color-swizzling mode itself does not require the secondary display controller 106 to scan the line-ring buffer because it is only in the color-corrected anti-aliasing mode where the color vector The color-swizzling and color-corrected anti-aliasing mode bits are active and require the use of a wafer's ring buffer.

Bit 3: Color-corrected anti-aliasing actuation The color-corrected anti-aliasing mode bit can also be set to 1 when the color-swizzling mode is actuated. The color correction anti-aliasing mode should be active when both bits are set. In this mode, color-swizzling processing is performed as described above, but the resulting output values are filtered to avoid color-corrected anti-aliasing. The filtering process is performed by combining the color values of the current pixel of the pixel coordinates (V, H) with (V-1, H), (V+1, H), (V, H-1) left and (V, H+1) The manner in which the corresponding color gamut of the right pixel is performed.

This includes adding the corresponding gamut value to the corresponding gamut value of four adjacent pixels. The result is shifted to the right by 3 bits, and the result is added to the current pixel value to the right by one bit. The resulting output is truncated to six bits, which is the color-swizzling processed filtered equivalent when the color correction anti-aliasing is not actuatable. The 6-bit value is stored in the picture buffer 206 of the current pixel.

It is especially important to emphasize that when color correction anti-aliasing is not possible, color-corrected anti-aliasing can be applied at 16-bit color values, but not in color vector channels ( Color-swizzling) works by processing the 6-bit color value of the output value. The mathematical approach described above is specific to gamut operations that are suitable for current pixels. In other words, if the current pixel has a red color filter, the mathematical method adds and combines the red color gamut of the adjacent pixel with the current pixel color gamut. The next pixel to the right performs the same function on the green gamut of current and adjacent pixels.

In order to obtain the appropriate color gamut of the color correction anti-aliasing, two facts immediately become apparent. One of them is a buffer ring that must utilize two scan line lengths to perform processing operations. The other is that each component of the buffer ring must have a color form of 5-6-5 input values instead of 16 bits of color data of a 6-bit output value type.

Execution details: The input line buffer is typically 2x1110-character long or 2x830-character long, depending on whether the display content drives a portrait or a landscape. However, once the buffer is operating, it is important to update each pixel ring buffer. Otherwise, three full scan lines are required to perform the color correction anti-aliasing function.

Implementation warning: The above simplified mathematical calculation formula is intended to be easy to understand, not actual implementation. For example, using a right-shift operation, the purpose is to explicitly align the bits to different color compositions, rather than implying that any bit will be lost in the color correction anti-aliasing process. In order to visually display quality, it is necessary to maintain full 10-bit accuracy until the output is complete. Only the final output value of the modified anti-aliasing process can be reduced to six bits by abandoning the four LSBs.

It is unacceptable to abandon the color correction anti-aliasing operation process before outputting the pruning result.

Bit 4: Monochrome Illumination Actuation As long as the color-swizzling and color-corrected anti-aliasing bits are zero, the secondary display controller 106 can write the bit as 1 The way to become a monochrome lighting mode. In this mode, the 16-bit input color value of the 5-6-5 RGB pattern is converted into a 6-bit pixel display value by the following simple integer approximation into a standard NTSC luminosity conversion formula: pixel value = (R>>2 )+(R>>4)+(G>>1)+(G>>4)+(B>>3)

Note that unlike the color correction anti-aliasing mode, the monochrome illumination function only works on the current pixel gamut. As a result, a 2-wire ring buffer on the wafer is not used in this mode.

Implementation warning: The above simplified mathematical calculation formula is intended to be easy to understand, not actual implementation. For example, using a right-shift operation, the purpose is to explicitly align the bits to different color compositions, rather than implying that any bit will be "lost" during the luminosity conversion process. In order to visually display quality, it is necessary to maintain full 10-bit accuracy until the output is complete. Only the last output value of the luminosity conversion process can be reduced to six bits. The operation of discarding the least significant bit before outputting the pruning value during the luminosity conversion process is not accepted.

Bits 5-7: Point Clock Splitter In order to support minimum power supply, the secondary display controller 106 supports the ability to reduce the clock frequency of the panel interface point. This gamut value reduces the quartz oscillator divider by one, producing a system point clock frequency. All image timings are derived from the point clock. If the gamut value contains 0, the point clock is equal to the clock frequency of quartz, whereas one of the seven gamut values produces a point clock of one-eighth of the quartz frequency. The actual panel update rate of 50.00 Hz, 25.00 Hz, 16.67 Hz, 12.50 Hz is generated by using 54.06 MHz quartz to generate nominally programmed image timing parameters for the 50-Hz panel update rate and changing the point clock divider separately. 10.00 Hz, 8.33 Hz, 7.14 Hz or 6.25 Hz.

Implementation Details: Using the 2X Memory Clock PLL as the input clock source for the point clock divider is a possible way to simplify the generation of 50% duty cycle clocks with all splitters.

Bit 8: Image Autosync Mode If the bit is set, the secondary display controller 106 automatically resets all of its internal image timing calculators whenever the Display Load sequence is initiated, ie, encountered The end of the first VsyncIn clock. This mode is used when the VsyncIn and VsyncOut frequencies are programmed to be exactly the same. If not, this mode should be used with care.

For example, if the secondary display controller 106 point clock divider is programmed to support a 25 Hz panel update rate, but the system's primary display controller 104 has a 50 Hz output rate, only the first half of the panel is secondary. The image timer of controller 106 is updated before being reset. The above artifacts can be avoided by performing the input and output frequencies at the same rate. However, it is possible to try to use the scan line interruption capability of the secondary display controller 106 to support the mixed use of the screen display rate.

Note that Video Auto Sync only works when the secondary display controller 106 follows the input 埠 indication, that is, when the Display Load sequence is being processed. This avoids display problems that may occur when the output value re-started by the primary display controller 104 is disturbed by the image update of the secondary display controller 106.

Bit 9: Display Time Out (Timeout) Actuation When the bit is set to 1, the secondary display controller 106 automatically stops the display process.

When the display timeout (Timeout) value image screen has been output without the display load (Load) sequence, the operation of displaying the load (Load) will automatically reset the internal pause calculator to display the timeout value register. The value inside. When the bit is set to 0, the secondary display controller 106 continuously displays output updates that are independent of the display load cycle.

Bit 10: Scan Line Interrupt Actuation Sets the bit to 1 to actuate the secondary display controller 106 to output a scan line interrupt output value to be generated during the image scan line, the value being programmed into a scan line Interrupt value register. The interrupt value becomes active at the beginning of the programmed line and remains active for one line of each picture. The sequence continues in this manner as long as the scan line interrupt value actuates the bit to one.

Bits 11-14: Reserved to retain these read-only bits and return to a value of 0 when read.

Bit 15: Self Test Mode When the power is turned on, the secondary display controller 106 samples the BIST0 pin to determine if it should enter normal operation, BIST0 low level, self test operation, or BIST0 high level. Once the reset is left, the state of the BIST pin is copied to the self test mode pin. The software can also enter the BIST mode by writing the bit to 1, and can resume normal operation by writing the bit to zero.

Embodiments of the present invention confirm that power consumption is reduced when the display subsystem is still driving. The secondary display controller can automatically update the display device regardless of the state of the processor and the primary display controller, thereby eliminating the need for continuous processor intervention. The primary and secondary display controllers and display devices can be powered down when there is no action for a long time, resulting in significant savings in power consumption of the display system.

Embodiments of the present invention do not require dedicated and expensive hardware and do not require the provision of an ideal system and can therefore be used in electronic components for cost and power sensitive applications.

The system or components thereof of the present invention can be used as an example of a computer system type. Computer systems include, for example, general purpose computers, programmed microprocessors, microcontrollers, peripheral integrated circuit components, and other devices or combinations thereof that may substantially constitute the steps of the method of the present invention.

The computer system includes a computer, an input device, a display unit, and a network. The computer includes a microprocessor that connects to the communication bus. The computer also includes memory, including, for example, unordered access memory (RAM) and read only memory (ROM). In addition, the computer system includes a storage device such as a hard disk or a removable storage device (such as a floppy disk drive, a CD player, etc.). The storage device can also be a device for carrying a computer program or other instructions on a computer system.

The computer system executes a set of instructions stored in one or more storage elements to process the input data. The storage component or other data may also retain data if necessary, or may be a source of data or a physical memory component present in the processing machine.

The set of instructions includes various computer instructions that instruct the processing machine to perform a particular task, such as constructing the method of the present invention. The instruction set can be a type of software program. Software can be of various types, such as system software or application software. In addition, the software can be a collection of different programs, a program module with a larger program, or a part of a program module. The software can also include a program-oriented modular program. Respond to the results of previous processing by responding to the user's commands by processing machine input data, or responding to requests from another processing machine.

However, the above description is only a detailed description of the preferred embodiments of the present invention, and the present invention is not limited thereto, and is not intended to limit the present invention. The scope of the patent application is subject to the scope of the present invention, and any one skilled in the art can easily include it in the field of the present invention. Any changes or modifications considered may be covered by the patents in this case below.

Show secondary system. . . 100

processor. . . 102

Main display controller. . . 104

Secondary display controller. . . 106

Display device. . . 108

Enter 埠. . . 202

Output 埠. . . 204

Picture buffer. . . 206

Clock. . . 208

First pin. . . 210

Second pin. . . 212

Third pin. . . 214

Fourth pin. . . 216

Fifth pin. . . 218

Processing module. . . 220

Decide on the module. . . 222

SDRAM interface 埠. . . 224

The first drawing shows a schematic diagram of an environment in which the specific embodiments of the present invention can be implemented; the second drawing shows a schematic diagram of each component in the secondary display controller according to an embodiment of the present invention; A flowchart of a method of conserving power consumption when a display device is being updated, according to an embodiment of the present invention; and FIGS. 4A and 4B are diagrams showing a control according to an embodiment of the present invention A flowchart of a method for switching a display device from a primary display controller to a secondary display controller; a fifth diagram illustrating a control display device switching from a secondary display controller to a primary display control in accordance with an embodiment of the present invention FIG. 6 is a flow chart showing a method for causing a secondary display controller to be activated from an inactive mode according to an embodiment of the present invention; and FIG. 7 is a diagram showing a specific method according to the present invention. Embodiments, a flowchart of a method step of converting primary display controller data content into reduced bit pattern; and eighth diagram showing a specific embodiment according to the present invention, Color vector read schematic channels (color-swizzling) processing method; and FIG line shows a ninth embodiment in accordance with one specific embodiment of the present invention, a secondary display controller from the inactive mode to start the timing of - a flowchart.

Enter 埠. . . 202

Output 埠. . . 204

Picture buffer. . . 206

Clock. . . 208

First pin. . . 210

Second pin. . . 212

Third pin. . . 214

Fourth pin. . . 216

Fifth pin. . . 218

Processing module. . . 220

Decide on the module. . . 222

SDRAM interface 埠. . . 224

Claims (28)

A method for reducing power consumption of a display subsystem in a computing unit, wherein the computing unit includes a display device, a processor, a primary display controller, and a primary display controller, the method comprising the steps of: Switching from an active mode to an inactive mode, if the processor does not generate a new update data; generating a second update data according to the processor or the primary display controller for updating an update data of the display device, The second update data is used to cause the secondary display controller to update the display device, wherein the second update data is different from the update data; and command the secondary display controller to update the display device with the second update data, Regarding the primary display controller and the processor and the display device within the display subsystem, wherein the secondary display controller consumes substantially less power than the primary display controller. The method of claim 1, further comprising converting the update data existing in the main display controller into a reduced bit pattern, the reduced bit pattern being visually incapable of being present in the main display controller The update data is different. The method of claim 2, wherein the reduced bit pattern is stored in a picture buffer, the picture buffer being coupled to the secondary display controller. The method of claim 2, wherein the step of converting the updated data present in the primary display controller into a reduced bit pattern comprises: a. processing the update present in the primary display controller Red bit of data Forming a reduced bit pattern, the red bit of the update data of the primary display controller and the reduced bit pattern corresponding to the first pixel of the first line of the display device; b. processing the primary display control The green bit of the update data is formed to form a reduced bit, and the green bit and the reduced bit pattern of the update data of the primary display controller are corresponding to the second pixel of the first line of the display device And c. processing the blue bit of the update data of the primary display controller to form a reduced bit pattern, wherein the blue bit and the reduced bit pattern of the updated data of the primary display controller correspond to The third pixel of the first line of the display device. The method of claim 4, further comprising processing the update data in the primary display controller for each pixel of each line of the display device, wherein the horizontal compensation color between each adjacent line different. The method of claim 2, further comprising the step of modifying an anti-aliasing reducing bit pattern, the step comprising determining each pixel value of each line of the display device, the pixel of each pixel The modified sawtooth edge value is obtained by calculating the current pixel value and the adjacent pixel value. The method of claim 2, comprising the step of processing the update data in the primary display controller to form a reduced bit pattern comprising converting the input color data of the updated data in the primary display controller into a single The color representative value, which coincides with the human luminosity perception of the updated data in the main display controller. The method of claim 2, wherein the step of processing the update data in the primary display controller comprises: passing another form through a green component of the update data in the primary display controller, the another type being The material is visually equivalent to the green content of the updated data within the primary display controller. The method of claim 1, further comprising: a. commanding the primary display controller to enter the active mode from the inactive mode, when the processor generates the new update data; b. informing the secondary display The controller processor has generated the new update data; and c. commands the primary display controller to update the display device. The method of claim 9, further comprising the step of converting a single update data picture in the primary display controller into the reduced bit pattern, the converting step instructing the secondary display controller to update the This is performed before the display device, and the conversion step is thereby used to improve display efficiency. The method of claim 1, wherein the secondary display controller is capable of entering an inactive mode, the inactive mode being entered by causing the display device to be inoperable without processor intervention. The method of claim 11, wherein the secondary display controller is capable of completely turning off the power of the display device. The method of claim 11, wherein the secondary display controller automatically switches from the inactive mode to the active mode upon receiving an input signal from the one or more input devices, the one or more The input device is connected to the computing unit, and the input signal is received by the secondary display controller without using the location The device is involved. The method of claim 13, wherein the input signal from the input device connected to the computing unit is received by a pin in the secondary display controller. The method of claim 11, wherein the secondary display controller can automatically switch from the inactive mode to the active mode upon receiving an input signal from the one or more input devices, the one or more An input device is coupled to the computing unit, the input signal being received by the secondary display controller via the intervention of the processor. The method of claim 1, wherein the processor is configured to reduce power consumption of the display subsystem within the computing unit based on a computer executable instruction stored in the computer readable medium. A display system includes: a computing unit, the computing unit includes a display device, a processor, a primary display controller, and a primary display controller; a display subsystem disposed in the computing unit; wherein the computing unit Used to: switch the primary display controller from an active mode to an inactive mode if the processor does not generate a new update data; according to the processor or the primary display controller is used to update the display device Updating data to generate a second update data, the second update data being used to cause the secondary display controller to update the display device, wherein the second update data is different from the update data; Commanding the secondary display controller to update the display device with the second update data, the update performed by the secondary display controller is independent of the primary display controller and the processor within the display secondary system, the display device setting In the display subsystem, the secondary display controller consumes substantially less power than the primary display controller. The display system of claim 17, wherein the calculating unit is further configured to convert the update data existing in the main display controller into a reduced bit pattern, wherein the reduced bit pattern is visually incapable of being present The update data in the primary display controller is different. The display system of claim 18, wherein the reduced bit pattern is stored in a picture buffer, the picture buffer being coupled to the secondary display controller. The display system of claim 18, wherein the calculating unit is further configured to: a. process a red bit of the update data existing in the main display controller to form a reduced bit pattern, The red bit of the update data of the main display controller and the reduced bit pattern correspond to the first pixel of the first line of the display device; b. the green bit of the update data in the main display controller is processed to Forming a reduced bit formation, the green bit and the reduced bit pattern of the update data of the primary display controller are corresponding to the second pixel of the first line of the display device; and c. processing the primary display controller The blue bit of the update data to shape In a reduced bit pattern, the blue bit and the reduced bit pattern of the update data of the primary display controller are corresponding to the third pixel of the first line of the display device. The display system of claim 18, wherein the calculating unit is further configured to perform a step of modifying an anti-aliasing reduction bit pattern, the step comprising determining each pixel of each line of the display device. The value of the modified sawtooth edge value for each pixel is calculated by calculating the current pixel value and the adjacent pixel value. The display system of claim 18, wherein the calculating unit is further configured to convert the input color data of the update data in the main display controller into a monochrome representative value, the monochrome representative value matching the main display control The human luminosity perception of the updated data within the device. The display system of claim 18, wherein the computing unit is further configured to pass another type of green composition of the updated data in the primary display controller, the other type being visually equivalent to the primary display The green content of the updated data in the controller. The display system of claim 17, wherein the computing unit is further configured to: a. command the primary display controller to enter the active mode from the inactive mode, when the processor generates the new update data; b. informing the secondary display that the controller processor has generated the new update data; and c. instructing the primary display controller to update the display device. The display system of claim 24, wherein the calculating unit is further configured to convert the single update data picture in the main display controller into the reduced bit pattern, the converting step is to command the secondary The display controller performs the update before the display device. The display system of claim 17, wherein the secondary display controller is capable of entering an inactive mode, the inactive mode being accessed by causing the display device to be inoperable without processor intervention. The display system of claim 17, wherein the secondary display controller is capable of completely turning off the power of the display device. The display system of claim 17, wherein the secondary display controller automatically switches from the inactive mode to the active mode upon receiving an input signal from the one or more input devices, the one or more The input device is connected to the computing unit, and the input signal is received by the secondary display controller without intervention by the processor.