TWI750979B - Control device and display device for reducing usage pin of component - Google Patents

Control device and display device for reducing usage pin of component Download PDF

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TWI750979B
TWI750979B TW109146774A TW109146774A TWI750979B TW I750979 B TWI750979 B TW I750979B TW 109146774 A TW109146774 A TW 109146774A TW 109146774 A TW109146774 A TW 109146774A TW I750979 B TWI750979 B TW I750979B
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pin
signal
display
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control
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TW109146774A
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TW202226186A (en
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郭盟煌
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新唐科技股份有限公司
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

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  • Computer Hardware Design (AREA)
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  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A control device suitable to a display device includes a control module. A first pin of the control module provides a control signal. A second pin of the control module provides a clock signal. A third pin of the control module provides a data signal, wherein the data signal includes display data and configuration setting data. A foruth pin of the control module provides a vertical synchronizing signal. During an enabling duration of the vertical synchronizing signal, the control module provides the control signal with a first level, the clock signal and the data signal including the configuration setting data to the display device, such that the display device performs a configuration setting according to the control signal, the clock signal and the the configuration setting data. During a disabling duration of the vertical synchronizing signal, the control module provides the control signal with a second level, the clock signal and the data signal incliding the display data to the display device, such that the display device performs a normal display according to the control signal, the clock signal and the display data.

Description

用於減少元件之使用接腳的控制裝置與顯示裝置Control device and display device for reducing the use of components

本發明關於一種控制裝置，特別是關於一種用於減少元件之使用接腳的控制裝置與顯示裝置。The present invention relates to a control device, in particular to a control device and a display device for reducing the use of pins for components.

一般來說，部分的顯示裝置需要透過序列周邊介面(serial peripheral interface, SPI)，來設定顯示裝置的內部暫存器，以調整顯示裝置的顯示特性(例如解析度等)。然而，顯示裝置的控制器會使用3個接腳分別提供SPI控制信號、SPI時脈信號、SPI資料信號，以便顯示裝置可以對應地設定及調整顯示特性。由於對顯示裝置的顯示特性進行設定會佔用到顯示裝置之控制器的3個接腳，會使控制器的使用功能受到侷限，而降低使用上的便利性。Generally speaking, some display devices need to configure the internal registers of the display device through a serial peripheral interface (SPI), so as to adjust the display characteristics (such as resolution, etc.) of the display device. However, the controller of the display device uses three pins to respectively provide the SPI control signal, the SPI clock signal, and the SPI data signal, so that the display device can set and adjust the display characteristics accordingly. Since the setting of the display characteristics of the display device will occupy three pins of the controller of the display device, the use function of the controller will be limited, and the convenience of use will be reduced.

因此，如何有效地減少控制器之使用接腳的數量是當前重要的課題。Therefore, how to effectively reduce the number of pins used by the controller is an important issue at present.

本發明提供一種控制裝置與顯示裝置，藉以有效地減少元件之使用接腳的數量，以便有空出來的接腳進行功能擴充，並可維持正常顯示功能，以增加使用上的便利性。The present invention provides a control device and a display device, which can effectively reduce the number of pins used for components, so that there are free pins for function expansion, and the normal display function can be maintained to increase the convenience in use.

本發明提供一種控制裝置，適用於顯示裝置。控制裝置包括控制模組。控制模組具有第一接腳、第二接腳、第三接腳與第四接腳。控制模組的第一接腳提供控制信號。控制模組的第二接腳提供時脈信號。控制模組的第三接腳提供資料信號，且資料信號包括顯示資料與配置設定資料。控制模組的第四接腳提供垂直同步信號。於垂直同步信號的致能期間，控制模組提供第一準位的控制信號、時脈信號與包括配置設定資料的資料信號給顯示裝置，使顯示模組依據控制信號、時脈信號與配置設定資料進行配置設定。於垂直同步信號的禁能期間，控制模組提供第二準位的控制信號、時脈信號與包括顯示資料的資料信號給顯示裝置，使顯示模組依據控制信號、時脈信號與顯示資料進行正常顯示。The present invention provides a control device suitable for a display device. The control device includes a control module. The control module has a first pin, a second pin, a third pin and a fourth pin. The first pin of the control module provides a control signal. The second pin of the control module provides a clock signal. The third pin of the control module provides data signals, and the data signals include display data and configuration setting data. The fourth pin of the control module provides a vertical synchronization signal. During the enabling period of the vertical synchronization signal, the control module provides the control signal of the first level, the clock signal and the data signal including the configuration setting data to the display device, so that the display module is set according to the control signal, the clock signal and the configuration setting data for configuration settings. During the disabling period of the vertical synchronization signal, the control module provides the control signal of the second level, the clock signal and the data signal including the display data to the display device, so that the display module performs the operation according to the control signal, the clock signal and the display data. normal display.

本發明提供一種顯示裝置，包括控制模組與顯示模組。控制模組具有第一接腳、第二接腳、第三接腳與第四接腳，控制模組的第一接腳提供控制信號，控制模組的第二接腳提供時脈信號，控制模組的第三接腳提供資料信號，且資料信號包括顯示資料與配置設定資料。顯示模組具有第一接腳、第二接腳、第三接腳、第四接腳、第五接腳與第六接腳。顯示模組的該第一接腳耦接控制模組的第一接腳。顯示模組的第二接腳與第三接腳耦接控制模組的第二接腳。顯示模組的第四接腳與第五接腳耦接控制模組的第三接腳。顯示模組的第六接腳耦接控制模組的第四接腳。於垂直同步信號的致能期間，控制模組提供第一準位的控制信號、時脈信號與包括配置設定資料的資料信號給顯示模組，使顯示模組依據控制信號、時脈信號與配置設定資料進行配置設定。於垂直同步信號的禁能期間，控制模組提供第二準位的控制信號、時脈信號與包括顯示資料的資料信號給顯示模組，使顯示模組依據控制信號、時脈信號與顯示資料進行正常顯示。The invention provides a display device including a control module and a display module. The control module has a first pin, a second pin, a third pin and a fourth pin. The first pin of the control module provides a control signal, and the second pin of the control module provides a clock signal to control the The third pin of the module provides data signals, and the data signals include display data and configuration setting data. The display module has a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin. The first pin of the display module is coupled to the first pin of the control module. The second pin and the third pin of the display module are coupled to the second pin of the control module. The fourth pin and the fifth pin of the display module are coupled to the third pin of the control module. The sixth pin of the display module is coupled to the fourth pin of the control module. During the enabling period of the vertical synchronization signal, the control module provides the control signal of the first level, the clock signal and the data signal including the configuration setting data to the display module, so that the display module can be configured according to the control signal, the clock signal and the configuration data. Configuration data for configuration settings. During the disabling period of the vertical synchronization signal, the control module provides the control signal of the second level, the clock signal and the data signal including the display data to the display module, so that the display module is based on the control signal, the clock signal and the display data. normal display.

本發明所揭露之控制裝置與顯示裝置，透過控制模組的第一接腳提供控制信號，控制模組的第二接腳提供時脈信號，控制模組的第三接腳提供資料信號，且資料信號包括顯示資料與配置設定資料，且於垂直同步信號的致能期間，控制模組提供第一準位的控制信號、時脈信號與包括配置設定資料的資料信號給顯示模組(顯示裝置)，使顯示模組依據控制信號、時脈信號與配置設定資料進行配置設定，以及於垂直同步信號的禁能期間，控制模組提供第二準位的控制信號、時脈信號與包括顯示資料的資料信號給顯示模組(顯示裝置)，使顯示模組(顯示裝置)依據控制信號、時脈信號與顯示資料進行正常顯示。另外，顯示模組的第二接腳與第三接腳可以共用控制模組的第二接腳以及顯示模組的第四接腳與第五接腳可以共用控制模組的第三接腳。如此一來，可以有效地減少控制模組之使用接腳的數量，使控制模組可以有空出來的接腳對控制模組的功能進行擴充，並可維持顯示模組的正常顯示功能，以增加使用上的便利性。In the control device and the display device disclosed in the present invention, the control signal is provided through the first pin of the control module, the clock signal is provided by the second pin of the control module, the data signal is provided by the third pin of the control module, and The data signal includes display data and configuration setting data, and during the enabling period of the vertical synchronization signal, the control module provides a first-level control signal, a clock signal and a data signal including the configuration setting data to the display module (display device). ), so that the display module is configured and set according to the control signal, the clock signal and the configuration setting data, and during the disable period of the vertical synchronization signal, the control module provides the control signal of the second level, the clock signal and the display data including the second level The data signal is sent to the display module (display device), so that the display module (display device) can display normally according to the control signal, clock signal and display data. In addition, the second pin and the third pin of the display module can share the second pin of the control module, and the fourth pin and the fifth pin of the display module can share the third pin of the control module. In this way, the number of pins used by the control module can be effectively reduced, so that the control module can have free pins to expand the functions of the control module, and the normal display function of the display module can be maintained, so that the Increase the convenience of use.

在以下所列舉的各實施例中，將以相同的標號代表相同或相似的元件或組件。In the various embodiments listed below, the same or similar elements or components will be represented by the same reference numerals.

第1圖為依據本發明之一實施例之顯示裝置的示意圖。請參考第1圖，顯示裝置100可以包括控制模組110與顯示模組130。在本實施例中，控制模組110例如為微控制器(micro control unit, MCU)、微處理器(micro processor)或中央處理器(central processing unit, CPU)，顯示模組130例如為液晶顯示器(liquid crystal display, LCD)。FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention. Please refer to FIG. 1 , the display device 100 may include a control module 110 and a display module 130 . In this embodiment, the control module 110 is, for example, a microcontroller (micro control unit, MCU), a microprocessor (micro processor), or a central processing unit (central processing unit, CPU), and the display module 130 is, for example, a liquid crystal display (liquid crystal display, LCD).

控制模組110可以至少具有第一接腳111、第二接腳112、第三接腳113、第四接腳114、第五接腳115與第六接腳116。The control module 110 may at least have a first pin 111 , a second pin 112 , a third pin 113 , a fourth pin 114 , a fifth pin 115 and a sixth pin 116 .

控制模組110的第一接腳111(例如為序列周邊介面(SPI)之控制信號接腳)提供控制信號CS。控制模組110的第二接腳112(例如為顯示器介面之時脈信號接腳)提供時脈信號CLK，控制模組110的第三接腳113(例如為顯示器介面之資料信號接腳)提供資料信號DAT。另外，資料信號DAT包括顯示資料與配置設定資料。控制模組110的第四接腳114(例如為顯示器介面之垂直同步信號接腳)提供垂直同步信號VSYNC。控制模組110的第五接腳115(例如為顯示器介面之水平同步信號接腳)提供水平同步信號HSYNC。控制模組110的第六接腳116(例如為顯示器介面之資料顯示指示信號接腳)提供資料顯示指示信號DE。The first pin 111 of the control module 110 (eg, a control signal pin of a serial peripheral interface (SPI)) provides a control signal CS. The second pin 112 of the control module 110 (for example, the clock signal pin of the display interface) provides the clock signal CLK, and the third pin 113 of the control module 110 (for example, the data signal pin of the display interface) provides Data signal DAT. In addition, the data signal DAT includes display data and configuration setting data. The fourth pin 114 of the control module 110 (eg, the vertical synchronization signal pin of the display interface) provides the vertical synchronization signal VSYNC. The fifth pin 115 of the control module 110 (for example, the horizontal synchronization signal pin of the display interface) provides the horizontal synchronization signal HSYNC. The sixth pin 116 of the control module 110 (eg, a data display instruction signal pin of the display interface) provides a data display instruction signal DE.

顯示模組130可以至少具有第一接腳131、第二接腳132、第三接腳133、第四接腳134、第五接腳135、第六接腳136、第七接腳137與第八接腳138。The display module 130 may at least have a first pin 131 , a second pin 132 , a third pin 133 , a fourth pin 134 , a fifth pin 135 , a sixth pin 136 , a seventh pin 137 and a first pin 137 . Eight pins 138.

顯示模組130的第一接腳131(例如為SPI之控制信號接腳)耦接控制模組110的第一接腳111，接收控制信號CS。顯示模組130的第二接腳132(例如為SPI之時脈信號接腳)與第三接腳133(例如為顯示器介面之時脈信號接腳)耦接控制模組110的第二接腳112，接收時脈信號CLK。顯示模組130的第四接腳134(例如為SPI之資料信號接腳)與第五接腳135(例如為顯示器介面之時脈信號接腳)耦接控制模組110的第三接腳113，接收資料信號DAT。The first pin 131 of the display module 130 (eg, a control signal pin of SPI) is coupled to the first pin 111 of the control module 110 to receive the control signal CS. The second pin 132 of the display module 130 (for example, the SPI clock signal pin) and the third pin 133 (for example, the display interface clock signal pin) are coupled to the second pin of the control module 110 112. Receive the clock signal CLK. The fourth pin 134 of the display module 130 (for example, the data signal pin of SPI) and the fifth pin 135 (for example, the clock signal pin of the display interface) are coupled to the third pin 113 of the control module 110 , receive the data signal DAT.

顯示模組130的第六接腳136(例如為顯示器介面之垂直同步信號接腳)耦接控制模組110的第四接腳114，接收垂直同步信號VSYNC。顯示模組130的第七接腳137(例如為顯示器介面之水平同步信號接腳)耦接控制模組110的第五接腳115，接收水平同步信號HSYNC。顯示模組130第八接腳138(例如為顯示器介面之資料顯示指示信號接腳)耦接控制模組110的第六接腳116，接收資料顯示指示信號DE。The sixth pin 136 of the display module 130 (eg, the vertical synchronization signal pin of the display interface) is coupled to the fourth pin 114 of the control module 110 to receive the vertical synchronization signal VSYNC. The seventh pin 137 of the display module 130 (eg, the horizontal synchronization signal pin of the display interface) is coupled to the fifth pin 115 of the control module 110 to receive the horizontal synchronization signal HSYNC. The eighth pin 138 of the display module 130 (eg, a data display indication signal pin of the display interface) is coupled to the sixth pin 116 of the control module 110 to receive the data display indication signal DE.

於垂直同步信號VSYNC的致能期間，控制模組110提供第一準位的控制信號CS、時脈信號CLK與包括配置設定資料的資料信號DAT給顯示模組130，使顯示模組130可以依據控制信號CS、時脈信號CLK與配置設定資料進行配置設定。在本實施例中，於垂直同步信號VSYNC的致能期間，控制信號CS可以作為SPI控制信號，時脈信號CLK可以作為SPI時脈信號，資料信號DAT可以作為SPI資料信號。另外，本實施例之垂直同步信號VSYNC例如為負緣觸發，亦即於垂直同步信號VSYNC之致能期間，垂直同步信號VSYNC為低邏輯準位，但本發明實施例不限於此。在其他實施例中，垂直同步信號VSYNC也可以為正緣觸發，亦即於垂直同步信號VSYNC之致能期間，垂直同步信號VSYNC為高邏輯準位。During the enabling period of the vertical synchronization signal VSYNC, the control module 110 provides the first-level control signal CS, the clock signal CLK and the data signal DAT including the configuration setting data to the display module 130, so that the display module 130 can The control signal CS, the clock signal CLK and the configuration setting data are used for configuration setting. In this embodiment, during the enabling period of the vertical synchronization signal VSYNC, the control signal CS can be used as the SPI control signal, the clock signal CLK can be used as the SPI clock signal, and the data signal DAT can be used as the SPI data signal. In addition, the vertical synchronization signal VSYNC in this embodiment is, for example, negative edge triggered, that is, during the enabling period of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a low logic level, but the embodiment of the present invention is not limited to this. In other embodiments, the vertical synchronization signal VSYNC can also be positive edge triggered, that is, during the enabling period of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a high logic level.

舉例來說，控制模組110的第一接腳111可以提供第一準位(例如低邏輯準位)的控制信號CS，控制模組110的第二接腳112可以提供時脈信號CLK、控制模組110的第三接腳113可以提供包括配置設定資料的資料信號DAT給顯示模組130。For example, the first pin 111 of the control module 110 can provide the control signal CS of a first level (eg, a low logic level), and the second pin 112 of the control module 110 can provide the clock signal CLK, control The third pin 113 of the module 110 can provide a data signal DAT including configuration setting data to the display module 130 .

此時，顯示模組130的第一接腳131接收提供第一準位(例如低邏輯準位)的控制信號CS，顯示模組130的第二接腳132接收時脈信號CLK，顯示模組130的第四接腳134接收包括配置設定資料的資料信號DAT。接著，顯示模組130可以依據第一準位(例如低邏輯準位)的控制信號CS、時脈信號CLK與資料信號DAT的配置設定資料進行配置設定。At this time, the first pin 131 of the display module 130 receives the control signal CS providing a first level (eg, a low logic level), the second pin 132 of the display module 130 receives the clock signal CLK, and the display module The fourth pin 134 of 130 receives a data signal DAT including configuration setting data. Then, the display module 130 can perform configuration setting according to the configuration setting data of the control signal CS of the first level (eg, a low logic level), the clock signal CLK and the data signal DAT.

在本實施例中，配置設定資料包括顯示模組130的解析度、影像格式等初始設定，但本發明實施例不限於此。舉例來說，顯示模組130可以利用資料信號DAT的配置設定資料，對顯示模組130的內部暫存器(internal register)進行配置設定，使得顯示模組130可以依據所設定之解析度、影像格式，顯示對應的顯示畫面。In this embodiment, the configuration setting data includes initial settings such as the resolution and image format of the display module 130, but the embodiment of the present invention is not limited thereto. For example, the display module 130 can use the configuration setting data of the data signal DAT to configure and set the internal register of the display module 130, so that the display module 130 can use the set resolution, image format to display the corresponding display screen.

另一方面，於垂直同步信號VSYNC的致能期間，控制模組110的第六接腳116可以提供例如低邏輯準位的資料顯示指示信號DE(例如資料顯示指示信號DE的禁能期間)。此時，顯示模組130的第三接腳133接收時脈信號CLK、顯示模組130的第五接腳135接收包括配置設定資料的資料信號DAT，顯示模組130的第八接腳138接收低邏輯準位的資料顯示指示信號DE。由於資料顯示指示信號DE為低邏輯準位，表示資料顯示指示信號DE的禁能期間，因此顯示模組130會忽略顯示模組130之第三接腳133所接收之時脈信號CLK與顯示模組130之第五接腳135所接收之包括配置設定資料的資料信號DAT，亦即顯示模組130不會對包括配置設定資料的資料信號DAT進行顯示。On the other hand, during the enabling period of the vertical synchronization signal VSYNC, the sixth pin 116 of the control module 110 can provide, for example, a low logic level data display indication signal DE (for example, during the disabling period of the data display indication signal DE). At this time, the third pin 133 of the display module 130 receives the clock signal CLK, the fifth pin 135 of the display module 130 receives the data signal DAT including the configuration setting data, and the eighth pin 138 of the display module 130 receives The data of the low logic level shows the indicator signal DE. Since the data display indication signal DE is at a low logic level, indicating the disable period of the data display indication signal DE, the display module 130 ignores the clock signal CLK received by the third pin 133 of the display module 130 and the display module The data signal DAT including the configuration setting data received by the fifth pin 135 of the group 130 , that is, the display module 130 does not display the data signal DAT including the configuration setting data.

於垂直同步信號VSYNC的禁能期間，控制模組110提供第二準位的控制信號CS、時脈信號CLK與包括顯示資料的資料信號DAT給顯示模組130，使顯示模組130依據控制信號CS、時脈信號CLK與顯示資料進行正常顯示。在本實施例中，於垂直同步信號VSYNC的禁能期間，時脈信號CLK可以作為顯示器介面的時脈信號，資料信號DAT可以作為顯示器介面的資料信號。另外，於垂直同步信號VSYNC之禁能期間，垂直同步信號VSYNC例如為高邏輯準位。During the disable period of the vertical synchronization signal VSYNC, the control module 110 provides the control signal CS of the second level, the clock signal CLK and the data signal DAT including the display data to the display module 130, so that the display module 130 is based on the control signal CS, clock signal CLK and display data are displayed normally. In this embodiment, during the disable period of the vertical synchronization signal VSYNC, the clock signal CLK can be used as the clock signal of the display interface, and the data signal DAT can be used as the data signal of the display interface. In addition, during the disable period of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is, for example, a high logic level.

舉例來說，控制模組110的第一接腳111可以提供第二準位(例如高邏輯準位)的控制信號CS，控制模組110的第二接腳112可以提供時脈信號CLK，控制模組110的第三接腳113可以提供包括顯示資料的資料信號DAT。For example, the first pin 111 of the control module 110 can provide the control signal CS of a second level (eg, a high logic level), and the second pin 112 of the control module 110 can provide the clock signal CLK, to control the The third pin 113 of the module 110 can provide a data signal DAT including display data.

此時，顯示模組130的第一接腳131接收提供第二準位的控制信號CS，顯示模組130的第二接腳132接收時脈信號CLK、顯示模組130的第四接腳134接收包括顯示資料的資料信號DAT。由於控制信號CS為高邏輯準位，因此顯示模組130會忽略顯示模組130之第二接腳132所接收之時脈信號CLK與顯示模組130之第四接腳134所接收之包括顯示資料的資料信號DAT，亦即顯示模組130不會對內部暫存器進行配置設定。At this time, the first pin 131 of the display module 130 receives the control signal CS providing the second level, the second pin 132 of the display module 130 receives the clock signal CLK, and the fourth pin 134 of the display module 130 receives the clock signal CLK. A data signal DAT including display data is received. Since the control signal CS is at a high logic level, the display module 130 ignores the clock signal CLK received by the second pin 132 of the display module 130 and the display module 130 received by the fourth pin 134 including display The data signal DAT of the data, that is, the display module 130 does not configure the internal register.

另一方面，於顯示模組130之垂直同步信號VSYNC的禁能期間，控制模組110的第六接腳116可以提供例如高邏輯準位的資料顯示指示信號DE(例如資料顯示指示信號DE的致能期間)。此時，顯示模組130的第三接腳133接收時脈信號CLK，顯示模組130的第五接腳135接收包括顯示資料的資料信號DAT，顯示模組130的第八接腳138接收高邏輯準位的資料顯示指示信號DE。接著，顯示模組130可以依據高邏輯準位的資料顯示指示信號DE、時脈信號CLK與包括顯示資料的資料信號DAT進行正常顯示，亦即顯示模組130可以於資料顯示指示信號DE的致能期間，透過時脈信號CLK來顯示包括顯示資料的資料信號DAT。On the other hand, during the disabling period of the vertical synchronization signal VSYNC of the display module 130, the sixth pin 116 of the control module 110 can provide, for example, a data display indication signal DE of a high logic level (for example, a data display indication signal DE of a high logic level). enabling period). At this time, the third pin 133 of the display module 130 receives the clock signal CLK, the fifth pin 135 of the display module 130 receives the data signal DAT including the display data, and the eighth pin 138 of the display module 130 receives the high The data of the logic level shows the indicator signal DE. Then, the display module 130 can display normally according to the high logic level data display indication signal DE, the clock signal CLK and the data signal DAT including the display data, that is, the display module 130 can display the data normally when the data display indication signal DE During the active period, the data signal DAT including the display data is displayed through the clock signal CLK.

在本實施例中，每個垂直同步信號VSYNC的致能期間會包括數條掃描線(scanning line)，且這些掃描線可以分別對應水平同步信號HSYNC的一個水平同步期間，亦即垂直同步信號VSYNC的致能期間可以包括水平同步信號HSYNC的多個水平同步期間。另外，每條掃描線會依據顯示模組130的解析度而具有對應數量之時脈信號CLK的時脈脈波，亦即水平同步期間的每一者包括時脈信號CLK的多個時脈脈波。此外，每條掃描線所具有之時脈信號CLK的時脈脈波的數量會依據顯示模組的130不同解析度而不同。In this embodiment, each enable period of the vertical synchronization signal VSYNC includes several scanning lines, and these scanning lines may respectively correspond to a horizontal synchronization period of the horizontal synchronization signal HSYNC, that is, the vertical synchronization signal VSYNC The enable period of can include a plurality of horizontal synchronization periods of the horizontal synchronization signal HSYNC. In addition, each scan line has a corresponding number of clock pulses of the clock signal CLK according to the resolution of the display module 130 , that is, each horizontal synchronization period includes a plurality of clock pulses of the clock signal CLK Wave. In addition, the number of clock pulses of the clock signal CLK of each scan line varies according to different resolutions of the display module 130 .

舉例來說，假設顯示模組130的解析度為640x480，則每條掃描線至少有640個時脈脈波，亦即水平同步期間的每一者包括時脈信號CLK之640個時脈脈波。若垂直同步信號VSYNC的致能期間有10條掃描線，則垂直同步信號VSYNC的致能期間會有時脈信號CLK之6,400(640*10)個時脈脈波，而此6,400個時脈脈波就可以作為SPI時脈信號使用。如此一來，顯示模組130就可以在6,400個時脈脈波的期間，利用資料信號DAT的配置設定資料對顯示模組130之內部暫存器的配置設定。For example, if the resolution of the display module 130 is 640×480, each scan line has at least 640 clock pulses, that is, each horizontal synchronization period includes 640 clock pulses of the clock signal CLK . If there are 10 scan lines during the enabling period of the vertical synchronization signal VSYNC, there will be 6,400 (640*10) clock pulses of the clock signal CLK during the enabling period of the vertical synchronization signal VSYNC, and the 6,400 clock pulses The wave can be used as the SPI clock signal. In this way, the display module 130 can use the configuration setting data of the data signal DAT to set the configuration of the internal register of the display module 130 during the period of 6,400 clock pulses.

另外，若垂直同步信號VSYNC的致能期間有2條掃描線，則垂直同步信號VSYNC的致能期間會有時脈信號CLK之1,280(640*2)個時脈脈波，而此1,280個時脈脈波可以作為SPI時脈信號使用。其餘則類推。上述顯示模組130的解析度為640x480僅為本發明的一種實施範例，但本發明實施例不限於此。使用者可視其需求調整垂直同步信號VSYNC的致能期間所包括之掃描線的數量，亦即垂直同步信號VSYNC的致能期間所包括之水平同步信號HSYNC之水平同步期間的數量。In addition, if there are 2 scan lines during the enable period of the vertical synchronization signal VSYNC, there will be 1,280 (640*2) clock pulses of the clock signal CLK during the enable period of the vertical synchronization signal VSYNC, and the 1,280 time The pulse wave can be used as the SPI clock signal. The rest are analogous. The above-mentioned resolution of the display module 130 of 640×480 is only an embodiment of the present invention, but the embodiment of the present invention is not limited thereto. The user can adjust the number of scan lines included in the enable period of the vertical synchronization signal VSYNC, that is, the number of horizontal synchronization periods of the horizontal synchronization signal HSYNC included in the enable period of the vertical synchronization signal VSYNC according to his needs.

另外，控制信號CS的第一準位與控制信號的CS的第二準位可以為互補。舉例來說，當控制信號CS的第一準位為低邏輯準位時，控制信號的CS的第二準位為高邏輯準位，如前述實施例的例子。但本發明實施例不限於此。在一些實施例中，當控制信號CS的第一準位為高邏輯準位時，控制信號的CS的第二準位為低邏輯準位。In addition, the first level of the control signal CS and the second level of the control signal CS may be complementary. For example, when the first level of the control signal CS is a low logic level, the second level of the control signal CS is a high logic level, as in the examples of the foregoing embodiments. However, the embodiments of the present invention are not limited thereto. In some embodiments, when the first level of the control signal CS is a high logic level, the second level of the control signal CS is a low logic level.

藉由上述實施例的說明，可知本實施例之顯示模組130的第二接腳132(例如SPI之時脈信號接腳)與第三接腳133(例如顯示介面之時脈信號接腳)可以共用控制模組110的第二接腳112(例如顯示器介面之時脈接腳)以及顯示模組130的第四接腳(例如SPI之資料信號接腳)134與第五接腳135(例如顯示器介面之資料信號接腳可以共用控制模組110的第三接腳113(例如顯示器介面之資料信號接腳)，並透過控制模組110於垂直同步信號VSYNC的致能期間與禁能期間，分別提供對應的控制信號、時脈信號與資料信號給顯示模組130，使得顯示模組130可以進行配置設定或正常顯示。如此一來，可以有效地減少控制模組110之使用接腳的的數量，亦即減少控制模組110產生SPI時脈信號與SPI資料信號的接腳，以達成使用在顯示裝置100上的簡化串列週邊介面(simplified serial peripheral interface)的效果。另外，由於控制模組110之使用接腳的數量減少，使控制模組110可以有空出來的接腳對控制模組110的功能進行擴充，並可維持顯示模組130的正常顯示功能，以增加使用上的便利性。From the description of the above embodiment, it can be known that the second pin 132 (eg, the clock signal pin of SPI) and the third pin 133 (eg, the clock signal pin of the display interface) of the display module 130 of the present embodiment The second pin 112 of the control module 110 (such as the clock pin of the display interface) and the fourth pin (such as the data signal pin of the SPI) 134 and the fifth pin 135 (such as the data signal pin of the SPI) of the display module 130 can be shared. The data signal pins of the display interface can share the third pin 113 of the control module 110 (for example, the data signal pins of the display interface), and through the control module 110 during the enabling period and the disabling period of the vertical synchronization signal VSYNC, Corresponding control signals, clock signals and data signals are respectively provided to the display module 130, so that the display module 130 can be configured or displayed normally. In this way, the use of pins of the control module 110 can be effectively reduced. Quantity, namely reducing the pin of control module 110 to produce SPI clock signal and SPI data signal, to reach the effect of the simplified serial peripheral interface (simplified serial peripheral interface) used on display device 100. In addition, due to the control module The number of pins used in the group 110 is reduced, so that the control module 110 can have free pins to expand the function of the control module 110, and can maintain the normal display function of the display module 130, so as to increase the convenience of use sex.

在第1圖中，控制模組110之第三接腳113與顯示模組130的第五接腳115繪示為1個。但實際上，顯示裝置100可以具有多條資料信號線，亦即控制模組110與顯示器模組130可以具有多個資料信號接腳，其中控制模組110之第三接腳113與顯示模組130的第五接腳135為上述資料信號接腳的其中一個。另外，不同的顯示裝置100會具有不同數量的資料信號線。In FIG. 1, the third pin 113 of the control module 110 and the fifth pin 115 of the display module 130 are shown as one. But in fact, the display device 100 may have a plurality of data signal lines, that is, the control module 110 and the display module 130 may have a plurality of data signal pins, wherein the third pin 113 of the control module 110 and the display module The fifth pin 135 of 130 is one of the above-mentioned data signal pins. In addition, different display devices 100 may have different numbers of data signal lines.

舉例來說，當顯示裝置100有8條資料信號線時，控制模組110與顯示器模組130可以具有8個資料信號接腳，其中控制模組110之第三接腳113與顯示模組130的第五接腳135可以上述8個資料信號接腳的其中一個。當顯示裝置100有16條資料信號線時，控制模組110與顯示器模組130可以具有16個資料信號接腳，其中控制模組110之第三接腳113與顯示模組130的第五接腳135可以上述16個資料信號接腳的其中一個。當顯示裝置100有有24條資料信號線時，控制模組110與顯示器模組130可以具有24個資料信號接腳，其中控制模組110之第三接腳113與顯示模組130的第五接腳135可以上述24個資料信號接腳的其中一個。其餘則類推。For example, when the display device 100 has 8 data signal lines, the control module 110 and the display module 130 may have 8 data signal pins, wherein the third pin 113 of the control module 110 and the display module 130 The fifth pin 135 can be one of the above-mentioned eight data signal pins. When the display device 100 has 16 data signal lines, the control module 110 and the display module 130 can have 16 data signal pins, wherein the third pin 113 of the control module 110 and the fifth connection of the display module 130 The pin 135 can be one of the above-mentioned 16 data signal pins. When the display device 100 has 24 data signal lines, the control module 110 and the display module 130 can have 24 data signal pins, wherein the third pin 113 of the control module 110 and the fifth pin of the display module 130 The pin 135 may be one of the above 24 data signal pins. The rest are analogous.

第2圖為依據本發明之一實施例之垂直同步信號與水平同步信號的波形圖。第3圖為第2圖之水平同步信號的一部分、控制信號、時脈信號、資料信號、資料顯示指示信號的波形圖。第4圖為第2圖之水平同步信號的另一部分、控制信號、時脈信號、資料信號、資料顯示指示信號的波形圖。FIG. 2 is a waveform diagram of a vertical synchronization signal and a horizontal synchronization signal according to an embodiment of the present invention. Figure 3 is a waveform diagram of a part of the horizontal synchronization signal, control signal, clock signal, data signal, and data display indication signal in Figure 2. FIG. 4 is a waveform diagram of another part of the horizontal synchronization signal, the control signal, the clock signal, the data signal, and the data display indication signal in FIG. 2 .

在第2圖~第4圖中，標號“VSYNC”表示垂直同步信號，標號“HSYNC”表示水平同步信號，標號“TF”表示顯示模組130的一個畫面(frame)期間，標號“TE”表示垂直同步信號VSYNC的致能期間，標號“TD”表示垂直同步信號VSYNC的禁能期間，標號“TH1”、“TH2”分別表示水平同步信號HSYNC的水平同步期間(例如包括水平同步信號HSYNC的致能期間(例如低邏輯準位)與禁能期間(例如高邏輯準位))，標號“CLK”表示時脈信號，標號“DE”表示資料顯示指示信號，標號“DAT”表示資料信號，標號“D”表示顯示資料，標號“INV”表示無效資料，標號“CSD”表示配置設定資料，標號“CS”表示控制信號。In Figs. 2 to 4, the symbol "VSYNC" denotes a vertical synchronization signal, the symbol "HSYNC" denotes a horizontal synchronization signal, the symbol "TF" denotes a frame period of the display module 130, and the symbol "TE" denotes a frame period of the display module 130. The enable period of the vertical synchronization signal VSYNC, the symbol "TD" indicates the disable period of the vertical synchronization signal VSYNC, and the symbols "TH1" and "TH2" respectively indicate the horizontal synchronization period of the horizontal synchronization signal HSYNC (for example, including the enable period of the horizontal synchronization signal HSYNC. During the enable period (eg low logic level) and disable period (eg high logic level)), the symbol "CLK" represents the clock signal, the symbol "DE" represents the data display indication signal, the symbol "DAT" represents the data signal, the symbol "D" indicates display data, "INV" indicates invalid data, "CSD" indicates configuration setting data, and "CS" indicates control signal.

請同時參考第1圖~第4圖。如第2圖所示，在顯示模組130的一個畫面期間TF，於垂直同步信號VSYNC的致能期間TE，垂直同步信號VSYNC為低邏輯準位，並且垂直同步信號VSYNC的致能期間TE包括2條掃描線，亦即垂直同步信號VSYNC的致能期間TE包括2個水平同步信號HSYNC的水平同步期間TH1，且這2個水平同步信號HSYNC的水平同步期間TH1的每一者可以包括時脈信號CLK的多個時脈脈波。此時，如第3圖所示，控制模組110提供低邏輯準位的控制信號CS、時脈信號CLK、包括配置設定資料CSD的資料信號DAT與低邏輯準位的資料顯示信號DE給顯示模組130。Please refer to Figures 1 to 4 at the same time. As shown in FIG. 2, in a frame period TF of the display module 130, during the enabling period TE of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a low logic level, and the enabling period TE of the vertical synchronization signal VSYNC includes The two scan lines, that is, the enable period TE of the vertical synchronization signal VSYNC includes the horizontal synchronization period TH1 of the two horizontal synchronization signals HSYNC, and each of the horizontal synchronization periods TH1 of the two horizontal synchronization signals HSYNC may include a clock Multiple clock pulses of signal CLK. At this time, as shown in FIG. 3, the control module 110 provides a low logic level control signal CS, a clock signal CLK, a data signal DAT including the configuration setting data CSD, and a low logic level data display signal DE to the display Module 130.

接著，顯示模組130可以依據低邏輯位準的控制信號CS、時脈信號CLK與配置設定資料CSD進行配置設定。另一方面，顯示模組130可以依據低邏輯準位的資料顯示指示信號DE(例如資料顯示指示信號DE的禁能期間)，忽略顯示模組130之第三接腳133所接收之時脈信號CLK與顯示模組130之第五接腳135所接收之包括配置設定資料CSD的DAT，亦即顯示模組130不會對包括配置設定資料CSD的資料信號DAT進行顯示。Next, the display module 130 can perform configuration setting according to the control signal CS, the clock signal CLK and the configuration setting data CSD of the low logic level. On the other hand, the display module 130 can ignore the clock signal received by the third pin 133 of the display module 130 according to the data display indication signal DE at a low logic level (for example, during the disable period of the data display indication signal DE) The DAT including the configuration setting data CSD received by the CLK and the fifth pin 135 of the display module 130 , that is, the display module 130 does not display the data signal DAT including the configuration setting data CSD.

接著，如第2圖所示，於垂直同步信號VSYNC的禁能期間TD，垂直同步信號VSYNC為高邏輯準位，並且垂直同步信號VSYNC的禁能期間TD可以包括多個水平同步信號HSYNC的水平同步期間TH2，且這些水平同步期間TH2的每一者可以包括時脈信號CLK的多個時脈脈波。此時，如第4圖所示，控制模組110可以提供高邏輯準位的控制信號CS、時脈信號CLK、包括顯示資料D的資料信號DAT、高邏輯位準的資料顯示指示信號DE給顯示模組130。Next, as shown in FIG. 2, during the disable period TD of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a high logic level, and the disable period TD of the vertical synchronization signal VSYNC may include a plurality of horizontal synchronization signals HSYNC. The synchronization period TH2, and each of these horizontal synchronization periods TH2 may include a plurality of clock pulses of the clock signal CLK. At this time, as shown in FIG. 4 , the control module 110 can provide a high logic level control signal CS, a clock signal CLK, a data signal DAT including display data D, and a high logic level data display indication signal DE to the Display module 130 .

接著，顯示模組130可以依據高邏輯準位的控制信號CS，忽略顯示模組130之第二接腳132所接收之時脈信號CLK與顯示模組130之第四接腳134所接收之包括顯示資料D的資料信號DAT，亦即顯示模組130不會對內部暫存器進行配置設定。Next, the display module 130 can ignore the clock signal CLK received by the second pin 132 of the display module 130 and the clock signal CLK received by the fourth pin 134 of the display module 130 according to the control signal CS of the high logic level. The data signal DAT of the display data D, that is, the display module 130 does not perform configuration settings on the internal register.

另一方面，顯示模組130可以依據高邏輯準位的資料顯示指示信號DE(例如資料顯示指示信號DE的致能期間)、時脈信號CLK與包括顯示資料D的資料信號DAT進行正常顯示，亦即顯示模組130可以於資料顯示指示信號DE的致能期間，透過時脈信號CLK來顯示包括顯示資料D的資料信號DAT。On the other hand, the display module 130 can display normally according to the data display indication signal DE at a high logic level (for example, during the enabling period of the data display indication signal DE), the clock signal CLK and the data signal DAT including the display data D, That is, the display module 130 can display the data signal DAT including the display data D through the clock signal CLK during the enabling period of the data display indication signal DE.

在第2圖中，繪示出垂直同步信號VSYNC的致能期間TE包括2條掃描線，亦即致能期間TE包括水平同步信號HSYNC的2個水平同步期間TH1，但本發明實施例不限於此。使用者可視其需求調整垂直同步信號VSYNC的致能期間TE包括3條或3條以上的掃描線，亦即致能期TE可以包括水平同步信號HSYNC的3個或3個以上的水平同步期間TH1，都可以達成相同的效果。In FIG. 2, it is shown that the enable period TE of the vertical synchronization signal VSYNC includes two scan lines, that is, the enable period TE includes two horizontal synchronization periods TH1 of the horizontal synchronization signal HSYNC, but the embodiment of the present invention is not limited to this. The user can adjust the enable period TE of the vertical synchronization signal VSYNC to include three or more scan lines according to his needs, that is, the enable period TE can include three or more horizontal synchronization periods TH1 of the horizontal synchronization signal HSYNC , can achieve the same effect.

綜上所述，本發明所揭露之控制裝置與顯示裝置，透過控制模組的第一接腳提供控制信號，控制模組的第二接腳提供時脈信號，控制模組的第三接腳提供資料信號，且資料信號包括顯示資料與配置設定資料，且於垂直同步信號的致能期間，控制模組提供第一準位的控制信號、時脈信號與包括配置設定資料的資料信號給顯示模組(顯示裝置)，使顯示模組依據控制信號、時脈信號與配置設定資料進行配置設定，以及於垂直同步信號的禁能期間，控制模組提供第二準位的控制信號、時脈信號與包括顯示資料的資料信號給顯示模組(顯示裝置)，使顯示模組(顯示裝置)依據控制信號、時脈信號與顯示資料進行正常顯示。另外，顯示模組的第二接腳與第三接腳可以共用控制模組的第二接腳以及顯示模組的第四接腳與第五接腳可以共用控制模組的第三接腳。如此一來，可以有效地減少控制模組之使用接腳的數量，使控制模組可以有空出來的接腳對控制模組的功能進行擴充，並可維持顯示模組的正常顯示功能，以增加使用上的便利性。To sum up, in the control device and the display device disclosed in the present invention, the control signal is provided through the first pin of the control module, the clock signal is provided by the second pin of the control module, and the third pin of the control module is provided. Provide a data signal, and the data signal includes display data and configuration setting data, and during the enabling period of the vertical synchronization signal, the control module provides a first-level control signal, a clock signal and a data signal including the configuration setting data to the display The module (display device) enables the display module to perform configuration settings according to the control signal, the clock signal and the configuration setting data, and during the disabling period of the vertical synchronization signal, the control module provides the control signal and clock of the second level The signal and the data signal including the display data are sent to the display module (display device), so that the display module (display device) can display normally according to the control signal, the clock signal and the display data. In addition, the second pin and the third pin of the display module can share the second pin of the control module, and the fourth pin and the fifth pin of the display module can share the third pin of the control module. In this way, the number of pins used by the control module can be effectively reduced, so that the control module can have free pins to expand the functions of the control module, and the normal display function of the display module can be maintained, so that the Increase the convenience of use.

本發明雖以實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention is disclosed above by the embodiments, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100:顯示裝置100: Display device

110:控制模組110: Control Module

111,131:第一接腳111,131: Pin 1

112,132:第二接腳112,132: The second pin

113,133:第三接腳113,133: The third pin

114,134:第四接腳114,134: Fourth pin

115,135:第五接腳115,135: Fifth pin

116,136:第六接腳116, 136: sixth pin

130:顯示模組130: Display Module

137:第七接腳137: seventh pin

138:第八接腳138: Eighth pin

CS:控制信號CS: control signal

CLK:時脈信號CLK: clock signal

DAT:資料信號DAT: data signal

VSYNC:垂直同步信號VSYNC: vertical sync signal

HSYNC:水平同步信號HSYNC: horizontal sync signal

DE:資料顯示指示信號DE: data display indicator signal

TF:畫面期間TF: During the picture

TE:致能期間TE: Enable period

TD:禁能期間TD: Disable period

TH1,TH2:水平同步期間TH1, TH2: Horizontal synchronization period

D:顯示資料D: display data

INV:無效資料INV: invalid data

CSD:配置設定資料CSD: Configuration Setting Data

第1圖為依據本發明之一實施例之顯示裝置的示意圖。 第2圖為依據本發明之一實施例之垂直同步信號與水平同步信號的波形圖。 第3圖為第2圖之水平同步信號的一部分、控制信號、時脈信號、資料信號、資料顯示指示信號的波形圖。 第4圖為第2圖之水平同步信號的另一部分、控制信號、時脈信號、資料信號、資料顯示指示信號的波形圖。 FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention. FIG. 2 is a waveform diagram of a vertical synchronization signal and a horizontal synchronization signal according to an embodiment of the present invention. Figure 3 is a waveform diagram of a part of the horizontal synchronization signal, control signal, clock signal, data signal, and data display indication signal in Figure 2. FIG. 4 is a waveform diagram of another part of the horizontal synchronization signal, the control signal, the clock signal, the data signal, and the data display indication signal in FIG. 2 .

100:顯示裝置 100: Display device

110:控制裝置 110: Control device

111,131:第一接腳 111,131: Pin 1

112,132:第二接腳 112,132: The second pin

113,133:第三接腳 113,133: The third pin

114,134:第四接腳 114,134: Fourth pin

115,135:第五接腳 115,135: Fifth pin

116,136:第六接腳 116, 136: sixth pin

130:顯示模組 130: Display Module

137:第七接腳 137: seventh pin

138:第八接腳 138: Eighth pin

CS:控制信號 CS: control signal

CLK:時脈信號 CLK: clock signal

DAT:資料信號 DAT: data signal

VSYNC:垂直同步信號 VSYNC: vertical sync signal

HSYNC:水平同步信號 HSYNC: horizontal sync signal

DE:資料顯示指示信號 DE: data display indicator signal

Claims (10)

一種控制裝置，適用於一顯示裝置，包括： 一控制模組，具有一第一接腳、一第二接腳、一第三接腳與一第四接腳，該控制模組的該第一接腳提供一控制信號，該控制模組的該第二接腳提供一時脈信號，該控制模組的該第三接腳提供一資料信號，且該資料信號包括一顯示資料與一配置設定資料，該控制模組的該第四接腳提供一垂直同步信號； 其中，於該垂直同步信號的一致能期間，該控制模組提供一第一準位的該控制信號、該時脈信號與包括該配置設定資料的該資料信號給該顯示裝置，使該顯示裝置依據該控制信號、該時脈信號與該配置設定資料進行一配置設定； 其中，於該垂直同步信號的一禁能期間，該控制模組提供一第二準位的該控制信號、該時脈信號與包括該顯示資料的該資料信號給該顯示裝置，使該顯示裝置依據該控制信號、該時脈信號與該顯示資料進行一正常顯示。 A control device, suitable for a display device, includes: A control module has a first pin, a second pin, a third pin and a fourth pin, the first pin of the control module provides a control signal, the control module The second pin provides a clock signal, the third pin of the control module provides a data signal, and the data signal includes a display data and a configuration setting data, the fourth pin of the control module provides a vertical synchronization signal; Wherein, during an enabling period of the vertical synchronization signal, the control module provides the control signal of a first level, the clock signal and the data signal including the configuration setting data to the display device, so that the display device perform a configuration setting according to the control signal, the clock signal and the configuration setting data; Wherein, during a disabled period of the vertical synchronization signal, the control module provides the control signal of a second level, the clock signal and the data signal including the display data to the display device, so that the display device A normal display is performed according to the control signal, the clock signal and the display data. 如請求項1之控制裝置，其中該配置設定資料包括該顯示裝置的解析度、影像格式。The control device of claim 1, wherein the configuration setting data includes a resolution and an image format of the display device. 如請求項1之控制裝置，其中該控制模組更包括一第四接腳，該控制模組的該第四接腳提供一水平同步信號。The control device of claim 1, wherein the control module further comprises a fourth pin, and the fourth pin of the control module provides a horizontal synchronization signal. 如請求項3之控制裝置，其中該垂直同步信號的該致能期間包括該水平同步信號的多個水平同步期間，且該些水平同步期間的每一者包括該時脈信號的多個時脈脈波。The control device of claim 3, wherein the enable period of the vertical synchronization signal includes a plurality of horizontal synchronization periods of the horizontal synchronization signal, and each of the horizontal synchronization periods includes a plurality of clocks of the clock signal pulse wave. 如請求項1之控制裝置，其中該第一準位與該第二準位為互補。The control device of claim 1, wherein the first level and the second level are complementary. 一種顯示裝置，包括： 一控制模組，具有一第一接腳、一第二接腳、一第三接腳與一第四接腳，該控制模組的該第一接腳提供一控制信號，該控制模組的該第二接腳提供一時脈信號，該控制模組的該第三接腳提供一資料信號，且該資料信號包括一顯示資料與一配置設定資料，該控制模組的該第四接腳提供一垂直同步信號；以及 一顯示模組，具有一第一接腳、一第二接腳、一第三接腳、一第四接腳、一第五接腳與一第六接腳，該顯示模組的該第一接腳耦接該控制模組的該第一接腳，該顯示模組的該第二接腳與該第三接腳耦接該控制模組的該第二接腳，該顯示模組的該第四接腳與該第五接腳耦接該控制模組的該第三接腳，該顯示模組的該第六接腳耦接該控制模組的該第四接腳； 其中，於該垂直同步信號的一致能期間，該控制模組提供一第一準位的該控制信號、該時脈信號與包括該配置設定資料的該資料信號給該顯示模組，使該顯示模組依據該控制信號、該時脈信號與該配置設定資料進行一配置設定； 其中，於該垂直同步信號的一禁能期間，該控制模組提供一第二準位的該控制信號、該時脈信號與包括該顯示資料的該資料信號給該顯示模組，使該顯示模組依據該控制信號、該時脈信號與該顯示資料進行一正常顯示。 A display device, comprising: A control module has a first pin, a second pin, a third pin and a fourth pin, the first pin of the control module provides a control signal, the control module The second pin provides a clock signal, the third pin of the control module provides a data signal, and the data signal includes a display data and a configuration setting data, the fourth pin of the control module provides a vertical sync signal; and A display module has a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin, the first pin of the display module The pin is coupled to the first pin of the control module, the second pin and the third pin of the display module are coupled to the second pin of the control module, the display module The fourth pin and the fifth pin are coupled to the third pin of the control module, and the sixth pin of the display module is coupled to the fourth pin of the control module; Wherein, during the enabling period of the vertical synchronization signal, the control module provides the control signal of a first level, the clock signal and the data signal including the configuration setting data to the display module, so that the display module is The module performs a configuration setting according to the control signal, the clock signal and the configuration setting data; Wherein, during a disabled period of the vertical synchronization signal, the control module provides the control signal of a second level, the clock signal and the data signal including the display data to the display module, so that the display The module performs a normal display according to the control signal, the clock signal and the display data. 如請求項6之顯示裝置，其中該配置設定資料包括該顯示模組的解析度、影像格式。The display device of claim 6, wherein the configuration setting data includes a resolution and an image format of the display module. 如請求項6之顯示裝置，其中該控制模組更包括一第四接腳，該控制模組的該第四接腳提供一水平同步信號，且該顯示模組更包括一第六接腳，該顯示模組的第六接腳耦該接控制模組的該第四接腳。 The display device of claim 6, wherein the control module further comprises a fourth pin, the fourth pin of the control module provides a horizontal synchronization signal, and the display module further comprises a sixth pin, The sixth pin of the display module is coupled to the fourth pin of the connection control module. 如請求項8之顯示裝置，其中該垂直同步信號的該致能期間包括該水平同步信號的多個水平同步期間，且該些水平同步期間的每一者包括該時脈信號的多個時脈脈波。 The display device of claim 8, wherein the enable period of the vertical synchronization signal includes a plurality of horizontal synchronization periods of the horizontal synchronization signal, and each of the horizontal synchronization periods includes a plurality of clocks of the clock signal pulse wave. 如請求項6之顯示裝置，其中該第一準位與該第二準位為互補。The display device of claim 6, wherein the first level and the second level are complementary.
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