WO2024061318A1

WO2024061318A1 - Method and apparatus for transmitting signals to rgb interface of display device

Info

Publication number: WO2024061318A1
Application number: PCT/CN2023/120401
Authority: WO
Inventors: 费维和
Original assignee: 施耐德电器工业公司; 费维和
Priority date: 2022-09-23
Filing date: 2023-09-21
Publication date: 2024-03-28
Also published as: CN117809542A

Abstract

A method and apparatus (400) for transmitting signals to an RGB interface of a display device. The apparatus (400) comprises: a multi-channel serial bus module (410), which generates a clock CLK signal, and transmits an image data signal and the clock CLK signal to an RGB interface; a counter module (420), which generates a horizontal sync HSYNC signal, a vertical sync VSYNC signal, and a data enable DE signal; and a general purpose input/output (GPIO) module (430), which transmits the HSYNC signal, the VSYNC signal and the DE signal to the RGB interface. A display device which employs the RGB interface can be driven without an RGB-specific interface or a specific interface chip, so that more models of apparatuses can drive the display device which employs the RGB interface, a model selection range of the apparatus is increased, and hardware costs of the apparatus are reduced.

Description

Method and device for transmitting signals to RGB interface of display device

Technical field

The present disclosure relates to a method and device for transmitting signals to an RGB (red, green, and blue) interface of a display device.

Background technique

With the development of display technology, more and more human-machine interface products tend to use displays with rich colors, detailed images, and wide viewing angles, such as color high-resolution thin film transistor (TFT) liquid crystal displays. As display resolution increases, the amount of image data transferred increases. In the past, only low-transmission rate display interfaces were supported, such as Serial Peripheral Interface (SPI), 8080 parallel interface, etc., which can no longer meet the data transmission requirements of high-resolution color displays. Replaced by RGB interface, Low Voltage Differential Signaling (LVDS) interface, Mobile Industry Processor Interface (MIPI), etc.

Contents of the invention

The present disclosure relates to a method and device for transmitting signals to an RGB interface of a display device, which can drive a display device using an RGB interface without an RGB dedicated interface or a dedicated interface chip, thereby enabling more types of devices to drive using the RGB interface. The RGB interface display device increases the selection range of the device and reduces the hardware cost of the device.

According to a first aspect of the present disclosure, a method of transmitting a signal to an RGB interface of a display device is provided. The method includes: using a multi-channel serial bus module to generate a clock CLK signal; using a counter module to generate a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal; and using a multi-channel serial bus module to generate the image data signal and clock The CLK signal is transmitted to the RGB interface, and the HSYNC signal, VSYNC signal and DE signal are transmitted to the RGB interface using the general-purpose input and output GPIO module.

According to a second aspect of the present disclosure, an apparatus for transmitting a signal to an RGB interface of a display device is provided. The device includes: a multi-channel serial bus module that generates a clock CLK signal and transmits the image data signal and clock CLK signal to the RGB interface; a counter module that generates a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal ; and a general-purpose input and output GPIO module, which transmits HSYNC signals, VSYNC signals and DE signals to the RGB interface.

Description of the drawings

Aspects, features and advantages of the present disclosure will become clearer and easier to understand through the following description of the embodiments in conjunction with the accompanying drawings, in which:

Figure 1 schematically shows a known scheme for communication between a device and a display device.

Figure 2 schematically shows a known scheme for communication between a device and a display device.

FIG. 3 shows a timing diagram of various signals related to the RGB interface.

FIG. 4 is a schematic diagram of a device for transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.

FIG. 5 schematically shows the process of outputting image data signals by the multi-channel serial bus module of the device according to the embodiment of the present disclosure.

FIG. 6 schematically shows a flow chart of reading and writing image data in a device according to an embodiment of the present disclosure.

FIG. 7 is a flowchart of a method of transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.

Detailed ways

The present disclosure will be described in detail below with reference to exemplary embodiments of the present disclosure. However, the present disclosure is not limited to the embodiments described herein, but may be implemented in many different forms. The described embodiments are merely intended to make this disclosure thorough and complete, and to fully convey the concept of the disclosure to those skilled in the art. Features of the various embodiments described may be combined with or substituted for each other unless expressly excluded or should be excluded by context.

As mentioned above, currently display devices usually use RGB interfaces to achieve image data transmission. This requires that the device for transmitting image data (such as a microcontroller (MCU) or a microprocessor (MPU)) connected to the display device also adopts a corresponding dedicated RGB interface chip. Some devices also have built-in dedicated interfaces such as RGB or MIPI interfaces. Figures 1 and 2 schematically show known schemes for communication between a device (shown as an MCU/MPU) and a display device. In order to achieve high-resolution color image display, control signals and data signals need to be transmitted between the device and the display device. Specifically, as shown in Figures 1 and 2, the control signals transmitted between the device and the display device include: (1) horizontal synchronization (HSYNC) signal, also known as line synchronization signal; (2) vertical synchronization (VSYNC) signal, also known as frame synchronization signal; (3) data enable (DE) signal; (4) clock (CLK) signal. The data signal transmitted between the device and the display device includes image data for controlling the display brightness of red, green, and blue, respectively, shown as R/G/B. In the scheme of Figure 1, the RGB interface of the MCU/MPU is used to transmit the above control signals and data signals. The solution in Figure 2 uses a dedicated RGB bridge chip, so that the RGB bridge chip and the MCU/MPU can communicate using a serial interface (such as SPI) or a parallel interface (such as an 8080 interface), and the RGB bridge chip and the display device communicate using an RGB interface to transmit the above control signals and data signals. However, whether it is a solution using a dedicated interface chip or a solution with a dedicated interface, the hardware cost of the device will be increased, which will make it difficult to select the hardware of the device.

Embodiments of the present disclosure propose a method and device for transmitting signals to an RGB interface of a display device, which can drive a display device using an RGB interface without a dedicated RGB interface or dedicated interface chip, thereby enabling more types of devices to Driving display devices using RGB interfaces increases the selection range of devices and reduces the hardware costs of the devices.

Figure 3 shows the timing diagram of various signals related to the RGB interface. According to the RGB interface protocol, image data is output line by line in a sequence of pixel lines, and one frame of image consists of multiple pixel lines. Through the cooperation of the timing of each signal in Figure 3, frame-by-frame display of image data can be achieved. Table 1 below shows the meaning of each signal or parameter in Figure 3.

Table 1

Combining Table 1 and Figure 3, it can be understood that the display of each row of pixels relies on the first pulse edge of the HSYNC signal for synchronization, and the time required to display one row of pixel data is HSYNC = (HBP + HDOTS + HFP) CLK cycles. Each row of pixel display needs to output (HBP+HDOTS+HFP) data clock bits. Each frame of pixel display relies on the first pulse edge of the VSYNC signal for synchronization. The time required to display one frame of pixel data is VSYNC = (VBP + VDOTS + VFP) line time HSYNC. Each line time outputs (HBP+HDOTS+HFP) data clock bits, so in order to display each frame of image (i.e. one screen image), the number of data clock bits that need to be transmitted is (HBP+HDOTS+HFP)*(VBP+VDOTS +VFP). When the interface outputs valid pixel data, the interface generates the first pulse edge of the DE signal (for example, the rising edge when the high level is active); when the output of valid pixel data is completed, the interface generates the second pulse edge of the DE signal (for example, the high level is active). When it is valid, it is the falling edge). The HSW, HBP, HDOTS, HFP, VSW, VBP, VDOTS and VFP parameters of the display device are all known.

The method and device for transmitting signals to the RGB interface of the display device according to the embodiments of the present disclosure use the above parameters to generate and provide the control signals HSYNC, HSYNC, and VSYNC, DE, CLK and data signals R/G/B, so display devices using RGB interfaces can be driven without a dedicated RGB interface or dedicated interface chip, allowing more types of devices to drive displays using RGB interfaces equipment, increasing the selection range of devices used for driving and reducing their hardware costs.

FIG. 4 is a schematic diagram of an apparatus 400 for transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure. The device 400 may be a general-purpose processor, such as an MCU/MPU. As shown in FIG. 4 , the device 400 may include a multi-channel serial bus module 410 , a counter module 420 and a general purpose input and output (GPIO) module 430 . The device 400 can use its own modules to generate the above control signals HSYNC, VSYNC, DE, CLK and data signals R/G/B, and transmit them to the RGB interface of the display device without the need for a RGB dedicated interface or a dedicated interface chip.

Multiplex serial bus module 410 may generate the CLK signal described with respect to FIG. 3 and Table 1. The clock signal of the multi-channel serial bus module itself can be used as the CLK signal output to the RGB interface of the display device. Multiplexed serial bus module 410 may include a Quad-Line Serial Peripheral Interface (QSPI), an Eight-Line Serial Peripheral Interface (OSPI), or a FlexIO module (such as the FlexIO module in NXP's I.MX RT series ), etc., to realize multi-bit serial transmission of R/G/B image data signals to the RGB interface of the display device. The QSPI module includes 4 serial data lines, which can realize 4-bit R/G/B serial data output. The OSPI module includes 8 serial data lines, which can realize 8-bit R/G/B serial data output. The FlexIO module Can be configured to include 4 or 8 data buses, enabling 4-bit or 8-bit R/G/B serial data output.

FIG. 5 schematically shows the process of the multi-channel serial bus module 410 outputting R/G/B image data signals. The multi-channel serial bus module 410 can send the binary image data (shown as bit0 to bit31) in its data buffer area to the output terminal in batches according to the number N of the bus. Figure 5 takes the multi-channel serial bus module 410 as a QSPI module as an example, showing that 4-bit R/G/B serial data output is achieved through N=4 serial data lines. As shown in Figure 5, every time binary image data is sent, the CLK port of the multi-channel serial bus module 410 outputs a pulse. At the same time, the data in the data buffer area is shifted to the right by N bits. Each bit of the shifted binary data is mapped separately. At the data output port of the multi-channel serial bus module 410. This data shift dispatch operation will continue until all data in the data buffer has been moved out. pass The image data is sequentially written into the data buffer area of the multi-channel serial bus module 410, and the CLK port and data output port of the multi-channel serial bus module 410 will output clock signals and image data signals.

Counter module 420 may generate the HSYNC signal, VSYNC signal, and DE signal described with respect to FIG. 3 and Table 1. Specifically, as shown in FIG. 4 , the counter module 420 may include a first pulse counter module 421 , a second pulse counter module 422 and a third pulse counter module 423 for generating an HSYNC signal, a VSYNC signal and a DE signal respectively. In addition, the apparatus 400 may include a general purpose input output (GPIO) module 430 that transmits the HSYNC signal, VSYNC signal and DE signal generated by the counter module 420 to the RGB interface of the display device.

The pulse counting source, counting period, channel matching value, output mode, etc. of the first pulse counter module 421, the second pulse counter module 422, and the third pulse counter module 423 can be set to output the above signal. As known to those skilled in the art, the counter module can generally include one or more channels. By setting the corresponding counting period and the channel matching value, the counter can be made to generate a counter whose period corresponds to the counting period and has a corresponding channel matching value. pulse width.

In one embodiment, the first pulse counter module 421 can be a single-channel counter module, and the first pulse counter module 421 can be set as follows to generate the above-mentioned HSYNC signal: (1) Set the counting period T1 of the first pulse counter module 421 to Set to the sum of HBP, HDOTS, HFP as described with respect to Figure 3 and Table 1, i.e. T1=HBP+HDOTS+HFP. The counting period T1 determines the period of the pulses generated by the first pulse counter module 421 . (2) Set the channel matching value C1 of the first pulse counter module 421 to the HSW described with respect to FIG. 3 and Table 1, that is, C1=HSW. The channel matching value C1 determines the pulse width of the pulse generated by the first pulse counter module 421, that is, the effective duration. (3) Set the output mode of the first pulse counter module 421 to the pulse width modulation (PWM) pulse continuous output mode, so that the first pulse counter module 421 can continuously output PWM pulses. (4) Set the pulse counting source of the first pulse counter module 421 to the CLK signal generated by the multi-channel serial bus module 410, so that every time a CLK signal is received, the count of the first pulse counter module 421 will increase by 1. In addition, the PWM pulse output by the first pulse counter module 421 can be set to be a high level or a low level according to whether the HSYNC signal to be output is high level or low level. Through the above settings, when the multi-channel serial bus module 410 outputs the CLK signal and the R/G/B image data signal, the first pulse counter module 421 will output a PWM with a pulse width of HSW and a period of (HBP+HDOTS+HFP) Pulse, the above-mentioned HSYNC signal.

In one embodiment, the second pulse counter module 422 can be a single-channel or multi-channel counter module, and the second pulse counter module 422 can be set as follows to generate the above-mentioned VSYNC signal: (1) Set the second pulse counter module 422 to The counting period T2 is set to the sum of VBP, VDOTS, VFP described with respect to Figure 3 and Table 1, that is, T2=VBP+VDOTS+VFP. The counting period T2 determines the period of the pulses generated by the second pulse counter module 422 . (2) Set the first channel matching value C2,1 of the second pulse counter module 422 to the VSW described with respect to FIG. 3 and Table 1, that is, C2,1=VSW. The channel matching value C2,1 determines the pulse width of the pulse generated by the second pulse counter module 422, that is, the effective duration. (3) Set the output mode of the second pulse counter module 422 to the PWM pulse continuous output mode, so that the second pulse counter module 422 can continuously output PWM pulses. (4) Set the pulse counting source of the second pulse counter module 422 to the HSYNC signal generated by the first pulse counter module 421. number, so that every time an HSYNC signal is received, the count of the second pulse counter module 422 will be increased by 1. In addition, the PWM pulse output by the second pulse counter module 422 can be set to be a high level or a low level according to whether the VSYNC signal to be output is high level or low level. Through the above settings, when the multi-channel serial bus module 410 outputs the CLK signal and the R/G/B image data signal, as the first pulse counter module 421 outputs the HSYNC signal, the second pulse counter module 422 will output a pulse width of VSW , a PWM pulse with a period of (VBP+VDOTS+VFP), which is the above-mentioned VSYNC signal.

In one embodiment, the third pulse counter module 423 may be a single-channel counter module, and the third pulse counter module 423 may be configured as follows to generate the above DE signal: (1) Set the counting period T3 of the third pulse counter module 423 Set to the sum of HBP and the HDOTS described with respect to Figure 3 and Table 1, ie T3=HBP+HDOTS. (2) Set the channel matching value C3 of the third pulse counter module 423 to the HBP described with respect to FIG. 3 and Table 1, that is, C3=HBP. The channel matching value C3 determines the pulse width of the pulse generated by the third pulse counter module 423, that is, the effective duration. (3) Set the output mode of the third pulse counter module 423 to the single pulse output mode, so that the third pulse counter module 423 outputs one pulse each time it is triggered by the trigger source. The single pulse output by the third pulse counter module 423 can be set to be low level or high level according to whether the DE signal to be output is high level or low level. (4) Set the pulse counting source of the third pulse counter module 423 to the CLK signal generated by the multi-channel serial bus module 410, so that every time a CLK signal is received, the count of the third pulse counter module 423 will increase by 1. (5) Set the trigger source of the third pulse counter module 423 to the overflow flag of the first pulse counter module 421 . After the third pulse counter module 423 is triggered, it starts counting from 0 and outputs the first pulse edge (for the case where DE is a high level active, the first pulse edge can be a falling edge). When the count value reaches HBP, the third pulse counter module 423 outputs a second pulse edge (for the case where DE is active high, the second pulse edge may be a rising edge). When the count value reaches HBP+HDOTS, the third pulse counter module 423 stops counting and outputs the third pulse edge (for the case where DE is high-level active, the third pulse edge may be a falling edge). Since the counting period T1=HBP+HDOTS+HFP of the first pulse counter module 421 is larger than the counting period of the third pulse counter module 423, the third pulse counter module 423 maintains the stopped state after outputting the third pulse edge until the third pulse edge. The count value of a pulse counter module 421 reaches T1=HBP+HDOTS+HFP. As a result, the counting of the first pulse counter module 421 overflows and is reset. At this time, the overflow flag of the first pulse counter module 421 becomes 1, thereby triggering the third pulse counter module 423 to restart counting. Through the above settings, when the multi-channel serial bus module 410 outputs the CLK signal and the R/G/B image data signal, the third pulse counter module 422 will output the above-mentioned DE signal.

According to the RGB interface protocol, the DE signal can be generated only when one frame of valid pixel data is displayed (that is, a valid display pixel row) to prevent interference. Therefore, in one embodiment, the third pulse counter module 423 can be enabled and disabled by the second pulse counter module 422 so that the third pulse counter module 423 only generates the DE signal when a valid display pixel row is displayed. Therefore, the following settings can be made: (1) Set the second channel matching value C2,2 of the second pulse counter module 422 to the VBP described with respect to FIG. 3 and Table 1, that is, C2,2=VBP. (2) Set the third channel matching value C2,3 of the second pulse counter module 422 to the VBP and VDOTS described in Figure 3 and Table 1 The sum is C2,3=VBP+VDOTS. Through the above settings, the third pulse counter module 423 can be enabled when the count value of the second pulse counter module 422 reaches VBP, and the third pulse can be disabled when the count value of the second pulse counter module 422 reaches (VBP+VDOTS). Counter module 423. Specifically, the above enabling and disabling can be performed by triggering an interrupt request. Therefore, as shown in Figure 4, in one embodiment, the apparatus 400 may also include a central processing unit (CPU) 440. When the count value of the second pulse counter module 422 reaches the second channel matching value C2,2=VBP, the second channel of the second pulse counter module 422 may trigger an interrupt request to enable the third pulse counter module 423 through the CPU 440 . When the count value of the second pulse counter module 422 reaches the third channel matching value C2,3=VBP+VDOTS, the third channel of the second pulse counter module 422 triggers an interrupt request to disable the third pulse counter module 423 through the CPU 440 .

In one embodiment, in order to reduce the interrupt burden of the CPU 440 of the device 400, the device 400 may also include a direct memory access (DMA) module 450 and a data storage module 460. The data storage module 460 may be a memory, for example. The DMA module 450 can read the R/G/B image data signal from the data storage module 460 and write the R/G/B image data signal to the multiplex serial bus module 410 without relying on a large number of interrupt operations of the CPU 440 .

FIG. 6 schematically shows a flow chart of the DMA module 450 reading image data from the data storage module 460 and writing the image data to the multi-channel serial bus module 410. In step S610, the DMA module 450 is initialized. This initialization may include setting a source address from which the DMA module 450 reads image data, a target address to which the DMA module 450 writes image data, and a target count value. There is a continuous address space in the data storage module 460 to store one frame of image data, and the above-mentioned source address corresponds to the starting address of this continuous address space. The above target count value corresponds to the total data amount of one frame of image/the amount of data stored in the storage space of the data storage module 460 corresponding to each address. The counter value of the DMA module 450 is set correspondingly according to the target count value. The DMA module 450 may read the image data address by address and write it into the data buffer area of the multiplex serial bus module 410 , where the destination address corresponds to the address of the data buffer area of the multiplex serial bus module 410 .

In step S620 , the DMA module 450 transfers the image data from the source address to the destination address.

In step S630, the DMA module 450 updates the source address pointer to point to the next data storage address in the data storage module 460 as the new source address.

In step S640, the counter value of the DMA module 450 is decremented by 1, which indicates that the DMA module 450 has completed a data transmission task.

In step S650, the multi-channel serial bus module 410 performs output according to the timing sequence of FIG. 5, and sends the image data signal and CLK signal to the RGB interface of the display device.

In step S660, it is determined whether the data buffer area of the multi-channel serial bus module 410 is empty. If it is not empty, it means that the image data in the data buffer area has not been completely output, so return to step S650 to continue the above operation. If the data cache area is empty, proceed to step S670.

In step S670, it is determined whether the counter value of the DMA module 450 has decremented to 0. If it is not 0, it means that one frame of image data has not been completely output, so return to step S620 to continue the above operation. If the counter value is 0, it means that one frame of image data has been completely output, and it is necessary to return to the original source address to read and read the next frame of image. output. Therefore, in step S680, the DMA module 450 updates the source address pointer to point to the original source address and resets the counter value to the target count value, that is, restores the initialization settings, and then repeats the above steps S620 to S680 to perform the next DMA transfer cycle. Transmit a new frame of image data.

It should be pointed out that the RGB interface of the existing display device currently supports three working modes, namely SYNC mode (control signals are HSYNC, VSYNC, CLK, excluding DE), SYNC+DE mode (control signals are HSYNC, VSYNC, CLK, DE), and DE mode (control signals are CLK, DE, excluding HSYNC and VSYNC). The technical solution described above is aimed at the most complex SYNC+DE mode. The above technical solution can be modified as required to implement the other two working modes. For example, for the SYNC mode, the third pulse counter module 423 may not be set, and there is no need to perform interrupt-related operations. For the DE mode, the second pulse counter module 422 may not be set, and the third pulse counter module 423 may be enabled at the initial stage, so that there is no need to perform interrupt-related operations. It can be seen that for the SYNC mode and the DE mode, since there is no need to execute interrupts, the method and device according to the embodiment of the present disclosure do not need to occupy the CPU's time resources, thereby reducing the burden on the CPU. Even for the SYNC+DE mode, except for the second pulse counter module 422 triggering interrupt requests twice to occupy the CPU, the rest of the operations are implemented by the hardware module of the device 400, and the two interrupt requests of the second pulse counter module 422 are only for enabling and disabling the third pulse counter module 423, respectively. The relevant instructions are simple, occupy less CPU time resources, and greatly reduce the burden on the CPU.

According to the embodiment of the present disclosure, the device for transmitting signals to the RGB interface of the display device can drive the display device using the RGB interface without the RGB dedicated interface or dedicated interface chip, so that more types of devices can drive the display device using the RGB interface, increase the selection range of the device, and reduce the hardware cost of the device. In addition, the burden on the CPU of the device can be reduced.

Figure 7 is a flowchart of a method 700 of transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure. The method 700 may be performed by the apparatus 400 described with reference to FIG. 4 . Device 400 may be a general-purpose processor, such as an MCU/MPU. The method 700 is briefly described below with reference to FIG. 4 and FIG. 7 . The method 700 begins at step S710, where the CLK signal described with respect to FIG. 3 is generated by the multiplex serial bus module 410 of the device 400. Multiplex serial bus modules can include Quad-Line Serial Peripheral Interface (QSPI), Eight-Line Serial Peripheral Interface (OSPI), or FlexIO modules. At step S720, the HSYNC signal, VSYNC signal and DE signal described with respect to FIG. 3 are generated by the counter module 420 of the device 400. In step S730, the multi-channel serial bus module 410 of the device 400 transmits the image data signal and the CLK signal to the RGB interface of the display device, and the GPIO module 430 of the device 400 transmits the HSYNC signal, VSYNC signal and DE signal to the display device. The RGB interface of the device.

Generating the HSYNC signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the first pulse counter module 421 to the sum of HBP, HDOTS, and HFP; setting the channel matching value of the first pulse counter module 421 to HSW ; Set the output mode of the first pulse counter module 421 to the PWM pulse continuous output mode, and set the pulse counting source of the first pulse counter module 421 to the CLK signal.

Generating the VSYNC signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the second pulse counter module 422 to the sum of VBP, VDOTS, and VFP; The first channel matching value of 422 is set to VSW; the output mode of the second pulse counter module 422 is set to the PWM pulse continuous output mode, and the pulse counting source of the second pulse counter module 422 is set to the HSYNC signal.

Generating the DE signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the third pulse counter module 423 to the sum of HBP and HDOTS; setting the channel matching value of the third pulse counter module 423 to HBP; The output mode of the third pulse counter module 423 is set to the single pulse output mode, the pulse counting source of the third pulse counter module 423 is set to the CLK signal, and the trigger source of the third pulse counter module 423 is set to the first pulse counter module 421 overflow flag.

Generating the DE signal by the counter module 420 of the device 400 in step S720 may also include: setting the second channel matching value of the second pulse counter module 422 to VBP and setting the third channel matching value of the second pulse counter module 422 to VBP. and VDOTS, such that the third pulse counter module 423 is enabled when the count value of the second pulse counter module 422 reaches VBP, and is disabled when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS. Pulse counter module 423.

Enabling the third pulse counter module 423 when the count value of the second pulse counter module 422 reaches VBP may include: when the count value of the second pulse counter module 422 reaches VBP, the second channel of the second pulse counter module 422 triggers an interrupt. A request is made to enable the third pulse counter module 423 via the CPU 440. Disabling the third pulse counter module 423 when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS may include: when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS, the second pulse counter module The third channel of 422 triggers an interrupt request to disable the third pulse counter module 423 through the CPU 440.

In step S730, the image data signal transmitted by the multi-channel serial bus module 410 of the device 400 to the RGB interface of the display device may be read from the data storage module 460 using the DMA module 450 and written to the multi-channel serial bus module 410. .

The method of transmitting signals to the RGB interface of a display device according to embodiments of the present disclosure can drive a display device using an RGB interface without an RGB dedicated interface or a dedicated interface chip, thereby enabling more types of devices to drive using the RGB interface. display equipment, improve the selection range of the device, and reduce the hardware cost of the device. In addition, the load on the device's CPU can be reduced.

It should be noted that although the various steps are described above in a specific order, this should not be understood as requiring that these steps be performed in the specific order or sequence described.

The block diagrams of devices, equipment, and systems involved in the present disclosure are only exemplary, and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these circuits, devices, devices, equipment, and systems may be connected, arranged, and configured in any manner as long as the desired purpose is achieved.

The processes and logic flows described in this specification may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. Processes and logic flows may also be executed by, and devices may be implemented as, dedicated logic circuits, such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits).

Certain features described in this specification in the context of separate embodiments may also be combined. Conversely, various features that are described in the context of separate embodiments can also be implemented in multiple embodiments separately or in any suitable subcombination.

Those skilled in the art should understand that the above-mentioned specific embodiments are only examples and not limitations, and the embodiments of the present disclosure can be variously modified, combined, partially combined and replaced according to design requirements and other factors, as long as they are in the appended claims. or its equivalent scope, it shall fall within the scope of rights to be protected by this disclosure.

Claims

A method of transmitting signals to the RGB interface of a display device, including:

Use multiple serial bus modules to generate clock CLK signals;

Use the counter module to generate the horizontal synchronization HSYNC signal, vertical synchronization VSYNC signal and data enable DE signal; and

The multi-channel serial bus module is used to transmit the image data signal and the clock CLK signal to the RGB interface, and the general input and output GPIO module is used to transmit the HSYNC signal, the VSYNC signal and the DE signal to The RGB interface.
The method of claim 1, wherein the counter module includes a first pulse counter module, and using the counter module to generate the HSYNC signal includes:

The counting period of the first pulse counter module is set to the sum of the horizontal synchronization signal back shoulder HBP, the total number of effective display RGB pixels in each row HDOTS, and the horizontal synchronization signal front shoulder HFP;

Set the channel matching value of the first pulse counter module to the pulse width HSW of the HSYNC signal;

The output mode of the first pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the first pulse counter module is set to the CLK signal.
The method of claim 2, wherein the counter module includes a second pulse counter module, and using the counter module to generate the VSYNC signal includes:

The counting period of the second pulse counter module is set to the sum of the vertical synchronization signal rear shoulder VBP, the effective display pixel row VDOTS, and the vertical synchronization signal front shoulder VFP;

Set the first channel matching value of the second pulse counter module to the pulse width VSW of the VSYNC signal;

The output mode of the second pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the second pulse counter module is set to the HSYNC signal.
The method of claim 3, wherein the counter module includes a third pulse counter module, and using the counter module to generate the DE signal includes:

Set the counting period of the third pulse counter module to the sum of the HBP and the HDOTS;

Setting the channel matching value of the third pulse counter module to the HBP;

The output mode of the third pulse counter module is set to the single pulse output mode, the pulse counting source of the third pulse counter module is set to the CLK signal, and the trigger source of the third pulse counter module is set is the overflow flag bit of the first pulse counter module.
The method of claim 4, wherein using the counter module to generate the DE signal further includes:

The second channel matching value of the second pulse counter module is set to the VBP and the third channel matching value of the second pulse counter module is set to the sum of the VBP and the VDOTS, so that at the The third pulse counter module is enabled when the count value of the second pulse counter module reaches the VBP, and when the second The third pulse counter module is disabled when the count value of the pulse counter module reaches the sum of the VBP and the VDOTS.
The method of claim 5, wherein:

When the count value of the second pulse counter module reaches the VBP, the second channel of the second pulse counter module triggers an interrupt request to enable the third pulse counter module through the central processor;

When the count value of the second pulse counter module reaches the sum of the VBP and the VDOTS, the third channel of the second pulse counter module triggers an interrupt request to disable the third pulse counter module through the central processor. .
The method according to claim 1, wherein a direct memory access DMA module is used to read the image data signal from the data storage module and write the image data signal to the multiplex serial bus module.
The method of claim 1, wherein the multi-channel serial bus module includes a four-line serial peripheral interface (QSPI), an eight-line serial peripheral interface (OSPI) or a FlexIO module.
A device for transmitting signals to the RGB interface of a display device, including:

A multi-channel serial bus module generates a clock CLK signal and transmits the image data signal and the clock CLK signal to the RGB interface;

a counter module, which generates a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal; and

General input and output GPIO module, which transmits the HSYNC signal, the VSYNC signal and the DE signal to the RGB interface.
The device of claim 9, wherein the counter module includes a first pulse counter module, and the counter module generating the HSYNC signal includes:

The counting period of the first pulse counter module is set to the sum of the horizontal synchronization signal back shoulder HBP, the total number of effective display RGB pixels in each row HDOTS, and the horizontal synchronization signal front shoulder HFP;

Set the channel matching value of the first pulse counter module to the pulse width HSW of the HSYNC signal;

The output mode of the first pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the first pulse counter module is set to the CLK signal.
The device according to claim 10, wherein the counter module comprises a second pulse counter module, and the counter module generates the VSYNC signal comprising:

The counting period of the second pulse counter module is set to the sum of the vertical synchronization signal rear shoulder VBP, the effective display pixel row VDOTS, and the vertical synchronization signal front shoulder VFP;

Set the first channel matching value of the second pulse counter module to the pulse width VSW of the VSYNC signal;

The output mode of the second pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the second pulse counter module is set to the HSYNC signal.
The device of claim 11, wherein the counter module includes a third pulse counter module, the The counter module generating the DE signal includes:

Set the counting period of the third pulse counter module to the sum of the HBP and the HDOTS;

Set the channel matching value of the third pulse counter module to the HBP;

The output mode of the third pulse counter module is set to the single pulse output mode, the pulse counting source of the third pulse counter module is set to the CLK signal, and the trigger source of the third pulse counter module is set is the overflow flag bit of the first pulse counter module.
The apparatus of claim 12, wherein generating the DE signal by the counter module further includes:

The second channel matching value of the second pulse counter module is set to the VBP and the third channel matching value of the second pulse counter module is set to the sum of the VBP and the VDOTS, so that at the The third pulse counter module is enabled when the count value of the second pulse counter module reaches the VBP, and is disabled when the count value of the second pulse counter module reaches the sum of the VBP and the VDOTS. The third pulse counter module.
The apparatus of claim 13, further comprising a central processing unit, wherein:

When the count value of the second pulse counter module reaches the VBP, the second channel of the second pulse counter module triggers an interrupt request to enable the third pulse counter module through the central processor;

When the count value of the second pulse counter module reaches the sum of the VBP and the VDOTS, the third channel of the second pulse counter module triggers an interrupt request to disable the third pulse through the central processor Counter module.
The apparatus of claim 9, further comprising a direct memory access DMA module and a data storage module, wherein the DMA module reads the image data signal from the data storage module and writes the image data signal to the data storage module. Described multi-channel serial bus module.
The device of claim 9, wherein the multi-channel serial bus module includes a four-line serial peripheral interface (QSPI), an eight-line serial peripheral interface (OSPI), or a FlexIO module.