TWI337356B - Memory device with self refresh cycle control function - Google Patents

Memory device with self refresh cycle control function Download PDF

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Publication number
TWI337356B
TWI337356B TW095136292A TW95136292A TWI337356B TW I337356 B TWI337356 B TW I337356B TW 095136292 A TW095136292 A TW 095136292A TW 95136292 A TW95136292 A TW 95136292A TW I337356 B TWI337356 B TW I337356B
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voltage
memory device
output
unit
terminal
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TW095136292A
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TW200729208A (en
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Jee-Yul Kim
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Description

1337356 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體設計技術，而更特^言之係關於一 種具有一自我更新週期控制功能之記憶裝置。 【先前技術】 一般地，由於動態隨機存取記憶體（DRAM)細胞係以一 動態方式配置，因此會由於茂漏電流而發生資料毀損。因 此’需要讀出記憶胞中的資料，並依據在該細胞資料出現 損失之前所讀取的資料再次將其重新裝填至一初始裝填數 量（因細胞資料不而達到感測不到不足之程度。記憶胞 之此重新裝填程序稱為更新。此外，自我更新意 ^著 DRAM之-半導體記憶裝置在—固定週射針對其自己執 行該更新以便令儲存於記憶胞内的資料保持處於一備用狀 態。 另-方面，電流之特徵係其在溫度升高抓時增加 兩倍。換言之，當溫度上弁]Λ # 升1〇 C時細胞資料之保存時間減 小到1/2，而當溫度上升5〇〇c時減小到。 如上所述’該洩漏電流與該溫度密切相關，而因此，該 更新週期受到充當一重要因素的溫度之影響1，在一相 對較高的溫度處，該自我更新週期應較短。 因此，在藉由摘測—環境溫度來調節該自我更新週期 時，需要溫度補償自我更新（TCSR)。 傳統上’已使用一使用去.甘士分从 者在/、中依據—溫度變化來將一週 期變化程式化之裝置。即，在 ^ 在擴充模式暫存器集（EMRS)之設定 114956.doc 我更新週期 溫度而並不藉由設定EMRS碼來自動控制— 之記憶裝置。 依據本發明之-方面，提供—種具有—自我更新週期控 制功能之記憶裝置，其包括：一溫度感測單元，其係用： 產生與-溫度變化無關之一第一電壓以及與一溫度變化相 關之一第二電麼；-比較單元，其係用以將該第一電壓與 該第二電壓相比較以提供一比較結果信號；以及—自我更 新信號產生單元’其係用以在該比較結果信號之控制下接 收自我更新進入信號並產生溫度補償週期之一自我 信號。 依據本發明之另-方面’提供一種具有—自我更新週期 控制功能之記憶裝置，其包括：一溫度感測單元，其係用 以產生與一溫度變化無關之一第一電壓以及與一溫度變化 相關之一第二電壓；一比較單元，其係用以將該第一電壓 與該第二電壓相比較以提供一比較結果信號；一振盪單 元’其係用以接收並振盪一自我更新進入信號；以及一分 頻單元，其係用以分割該振盪單元之一輸出並回應於該比 較結果信號而提供複數個分頻值中的一值作為—自我更新 信號。 依據本發明之另一方面，提供一種具有一自我更新週期 控制功能之記憶裝置，其包括：一溫度感測單元，其係用 以產生與一溫度變化無關之一第一電壓以及與一溫度變化 相關之一第二電壓；一比較單元，其係用以將該第一電壓 與該第二電壓相比較以提供一比較結果信號；—振堡單 114956.doc 1337356 元’其係用以接收並錄-自我更新進人信號，α中依據 該比較結果信號來控制一振盪週期；以及—分頻單元，其 係用以分割該振盪單元之一輸出並產：： 新信號。 -補仏自我更 、本發明之其他目的及優點將藉由以下說明而為人瞭解， 並藉由本發明之具逋實施例而得到更清楚地彰顯。進一 步’本發明之目的及優點易於明白並可藉由申請專利範圍 Φ 中指定的方法及其組合來實現。 【實施方式】 下面，將參考附圖來詳細閱述本發明之較佳具體實施 例，以便與本發明相關的熟習此項技術者輕易便可實施本 發明。 圖2係一解說依據本發明之一第一具體實施例具有一自 我更新週期控制功能之一記憶裝置之一組態之方塊圖。參 考圖2，本發明之記憶裝置包括一溫度感測單元1 〇〇、一比 • 較單元200、一振盪單元300及一分頻單元40〇。 忒皿度感測單元1 〇〇用於產生與一溫度變化相關之一第 二電壓VtemP以及與該溫度變化無關之一第一電壓Vbias。 如後面參考圖3所說明，該溫度感測單元！ 〇〇應用此項技術 中熟知之一帶隙參考電路。 在該比較單元2〇〇處’將該第二電壓vtemp與該第一電壓 VbiaS相比較以產生—比較結果信號compare。 同時’藉由一自我更新進入信號SREF來致動一振盪單 元3〇〇，以提供—基本自我更新信號srefreg。 I14956.doc -8 · 1337356 在該分頻單元400，回應於充當一分頻值選擇信號之比 較結果信號compare而分割該基本自我更新信號， 從而產生一最終更新信號newsrefreg。 圖3解說圖2所示溫度感測單元1〇〇之一詳細電路圖。參 考圖3，該溫度感測單元1〇〇包括：一帶隙參考電壓產生器 n〇，其係用以依據雙極電晶體之一接面電壓特徵（(）1與(52 的發射極與基極之間的一接面電壓）及熱電壓特徵 φ (VT=kT/q)而產生一位準與一程序變化及溫度變化無關之 參考電壓vref; —第一電壓產生器12〇，其係用以藉使用 該參考電壓Vref來提供該第一電壓Vbias ;以及一第二電壓 產生器130，其係用以依據雙極電晶體之接面電壓特徵 的發射極與基極之間的接面電壓）來產生該第二電壓 Vtemp。 更明確言之，該帶隙參考電壓產生器11〇具有：電阻器 R2及R1與—雙極電晶體92，其係用於在該參考電壓 • 之一輸出節點N1與一接地電壓端子之間串聯連接以組成一 第一電流路徑的二極體；一電阻器R3及一雙極電晶體 Q1 ’其係用於在該參考MWef的輸出節點N1與該接地電 壓端子之間串聯連接以形成一第二電流路徑的二極體卜 運开放大盗op一amp I，其正輸入端子係與該等電阻器及 R1之連接即點搞合，@負輪入端子係與該電阻器们及 該雙極電晶體Q1之-連接節點輕合；以及一pM〇s電晶體 MP1，其開極擷取該運算放大器。p——之一輸出，而在 電源供應電麼端子Vdd與該輸出節點Νι之間建立源極到 1 J4956.doc 1337356 汲極路徑。 該苐一電壓產生器120具# :一分壓器121，其係用以分 割一輸入電源供應電壓以提供該第一電壓^^丨衫與一分壓 Vm ’ -運异放大器Gp—amp2 ’丨負輸人端+接受該參考電 MVref而正輸入端子接收分壓Vm ;以及一電流源Η〗，其 係用以回應於。亥運算放大器〇p_amp2之一輸出而向該分壓 β 121供應電源供應電壓。該電流源122係由—pM〇s電晶 φ 體㈣組成’該？_5電晶趙MP2之閘極_取該運算放大 器op一amP2之一輸出，而源極到汲極路徑係連接於該電源 供應電壓端子vdd與該分壓器121之間。而該分壓器% 形成藉由串聯連接的複數個電阻器形成，並在該等電阻器 之任一連接節點提供該第一電壓Vbias與該分sVm。 β 該第二電壓產生器130配備有：電阻器R4&R5，其係串 聯連接於該第：電avtemp之—輸出節點N2與—接地電虔 端子Vss之間；-運算放大器〇p—amp3，其正輸入端子係與 鲁該等電阻之—連接節㈣合，而負輸人端子係 連接至該帶隙參考電壓產生器11〇的雙極電晶體Q2之一發 ㈣；以及一PM0S電晶體Mp3，其閘極擷取該運算放大 器op一’3之-輸ώ，而源極到汲極路徑係連接於該電源 供應電壓端子與該輸出節點Ν2之間。 。明確言之’在該溫度感測單元_之帶隙參考電壓產生 器Π0提供與溫度變化無關而對處理條件及驅動電壓變化 不敏感之參考電麗Vref。在該運算放大器。p—㈣，發出 一特定錢來接通該MQS電晶體Mp卜回應該特定電壓， II4956.doc 1337356 雙極電晶體Q2的發射極之電壓係藉由該等電阻器以及R5 比率而放大並接著輸出。此時，當該溫度變得更高時，該 第二電壓Vtemp具有一更低的位準。 另一方面，向該第一電壓產生器120之輸入係對處理條 件及驅動電壓變化不敏感之參考電壓Vref。在該分壓器 121分割該參考電壓Vref，以產生該第一電壓乂出“與該分 壓Vm。依據半導體記憶體之規格，標準溫度係85它，而 因此若《玄刀壓器12 1係配置用於如同該第一電愿vbias 一樣 在85C時提供該第二電壓Vtemp之位準，則該第二電壓 Vtemp與該第一電壓¥1)丨“在溫度為85t時具有相同的值。 圖4解說圖2所示比較單元2〇〇之一詳細電路圖。參考圖 4，該比較單元200具有：一運算放大器op—amP4，該運算 放大器之負輸入端子係連接至該第二電壓Vtemp，而正輸 入端子係連接至該第一電壓Vbias ;第一反相器iNv〗，其 係用以接收該運算放大器〇p_amp4i 一輸出作為其輸入； 以及一第二反相器INV2，其係用以擷取該第一反相器 INV 1之—輸出來提供一比較結果信號compare。 更確定地講，若溫度低於85〇c，則該二電壓Vtemp之位 準會高於該第一電壓VbiaS2位準；而因此，該比較單元 2〇〇之輸出、該比較結果信號compare會處於邏輯低位。 相反’若溫度高於85〇c，則該二電壓Vtemp之位準會高於 該第一電麼Vbias之位準；而因此，該比較結果信號 compare會處於邏輯高位。 圖5例示圖2所示振盪單元300之一詳細電路圖。參考圖 114956.doc 1337356 5,該振盈單元300係由以下組件組成：串聯連接的奇數個 反相器㈣扇」至INV300_n;以及，複數個電容器⑼至 CPm，每-電容器之-端子係、連接至接地，而另—端子係 連接至該等奇數個反相器中每一反相器之一輪出端子與一 輸入端子的至少—共用節點。在此配置中，該振盈單元 3〇〇接收一自我更新進入信號贿並產生一具有觸發的基 本更新週期之信號srefreg。 圖6提供圖2所示分頻單元彻之一詳細方塊圖。來考圖 6’該分頻單元400配備有：―第一除頻器41〇，其係用以 分割該基本自我更新信號srefreg; 一第二除頻器42〇，其 j用以分割該第-除頻器彻之—輸出信號；以及一選擇 器430 ’其係用以回應於夯杏 ^ ^ "選擇信號之比較結果信號 compare而選擇該等第—與第二除頻器的輸出信號中之一 輸出信號；以及提供所選擇的輸出作為最終溫度補償週期 之自我更新信號newsrefreg。 更具體而言’可藉由一 1/2除頻器來實施該第一除頻器 指’而可藉由一單一的1/2除頻器或一單一的"2n除頻器 來將該第二除頻器42〇具體化，n係一自然數。 。 圖7係一解說圖2所示分頻單元彻之另一具體實施例之 -方塊圖。如圖7所示’該分頻單元伽係配置用於蓋生 具有不同分頻值之複數個分頻信號，·並包括串聯連接的複 數個"2除頻器420—m20_n;以及熔絲42。至425 ^ 其係用以藉由熔絲燒蝕來選擇並提供該複數個單元除頻 η 42(U至42〇-Π的輸出中之任一輪出。此外，可採用金屬選 U4956.doc -13- 1337356 項來替代該等熔絲。由於考量洩漏電流數量會改變而因此 更新週期可因外部環境而多樣化，故而藉由測試來選擇一 最佳更新信號並因此接通僅一對應熔絲。 圖8例示一依據本發明之一第二具體實施例具有一自我 更新週期控制功能之一記憶裝置之方塊圖。參考圖8，具 有自我更新週期控制功能之記憶裝置包括：一溫度感測單 元500，其係用以產生與一溫度變化相關之一第二電壓 Vtemp以及與一溫度變化無關之一第一電壓Vbias ; 一比較 單元600，其係用以將該第二電塵vternp與該第一電壓 Vbias相比較以提供一比較結果信號c〇nipare ;以及一振盈 單元700，其係用以使用該比較結果信號作為其自 己的電容器致動信號，並對應於該溫度變化而產生一自我 更新仏號c_srefreg ;以及一分頻單元800，其係用以接收 並分割該自我更新信號c_srefreg以提供最終溫度補償週期 之一更新信號newsrefreg。 該溫度感測單元500及該比較單元6〇〇實質上與如上所述 該第一具體實施例中所提出者相同。因此，在此省略關於 其的詳細說明，下面將說明該振盪單元7〇〇與該分頻單元 800 〇 圖9解說圖8所示振盪單元700之一詳細電路圖。參考圖 9’ 6玄振盈單元700具有：串聯連接的奇數個反相器 INV700_1至INV700_n ;以及複數個電容器cp7〇〇 !至 CP700一η ’其中每一電容器之一端子接收該比較結果信號 compare作為一電容器致動信號而另一端子係連接於該等 114956.doc 1337356 奇數個反相器INV700一1至INV700_n中每一反相器的輸出 端子之間。明確言之’該振盪單元700使用該比較結果信 號compare作為*玄電谷盗致動彳目號並接通/斷開該複數個電 容器CP700_1至CP700_n，從而產生具有溫度補償週期之 一自我更新信號c_srefreg。在此一組態中，若該溫度低於 8 5 °C，則該比較結果信號compare變成邏輯低位而因此致 動該等電容器以產生一具有較長自我更新週期之信號 c_srefreg ;而若該溫度高於85 °C，則該比較結果信號 compare變成邏輯高位而因此停用特定電容器以提供一具 有較短自我更新週期之信號c_srefreg。 圖10例示圖8所示分頻單元800之一詳細方塊圖。依據本 發明之第二具體實施例之分頻單元8〇0可由一單一的1/2除 頻器或一單一的l/2n除頻器組成，n係一自然數。 圖11解說一依據本發明之一第三具體實施例具有一自我 更新週期控制功能之一記憶裝置之方塊圖。 如圖11所示，其實施方式使得一振盪單元與一分頻 單元1400皆受到一比較結果信號⑶爪…!^之控制。 在本發明之第三具體實施例中，該振盪單元丨3〇〇可以係 如圖9所示而結構化’而該分頻單元1400可以係如圖6或7 所不而配置。當然，該溫度感測單元〗100可以係如圖3所 不而構造’而該比較單元丨2〇〇可以係如圖4所示而配置。 如上所述’本發明並不採用EMRS碼設定而具有一藉由 應用一帶隙參考電路而感測溫度之溫度感測單元。因此， 本發明可提供具有自我更新週期控制功能之記憶裝置其 114956.doc 1337356 更方便使用者藉由透過使用該溫度感測單元感測一特定溫 度來控制一自我更新週期。 本申請案包含與2005年9月29曰向韓國智慧財產局申請 的韓國專利申請案第2〇〇5_9〇913及2〇〇6 49122號有關之標 的，該等申請案之全部内容係以引用的方式併入於此。1337356 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor design techniques, and more particularly to a memory device having a self-renewal period control function. [Prior Art] Generally, since a dynamic random access memory (DRAM) cell system is configured in a dynamic manner, data corruption occurs due to leakage current. Therefore, it is necessary to read the data in the memory cell and re-load it to an initial loading amount according to the data read before the loss of the cell data (the cell data does not reach the degree of insufficiency. This refilling process of the memory cell is referred to as an update. In addition, the self-updating means that the DRAM-semiconductor memory device performs the update on its own for the purpose of keeping the data stored in the memory cell in a standby state. On the other hand, the characteristic of the current is that it doubles when the temperature rises. In other words, when the temperature is 弁 Λ Λ # 〇 1 〇 C, the storage time of the cell data is reduced to 1/2, and when the temperature rises 5 〇〇c is reduced to. As mentioned above, the leakage current is closely related to the temperature, and therefore, the update period is affected by the temperature acting as an important factor. 1 At a relatively high temperature, the self-renewal The period should be shorter. Therefore, temperature compensation self-renewal (TCSR) is required when the self-renewal cycle is adjusted by the smear-ambient temperature. Traditionally, one has been used. The Gans is divided into the device based on the temperature change to program a cycle change. That is, in the extended mode register set (EMRS) setting 114956.doc I update the cycle temperature without A memory device that is automatically controlled by setting an EMRS code. According to an aspect of the present invention, a memory device having a self-renewal period control function is provided, comprising: a temperature sensing unit, which is used to: generate and The temperature change is independent of a first voltage and a second voltage associated with a temperature change; a comparison unit for comparing the first voltage to the second voltage to provide a comparison result signal; and The self-renewing signal generating unit is configured to receive a self-update incoming signal and generate one of the temperature compensation periods under the control of the comparison result signal. According to another aspect of the present invention, a self-renewing period control function is provided. The memory device includes: a temperature sensing unit configured to generate a first voltage independent of a temperature change and a temperature change a second voltage; a comparing unit for comparing the first voltage with the second voltage to provide a comparison result signal; an oscillating unit 'which is configured to receive and oscillate a self-update incoming signal; And a frequency dividing unit for dividing one of the output of the oscillating unit and providing a value of the plurality of frequency dividing values as a self-updating signal in response to the comparison result signal. According to another aspect of the present invention, A memory device having a self-renewing period control function, comprising: a temperature sensing unit configured to generate a first voltage unrelated to a temperature change and a second voltage associated with a temperature change; a unit for comparing the first voltage with the second voltage to provide a comparison result signal; - Zhenbaodan 114956.doc 1337356 yuan 'is used to receive and record - self-updating into the human signal, α Controlling an oscillation period according to the comparison result signal; and - a frequency dividing unit for dividing one of the output of the oscillation unit and generating: a new signal. Other objects and advantages of the present invention will become apparent from the following description, and will be more apparent from the embodiments of the invention. Further, the objects and advantages of the present invention are readily apparent and can be achieved by the methods specified in the patent application Φ and combinations thereof. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which the present invention can be easily implemented by those skilled in the art. Figure 2 is a block diagram showing the configuration of one of the memory devices having a self-renewing cycle control function in accordance with a first embodiment of the present invention. Referring to FIG. 2, the memory device of the present invention includes a temperature sensing unit 1 , a ratio unit 200 , an oscillating unit 300 , and a frequency dividing unit 40 。 . The sensing unit 1 is configured to generate a second voltage VtemP associated with a temperature change and a first voltage Vbias independent of the temperature change. As described later with reference to Figure 3, the temperature sensing unit! A bandgap reference circuit is well known in the art. The second voltage vtemp is compared with the first voltage VbiaS at the comparison unit 2'' to generate a comparison result signal compare. At the same time, an oscillating unit 3 is actuated by a self-renewal into signal SREF to provide a basic self-renewal signal srefreg. I14956.doc -8 - 1337356 In the frequency dividing unit 400, the basic self-update signal is divided in response to the comparison result signal compare acting as a frequency dividing value selection signal, thereby generating a final update signal newsrefreg. FIG. 3 illustrates a detailed circuit diagram of one of the temperature sensing units 1A shown in FIG. 2. Referring to FIG. 3, the temperature sensing unit 1A includes: a bandgap reference voltage generator n〇 for utilizing one of the junction voltage characteristics of the bipolar transistor (() 1 and (52 of the emitter and the base) a junction voltage between the poles and a thermal voltage characteristic φ (VT=kT/q) to generate a reference voltage vref that is independent of a program change and temperature change; — a first voltage generator 12〇 The first voltage Vbias is provided by using the reference voltage Vref; and a second voltage generator 130 is used for connecting the emitter and the base according to the junction voltage characteristic of the bipolar transistor. Voltage) to generate the second voltage Vtemp. More specifically, the bandgap reference voltage generator 11A has: resistors R2 and R1 and a bipolar transistor 92 for use between the reference voltage one output node N1 and a ground voltage terminal. a diode connected in series to form a first current path; a resistor R3 and a bipolar transistor Q1' are connected in series between the output node N1 of the reference MWef and the ground voltage terminal to form a The second current path of the diode is open to the thief op amp I, the positive input terminal is connected with the resistors and R1, the @negative wheel terminal and the resistor and the pair The junction of the polar transistor Q1 is lightly coupled; and a pM〇s transistor MP1 is opened to capture the operational amplifier. p - one of the outputs, and between the power supply terminal Vdd and the output node 建立ι establish a source to 1 J4956.doc 1337356 bungee path. The first voltage generator 120 has a voltage divider 121 for dividing an input power supply voltage to provide the first voltage and a voltage divider Vm'-transmission amplifier Gp-amp2' The input terminal + accepts the reference power MVref and the positive input terminal receives the divided voltage Vm; and a current source Η〗, which is used to respond. One of the operational amplifiers 〇p_amp2 outputs and supplies a power supply voltage to the divided voltage β 121 . The current source 122 is composed of -pM〇s electro-crystal φ body (four)'. The gate of the _5 electro-crystal Zhao MP2 takes one of the operational amplifiers op-amP2, and the source-to-drain path is connected between the power supply voltage terminal vdd and the voltage divider 121. The voltage divider % is formed by a plurality of resistors connected in series, and the first voltage Vbias and the minute sVm are provided at any of the connection nodes of the resistors. The second voltage generator 130 is provided with: a resistor R4 & R5 connected in series between the first: the electrical avtemp - the output node N2 and the grounding electrical terminal Vss; - an operational amplifier 〇p-amp3, The positive input terminal is connected with the connecting resistor (4) of the resistor, and the negative input terminal is connected to the bipolar transistor Q2 of the bandgap reference voltage generator 11〇 (4); and a PM0S transistor Mp3, whose gate is taken from the operational amplifier op-'3', and the source-to-drain path is connected between the power supply voltage terminal and the output node Ν2. . Specifically, the bandgap reference voltage generator Π0 at the temperature sensing unit provides a reference voltage Vref that is insensitive to processing conditions and driving voltage variations regardless of temperature variations. In the op amp. P—(d), issuing a specific amount of money to turn on the MQS transistor Mp back to a specific voltage, II4956.doc 1337356 The voltage of the emitter of the bipolar transistor Q2 is amplified by the resistors and the R5 ratio and then Output. At this time, when the temperature becomes higher, the second voltage Vtemp has a lower level. On the other hand, the input to the first voltage generator 120 is a reference voltage Vref that is insensitive to processing conditions and drive voltage variations. Dividing the reference voltage Vref by the voltage divider 121 to generate the first voltage output "with the partial voltage Vm. According to the specification of the semiconductor memory, the standard temperature system 85, and thus if the "the squeegee 12 1 The system is configured to provide the level of the second voltage Vtemp at 85 C like the first wish vbias, and the second voltage Vtemp has the same value as the first voltage ¥1) 丨 "at a temperature of 85t" . 4 illustrates a detailed circuit diagram of one of the comparison units 2A shown in FIG. 2. Referring to FIG. 4, the comparison unit 200 has an operational amplifier op-amP4, a negative input terminal of the operational amplifier is connected to the second voltage Vtemp, and a positive input terminal is connected to the first voltage Vbias; And a second inverter INV2 for extracting the output of the first inverter INV1 to provide a comparison The result signal is compare. More specifically, if the temperature is lower than 85〇c, the level of the second voltage Vtemp will be higher than the first voltage VbiaS2 level; therefore, the output of the comparison unit 2〇〇, the comparison result signal compare will At a logical low. Conversely, if the temperature is higher than 85〇c, the level of the second voltage Vtemp will be higher than the level of the first voltage Vbias; therefore, the comparison result signal compare will be at a logic high level. FIG. 5 illustrates a detailed circuit diagram of one of the oscillation units 300 shown in FIG. 2. Referring to FIG. 114956.doc 1337356 5, the vibration unit 300 is composed of: an odd number of inverters connected in series (four) fans to INV300_n; and, a plurality of capacitors (9) to CPm, each capacitor-terminal system, Connected to ground, and the other terminal is connected to at least a common node of one of the inverters of each of the odd-numbered inverters and one of the input terminals. In this configuration, the oscillating unit 3 receives a self-renewal incoming signal and generates a signal srefreg with a triggered basic update period. FIG. 6 provides a detailed block diagram of the frequency dividing unit shown in FIG. 2. Referring to FIG. 6', the frequency dividing unit 400 is equipped with: a first frequency divider 41A for dividing the basic self-update signal srefreg; a second frequency divider 42A for dividing the first a frequency divider - the output signal; and a selector 430' for selecting the output signals of the first and second frequency dividers in response to the comparison signal of the selection signal One of the output signals; and a self-renewing signal newsrefreg that provides the selected output as the final temperature compensation period. More specifically, 'the first frequency divider finger can be implemented by a 1/2 frequency divider' and can be implemented by a single 1/2 frequency divider or a single "2n frequency divider. The second frequency divider 42 is embodied, and n is a natural number. . Figure 7 is a block diagram showing another embodiment of the frequency dividing unit shown in Figure 2; As shown in FIG. 7 'the frequency division unit gamma configuration is used to cover a plurality of frequency division signals having different frequency division values, and includes a plurality of series-connected "2 frequency dividers 420-m20_n; and a fuse 42. Up to 425 ^ is used to select and provide the plurality of cells by frequency fuse η 42 (U to 42 〇 - Π output of any of the rounds. In addition, the metal can be selected U4956.doc - 13- 1337356 is substituted for these fuses. Since the number of leakage currents is changed, the update period can be varied due to the external environment, so by testing a best update signal and thus turning on only one corresponding fuse Figure 8 illustrates a block diagram of a memory device having a self-renewal period control function in accordance with a second embodiment of the present invention. Referring to Figure 8, a memory device having a self-renewal period control function includes: a temperature sensing unit 500, which is used to generate a second voltage Vtemp associated with a temperature change and a first voltage Vbias independent of a temperature change; a comparison unit 600 for using the second electric dust vternp with the first A voltage Vbias is compared to provide a comparison result signal c〇nipare; and a vibrating unit 700 for using the comparison result signal as its own capacitor actuation signal and corresponding to the The degree change generates a self-update nickname c_srefreg; and a frequency dividing unit 800 for receiving and dividing the self-update signal c_srefreg to provide an update signal newsrefreg of the final temperature compensation period. The temperature sensing unit 500 and the The comparison unit 6 is substantially the same as that proposed in the first embodiment as described above. Therefore, a detailed description thereof will be omitted herein, and the oscillation unit 7A and the frequency division unit 800 will be described below. 9 is a detailed circuit diagram of an oscillating unit 700 shown in FIG. 8. Referring to FIG. 9', the oscillating unit 700 has: an odd number of inverters INV700_1 to INV700_n connected in series; and a plurality of capacitors cp7 〇〇! to CP700 η 'One of the terminals of each of the capacitors receives the comparison result signal compare as a capacitor actuation signal and the other terminal is connected to the 114956.doc 1337356 each of the odd number of inverters INV700-1 to INV700_n Between the output terminals, it is clear that the oscillating unit 700 uses the comparison result signal compare as the *Xuan Electric Valley thief action target number and turns on/off a plurality of capacitors CP700_1 to CP700_n, thereby generating a self-renewing signal c_srefreg having a temperature compensation period. In this configuration, if the temperature is lower than 85 ° C, the comparison result signal becomes a logic low and thus actuated The capacitors generate a signal c_srefreg having a longer self-renewing period; and if the temperature is above 85 °C, the comparison result signal becomes a logic high and thus deactivating the particular capacitor to provide a shorter self-renewing period The signal c_srefreg. FIG. 10 illustrates a detailed block diagram of one of the frequency dividing units 800 shown in FIG. The frequency dividing unit 8〇0 according to the second embodiment of the present invention may be composed of a single 1/2 frequency divider or a single l/2n frequency divider, and n is a natural number. Figure 11 illustrates a block diagram of a memory device having a self-renewal period control function in accordance with a third embodiment of the present invention. As shown in Fig. 11, the embodiment is such that an oscillating unit and a frequency dividing unit 1400 are both controlled by a comparison result signal (3). In a third embodiment of the present invention, the oscillating unit 丨3〇〇 may be structured as shown in Fig. 9 and the frequency dividing unit 1400 may be configured as shown in Fig. 6 or 7. Of course, the temperature sensing unit 100 can be constructed as shown in FIG. 3 and the comparison unit 丨2 can be configured as shown in FIG. As described above, the present invention does not employ an EMRS code setting but has a temperature sensing unit that senses temperature by applying a bandgap reference circuit. Accordingly, the present invention can provide a memory device having a self-renewal period control function. 114956.doc 1337356 is more convenient for a user to control a self-renewal period by sensing a specific temperature using the temperature sensing unit. This application contains the subject matter related to Korean Patent Application Nos. 2〇〇5_9〇913 and 2〇〇6 49122, which were filed with the Korean Intellectual Property Office on September 29, 2005. The entire contents of these applications are incorporated by reference. The way is incorporated here.

儘管已結合特定具體實施例說明本發明，但熟習此項技 術者會明白在不脫離以下申請專利範圍所定義之本發明精 神與範疇的情況下，可進行各種改變及修改。 【圖式簡單說明】 從上面結合附圖對較佳具體實施例之說明會明白本發明 之上述及其他目的及特徵，在圖式中： 圖1顯示具有-自我更新週期控制功能之一傳統記憶裝 置之一方塊圖； 圖2係-解說依據本發明之一第—具體實施例具有一自 我更新週期控制功能之一記憶裝置之_組態之方塊圖. 圖3解說圖2所示溫度感測單元之—詳細電路圖，· 圖4解說圖2所示比較單元之一詳細電路圖； 圖5例示圖2之振盪單元之一詳細電路圖； 圖6提供圖2所示分頻單元之一詳細電路圖； 圖7係一解說圖2所示分頻單 〈另—犯例之一方塊圖； 圖8例示一依據本發明之一笙_ δ 第—具體實施例具有-自我 更新週期控制功能之一記憶 '裝置之方塊圖； 圖9解說圖8所示振盪單元之一线 抓益早兀之砰細電路圖； 圖1〇例示圖8之分頻單元之一嶸* $ 用早兀之洋細電路圖；以及 114956.doc -16- 1337356Although the present invention has been described in connection with the specific embodiments thereof, it will be understood that various changes and modifications may be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments illustrated in the drawings. Figure 2 is a block diagram of a memory device having a self-renewing period control function according to one embodiment of the present invention. Figure 3 illustrates the temperature sensing shown in Figure 2. Figure 4 illustrates a detailed circuit diagram of a comparison unit shown in Figure 2; Figure 5 illustrates a detailed circuit diagram of one of the oscillation units of Figure 2; Figure 6 provides a detailed circuit diagram of one of the frequency division units shown in Figure 2; 7 is a block diagram of the frequency division list shown in FIG. 2; another block diagram of one of the crime cases; FIG. 8 illustrates a memory device according to one of the present inventions 笙 δ - the specific embodiment has a self-renewal period control function FIG. 9 illustrates a detailed circuit diagram of one of the oscillating units shown in FIG. 8; FIG. 1 exemplifies one of the frequency dividing units of FIG. 8 嵘 * $ with a fine circuit diagram of early morning; and 114956. Doc -16- 1337356

800 分頻單元 1100 溫度感測單元 1200 比較單元 1300 振盪單元 1400 分頻單元 CP1至 CPm 電容器 CP700_1至 CP700_n 電容器 INV1 第一反相器 INV2 第二反相器 INV300—1 至 INV300_n 反相器 INV700_1 至 INV700_n 反相器 MP1 PMOS電晶體 MP2 PMOS電晶體 MP3 PMOS電晶體 N1 輸出節點 N2 輸出節點 op_amp 1 運算放大器 op_amp2 運算放大器 op_amp3 運算放大器 op_amp4 運算放大器 Qi 雙極電晶體 Q2 雙極電晶體 R1 電阻器 R2 電阻器 114956.doc -18- 1337356 R3 電阻器 R4 電阻器 R5 電阻器 Vdd 電源供應電壓端子 Vss 接地電壓端子 114956.doc 19-800 frequency division unit 1100 temperature sensing unit 1200 comparison unit 1300 oscillation unit 1400 frequency division unit CP1 to CPm capacitors CP700_1 to CP700_n capacitor INV1 first inverter INV2 second inverter INV300-1 to INV300_n inverters INV700_1 to INV700_n Inverter MP1 PMOS transistor MP2 PMOS transistor MP3 PMOS transistor N1 Output node N2 Output node op_amp 1 Operational amplifier op_amp2 Operational amplifier op_amp3 Operational amplifier op_amp4 Operational amplifier Qi Bipolar transistor Q2 Bipolar transistor R1 Resistor R2 Resistor 114956.doc -18- 1337356 R3 Resistor R4 Resistor R5 Resistor Vdd Power Supply Voltage Terminal Vss Ground Voltage Terminal 114956.doc 19-

Claims (1)

1337356 第095136292號專利申請案 中文申請專利範圍替換本(98年11月） 十、申請專利範圍： 1. 一種具有一自我更新週期控制功能之記憶裝置，其包 含： 一溫度感測單元，其係用以藉由使用一帶隙參考電壓 產生器產生與該溫度變化無關之一第一電壓以及與一溫 度變化相關之一第二電壓； 一比較單元，其係用以將該第一電壓與該第二電壓相 比較以提供一比較結果信號；以及 # 一自我更新信號產生單元，其係用以在該比較結果信 號之控制下接收一自我更新進入信號並產生溫度補償週 期之一自我更新信號。 2.如請求項1之記憶裝置，其中該溫度感測單元包括： I 該帶隙參考電壓產生器，其係用以產生一位準與程序 變化及溫度變化無關之參考電壓； 一第一電壓產生器，其係用以藉使用該參考電壓來產 生該第一電壓；以及 一第二電壓產生器’其係用以產生該第二電壓。 3 .如請求項2之記憶裝置，其中該帶隙參考電壓產生器包 括： 一第一輸出節點，其提供該參考電壓； -第-t阻器&一第二電阻器肖―第一雙極電晶體， 其係用於在該第-㉚出節點與—接&電壓端子之間串聯 連接而組成一第一電流路徑之二極體； -第三電阻器及-第二雙極電晶體，其係用於在該第 D4956-98U27.doc 1337356 :輸出節點與該接地電壓端子之間連接而形成一第二電 流路徑之二極體； 第運算放大器’其具有一正輪入端子係與該等第 -及第二電阻器之一連接節點耦合，而一負輸入端子係 與該第三電阻器及t亥第二雙極電晶體之一連接節點搞 合；以及 第MOS電晶體，其閘極擷取該第一運算放大器之 一輸出，而在一電源供應電壓端子與該第一輸出節點之 間建立源極到汲極路徑。 4.如請求項2之記憶裝置，其中該第_電壓產生器包括： 刀壓器，其係用以分割一電源供應電壓以提供該第 一電壓與一分壓； 第一運鼻放大器，其具有一負輸入端子接受該參考 電壓’而一正輸入端子接收該分壓；以及 一電流源，其係用以回應於該第二運算放大器之一輸 出向該分壓器供應該電源供應電壓。 5·如凊求項4之記憶裝置，其中該電流源包括一第二m〇s 電aa體3玄第二MOS電晶體之閘極接受該第二運算放大 器之"玄輸出，而源極到汲極路徑係連接於該電源供應電 壓端子與該分壓器之間。 6. 如清求項4之記憶裝置，其中該分壓器係由串聯連接的 複數個電阻器組成，並在該複數個電阻器的連接節點中 之—節點提供該第一電壓與該分壓。 7. 如請求項3之記憶裝置，其中該第二電壓產生器包括： 114956-981127.doc -第四及-第五電阻器’其係串聯連接於一輸出該第 一電壓的第二輸出節點與該接地電壓端子之間； 第—運异放大态’其具有一正輸入端子係與該等第 四及違等第五電阻器之一連接節點耦合，而一負輸入端 子係連接至該第-雙極電晶體之—發射極；以及 一 一第三MOS電晶體，其開極掘取該第三運算放大器之 輸出而源極到汲極路徑係連接於該電源供應電壓端 子與該第二輸出節點之間。 8·如請求項1之記憶裝置，其中該比較單元包括： 卜第運放大器，其具有一負輸入端子係連接至該 第一私壓，而一正輸入端子係連接至該第一電壓； 第一反相器，其係用以接收該第一運算放大器之— 輸出；以及 一第二反相器，其係用以擷取該第一反相器之一輸出 以輸出該比較結果信號。 9. 一種具有一自我更新週期控制功能之記憶裝置，其包 含： 一溫度感測單元，其係用以產生與該溫度變化無關之 一第一電壓以及與一溫度變化相關之一第二電壓； 一比較單疋’其係用以將該第一電壓與該第二電壓相 比較以提供一比較結果信號； 一振盈單元’其係用以接收一自我更新進入信號以產 生振盪；以及 —分頻單元，其係用以分割該振盪單元之一輸出並回 114956-981127.doc 1337356 應於該比較結果信號而提供複數個分頻值之一作為一自 我更新信號。 1〇·如請求項9之記憶裝置，其中該振盪單元包括： 奇數個反相器，其係串聯連接；以及 複數個電容器’每一電容器之一端子係連接至該接 =，而另一端子係連接至該等奇數個反相器中每一反相 器之一輸出端子。 11·如請求項9之記憶裝 號； 第一除頻器，其係、用以分割該振盘單S之_輸出> k波，以及 -選擇器’其係用以回應於充t—選擇信號之节比 結果信號而輸出該等第一與第- " 一…“ ，、弟一除頻為的輸出信號中 。唬作為一溫度補償自我更新信號。 12. 如請求仙之記憶裝置，其 器。 丨示頦态係_1/2除 13. 如請求項〗2之記憶 葙哭， 1具㈣弟-除頻器係_1/2, 頻益，以糸一自然數。 14. 如請求項之記憶 — 具中β玄第一除頻器包括： m個1/2早元除頻器，其係串聯連接， 不同分頻值之複數個分具等 一炼絲單元，1在m 〃、係用以藉由熔絲燒蝕來 複數個I /2單元除瓶哭 璉擇並提供該 平疋除頻益的輪出中之一輸出。 I14956-981127.doc 1337356 15.如請：項Π之記憶裝置’其中該第二除頻器包括： =數個1/2單元除頻器’其係串聯連接用以產生旦有 不同分頻值之複數個分割時脈， /、 二=Γ單元除頻器的輸出中之-輸出是藉由 孟屬選項程序來選擇並提供之。 16.如請求項9至〗5中任一項之 單元包括： “ #中该溫度感測 -帶隙參考電虔產生器，其係用以產生一位準 變化及溫度變化無關之參考電壓； 〃 一第—電壓產生器，其係用以藉 生該第-電壓，‘以及 曰使…考電壓來產 -第二電壓產生器’其係用以產生該第二電壓。 請求項16之記憶裝置，其中該帶隙參考電壓產生器包 第輸出節點，其提供該參考電壓； 於二及二第二電阻器與一第一雙極電晶體，其係用 二輸出節點與一接地電麼端子之間串聯連接而 ，，攻第一電流路徑之二極體； 一於電阻器及一第二雙極電晶體’其係用於在該第 々郎點與該接地電壓端子之間連接 流路徑之二極體; &第一電 一及^ 4异放大器’其具有-正輸入端子係與該等第 該第二:電阻器之一連接節點耗合和一負輸入端子係與 -阻益及該第二雙極電晶體之一連接節點耦合； I14956-981127.doc 以及 ――第一MOS電晶體，其閘極擷取該第一運算放大器之 2出’而在一電源供應電壓端子與該第一輸出節點之 曰建立源極到沒極路徑。 18·如：求項16之記憶裝置，其中該第一電壓產生器包括： 刀壓，其係用以分割一電源供應電壓以提供該第 一電壓與一分壓； 一第二運算放大器，其一負輪入端子接受該參考電 壓而—正輸入端子接收該分壓；以及 —電流源’其係用以回應於該第二運算放大器之一輸 出向該分壓器供應該電源供應電壓。 19.如：求項17之記憶裝置，其中該第二電壓產生器包括： 第四及-第五電阻器，其係串聯連接於一輸出該第 二電壓的第二輸出節點與該接地電壓端子之間； 第—運舁放大器，其具有一正輸入端子係與該等第 四及該等第五電阻器之一連接節點耗合，而一負輸入端 子係連接至該第一雙極電晶體之一發射極；以及 第—MQS電晶體，其閘極擷取該第三運算放大器之 輸出而源極到及極路徑係'連接於該電源供應電壓端 子與該第二輸出節點之間。 20_種，、有自我更新週期控制功能之記憶裝置，直包 含： ’、 度變化相關之—第二電壓； '皿度感測單元’其係用以產生與該溫度變化i關之 一第一電壓以及與— … 114956-981127.doc 1337356 一比較單元，其係用以將該第一電壓與該第二電壓相 比較以提供一比較結果信號； 一振盪單元，其係用以接收一自我更新進入信號以產 生振盪，其中依據該比較結果信號來控制一振盪週期； 以及 一分頻單元，其係用以分割該振盪單元之一輸出以產 生一溫度補償自我更新信號。 21. 如請求項20之記憶裝置’其中該振盪單元包括： 奇數個反相器’其係串聯連接；以及 複數個電容器，每-電容器之一端子接收作為一致動 信號之該比較信號，而另-端子係、連接至該等奇數個反 相器中每一反相器之一輸出端子。 22. 如請求項21之記憶裝置，其中該除 。。^ ^ 屑早兀係—l/2n除頰 益，η係一自然數。 只 23.1337356 Patent Application No. 095136292 (Replacement of Patent Application for Chinese Patent Application (November 1998) X. Patent Application Range: 1. A memory device having a self-renewing period control function, comprising: a temperature sensing unit, Using a bandgap reference voltage generator to generate a first voltage unrelated to the temperature change and a second voltage associated with a temperature change; a comparison unit for using the first voltage and the first The two voltages are compared to provide a comparison result signal; and # a self-renewing signal generating unit for receiving a self-update incoming signal under the control of the comparison result signal and generating a self-renewing signal of one of the temperature compensation periods. 2. The memory device of claim 1, wherein the temperature sensing unit comprises: I the bandgap reference voltage generator for generating a reference voltage that is independent of program variations and temperature changes; a first voltage a generator for generating the first voltage by using the reference voltage; and a second voltage generator for generating the second voltage. 3. The memory device of claim 2, wherein the bandgap reference voltage generator comprises: a first output node that provides the reference voltage; - a -t resistor & a second resistor XI - first double An electro-op crystal, which is used to form a diode of a first current path connected in series between the -30th node and the -voltage terminal; - a third resistor and a second bipolar a crystal for forming a second current path diode between the output node and the ground voltage terminal in the D4956-98U27.doc 1337356; the operational amplifier 'having a positive wheel terminal system Coupling with one of the first and second resistors, and a negative input terminal is coupled to the third resistor and one of the second bipolar transistors; and the MOS transistor, A gate thereof draws an output of the first operational amplifier, and a source-to-drain path is established between a power supply voltage terminal and the first output node. 4. The memory device of claim 2, wherein the _th voltage generator comprises: a squeezing device for dividing a power supply voltage to provide the first voltage and a partial pressure; a first nasal amplifier, Having a negative input terminal to receive the reference voltage' and a positive input terminal receiving the divided voltage; and a current source for supplying the power supply voltage to the voltage divider in response to an output of the second operational amplifier. 5. The memory device of claim 4, wherein the current source comprises a second m〇s electrical aa body 3 a second second MOS transistor gate accepts the second operational amplifier " Xuan output, and the source The drain path is connected between the power supply voltage terminal and the voltage divider. 6. The memory device of claim 4, wherein the voltage divider is composed of a plurality of resistors connected in series, and the first voltage and the partial voltage are provided at a node of the connection node of the plurality of resistors . 7. The memory device of claim 3, wherein the second voltage generator comprises: 114956-981127.doc - a fourth and a fifth resistor 'connected in series to a second output node that outputs the first voltage Between the ground voltage terminal and the first power input terminal, the first input terminal is coupled to one of the fourth and the fifth resistors, and a negative input terminal is connected to the first a bipolar transistor-emitter; and a third MOS transistor that opens the output of the third operational amplifier and the source-to-drain path is connected to the power supply voltage terminal and the second Between the output nodes. 8. The memory device of claim 1, wherein the comparison unit comprises: a second operational amplifier having a negative input terminal coupled to the first private voltage, and a positive input terminal coupled to the first voltage; An inverter for receiving an output of the first operational amplifier; and a second inverter for extracting an output of the first inverter to output the comparison result signal. 9. A memory device having a self-renewing period control function, comprising: a temperature sensing unit configured to generate a first voltage unrelated to the temperature change and a second voltage associated with a temperature change; a comparison unit for comparing the first voltage with the second voltage to provide a comparison result signal; an oscillation unit 'which is configured to receive a self-update incoming signal to generate an oscillation; A frequency unit for dividing one of the output of the oscillating unit and returning to 114956-981127.doc 1337356 to provide one of the plurality of frequency dividing values as a self-updating signal in the comparison result signal. The memory device of claim 9, wherein the oscillating unit comprises: an odd number of inverters connected in series; and a plurality of capacitors, one terminal of each capacitor is connected to the connection, and the other terminal Is connected to one of the output terminals of each of the odd-numbered inverters. 11. The memory number of claim 9; the first frequency divider, which is used to divide the _output > k wave of the vibration disk S, and the - selector ' is used to respond to the charging t Selecting the signal to the ratio result signal and outputting the first and the first - " one...", the younger one is the output signal of the frequency division. 唬 as a temperature compensated self-renewal signal.其 除 系 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如As the memory of the request item - the first β-definite first frequency divider includes: m 1/2 early-frequency frequency dividers, which are connected in series, a plurality of distribution units with different frequency division values, etc., 1 In m 〃, it is used to fuse a plurality of I /2 cells by fuse ablation and provide one of the outputs of the 疋 疋 频 。. I14956-981127.doc 1337356 15. Please: item memory device 'where the second frequency divider includes: = several 1/2 unit frequency dividers' which are connected in series to generate different frequency division values The plurality of split clocks, the output of the /, == unit demultiplexer, are selected and provided by the Meng option program. 16. The unit of any one of claims 9 to 5 includes : "# The temperature sensing-bandgap reference power generator is used to generate a reference voltage independent of a quasi-variation and temperature change; 〃 a first-voltage generator for borrowing the first - Voltage, 'and 曰 make ... test voltage to produce - second voltage generator' which is used to generate the second voltage. The memory device of claim 16, wherein the bandgap reference voltage generator includes an output node that provides the reference voltage; and the second and second second resistors and a first bipolar transistor are coupled to the two output nodes a grounding electrode is connected in series between the terminals, and the diode of the first current path is tapped; a resistor and a second bipolar transistor are used for the grounding voltage terminal and the ground voltage terminal Connecting the diode of the flow path; & the first electric one and the four different amplifiers, which have a positive input terminal and one of the second: one of the resistors connected to the node and a negative input terminal Coupling with - blocking and one of the second bipolar transistors; I14956-981127.doc and - the first MOS transistor, the gate of which is taken from the first operational amplifier A source-to-polar path is established between the power supply voltage terminal and the first output node. 18. The memory device of claim 16, wherein the first voltage generator comprises: a knife pressure for dividing a power supply voltage to provide the first voltage and a partial voltage; a second operational amplifier, A negative wheel input terminal receives the reference voltage - the positive input terminal receives the divided voltage; and - a current source ' is operative to supply the power supply voltage to the voltage divider in response to an output of the second operational amplifier. 19. The memory device of claim 17, wherein the second voltage generator comprises: a fourth and a fifth resistor connected in series to a second output node that outputs the second voltage and the ground voltage terminal And a first input terminal is coupled to one of the fourth and the fifth resistors, and a negative input terminal is coupled to the first bipolar transistor And one of the emitters; and the first MQS transistor, the gate of which draws the output of the third operational amplifier and the source-to-pole path is connected between the power supply voltage terminal and the second output node. 20_, a memory device with self-renewing period control function, directly containing: ', the degree of change related to the second voltage; 'the degree sensing unit' is used to generate one of the temperature changes a voltage and a comparison unit with - 114956-981127.doc 1337356 for comparing the first voltage with the second voltage to provide a comparison result signal; an oscillating unit for receiving a self The incoming signal is updated to generate an oscillation, wherein an oscillation period is controlled according to the comparison result signal; and a frequency dividing unit is configured to divide an output of the one of the oscillation units to generate a temperature compensated self-renewal signal. 21. The memory device of claim 20, wherein the oscillating unit comprises: an odd number of inverters connected in series; and a plurality of capacitors, each of the terminals of the capacitor receiving the comparison signal as a coincident signal, and a terminal system connected to one of the output terminals of each of the odd number of inverters. 22. The memory device of claim 21, wherein the dividing is. . ^ ^ 屑 early 兀 - l / 2n in addition to buccal benefits, η is a natural number. Only 23. 如請求項21之記憶裝置，其中該除頻單 一第一除頻器，其係用以分割該振盪 號； 元包括： 單元之一輸出信 -第二除頻器，其係用以分割該 信號；以及 除頻态之一輸出 一選擇器，其係用以回應於充當〜 結果信號而輸出該等第一與第二除、擇信號之該比較 -信號作為—溫度補償自我更新信錄。。。的輪出信號中之 24.如凊求項23之記憶裝置 器。 除頻器係-"2除頻 I14956-98I127.do, 1337356 Μ.如請求項24之記憶裝置，1中該 頻器，η係一自然數。 Λ — *頻器係一1/2"除 26·如請求項24之記憶裝置，其中該第 複數個1/2單元除頻器，其❹聯連接: 不同分頻值之複數個分割時脈；以& 產生具有 一熔絲單元，其係用LV &丄卜 複數個1/2單元除頻器的輸;之來選擇並提供該 A如請:广記憶裝置，其令該第二除頻器包括： 複固1/2單讀頻器，其係串聯連接 不同分頻值之複數個分割時脈， 肖乂產生具有 其中該複數個1/2單元除頻器的輸出中之 金屬選項程序來選擇並提供之。 &出疋錯由 28.如請求㈣至27巾任—項之記憶裝置， 單元包括： ，、中6亥溫度感測 一帶隙參考電壓產生器，並 變化及、〜“& -係用以產生-位準與程序 夂化及,皿度變化無關之參考電壓； 一第一電壓產生器， 生該第—電壓；以及 一第二電壓產生器， 29.如請求項28之記憶裝置 括： 其係用以藉使用該參考電壓來產 其係用以產生該第二電壓。 ’其中該帶隙參考電壓產生器包 第輸出節點，其提供該參考電壓； 一第一及一第二電阻器與一第一雙極電晶體，豆 於在該第-輪出節點與一接地電壓端子之間串聯連接而 114956-981127.doc 1337356 組成一第一電流路徑之二極體； -第三電阻器及一第二雙極電晶體，其係用於在該第 一輸出節點與該接地電壓端子之間連接而形成一第二電 流路徑之二極體； -運算放大器’其具有-正輸入端子係與該等第 -及第二電阻器之一連接節點耦合’而一負輸入端子係 與該第三電阻器及該第二雙極電晶體之一連接 合；以及The memory device of claim 21, wherein the frequency division single first frequency divider is configured to divide the oscillation number; the element comprises: one output signal of the unit - a second frequency divider, configured to divide the signal And outputting a selector in addition to the frequency state, in response to outputting the comparison-signals of the first and second divisor signals as a ~ result signal as a temperature compensated self-renewal record. . . 24. The memory device of the request 23 is as claimed. The frequency divider is -"2 frequency division I14956-98I127.do, 1337356 Μ. As in the memory device of claim 24, the frequency converter in η is a natural number. Λ — * The frequency is a 1/2 " except 26 · The memory device of claim 24, wherein the plurality of 1/2 unit frequency dividers are connected in series: a plurality of divided clocks of different frequency values And < generate a fuse unit with LV & 复 multiplex 1/2 unit divider; to select and provide the A as follows: wide memory device, which makes the second The frequency divider comprises: a complex 1/2 single frequency reader, which is connected in series with a plurality of divided clocks of different frequency dividing values, and the 乂 generates a metal having an output of the plurality of 1/2 unit frequency dividers Option program to choose and provide. & error is caused by 28. According to the request (four) to 27 towel--the memory device, the unit includes: ,, the middle 6 sea temperature sensing a bandgap reference voltage generator, and the change and ~ "& - system a reference voltage that produces a - level and program degeneration and a change in the degree of the dish; a first voltage generator that generates the first voltage; and a second voltage generator, 29. the memory device of claim 28 : the system is used to generate the second voltage by using the reference voltage. ' wherein the bandgap reference voltage generator includes an output node that provides the reference voltage; a first and a second resistor And a first bipolar transistor, the bean is connected in series between the first-round node and a ground voltage terminal, and 114956-981127.doc 1337356 constitutes a diode of a first current path; - a third resistor And a second bipolar transistor for connecting a diode between the first output node and the ground voltage terminal to form a second current path; - an operational amplifier 'having a positive input terminal And the first - and One of the two resistors is coupled to the node coupling' and a negative input terminal is coupled to one of the third resistor and the second bipolar transistor; 運算放大器之 一輸出節點之 一第一MOS電晶體，其閘極擷取該第一 一輸出，而在一電源供應電壓端子與該第 間建立源極到及極路徑。 30.如請求項28之記憶裝置，其中該第一電壓產生器包括： —分壓H ’其係用以分割一 f源供應電壓以提供該第 一電壓與一分壓； 、° ”―第二運算放大器’其—負輸人端子接受該參考電 壓’而一正輸入端子接收該分壓；以及 一電流源’其係用以回應於該第二運算放大器之―輸 出向該分壓器供應該電源供應電壓。 31.如請求項29之記憶裝置，其中該第二電壓產生器包括： 第'及一第五電阻器，其係奉聯連接於-輪出該第 一電壓的第二輸出節點與該接地電壓端子之間； 第二運舁放大器，其具有一正輸入端子係與該等第 四及該等第五電阻器之一連接節點糕合，而一負輪入端 子係連接至該第一雙極電晶體之—發射極；以及 114956-981127.do, 1337356 一第三MOS電晶體，其閘極擷取該第三運算放大器之 一輸出，而源極到汲極路徑係連接於該電源供應電壓端 子與該第二輸出節點之間。 Ι 14956-981127.doc -ΙΟ 1337356 第095136292號專利申請案 中文圖式替換頁(98年1月） 游I月'1日修正雜頁A first MOS transistor of an output node of the operational amplifier, the gate of which draws the first output, and establishes a source-to-pole path between a power supply voltage terminal and the first. 30. The memory device of claim 28, wherein the first voltage generator comprises: - a partial voltage H' for dividing an f source supply voltage to provide the first voltage and a partial voltage; , °" - a second operational amplifier 'the negative input terminal receives the reference voltage' and a positive input terminal receives the divided voltage; and a current source 'in response to the output of the second operational amplifier to the voltage divider 31. The power supply voltage. The memory device of claim 29, wherein the second voltage generator comprises: a first and a fifth resistor connected to the second output of the first voltage Between the node and the ground voltage terminal; the second operation amplifier has a positive input terminal coupled to one of the fourth and the fifth resistors, and a negative wheel terminal is connected to The first bipolar transistor-emitter; and 114956-981127.do, 1337356 a third MOS transistor, the gate of which draws one of the outputs of the third operational amplifier, and the source to the drain path is connected The power supply voltage terminal Between the second output node. Ι 14956-981127.doc -ΙΟ 1337356 Patent Application No. 095136292 replacement by Chinese FIG pages (1/98) Amusement May I 'correction heteroaryl page 1 114956-fig-980117.doc 2-114956-fig-980117.doc 2-
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI475562B (en) * 2012-06-07 2015-03-01 Elite Semiconductor Esmt Semiconductor memory device with self-refresh timing circuit

Families Citing this family (5)

* Cited by examiner, † Cited by third party
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KR100892723B1 (en) * 2007-11-19 2009-04-10 주식회사 하이닉스반도체 Digital temperature information generator of semiconductor integrated circuit
KR100909224B1 (en) * 2008-01-28 2009-07-23 (주)이엠엘에스아이 Temperature compensating self refresh control circuit having tolerance to manufacturing condition
KR100949271B1 (en) 2008-09-05 2010-03-25 주식회사 하이닉스반도체 On die thermal sensor suitable for auto self refresh, integrated circuit with the same and method for on die thermal sensor suitable for auto self refresh
TWI449889B (en) * 2012-08-13 2014-08-21 Univ Nat Taiwan Temperature sensing apparatus and methods
JP6779816B2 (en) * 2017-03-21 2020-11-04 キオクシア株式会社 Semiconductor storage device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0129197B1 (en) * 1994-04-21 1998-10-01 문정환 A refresh control circuit of memory cell array
JP4021643B2 (en) 2001-10-29 2007-12-12 富士通株式会社 Semiconductor device with temperature detection function
DE10214103A1 (en) 2002-03-28 2003-10-23 Infineon Technologies Ag Oscillator with adjustable temperature gradients of reference voltage and virtual ground has comparator that outputs memory cell refresh signal if capacitor voltage exceeds reference potential
JP2005222574A (en) 2004-02-03 2005-08-18 Renesas Technology Corp Semiconductor memory device
KR101096207B1 (en) * 2005-03-31 2011-12-23 주식회사 하이닉스반도체 Temperature compensated self refresh circuit
KR20060118733A (en) * 2005-05-17 2006-11-24 주식회사 하이닉스반도체 Temperature compensation oscillator of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI475562B (en) * 2012-06-07 2015-03-01 Elite Semiconductor Esmt Semiconductor memory device with self-refresh timing circuit

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