TWI335599B - Shift register and liquid crystal display device having same - Google Patents

Description

1335599 0Originary October 14, VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a shift register and a liquid crystal display device using the shift register. [Previous Technology] [0002] Currently, thin film transistor (TFT) liquid crystal display devices have gradually become standard output devices for various digital products. However, it is necessary to design an appropriate driving circuit to ensure that Stable work.

Generally, the driving circuit of the liquid crystal display device includes a data driving circuit and a scanning driving circuit, wherein the data driving circuit is used for controlling the display luminance of each pixel unit, and the scanning driving circuit is used for controlling the conduction of the thin flag transistor. cutoff. The two driver circuits are all applied to the core circuit as a core circuit. Generally, the shift register is formed by connecting a plurality of shift register units in series, and the output signal of the previous shift register unit is the input signal of the latter shift register unit.

_] The neck reading diagram is a schematic diagram of the circuit structure of the shift temporary storage unit of the prior art shift register. The shift register unit 100 includes a -th clock inverting circuit 11G, a commutation circuit 12 (), and a second clock inverting circuit 130. Each circuit of the shift register unit 1 is composed of a transistor of the type s (p-channel metal oxide semiconductor), and each __pmqs type transistor includes one Interpolar, one source and one bungee. [0005] 096124634 The first clock-inverting circuit 11A includes a first transistor Mi, a crystal M2, a third transistor M3, a fourth transistor M4, and a second surface: ·. The first transistor M1 ~ page 4 / total 32 page 0993370463-0 1335599

[0006] [0007]

On October 14, 099, the replacement page receives the output signal VS of the shift register unit before the shift register unit 100, and the source receives the high level signal VDD from the external circuit, and the drain is connected to the drain The source of the second transistor M2. The gate of the second transistor M2 and its drain receive a low level signal VSS from an external circuit. The source of the third transistor M3 is connected to the drain of the first transistor 11, and the source of the fourth transistor M4 is connected to the gate of the first transistor M1. The gates of the third transistor M3 and the fourth transistor M4 receive the inverted clock signal CLKB from the external circuit, and the drains of the two are respectively used as the first output terminal V01 of the first clocked inverter circuit 110 and The second output terminal V02. The converter circuit 120 includes a fifth transistor M5, a sixth transistor M6, and a signal output terminal VO. The gate of the fifth transistor M5 is connected to the first output terminal V01, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the sixth transistor M6. The gate of the sixth transistor M6 is connected to the second output terminal V02, and the drain thereof receives the low level signal VSS from the external circuit, and the source thereof is the signal output terminal V0. The second clock inverting circuit 130 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The gate of the seventh transistor M7 is connected to the signal output terminal VO, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the eighth transistor M8. The gate of the eighth transistor M8 and its drain receive a low level signal VSS from an external circuit. The source of the ninth transistor M9 is connected to the first output terminal V01, the gate thereof receives the clock signal CLK from the external circuit, and the drain thereof is connected to the drain of the seventh transistor 111. The gate of the tenth transistor receives the clock signal CLK of the external circuit, the source thereof is connected to the second output terminal V02, and the drain thereof is connected to the signal output terminal VO. 096124634 Form No. A0101 Page 5 of 32 0993370463-0 1335599 October 14th, 2017, the replacement page

[0008] Please refer to FIG. 2 together, which is a schematic diagram of the operation timing of the shift register unit 100. During the time T1, the output signal VS of the previous shift register unit is changed from a high level to a low level, and the inverted clock signal CLKB is changed from a low level to a high level to make the third transistor M3 and the fourth transistor M4 are turned off, and the first clock inverting circuit 110 is turned off. The clock signal CLK is changed from a high level to a low level, so that the ninth transistor M9 and the tenth transistor M10 are turned on, thereby turning on the second clock inverting circuit 130, and the signal output terminal V is turned on. The surface level of the initial state is turned off by the tenth transistor Μ1 0 ', and the low level of the output of the eighth transistor Μ8 is passed through the ninth transistor Μ9 to make the fifth The crystal Μ5 is turned on, and the south level signal VDD is output to the signal output terminal V0 via the turned-on fifth transistor Μ5, so the signal output terminal VO maintains a high level output.

[0009] In the Τ2 time, the inverted clock signal CLKB is changed from a high level to a low level, and the third transistor M3 and the fourth transistor Μ4 are turned on, thereby inverting the first clock. Circuit 110 is turned on. When the clock signal CLK is changed from a low level to a high level, the ninth transistor Μ9 and the tenth transistor Μ10 are turned off, and the second clocked inverter circuit 130 is turned off. The input signal VS is changed from the south level to the low level to turn on the first transistor Μ1, and the source high level VDD causes the fifth transistor Μ5 to be turned off via the third transistor M3. And the low level of the input signal VS is turned on by the fourth transistor Μ4 to turn on the sixth transistor Μ6, so that the signal output terminal VO outputs a low level. [0010] In the Τ3 time, the inverted clock signal CL Κ 跳 changes from a low level to a still level, the third transistor M3 and the fourth transistor Μ4 are turned off, thereby making the first The clock inverting circuit 110 is turned off. The clock signal CLK is numbered 096124634. The form number is Α0101. Page 6 of 32 0993370463-0 1335599 [0011]

[0013] [0013] On October 14, 099, the modified replacement page level jumps to a low level, and the ninth transistor (4) and the tenth transistor M10 are turned on, thereby causing the second clock inverting circuit 13 to be turned on. () is turned on, the low level of the signal output terminal VO turns on the seventh transistor M7, and the high level of the source thereof turns off the fifth transistor M5 through the ninth transistor M9. Meanwhile, the signal output The low level of the terminal VO also turns on the sixth transistor M6 via the tenth transistor mi ,, and the low level of the drain of the sixth transistor causes the signal output terminal VO to maintain a low level output. During the period of T4, the inverted clock signal CLKB is changed from a high level to a low level, and the third transistor M3 and the fourth transistor M4 are turned on, thereby turning on the first clock inverting circuit 110. . The clock signal CLK transitions from a low level to a high level to turn off the tenth transistor M10, thereby causing the second time to be disconnected. The level of the input signal VS is turned off by the fourth transistor M4, and the second level of the second transistor M2 is caused by the third transistor |^3 The crystal M5 is turned on, because the φ monument is high: the level signal VDD is output to the signal via the turned-on fifth transistor M5, so that the output of the signal output terminal VO changes from a low level to a high level. \ : ; However, in the first time, the first and second transistors M1, ... are simultaneously turned on, and the voltage difference between the high level signal VDD and the low level signal vss is large, thereby causing the first and the first There will be a large current on the two transistors M1 and M2, which causes the power consumption of the shift register to be large. Similarly, the first and second transistors M1 and M2 are simultaneously turned on during the T2 time, and the fifth and sixth transistors M5 and M6 are simultaneously turned on, and the seventh and eighth transistors M7 and M8 are simultaneously turned on. The above-mentioned simultaneously turned-on transistors have a large current flowing through them, causing a large power consumption of the shift register. At 096124634 Form No. A0101 Page 7 / Total 32 Page 0993370463-0 1335599 On October 14, 2009, the replacement page T3, the fifth and sixth transistors M5, M6 are simultaneously turned on, the seventh and eighth The crystals M7 and M8 are turned on at the same time, and the above-mentioned simultaneously turned on transistors have a large current flowing, which also causes the power consumption of the shift register to be large. Therefore, the power consumption of the shift register is large. [0014] Moreover, since the high level VDD and the low level signal VSS are simultaneously input to the shift register unit 100, some unnecessary signal interference is bound to be caused. [0015] In addition, when the shift register is applied to a data driving circuit or a scan driving circuit of a liquid crystal display device, since the power consumption of the shift register is large, the liquid crystal display device uses a shift temporary storage. The number of devices is also large, so that the power of the liquid crystal display device is greatly reduced. SUMMARY OF THE INVENTION [0016] In view of the above, it is necessary to provide a shift register with low power consumption. [0017] In view of the above, it is also necessary to provide a liquid crystal display device with low power consumption. [0018] A shift register includes a plurality of shift temporary storage units sequentially connected in series, each of the shift register units including an input circuit, a first output circuit, a second output circuit, and a a third output circuit, a fourth output circuit, an input terminal, a first output terminal, a second output terminal, a high-level input terminal and a low-level input terminal, a common node, and a first inversion And a second inverter. The high level input is used to receive a high level signal. The low level input is used to receive a low level signal. The first and second output circuits are coupled to the high level input, and the third and fourth output circuits are coupled to the low level input. The input of the first inverter is 096124634 Form No. A0101 Page 8 of 32 0993370463-0 October 14, 2004 Correction replacement 100 1335599 The input is connected to the second output, and the output is connected to the first and The third output circuit. An input of the second inverter is connected to the common node, and an output is connected to the first output. The input is used to receive one of the previous stage start pulse signals. The first output terminal is configured to output the start pulse signal to the next stage shift register unit. The second output is for outputting a pulse signal to an external circuit. The input is configured to receive the start pulse signal of the previous stage. The input circuit provides the output pulse signal to the second output terminal under the control of the first output terminal, the input terminal and the external clock signal. The first output circuit provides the high level signal to the common node under the control of the input terminal and the output terminal of the first inverter. The second output circuit provides the high level signal to the common node under the control of the second output terminal and the first output terminal. The third round-out circuit provides the common node with the low level signal under the control of the first 'output terminal and the output terminal of the first inverter. The fourth output circuit provides the low level signal to the common node under the control of the second output terminal and the input terminal. Wherein, the four output circuit has only one conduction at any time. [0019] A liquid crystal display device comprising: a 3⁄4 crystal display panel, a data driving circuit and a scan driving circuit. The data driving circuit provides a data signal to the liquid crystal display panel, and the scan driving circuit provides a scanning signal for the liquid crystal display panel. The data driving circuit and the scan driving circuit respectively include at least one shift register to control the output timing of the data signal and the scan signal. The shift register includes a plurality of shift register units. Each of the shift register units includes an input circuit, a first output circuit, a second output circuit, a third output circuit, a fourth output circuit, an input terminal, a first output terminal, and a second Output, a high level input 096124634 Form number A0101 Page 9 / Total 32 page 0993370463-0 1335599 October 14, 2017 correction replacement page

And a low level input terminal, a common node, a first inverter and a second inverter. The rfj level input terminal is configured to receive a south level signal. The low level input is used to receive a low level signal. The first and second output circuits are coupled to the high level input, and the third and fourth output circuits are coupled to the low level input. An input end of the first inverter is connected to the second output end, and an output end is connected to the first and third output circuits. An input of the second inverter is coupled to the common node, and an output is coupled to the first output. The input is used to receive one of the previous levels to initiate a pulse signal. The first output terminal is configured to output the start pulse signal to the next stage shift register unit. The second output is used to output a pulse signal to an external circuit. The input terminal is used for selecting the start pulse signal of the last color. The input circuit supplies the pulse signal outputted to the second output terminal under the control of the first output terminal, the wheel terminal and the external clock signal. The first output circuit provides the high level signal to the common node under the control of the input end and the output end of the first inverter. The second output circuit provides the high level signal to the common node under the control of the second output terminal and the first output terminal. The third output circuit provides the low level signal to the common node under control of the first output terminal and the output terminal of the first inverter. The fourth output circuit provides the low level signal to the common node under the control of the second output terminal and the input terminal. Among them, the four output circuit has only one conduction at any time. [0020] Compared with the prior art, each shift register unit of the shift register of the present invention has 'only one turn-on' of the four output circuits at any time and the direct-level input terminal is not directly connected. To the low-level input, the circuit does not generate a large operating current, thereby effectively reducing the power of the shift register 096124634 Form No. A0101 Page 10 / Total 32 Page 0993370463-0 _ I October 14 Since the power consumption of the shift register is small, the power consumption of the liquid crystal display device of the present invention using the shift register is small. [Embodiment] [_ = 囷 3, which is a shift register of the present invention - a preferred embodiment of the present invention - the shift register 2G of FIG. 4 includes a shift register unit of the same complex structure, the complex number The shift register units 2 are connected in series. Each shift is stored as early as 200 - clock signal input TS, - input VIN, _

The first-round terminal v〇UT1, the second output terminal v〇UT2, a high-level input terminal VH, and a low-level input terminal. _] Each of the shift register unit 2's clock signal input terminal ts receives an external clock signal red U or inverted clock signal _, the high terminal VH receives the external 8 level VDD, low-age hunger _ The external low level signal VSS, the input terminal VIN is electrically connected to the first output end v〇un of the previous stage shift register unit 200, and the first output end is electrically connected to the input of the rear stage shift temporary storage single WGG. The first VIN 'pre-stage shift register unit 200's first-round output touches the T1 output-starts the pulse signal to the next stage

The input terminal of the shift register unit 2 is used as a start pulse of the shift register unit 200 of the subsequent stage (start puls small external clock signal and inverted phase & CLKB interval input to the complex shift The temporary storage unit (10) causes the clock signal received by each of the shift register units to be inverted from the clock signal received by the shift register unit 200 of the previous stage and the shift register unit 200 of the subsequent stage. [0023] 096124634 Please - Refer to FIG. 4, which is a schematic diagram of the circuit structure of a shift temporary storage unit (10) shown in FIG. 3. The shift temporary storage unit includes a _ input power (10), a first-inverter 31, and a second reverse phase. 32, _ first output circuit 4 form number _ 1st page / a total of 32 pages __ 1335599 October 14 099 替换 replacement page a second output circuit 42, a third output circuit 43 and a The fourth output circuit 44. The first to fourth output circuits 41 to 44 have a common node P for supplying a high level signal VDD to the common node P. The second output circuit 42 Used to provide a high level signal VDD for the common node P. The third output circuit 43 is used to The common node P provides a low level signal VSS. The fourth output circuit 44 is configured to provide a low level signal VSS for the common node P. [0024] The input circuit 30 includes a AND gate 35 and an OR gate 36. The first output circuit 41 includes a first transistor M1 and a second transistor M2. The second output circuit 42 includes a third transistor M3 and a fourth transistor M4. The third output circuit 43 includes a fifth transistor M5 and a sixth transistor M6. The fourth wheel circuit 44 includes a seventh transistor M7 and an eighth transistor M8. wherein the first, second, third and fourth The transistors M1, M2, M3, and M4 are PMOS type transistors. The fifth, sixth, seventh, and eighth transistors M5, M6, M7, M8 > ^, NM0S type transistors. ... · ;.

[0025] the high-level input terminal V Η sequentially passes through the source and the drain of the first transistor Μ1, the source and the drain of the second transistor M2, and the β-pole of the fifth transistor Μ5. The source, the drain and the source of the sixth transistor Μ6 are connected to the low level input terminal VL. The high-level input terminal VH also sequentially passes through the source and the drain of the third transistor M3, the source and the drain of the fourth transistor Μ4, and the drain and the source of the seventh transistor M7. The eighth transistor is connected to the low level input terminal VL with a drain and a source of 8. The common node 连接 is connected to the drains of the second and fourth transistors M2 and Μ4, respectively. [0026] The gates of the first and eighth transistors M1, Μ8 are connected to the input terminal VI Ν. The gates of the second and sixth transistors M2, M6 are connected to the first inverter 096124634 Form No. A0101 Page 12 / Total 32 Page 0993370463-0 The output of the replacement page 31 is verified on October 14, 099 . The gates of the third and seventh transistors M3, M7 are connected to the second output terminal VOUT2. The gates of the fourth and fifth transistors M4, M5 are connected to the first output terminal VOUT1. One input of the OR gate 36 is connected to the input terminal VIN, the other input terminal is connected to the first output terminal VOUT1, and the output terminal is connected to one of the input terminals of the AND gate 35. The other input of the AND gate 35 is connected to the clock signal input terminal TS, and the output terminal thereof is connected to the second output terminal VOUT2. An input of the first inverter 31 is coupled to the second output terminal VOUT2. The input of the second inverter 32 is connected to the common node P, and the output is connected to the first output terminal VOUT1. Please refer to Figure 5 together, as shown in Figure 3; shift: bit, temporary: the working sequence of the car to 200. The shift register unit 2 is at the time of the signal CLK. In addition, IN represents the input signal input to the input terminal VIN, 0UT1 represents the start pulse signal outputted by the first output terminal VOUT1, and 0UT2 represents the pulse signal outputted by the second output terminal to the external circuit. During the time T1, the input signal IN of the input terminal VIN of the shift register unit 20 is at a high level, and then the eighth transistor: Μέ# is turned on, and the first transistor M1 is cut off. The input signal IN is simultaneously input to the OR gate 36, and the OR gate 36 outputs a high level signal. Since the clock signal CLK is at a low level, the gate 35 outputs a low level signal, and the second output terminal VOUT2 outputs a low level signal, so the third transistor M3 is turned on, and the seventh transistor is turned on. M7 deadline. The low level signal output by the AND gate 35 is inverted by the first inverter 31 to become a high level signal. The second transistor M2 is turned off, and the sixth transistor M6 is turned on. The first output terminal VOUT1 is a low level signal, so the fifth transistor M5 is turned off, and the fourth transistor M4 is turned on. In summary, the form number A0101 page 13 / total 32 page 0993370463-0 1335599 October 14, 2004 correction replacement page first, second, fifth and seventh transistors Ml, M2, M5, M7 cut off, the The third, fourth, sixth and eighth transistors M3, M4, M6, M8 are turned on, so that only the second output circuit 42 operates normally. The high level signal VDD is outputted to the common node P by the second output circuit 42 and inverted by the second inverter 32 to a low level signal, which is consistent with the low level of the first output terminal V0UT1. . The common node P is pulled up to a high level.

[0030] During the time T2, when the input signal IN of the input terminal VIN is at a high level, the eighth transistor M8 is turned on, and the first transistor M1 is turned off. The input signal IN is simultaneously input to the OR gate 36, and the OR gate 36 outputs a high level signal. Since the clock signal CLK is at the south level at this time, the third output terminal VOUT2 outputs a high level signal, and the third transistor M3 is turned off, and the seventh power is turned off. Crystal M7 is turned on. The high level signal outputted by the AND gate 35 is inverted by the first inverter 31 to become a low level signal. Then, the second transistor M2 is turned on, and the sixth transistor M6 is turned off. In summary, the first, third, fourth, and sixth transistors M1, M3, M4, and M6 are turned off, and the second, seventh, and eighth transistors M2, M7, and M8 are turned on, Only the fourth output circuit 44 normally operates. The low level signal VSS is input to the common node P through the fourth output circuit 44, and is inverted by the second inverter 32 into a south level signal. The common egg point P is pulled down to a low level. The first output terminal VOUT1 outputs a high level signal. The fifth transistor M5 is turned on. [0031] In the time T3, when the input signal IN of the input terminal VIN is at a low level, the eighth transistor M8 is turned off, and the first transistor M1 is turned on. The input signal IN is simultaneously input to the OR gate 36. The first output terminal VOUT1 outputs a high level signal, the fifth transistor M5 is turned on, and the OR gate 36 outputs a high level signal. At this time, the clock signal CLK is low level, then the gate 35 outputs a low level 096124634 Form No. A0101 Page 14 / Total 32 Pages 0993370463-0 1335599 ι__ October 14, 1999, Jun Zheng hides the page signal 'The first The second output terminal V0UT2 outputs a low level signal. The third transistor M3 is turned on, and the seventh transistor M7 is turned off. The low level signal outputted by the AND gate 35 is inverted by the first inverter 31 to become a high level signal. Then, the second transistor M2 is turned off, and the sixth transistor M6 is turned on. In summary, the second, seventh and eighth transistors M2, M7, M8 are turned off, and the first, third, fifth and sixth transistors M1, M3, M5, M6 are turned on, so only the third output Circuit 43 operates normally. The low level signal VSS is outputted to the common node p by the third output circuit 43 and inverted by the second inverter 32 to a high level signal, which is consistent with the high level of the first output terminal V0UT1. . [0032] During the time T4, when the input signal IN of the input terminal VIN is low, the eighth transistor M8 is turned off, and the first transistor-body signal IN is simultaneously input to the OR gate 36. The signal CLK from T3 changes from low level to high level. Since the first output terminal νοϋτι continues to output a high level, the OR gate 36 outputs a high level to the AND gate 35, and the AND gate 35 outputs a high level, thereby causing the second transistor M2 to be turned on. . The high level signal VDD is then input to the first output by the first t ▲ body M1 and the second electric read 2 input to the common node P'j. End V0UT1. Therefore, the first output terminal VOUT1 actually outputs a low level signal. At this time, the fifth transistor M5 is turned off, and the fourth transistor M4 is turned on. The OR gate 36 outputs a low level signal to the AND gate 35. The AND gate 35 outputs a low level signal to the second output terminal VOUT2, the third transistor M3 is turned on, and the seventh transistor M7 is turned off. The low level signal of the gate 35 is inverted to a high level signal via the first inverter 31. Therefore, the second transistor M2 is turned off, and the sixth transistor M6 is turned on. In summary, the second, fifth, seventh and eighth electric 096124634 Form No. A0101 Page 15 of 32 0993370463-0 1335599

In the case of 099, the first day, the third, the fourth and the sixth transistors M1, M3, M4, and M6 are turned on, so the fourth is only the fourth. The output circuit 42 operates normally. The high level signal VDD is rotated by the second output circuit 42 to the common node P'. The common node p is pulled up to a high level. The high level signal is inverted to a low level signal via the second inverter 32 and output to the first output terminal VOUT1. [0033]

Since the first output terminal v〇UT1 of the shift register unit 2 is connected to the wheel terminal m of the shift register unit of the next stage, the first round signal OUT1 of the shift register unit 200 is The clock signal phase cuB received by the clock signal input terminal ts of the shift register unit of the shift register unit 20 of the next stage is 0. The lower-level shift register unit 2 is similar to the above-mentioned TW4i^, and the second input__ will immediately output the high-level pulse signal in the Τ3 time. [0034] For the shift of the parent level, the temporary county element collapses the work of the above-mentioned process [0035]

Compared with the prior art, the shifting temporary chest 2q of the present invention shifts the temporary single, and the first to fourth output circuits 4 have a conduction, and the high-level wheel is said to be disconnected. To the low-voltage input terminal U, the power consumption of the shift temporary storage (4) can be effectively reduced. [0036] Please refer to FIG. 6 '宜得—, 〃 is another one of the shift register unit 2G0 Schematic diagram of the circuit structure of the mode. The reverse shift temporary storage unit 300 is substantially the same as the vertical shift register unit 2 of FIG. 4, and the difference is in the same; 096124634 Form No. A0101 Page 16 / Total 32 Page 0993370463-0 1335599 _ October 099 The 14th modified replacement page s hai shift register unit 3 〇〇 further includes a third inverter 5 〇, the input of the third inverter 50 is connected to the output end of the first inverter, and the output end Connected to the gate of s Xuo Di - and the sixth transistor M2, M6. And the second transistor **2 is a 0 § type transistor, and the sixth transistor M6 is a PMOS type transistor 〇 [0037] Please refer to FIG. 7 , which is a liquid crystal using the above shift register 2 〇 The structure of the display device is not intended. The liquid crystal display device 2 includes a liquid crystal display panel 21, a device, a material driving circuit 22, and a scan driving circuit 23. The data driving φ circuit 22 and the scan driving circuit 23 are respectively connected by a plurality of data lines and a plurality of scanning lines. The liquid crystal display surface bees 21 are connected. The data driving circuit 22 and the scan driving circuit 23 respectively include a memory 20. Under the control of the shift register 20, the sweep driving circuit 23 sequentially outputs a plurality of scanning signals to the liquid crystal display panel 21. The data driving circuit 22 sequentially outputs a plurality of data signals to the liquid crystal display panel 21 to make the liquid crystal. The display device 2 is capable of displaying a screen. Compared with the technology before the subtraction, the power consumption of the shift register 2 is small, and therefore the power consumption of the crystal display device 2 using the shift register is less than [0039] As such, this creation has indeed met the requirements of the invention patent, and has filed a patent application in accordance with the law. However, the above-mentioned preferred embodiments of the present invention are not intended to limit the scope of the present invention, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application. [Simple description of the diagram] _ is a schematic diagram of the electrical (10) structure of the prior art shift temporary storage unit. 096124634 Form No. A0101 Page 17 of 32 0993370463-0 1335599 Correction Replacement Page on October 14, 2010 [0041] Figure 2 is a timing diagram showing the operation of the shift register unit shown in Figure 1. 3 is a schematic diagram of a preferred embodiment of a shift register of the present invention. 4 is a schematic diagram showing the circuit structure of a shift temporary storage unit shown in FIG. 3. 5 is a schematic diagram showing the operation timing of a shift temporary storage unit shown in FIG. 3. 6 is a schematic diagram showing the circuit configuration of another embodiment of a shift register unit shown in FIG. 3. 7 is a schematic view of a preferred embodiment of a liquid crystal display device of the present invention.

[Main component symbol description] [0047] Shift register: 20 [0048] or gate: 36 [0049] Liquid crystal display panel: 21 [0050] First output circuit: 41 [0051] Data drive circuit: 22

[0052] Second Output Circuit: 42 [0053] Scan Drive Circuit: 23 [0054] Third Output Circuit: 43 [0055] Input Circuit: 30 [0056] Fourth Output Circuit: 44 [0057] First Inverter :31 [0058] Third Inverter: 50 096124634 Form Number Α 0101 Page 18 / Total 32 Page 0993370463-0 October 14th, 999 Nuclear Replacement Page 1335599 [0059] Second Inverter: 32 [0060] Shift register unit: 200, 300 [0061] and gate: 35 0993370463-0 096124634 Form number A0101 Page 19 of 32

Claims (1)

1335599 Revision of the replacement page on October 14, 099. Patent application scope: 1. A shift register comprising a plurality of shift register units electrically connected in sequence, each of the shift register units comprising: an input The terminal is configured to receive a start pulse signal of one of the shifting temporary storage units; a first output end for outputting the start pulse signal to the next stage shift register unit; and a second output end for outputting one Pulse signal to an external circuit; An input circuit for outputting the pulse signal to the second output terminal under the control of the first output terminal, the input terminal and the external clock signal; a high level input terminal for receiving the high level signal; a low level input terminal for receiving a low level signal; a common node; a first inverter having an input coupled to the second output terminal; a second inverter having an output coupled to the output terminal a first output end, the input end being connected to the common node; a first output circuit is connected to the high level input terminal, and the high level signal is provided to the common node under the control of the input end and the output end of the first inverter; a second output circuit is connected to the a high level input terminal, the common level node is provided with the direction level signal under the control of the second output end and the first output end; a third output circuit is connected to the low level input end, at the first output The terminal and the output of the first inverter are controlled to provide the low level signal to the common node; a fourth output circuit is connected to the low level input terminal, at the second output end 096124634, form number A0101, 20th Page / Total 32 pages 0993370463-0 1335599 On October 14, 099, the replacement page and the input control are provided with the low level signal for the common node; wherein the four output circuit has only one conduction at any time. 2. The shift register according to claim 1, wherein the input The circuit further includes a gate, a gate or a clock signal input terminal, and one input terminal of the OR gate is connected to an input end of the same shift register unit as the OR gate, and the other input terminal is connected to the first The output end of the orbital gate is connected to one of the input terminals of the gate, and the other input end of the gate is connected to the clock signal input end, and the output end of the gate is connected to the second output end. The clock signal input end is configured to receive an external clock signal or an inverted clock signal, and the clock signal received by each of the two adjacent shift register units of the plurality of shift register units is inverted. 3. The shift register of claim 1, wherein the first output circuit comprises a first transistor and a second electrical body, and the gate of the first transistor is connected to the gate An input terminal, a source connected to the high level input terminal, a drain electrode connected to the source of the second transistor, a gate of the second transistor connected to the output end of the first inverter, and a drain There is no such public node. 4. The shift register according to claim 3, wherein the first And a second electro-crystalline system PM0S type electric crystal 4. 5. The shift register of claim 1, wherein the second output circuit comprises a third transistor and a fourth transistor, and the gate of the third transistor is connected to the first a second output end, the source is connected to the high level input end, the drain is connected to the source of the fourth transistor, the gate of the fourth transistor is connected to the first output end, and the drain is connected to the common node. 6. The shift register of claim 5, wherein the third and fourth electro-crystalline systems are PMOS type transistors. 7. The shift register according to claim 1, wherein the 096124634 form number A0101 page 21/32 page 0993370463-0 October 14, 2008 Geng is replacing the page three output circuit The fifth transistor includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is connected to the first output end, the source is connected to the drain of the sixth transistor, and the drain is connected to the common node. a gate of the sixth transistor is connected to an output end of the first inverter, and a source is connected to the low-level input terminal The shift register according to claim 7, wherein the fifth and sixth electro-crystalline systems are NM0S type transistors. 10. The shift register of claim 1, wherein the fourth round circuit comprises a seventh transistor and an eighth transistor, the gate of the seventh transistor being connected to the gate a second output end, the source is connected to the drain of the eighth transistor, the drain is connected to the common node, the gate of the eighth transistor is connected to the input terminal, and the source is connected to the low level: Wheeled end. The shift register according to claim 9, wherein the seventh and eighth electric crystal system NM0S type transistors. 11. The shift register of claim 2, wherein the shifting unit comprises a third inverter, and an input of the third inverter is connected to the first An output of the inverter, the output of the third inverter is connected to the first output circuit and the third output circuit, and the output of the third inverter and the high level input control the first wheel The outgoing circuit provides a high level signal to the common node. 12. A liquid crystal display device comprising a liquid crystal display panel, a data driving circuit and a scan driving circuit, the data driving circuit providing data reduction for the liquid crystal display panel, and translating (four) electric materials, the shirt (four) panel provides a description The signal, the (10) drive charge receiving material _ circuit includes a page 22 / 32 pages = to control the output timing of the data signal and the scan signal, the shift register includes a plurality of shift register unit form number Ηη The pure temporary storage unit package 0993370463-0 1335599 The correction replacement page of October 14, 099 includes: an input terminal for receiving a start pulse signal of one of the last β shift temporary storage units; a first output terminal, For outputting the start pulse signal to the next stage shift register unit; a second output terminal for outputting a pulse signal to the external circuit; an input circuit at the first output end, the input end and the external The pulse signal is outputted to the second output terminal under the control of the clock signal; a south level input terminal is configured to receive the two-level signal; a low-level input terminal for receiving a low-level signal; a common node; ".:,, ·, ·, ί~' a first inverter whose input terminal is balanced to k second output: ; ψΛ ': :: , :· " a second inverter whose output is connected to # to the first input: the output terminal is connected to the common node; a first output circuit is connected to the high voltage a flat input terminal at the input terminal and V >: the output of the first inverter controls 丨卞_ the common node provides the high level ί ..... signal; a second output circuit is connected to the high level input X terminal, and the south level signal is provided to the common node under the control of the second output end and the first output end; a third output circuit is connected to the low level a flat input terminal, the low level signal is provided to the common node under control of the first output end and the output end of the first inverter; a fourth output circuit is connected to the low level input end, The low level signal is provided to the common node under control of the second output terminal and the input terminal; wherein the four output circuit has only one conduction at any time. 13. The liquid crystal display device of claim 12, wherein the input 096124634 form number Α 0101 page 23 / total 32 page 0993370463-0 1335599 October 14, 1999 correction replacement page entry circuit further includes a And a gate, a gate, and a clock signal input end, the one input of the OR gate is connected to the input end of the same shift register unit, and the other input end is connected to the first output end, The output end of the gate is connected to one input end of the gate, and the other input end of the gate is connected to the clock signal input end, and the output end of the gate is connected to the second output end, the clock signal input end For receiving an external clock signal or an inverted clock signal, the clock signal received by each of the two adjacent shift register units of the plurality of shift register units is inverted. 14. The liquid crystal display device of claim 12, wherein the An output circuit includes a first transistor and a second transistor, a gate of the first transistor is connected to the input terminal, a source is connected to the 扃 level input terminal, and a drain is connected to the second transistor a source of the crystal, a gate of the second transistor is coupled to an output of the first inverter, and a drain is coupled to the common node. The liquid crystal display device of claim 14, wherein the first and second electro-crystalline systems are PMOS type transistors. [16] The liquid crystal display device of claim 12, wherein the The second output circuit includes a third transistor and a fourth transistor, the gate of the third transistor is connected to the second output terminal, the source is connected to the high level input terminal, and the pole is connected to the first a source of four transistors, a gate of the fourth transistor being coupled to the first output, and a drain connected to the common node. The liquid crystal display device of claim 16, wherein the third and fourth electro-crystalline system PMOS type transistors. The liquid crystal display device of claim 12, wherein the third output circuit comprises a fifth transistor and a sixth transistor, and the gate of the fifth transistor is connected to the first An output terminal, a source connected to the drain of the sixth transistor, and a drain connected to the second common node, the sixth transistor 096124634 Form No. A0101 Page 24 / Total 32 Page 0993370463-0 1335599 October 1099 The gate of the 14th modified replacement page is connected to the output of the first inverter, and the source is connected to the low level input. The liquid crystal display device of claim 18, wherein the fifth and sixth electro-crystalline systems are NM0S type transistors. The liquid crystal display device of claim 12, wherein the fourth output circuit comprises a seventh transistor and an eighth transistor, and the gate of the seventh transistor is connected to the second output The source is connected to the drain of the eighth transistor, the drain is connected to the common node, the gate of the eighth transistor is connected to the input, and the source is connected to the low input. The liquid crystal display device of claim 20, wherein the seventh and eighth electro-crystalline systems are NM0S type electro-crystals, body y 096124634 Form No. A0101 Page 25 of 32 0993370463-0