TWI413097B - Shift register and driving circuit for liquid crystal display panel - Google Patents

Abstract

This invention relates to a shift register and a driving circuit for a liquid crystal display panel using the same. The shift register includes a plurality of first shift register units and a plurality of second register units. Two adjacent first shift registers receives a first and a second clock signals respectively, and two adjacent second shift registers receives a third and a fourth clock signals respectively. Each of the first and second shift register units includes a level input pin, a level output pin, an output pin, a feedback pin and a recovering pin. An output signal of a second shift register unit M feeds back to the feedback pin of a first shift register unit (N+1). An output signal of a first shift register unit N feeds back to the feedback pin of the second shift register unit M. The recovering pin and the level output pin of the first shift register unit N are connected to the output pin and the level input pin of a first shift register unit (N+1), respectively. The recovering pin and the level output pin of the second shift register unit M are connected to the output pin and the level input pin of a second shift register unit (M+1), respectively.

Description

Shift register and liquid crystal panel driver circuit

The present invention relates to a shift register and a liquid crystal panel drive circuit using the shift register.

At present, Thin Film Transistor (TFB) liquid crystal display devices have gradually become standard output devices for various digital products. However, it is necessary to design an appropriate driving circuit to ensure stable operation.

Generally, a liquid crystal panel of a liquid crystal display device needs a data driving circuit and a scan driving circuit to provide a desired scanning signal and display a data signal. Both drive circuits use a shift register as a core circuit unit. Generally, the shift register is formed by connecting a plurality of shift register units in series, and the stability of the output signal of each shift register unit directly affects the display data signal or the scan signal outputted by the data drive circuit or the scan drive circuit. stability. However, since the output of each shift register unit and its feedback branch form a loop, when the shift register unit carries a large load, the turn-on voltage for turning on the output transistor passes through the feedback. The leakage of the loop causes the output transistor to fail to ensure normal conduction, resulting in unstable output of the shift register unit.

In view of this, it is necessary to provide an output stable shift register.

In addition, it is also necessary to provide a liquid crystal panel control circuit with stable output.

A shift register includes: a plurality of first shift temporary storage units and a plurality of second shift temporary storage units. The adjacent two first shift register units respectively receive one of the first clock signal and the second clock signal provided by the external circuit, and the first clock signal and the second clock signal are in opposite phase periodic pulse signals; adjacent The second shift register unit respectively receives one of the third clock signal and the fourth clock signal provided by the external circuit, and the third clock signal and the fourth clock signal are periodic pulse signals of opposite phases, and the first clock The signal and the third clock signal are separated from each other by a half cycle. Each of the first shift temporary storage unit and the second shift temporary storage unit includes a primary data input end, a primary data output end, an output end for outputting a shift signal, a feedback end, and a reset The shift signal outputted by the Mth second shift temporary storage unit is fed back to the feedback end of the N+1th first shift temporary storage unit, and the shift signal of the Nth first shift temporary storage unit Feedback to the feedback end of the Mth second shift temporary storage unit, M takes a natural number, N=M, the reset end of the Nth first shift temporary storage unit and the cascaded data output end respectively The output ends of the N+1 first shift temporary storage units are connected to the cascade data input end, and the reset ends of the Mth second shift temporary storage unit and the cascaded data output ends are respectively associated with the M+1th The output end of the second shift register unit is connected to the cascade data input end, and when the cascade data input end of the Nth first shift register unit receives a starting voltage, the Nth first shift The output end of the bit buffer unit outputs a shift signal synchronized with the first clock signal, and the output of the (N+1)th first shift register unit is The second clock signal synchronizes the shift signal, and the reset end of the Nth first shift register unit controls the Nth number according to the shift signal of the (N+1)th first shift register unit Whether the output signal of the shift register unit is reset; when the cascade data input end of the Mth second shift register unit receives a start voltage signal, the Mth second shift register unit output a shift signal synchronized with the third clock signal, and the M+1 second shift register unit outputs a shift signal synchronized with the fourth clock signal, and at the same time, the Mth second shift temporary The reset end of the memory unit controls whether the output signal of the Mth second shift register unit is reset according to the shift signal of the M+1 second shift register unit.

A liquid crystal panel driving circuit capable of providing a scanning signal to a corresponding pixel electrode by using the shift register. The plurality of first shift register units are also required to provide scan signals to the pixel electrodes via the scan lines of the odd columns, and the plurality of second shift register units can sequentially provide scan signals to the pixel electrodes via the scan lines of the even columns. . In addition, the liquid crystal panel driving circuit may sequentially supply the scanning signals to the pixel electrodes through the complex scanning lines by using only the shift signals output by the plurality of first shift temporary storage units or the plurality of second shift temporary storage units.

Compared with the prior art, the shift register is implemented by the shift register, and the shift signal outputted by the Mth second shift register unit is fed back to the (N+1)th first shift register. a feedback signal of the unit, the shift signal of the Nth first shift register unit is fed back to the feedback end of the Mth second shift register unit, even if the Nth first shift register unit and the The M second shift temporary storage units receive a large load, but are used to control the corresponding output transistors from being affected by the feedback branch, thereby stabilizing the output of the corresponding first or second shift register unit. Further, the scan driving circuit of the liquid crystal panel driving circuit uses the shift register to provide a scan signal, so that the stability of the scan signal outputted by the driving circuit is also high.

Please refer to FIG. 1, which is a structural block diagram of a preferred embodiment of a shift register of the present invention. The shift register 10 includes a plurality of first shift register units 12 and a plurality of second shift register units 14. The plurality of first shift register units 12 can sequentially output the plurality of first shift signals Vout1, Vout3, Vout5, ..., Vout(2N-1), Vout(2N+1), Vout(2N+3)... N takes a natural number). The plurality of second shift register units 14 can sequentially output the complex second shift signals Vout2, Vout4, Vout6...VOUT2(M-1), Vout2M, Vout2(M+1), Vout2(M+2)... (M=N). The first shift signal Vout(2N-1) outputted by the Nth first shift register unit 12 and the second shift signal Vout2M outputted by the Mth second shift register unit 14 are different by half a cycle. The first shift signal Vout(2N-1) output by the Nth shift register unit is different from the first shift signal Vout(2N+1) output by the N+1th shift register unit by one cycle. .

Each of the first shift temporary storage unit 12 and each of the second shift temporary storage units 14 has a similar circuit structure, and includes a primary data input terminal LIN, a primary data output terminal LOUT, a feedback terminal FB, and a first The reset terminal RE and an output terminal OUT. The adjacent two first shift temporary storage units 12 or the adjacent two second shift temporary storage units 14 receive different clock signals. For convenience of understanding, the Nth and N+1th first shift temporary storage units are conveniently understood. 12. The Mth and M+1th second shift register units 14 are described as an example.

The Nth first shift register unit 12 receives a first clock signal CK1, and the first clock signal CK1 can drive and control the Nth first shift register unit 12. The cascaded data input terminal LIN of the Nth first shift register unit 12 is connected to the cascaded data output terminal LOUT of the N-1th first shift register unit 12, and the cascaded data output terminal LOUT and the first The cascaded data input terminal LIN of the N+1 first shift register unit 12 is connected, and the feedback terminal FB receives the second shift signal Vout2 outputted from the output terminal OUT of the Mth second shift register unit 14 ( M-1), the reset terminal RE receives the first shift signal Vout(2N+1) output from the output terminal OUT of the (N+1)th first shift register unit 12. The N+1th shift register unit 12 receives a second clock signal CK2 that can drive the N+1th first shift register unit 12, and the second clock signal CK2 and the first The clock signal CK1 is a periodic pulse signal of opposite phase. Further, the N+1th first shift register unit 12 receives a third clock signal CK3 and the first clock signal CK1, and the Nth first shift register unit 12 further receives a fourth The clock signal CK4 and the second clock signal CK2, wherein the first and second clock signals CK1 and CK2 are used to control the output of the N+1th and Nth first shift register units 12 to achieve fast reset. . The third and fourth clock signals CK3 and CK4 are used as feedback control signals of the N+1th and Nth first shift register units 12, respectively. In addition, the cascaded data input terminal LIN of the first first shift register unit 12 and the cascaded data output terminal LOUT of the first first shift register unit 12 receive an open signal STV from an external circuit.

The Mth second shift register unit 14 receives a third clock signal CK3, and the third clock signal CK3 can drive and control the Mth second shift register unit 14. The cascaded data input terminal LIN of the Mth second shift temporary storage unit 14 is connected to the cascaded data output terminal LOUT of the M-1 second shift temporary storage unit 14, and the cascaded data output terminal LOUT and the first The cascading data input terminal LIN of the M+1 second shift register unit 14 is connected, and the feedback terminal FB receives the first shift signal Vout from the output end OUT of the Nth first shift register unit 12. 2N-1), the reset terminal RE receives the second shift signal Vout2(M+1) output from the output terminal OUT of the M+1th second shift register unit 14. The M+1 second shift register unit 14 receives a fourth clock signal CK4 that can drive and control the M+1 second shift register unit 14. Further, the M+1 second shift register unit 14 further receives the third clock signal CK3 and the second clock signal CK2, and the Mth second shift register unit 14 further receives the first The fourth clock signal CK4 and the first clock signal CK1, wherein the third and fourth clock signals CK3 and CK4 control the output of the M+1th and Mth second shift register units 14 to achieve a fast reset. The first and second clock signals CK1 and CK2 are used as feedback control signals of the Mth and M+1th second shift register units 14, respectively. In addition, the cascaded data input terminal LIN of the first second shift temporary storage unit 14 and the cascaded data output terminal LOUT of the last second shift temporary storage unit 14 also receive the open signal STV.

When the cascading data input terminal LIN of the Nth first shift register unit 12 receives a high level starting voltage, for example, the first first shift register unit 12 receives the turn-on signal STV. When the level is high, or the cascaded data output terminal LOUT of the N-1th first shift register unit 12 outputs a high level to the cascaded data input terminal LIN of the Nth first shift register unit 12. The output terminal OUT of the Nth first shift register unit 12 outputs the first shift signal Vout(2N-1), and the N+1th first shift register unit 12 outputs the same The first shift signal Vout(2N+1) is separated by a first shift signal Vout(2N+1) of one cycle. When the reset terminal RE of the Nth first shift register unit 12 receives the first shift signal Vout(2N+1) output by the (N+1)th first shift register unit 12, the first The output signals of the N first shift register units 12 are lowered to a low level, that is, the output is reset. When the cascading data input terminal LIN of the Mth second shift register unit 14 receives a high level starting voltage, for example, the first second shift register unit 14 receives the turn-on signal STV. Is a high level, or the cascaded data output terminal LOUT of the M-1 second shift temporary storage unit 14 outputs a high level to the cascaded data input terminal LIN of the Mth second shift temporary storage unit 14 The output terminal OUT of the Mth second shift register unit 14 outputs the second shift signal Vout2M, and the M+1th second shift register unit 14 outputs the second shift signal Vout2M. The second shift signal Vout2 (M+1) separated by one cycle. When the reset terminal RE of the Mth second shift register unit 14 receives the second shift signal Vout2(M+1) output by the M+1th second shift register unit 14, the first The outputs of the M second shift register units 14 are reset.

Please refer to FIG. 2 , which is a specific circuit structure diagram of a preferred embodiment of the first shift register unit 12 and the second shift register unit 14 of the shift register 10 shown in FIG. 1 , wherein FIG. 2 Only the specific circuit structures of the first shift temporary storage unit 12 and the second shift temporary storage unit 14 when N=1 and 2, M=1 and 2 are shown, for convenience of description, the four shifts are temporarily stored. The units are denoted as first shift temporary storage units 12A and 12B, and second shift temporary storage units 14A and 14B, respectively.

The first shift register unit 12A includes an output transistor M11, a logic output control module 121, a feedback switch M17, a reset transistor M12, two pull-down transistors M13 and M14, and a pull-down signal control module 123.

The logic output control module 121 is composed of a plurality of transistors, and includes a first transistor M15 and a cascade control transistor M16. The source of the first transistor M15 serves as the cascade data input terminal LIN of the first shift register unit 12A, thereby receiving the turn-on signal STV, the gate is connected to the source, and the drain is used as the logic output. The output 125 of the control module 121. The gate of the cascade control transistor M16 is connected to the drain of the first transistor M15, the source is connected to the source of the output transistor M11, and the drain is connected to the cascade of the first shift register unit 12A. Data output LOUT.

The output transistor M11 includes a control terminal 126, a source and a drain. The control terminal 126 is connected to the output end 125 of the logic output control module 121. The source is received for driving the first shift register. The first clock signal CK1 of the cell 12A and the drain electrode serve as the output terminal OUT of the first shift register unit 12A. The output signal of the logic output control module 121 is used to control the on and off of the output transistor M11. When the output transistor M11 is turned on, the electrical signal synchronized with the first clock signal CK1 is controlled by the output transistor M11. The output terminal OUT outputs, thereby outputting the first first shift signal Vout1. The output transistor M11 has a larger parasitic capacitance Cgs than the other transistors of the first shift register unit 12A.

The feedback switch M17 can be a three-terminal transistor, the gate is connected to the fourth clock signal CK4, the source is the feedback terminal FB of the first shift register unit 12A, and the feedback terminal FB receives the turn-on signal STV. The drain is connected to the control terminal 126 of the output transistor M11.

The gate of the reset transistor M12 serves as the reset terminal RE of the first shift register unit 12A, the source and the output terminal 125 of the logic output control module 121, and the drain receives a low-level cutoff voltage VGL.

The two pull-down transistors M13 and M14 are connected between the drain of the output transistor M11 and a cutoff voltage VGL. The control signal outputted by the pull-down signal control module 123 controls the turn-on and turn-off of the pull-down transistor M13, and the second clock signal CK2 is used to control the turn-on and turn-off of the pull-down transistor M14. When the two pull-down transistors M13 and M14 are turned on, the first shift signal Vout1 outputted by the first shift register unit 12A is pulled from a high level to a low level, that is, the first shift signal is no longer output. Vout1.

The pull-down signal control module 123 receives the first clock signal CK1, and includes a control input terminal 128, a control output terminal 129, a second transistor M18, and a capacitor C1. The gate of the second transistor M18 serves as the control input terminal 128, which is connected to the drain of the cascade control transistor M16, and controls whether the output signal of the control output terminal 129 is output according to the output signal of the drain electrode. The pull-down transistor M13 is turned on; the source of the second transistor M18 receives the first clock signal CK1 via the capacitor C1, and the source also serves as the control output 129.

The second shift temporary storage unit 14A, the first shift temporary storage unit 12B and the second shift temporary storage unit 14B are basically the same as the first shift temporary storage unit 12A, and the difference is as shown in the block diagram of FIG. The specific circuit diagram shown in Figure 2, including:

The source of the output transistor M21 and the cascade control transistor M26 of the second shift register unit 14A receives the third time signal CK3, and the gate of the feedback switch M27 receives the first clock signal CK1, and the second The source of the crystal M28 receives the third time signal CK3 via the capacitor C2, the gate of the pull-down transistor M24 receives the fourth time signal CK4, and the second shift register unit 14A outputs a first shift The temporary storage unit 12A is different from the second shift signal Vout2 of half a clock cycle.

The source of the output transistor M31 and the cascade control transistor M36 of the first shift register unit 12B receives the second type signal CK2, and the gate of the feedback switch M37 receives the first clock signal CK1, and the second The source of the crystal M28 receives the second time signal CK2 via the capacitor C3, the gate of the pull-down transistor M34 receives the first clock signal CK1, and the first shift register unit 12B outputs a first shift The memory unit 12A differs by a first shift signal Vout3 of one clock cycle.

The source of the output transistor M41 and the cascade control transistor M46 of the second shift register unit 14B receives the fourth time signal CK4, and the gate of the feedback switch M47 receives the second clock signal CK2, the second power The source of the crystal M48 receives the fourth time signal CK4 via the capacitor C4, the gate of the pull-down transistor M44 receives the third time signal CK3, and the second shift register unit 14B outputs a first shift The temporary storage unit 12A differs by a second shift signal Vout4 of one and a half clock cycles.

Thereafter, the electrical connection relationship between the first shift temporary storage unit 12 and the second shift temporary storage unit 14 is the same as that of the four shift temporary storage units 12A, 12B, 14A and 14B, and therefore will not be described again.

Please refer to FIG. 3, which is a timing waveform diagram of the first shift temporary storage unit 12A, the second shift temporary storage unit 14A and the first shift temporary storage unit 12B shown in FIG. 2, wherein V _t11 indicates the first a node voltage waveform at the connection node t11 of the output terminal 125 of the logic output control module 121 of the shift register unit 12A and the control terminal 126 of the output transistor M11; V _t31 represents the logic of the first shift register unit 12B The node voltage waveform at the connection node t31 of the output terminal 325 of the output control module 321 and the control terminal 326 of the output transistor M31; Vout1, Vout2, and Vout3 respectively indicate the first shift register unit 12A and the second shift temporary The waveform of the corresponding shift signal output by the memory unit 14A and the first shift register unit 12B.

At the initial stage of operation, that is, during the P1 period, the turn-on signal STV is at a high level, and the levels of the first to fourth clock signals CK1 to CK4 are low level, high level, low level, and high level, respectively:

For the first shift register unit 12A, the first transistor M15 is turned on, and the logic output control module 121 outputs a high level, that is, the node t11 outputs a high level, and the node voltage V _{t11 is} recorded as VGH, and the output is The transistor M11 is forward biased to be turned on, and its parasitic capacitance Cgs starts to be stored until it is equal to the high level, and the cascade control transistor M16 is also turned on, however, because of the first for driving the first shift register unit 12A The clock signal CK1 is at a low level, so the output terminal OUT and the cascaded data output terminal LOUT maintain a low level output.

For the second shift register unit 14A, the first transistor M25 is also turned on, the output transistor M21 is forward biased, its parasitic capacitance Cgs is stored, and the cascade control transistor M26 is also turned on. The third clock signal CK3 driving the second shift register unit 14A is at a low level, so that both the output terminal OUT and the cascaded data output terminal LOUT maintain a low level output.

Since the cascaded data output terminals LOUT of the first and second shift register units 12A, 14A are all low level outputs, the latter first and second shift register units 12B, 14B also maintain a low level output. .

When entering the P2 period, the first clock signal CK1 transitions from a low level to a high level, and when the second clock signal CK2 transitions from a high level to a low level, the third clock signal CK3 maintains a low level, and the fourth clock Signal CK4 also maintains a high level, then:

For the first shift register unit 12A, the node voltage V _{t11 is} raised to 2VGH due to the energy storage of the parasitic capacitance Cgs of the output transistor M11, the output transistor M11 and the cascade control transistor M16 is forward biased to conduct, then the output terminal OUT outputs a high level first shift signal Vout1, the output voltage is VGH, and the cascaded data output terminal LOUT also outputs a high level. The control input terminal 128 of the pull-down signal control module 123 receives the high level of the output of the cascaded data output terminal LOUT to turn on the second transistor M18, and the first clock signal CK1 charges the capacitor C1, and the pull-down signal control The control output 129 of the module 123 outputs a low level, thereby turning off the pull-down transistor M13. At the same time, since the second clock signal CK2 is also at a low level, the pull-down transistor M14 is turned off, so that the pull-down transistors M13, M14 do not affect the first shift signal Vout1. Since the drain voltage of the feedback switch M17 is 2VGH, the feedback switch M17 is reverse biased and turned off, which does not affect the node voltage V _t11 and does not affect the voltage of the output first shift signal Vout1.

At the same time, since the third clock signal CK3 for driving the second shift register unit 14A is maintained at a low level, the second shift register unit 14A maintains a low level output.

For the first shift temporary storage unit 12B, the cascaded data input terminal LIN receives the high level outputted by the cascaded data output terminal LOUT of the first shift temporary storage unit 12A, and the first transistor M35 is turned on. The logic output control module 321 outputs the high-level output transistors M31 and M36. However, since the second driving signal CK2 for driving the first shift register unit 12B is at a low level, the output terminal OUT maintains a low level. When the output is turned off, the reset transistor M12 of the first shift register unit 12A is turned off, and the node voltage V _{t11 is} not affected, so the first shift signal Vout1 is not affected by the reset transistor M12.

During the P3 period, since the third clock signal CK3 transitions from a low level to a high level, the fourth clock signal CK4 transitions from a high level to a low level, and the first and second clock signals CK1 and CK2 are maintained. No change, then:

For the first shift register unit 12A, since the turn-on signal STV is at a low level, that is, the gate and the drain of the first transistor M15 are both at a low level, the logic output control module 121 outputs the first power. The first shift register unit 12A maintains the output of the first shift signal Vout1 due to the influence of the crystal M15.

At the same time, the first transistor M25 of the second shift register unit 14A does not affect the output of the logic output control module 221. Since CK3 is at a high level, the output terminal OUT starts to output a second shift of the high level. The signal Vout2 has an output voltage of VGH, and the second shift signal Vout2 is outputted half a cycle away from the first shift signal Vout1.

For the first shift register unit 12B, the cascaded data input terminal LIN continues to receive the high level output from the cascaded data output terminal LOUT of the first shift register unit 12A, the first transistor The M35 maintains the conduction, and the logic output control module 321 outputs a high level to the output transistor M31 and the cascade control transistor M36, that is, the node t31 outputs a high level, and the node voltage V _t31 maintains the VGH output, and the output transistor M31 The forward bias is turned on, and the cascade control transistor M36 is also turned on. However, since the second clock signal CK2 for driving the first shift register unit 12B is at a low level, the output terminal OUT and the cascaded data output are output. The terminal LOUT maintains the low level output, and the first shift register unit 12A does not affect the output of the first shift signal Vout1. Although the third clock signal CK3 is at a high level, since the three terminals of the feedback switch M37 are both VGH, the feedback switch M37 is turned off, and the node voltage V _{t31 is} not affected.

During the P4 period, the first clock signal CK1 transitions from a high level to a low level, the second clock signal CK2 transitions from a low level to a high level, and the third clock signal CK3 maintains a high level. The four clock signal CK4 is maintained at a low level. then:

For the first shift register unit 12A, since the turn-on signal STV is at a low level, that is, the gate and the drain of the first transistor M15 are both at a low level, the first shift register unit 12A The output of the logic output control module 121 is not affected by the first transistor M15. At this time, the output transistor M11 and the cascade control transistor M16 are still turned on, but since the first clock signal CK1 as the driving signal is low, The output terminal OUT and the high level of the output of the cascaded data output terminal LOUT transition to a low level. In addition, since the control input terminal 128 of the pull-down signal control module 123 receives the low level outputted by the cascaded data output terminal LOUT, the second transistor M18 is turned off, and the capacitor C1 is discharged to turn on the pull-down transistor M13. The first shift signal Vout1 outputted by the output terminal OUT can quickly jump to a low level.

At the same time, for the first shift register unit 12B, the signal received by the cascade data input terminal LIN also becomes a low level, that is, the gate and the drain of the first transistor M35 are both low, then the The first transistor M35 does not affect the output of the logic output control module 321, that is, does not affect the node voltage _Vt31 . Influenced by the parasitic capacitance Cgs of the output transistor M31, the node voltage V _{t31 is} raised to 2VGH, so that the output transistor M31 and the cascade control transistor M36 are kept turned on, because the first shift is temporarily used for driving The second clock signal CK2 of the memory unit 12B has jumped to a high level, so the first shift register unit 12B outputs a first shift signal Vout3 of a high level.

Then, the reset terminal RE of the first shift register unit 12A receives the high level signal, the reset transistor M12 is turned on, and the node voltage V _t11 is forcibly pulled low to a low level, so that the first shift The output transistor M11 of the bit buffer unit 12A and the cascade control transistor M16 are turned off, and the first shift register unit 12A ends its operation to maintain a low level output.

For the second shift register unit 14A, since the third clock signal CK3 used as the driving period of the P4 period is maintained at a high level, the fourth clock signal CK4 serving as the control pull-down transistor M24 is maintained at a low level, and its reset transistor is reset. Both the M22 and the pull-down transistor M23 are in an off state, so that the output terminal OUT of the second shift register unit 14A is unaffected, and the second shift signal Vout2 of the high level is output. The second shift signal Vout2 is separated from the first shift signal Vout1 by a half cycle.

When the feedback terminal FB of the first shift register unit 12B receives the second shift signal Vout2, even if the third clock signal CK3 is at a high level, since the node voltage V _t31 is 2VGH, the feedback switch M37 The three terminals are in a reverse bias state, and the first shift signal Vout3 output by the first shift register unit 12B is not affected.

During the P5 period, the third clock signal CK3 transitions from a high level to a low level, and the fourth clock signal CK4 transitions from a high level to a low level, and the first and second clock signals CK1 and CK2 remain unchanged. ,then:

For the second shift register unit 14A, since the turn-on signal STV becomes a low level, that is, the gate and the drain of the first transistor M25 are both at a low level, the logic output control module 221 outputs are not affected. The influence of the first transistor M25, at this time, the output transistor M21 and the cascade control transistor M26 are still turned on, but since the third clock signal CK3 as the driving signal is low level, the output terminal OUT and the cascade data The high level of the output of the output LOUT transitions to a low level. In addition, since the control input terminal 228 of the pull-down signal control module 223 receives the low level, the second transistor M28 is turned off, and the capacitor C2 is discharged to turn on the pull-down transistor M23, the second shift signal Vout2 can Fast jump to low level.

At the same time, for the first shift register unit 12B, the node voltage V _{t31 is} maintained at 2VGH, so that the output transistor M31 and the cascade control transistor M36 are kept turned on, and since the second clock signal CK2 is maintained at a high level, the first A shift register unit 12B maintains a first shift signal Vout3 that outputs a high level.

Thereafter, the working principles of the first shift temporary storage unit 12 and the second shift temporary storage unit 14 are the same as those of the above-mentioned several shift temporary storage units 12A, 12B, 14A, and 14B, and therefore will not be described again.

It can be seen from the foregoing working principle that the shift register 10 of the foregoing shifts the function of the shift, and the feedback terminal FB of the Nth first shift register unit 12 receives the Mth second shift. The signal of the output terminal OUT of the memory unit 14 and the feedback terminal FB of the Mth second shift register unit 14 receive the signal of the output terminal OUT of the Nth first shift register unit 12, even if the Nth A shift register unit 12 and the M second shift register units 14 carry a large load, but are used to control the corresponding output transistors, such as the node voltages V _t11 and V _{t31 of} M11 and M31 are not subject to feedback. The influence of the circuit in which the switches M17 and M37 are located, so that the output of the corresponding shift register unit 12, 14 is stabilized.

Please refer to FIG. 4, which is a structural block diagram of a preferred embodiment of a liquid crystal panel driving circuit of the present invention. The liquid crystal panel driving circuit 60 provides a liquid crystal panel 80 with scanning and displaying data signals. The liquid crystal panel 80 includes a driving array 82. The driving array 82 includes a plurality of scanning lines 821 and a plurality of data lines 822 perpendicularly insulated from the scanning lines 821, and a minimum area surrounded by two adjacent scanning lines 821 and two data lines 822. A pixel area P is defined. Each pixel region P includes a pixel pixel electrode 823 and a switching element 824. The scan signal controls the on and off of the switching element 824 via the scan line. When the switching element 824 is turned on, the display data signal is transmitted to the pixel electrode 823 via the corresponding data line 822.

The driving circuit 60 includes a scan driving circuit 62 for providing a scanning signal, and a data driving circuit 64 for providing a data display signal. The scan driving circuit 62 includes the shift register 10, and the first and second shift signals output by the shift register 10 serve as scan signals of the complex scan line 821. The plurality of first shift register units 12 can sequentially provide scan signals for the scan lines 821 of the odd columns, and the plurality of second shift register units 14 can sequentially provide scan signals for the scan lines 821 of the even columns. Optionally, the driving circuit 60 can also use the first or second shift signals output by the plurality of first shift temporary storage units 12 or the plurality of second shift temporary storage units 14 to sequentially be the scan line 821. Provide scanning signals.

Since the scan driving circuit 62 of the liquid crystal panel driving circuit 60 uses the shift register 10 to provide a scan signal, the stability of the scan signal outputted by the driving circuit 60 is also high.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Shift register

12, 12A, 12B‧‧‧ first shift temporary storage unit

14, 14A, 14B‧‧‧ second shift temporary storage unit

LIN‧‧‧ Cascade Data Input

LOUT‧‧‧ Cascade data output

FB‧‧‧Feedback

RE‧‧‧Reset end

OUT, 125, 325‧‧‧ output

126, 326‧‧‧ control end

STV‧‧‧Open signal

CK1‧‧‧ first clock signal

CK2‧‧‧ second clock signal

CK3‧‧‧ third clock signal

CK4‧‧‧ fourth clock signal

VGL‧‧‧ cutoff voltage

M11, M21, M31, M41‧‧‧ output transistors

M12, M22, M32‧‧‧ Reset transistor

M13, M23, M14, M24, M34, M44‧‧‧ pull-down transistors

M15, M25, M35‧‧‧ first transistor

M16, M26, M36, M46‧‧‧ cascade control transistor

M17, M27, M37, M47‧‧‧ feedback switch

M18, M28, M38, M48‧‧‧ second transistor

121, 221, 321‧ ‧ logical output control module

123, 223‧‧‧ Pull-down signal control module

128, 228‧‧‧ control input

129‧‧‧Control output

T11, t31‧‧‧ nodes

V _t11 , V _t31 ‧‧‧ node voltage

C1, C2, C3, C4‧‧‧ capacitors

Cgs‧‧‧ parasitic capacitance

60‧‧‧LCD panel driver circuit

62‧‧‧Scan drive circuit

64‧‧‧Data Drive Circuit

80‧‧‧LCD panel

82‧‧‧Drive array

821‧‧‧ scan line

822‧‧‧Information line

P‧‧‧pixel area

823‧‧‧pixel electrode

824‧‧‧Switching elements

Vout1, Vout3, Vout5, Vout(2N-1), Vout(2N+1), Vout(2N+3)‧‧‧ first shift signal

Vout2, Vout4, Vout6, Vout2(M-1), Vout2M, Vout2(M+1), Vout2(M+2)‧‧‧ second shift signal

1 is a structural block diagram of a preferred embodiment of a shift register of the present invention.

FIG. 2 is a specific circuit structural diagram of a preferred embodiment of a first shift register unit and a second shift register unit of the shift register shown in FIG.

3 is a timing waveform diagram of the first shift temporary storage unit, the second shift temporary storage unit, and the latter first shift temporary storage unit shown in FIG. 2.

4 is a structural block diagram of a preferred embodiment of a liquid crystal panel driving circuit of the present invention.

10‧‧‧Shift register

12‧‧‧First shift register unit

14‧‧‧Second shift register unit

LIN‧‧‧ Cascade Data Input

LOUT‧‧‧ Cascade data output

FB‧‧‧Feedback

RE‧‧‧Reset end

OUT‧‧‧ output

STV‧‧‧Open signal

CK1‧‧‧ first clock signal

CK2‧‧‧ second clock signal

CK3‧‧‧ third clock signal

CK4‧‧‧ fourth clock signal

VGL‧‧‧ cutoff voltage

Claims (21)

A shift register includes:
a first shift register unit, the adjacent two first shift register units respectively receive a first clock signal and a second clock signal provided by an external circuit, wherein the first clock signal and the second clock signal are Periodic pulse signal with opposite phase;
a plurality of second shift register units, wherein the adjacent two second shift register units respectively receive a third clock signal and a fourth clock signal provided by the external circuit, wherein the third clock signal is phased with the fourth clock signal An opposite periodic pulse signal, and the first clock signal and the third clock signal are separated from each other by a half cycle;
Each of the first shift temporary storage unit and the second shift temporary storage unit includes a primary data input terminal, a primary data output terminal, an output terminal for outputting a shift signal, a feedback terminal, and a reset. The shift signal of the Mth second shift register unit is fed back to the feedback end of the N+1th first shift register unit, and the shift signal feedback of the Nth first shift register unit To the feedback end of the Mth second shift temporary storage unit, wherein M takes a natural number, N=M, and the reset end of the Nth first shift temporary storage unit and the cascaded data output end respectively The output end of the N+1th first shift temporary storage unit is connected to the cascade data input end, and the reset end of the Mth second shift temporary storage unit and the cascaded data output end are respectively associated with the M+1th The output end of the second shift register unit is connected to the cascade data input end. When the cascade data input end of the Nth first shift register unit receives a starting voltage, the Nth first The output end of the shift register unit outputs a shift signal synchronized with the first clock signal, and the N+1th first shift register unit outputs The second clock signal synchronizes the shift signal, and the reset end of the Nth first shift register unit controls the Nth according to the shift signal of the (N+1)th first shift register unit Whether the output signal of the first shift register unit is reset; when the cascade data input end of the Mth second shift register unit receives a start voltage, the Mth second shift register unit output a shift signal synchronized with the third clock signal, and the M+1 second shift register unit outputs a shift signal synchronized with the fourth clock signal, and at the same time, the Mth second shift temporary The reset end of the memory unit controls whether the output signal of the Mth second shift register unit is reset according to the shift signal of the M+1 second shift register unit. The shift register according to claim 1, wherein each of the first and second shift register units comprises an output transistor, and the control end of the output transistor controls the conduction of the output transistor. When the output transistor of the Nth first shift register unit is turned on, the first clock signal or the second clock signal is output from the corresponding first shift register unit via the output transistor. End output; when the output transistor of the Mth second shift register unit or the M+1th second shift register unit is turned on, the third clock signal or the fourth clock signal passes the output The transistor is output from the output of the corresponding second shift register unit. The shift register according to claim 2, wherein each of the first and second shift register units further comprises a logic output control module, and an output of the logic output control module is connected to the output The control terminal of the transistor controls whether the starting voltage is supplied to the control terminal of the output transistor. The shift register according to claim 3, wherein the logic output control module comprises a first transistor, and the source of the first transistor is used as a cascade data input of the corresponding shift register unit. The gate is connected to the source and its drain is the output of the logic output control module. The shift register according to claim 3, wherein each of the first and second shift register units further comprises a feedback switch connected to the control end of the output transistor and correspondingly Between the feedback ends. The shift register of claim 5, wherein the feedback switch is a three-terminal transistor. The shift register according to claim 6, wherein when the Nth first shift register unit receives the first clock signal, the feedback switch of the Nth first shift register unit The gate receives the fourth clock signal, and the gate of the feedback switch of the (N+1)th first shift register unit receives the third clock signal. The shift register according to claim 6, wherein when the Mth second shift temporary storage unit receives the third clock signal, the feedback of the Mth second shift temporary storage unit The gate of the switch receives the first clock signal, and the gate of the feedback switch of the M+1th second shift register unit receives the second clock signal. The shift register according to claim 5, wherein each of the first and second shift register units further comprises a reset transistor, and the gate of the reset transistor serves as a corresponding reset terminal. The source is connected to the control terminal of the output transistor, and the drain receives a cutoff voltage. The shift register according to claim 9, wherein when the output end of the (N+1)th first shift register unit outputs a lead communication number, the Nth first shift register unit The reset transistor is turned on, and the cutoff voltage of the reset transistor output reduces the initial voltage of the output of the corresponding logic output control module to a cutoff voltage, so that the output transistor of the Nth first shift register unit is turned off. . The shift register according to claim 9, wherein when the output end of the M+1th second shift register unit outputs a lead communication number, the Mth second shift register unit The reset transistor is turned on, and the cutoff voltage of the reset transistor output reduces the initial voltage of the output of the corresponding logic output control module to a cutoff voltage, so that the output transistor of the Mth second shift register unit is turned off. . The shift register of claim 4, wherein the logic control output module further comprises a cascade control transistor, the gate of the cascade control transistor being connected to the drain of the first transistor The source is connected to the source of the corresponding output transistor, and the drain is used as the corresponding cascaded data output. The shift register of claim 12, wherein each of the first and second shift register units further comprises an at least one pull-down transistor connected to a cut-off voltage Between the drain of the corresponding output transistor. The shift register according to claim 13, wherein each of the first and second shift register units further includes a pull-down signal control module, and each pull-down signal control module includes a control input terminal and a control output terminal, and the pull signal control module of the first shift register unit receives the corresponding first or second clock signal, and the second shift register unit pulls the signal control module to receive the corresponding third or the third a four-clock signal, the control input is connected to the drain of the corresponding cascade control transistor, and according to the output signal of the drain, controlling whether the output signal of the control output turns on the at least one pull-down transistor, when the at least When a pull-down transistor is turned on, the first and second shift signals output by the corresponding first and second shift register units are lowered. The shift register of claim 14, wherein the pull-down signal control module comprises a second transistor, and the gate of the second transistor serves as a control input of the pull-down signal control module. The pole is connected to the corresponding clock signal via a capacitor, and the drain is connected to a cutoff voltage. The shift register according to claim 13, wherein the Nth first shift register unit further receives the second clock signal, and the second clock signal directly controls the corresponding at least one pull. The first and second first shift register units further receive the first clock signal, and the first clock signal directly controls the on and off of the corresponding at least one of the lower pull transistors. The shift register according to claim 13, wherein the Mth second shift register unit further receives the fourth clock signal, and the fourth clock signal directly controls the corresponding at least one pull. The M+1 second shift register unit further receives the third clock signal, and the third clock signal directly controls the on and off of the corresponding at least one pull-down transistor. A liquid crystal panel driving circuit comprising:
Complex pixel electrode;
Multiple scan lines;
a plurality of data lines, the plurality of data lines being insulated from the plurality of scan lines;
a scan driving circuit, the scan driving circuit supplies a scan signal to the corresponding pixel electrode via the plurality of scan lines; and a data driving circuit, the data driving circuit provides a display data signal to the corresponding pixel electrode via the plurality of data lines;
The scan driving circuit includes a shift register, and the shift signal outputted by the shift register is used as the scan signal, and the shift register is any one of the patent scopes 1 to 17. The shift register is described. The liquid crystal panel driving circuit of claim 18, wherein the plurality of first shift temporary storage units sequentially provide scanning signals for the scan lines of the odd columns, and the plurality of second shift temporary storage units are sequentially Provides scanning signals for scan lines of even columns. The liquid crystal panel driving circuit of claim 18, wherein the scan driving circuit uses only the plurality of first shift register units to provide a scan signal for the plurality of scan lines. The liquid crystal panel driving circuit of claim 18, wherein the scan driving circuit uses only the plurality of second shift register units to provide a scan signal for the plurality of scan lines.