TWI335596B - Method and system for data pattern sensitivity compensation using different voltage - Google Patents

Method and system for data pattern sensitivity compensation using different voltage Download PDF

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Publication number
TWI335596B
TWI335596B TW96117515A TW96117515A TWI335596B TW I335596 B TWI335596 B TW I335596B TW 96117515 A TW96117515 A TW 96117515A TW 96117515 A TW96117515 A TW 96117515A TW I335596 B TWI335596 B TW I335596B
Authority
TW
Taiwan
Prior art keywords
voltage
volatile storage
volatile
data
storage element
Prior art date
Application number
TW96117515A
Other languages
English (en)
Chinese (zh)
Other versions
TW200802378A (en
Inventor
Nima Mokhlesi
Yingda Dong
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/421,884 external-priority patent/US7310272B1/en
Priority claimed from US11/421,871 external-priority patent/US7450421B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200802378A publication Critical patent/TW200802378A/zh
Application granted granted Critical
Publication of TWI335596B publication Critical patent/TWI335596B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
TW96117515A 2006-06-02 2007-05-17 Method and system for data pattern sensitivity compensation using different voltage TWI335596B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/421,884 US7310272B1 (en) 2006-06-02 2006-06-02 System for performing data pattern sensitivity compensation using different voltage
US11/421,871 US7450421B2 (en) 2006-06-02 2006-06-02 Data pattern sensitivity compensation using different voltage

Publications (2)

Publication Number Publication Date
TW200802378A TW200802378A (en) 2008-01-01
TWI335596B true TWI335596B (en) 2011-01-01

Family

ID=38802197

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96117515A TWI335596B (en) 2006-06-02 2007-05-17 Method and system for data pattern sensitivity compensation using different voltage

Country Status (2)

Country Link
TW (1) TWI335596B (fr)
WO (1) WO2007143399A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7978527B2 (en) 2008-06-03 2011-07-12 Sandisk Technologies Inc. Verification process for non-volatile storage
US7839687B2 (en) * 2008-10-16 2010-11-23 Sandisk Corporation Multi-pass programming for memory using word line coupling
US9336891B2 (en) 2014-07-02 2016-05-10 Sandisk Technologies Inc. Look ahead read method for non-volatile memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3884448B2 (ja) * 2004-05-17 2007-02-21 株式会社東芝 半導体記憶装置
EP1991989B1 (fr) * 2006-03-03 2011-01-05 Sandisk Corporation Opération de lecture pour mémoire rémanente avec compensation pour couplage de grille flottante
US7436733B2 (en) * 2006-03-03 2008-10-14 Sandisk Corporation System for performing read operation on non-volatile storage with compensation for coupling
US7499319B2 (en) * 2006-03-03 2009-03-03 Sandisk Corporation Read operation for non-volatile storage with compensation for coupling
US7310272B1 (en) * 2006-06-02 2007-12-18 Sandisk Corporation System for performing data pattern sensitivity compensation using different voltage

Also Published As

Publication number Publication date
WO2007143399A3 (fr) 2008-03-13
WO2007143399A2 (fr) 2007-12-13
TW200802378A (en) 2008-01-01

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MM4A Annulment or lapse of patent due to non-payment of fees