TWI335596B - Method and system for data pattern sensitivity compensation using different voltage - Google Patents

Description

1335596 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to techniques for non-volatile memory. [Prior Art] Semiconductor S memory has become more and more widely used in various electronic devices. For example, non-volatile semiconductor memory is used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and the most common non-volatile semiconductor memory in flash memory systems. Both the EEPROM and the flash memory utilize floating gates that are positioned above the channel region and insulated from the channel region in the semiconductor substrate. The floating gate is positioned between the source and drain regions. The control gate is provided above the floating gate and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge retained by the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before conduction to the crystal to allow conduction between its source and > and the pole is controlled by the level of charge on the floating gate. An example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series between two select gates. The isoelectric body connected in series with the 荨 selection gate is referred to as an N AND string. When a EEPROM or flash memory device (such as a NAND type flash memory device) is programmed, a stylized voltage is typically applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. when

120932.doc 1335596 When electrons accumulate in the floating gate, the floating gate becomes a negative load state, and the threshold voltage of the S-resonant unit rises, causing the memory cell system to be in a stylized state. For more information, see U.S. Patent No. M59,397 entitled "Source side Self Boosting Technique f0r Non_Volatile Mem〇ry" and U.S. Patent No. 6,917,542 entitled "Detecting 〇ver Pr〇gra_ed Memory" The entire contents of these publications are incorporated herein by reference. Some EEPROM and flash memory devices have floating gates for storing two ranges of charge, and thus can be in two states (erased state and programmed) Stylized/erased memory unit. This type of flash memory device is sometimes referred to as a binary flash memory device. A multi-state flash memory device is identified by Multiple disparity allowed/effective stylized threshold voltage ranges with phase-inhibition disabled are implemented. Each distinct threshold voltage range corresponds to one for memory Predetermined values for each set of data bits that are coded. Errors can occur when reading non-volatile storage elements due to at least two mechanisms: (1) capacitance between adjacent floating gates Coupling; and (2) channel region conductivity changes after stylization (referred to as the back-type effect). The two topics are discussed below. The offset of the apparent charge stored on the floating gate can be attributed to the adjacent floating gate The electric field coupling of the charge stored in the pole occurs. This floating gate-to-floating gate coupling phenomenon is described in U.S. Patent No. 5,867,429, the entire disclosure of which is incorporated herein by reference. The gate may include: adjacent floating gates on the same bit line;

S 120932.doc 1335596 Adjacent floating gates on the same word line; or floating gates located at opposite corners of the target floating gate, the floating gates of which are located on adjacent bit lines and adjacent word lines. The floating gate to floating gate coupling phenomenon occurs most significantly between several sets of adjacent memory cells that have been programmed at different times. For example, a memory cell is programmed to add a charge level to its float: gate, which corresponds to the -group data. Thereafter, ~ or more adjacent memory cells are programmed to add a charge level to its floating gate, which corresponds to a second set of data. One or more memory cells in adjacent memory cells: after stylization, read from the first memory because the charge on the adjacent memory cells is coupled to the first memory cell The charge level of the body unit appears to be different from the programmed charge level. Coupling from adjacent memory cells can shift the apparent charge level in the read with an offset sufficient to cause erroneous reading of the stored data. Since the allowable threshold voltage range and the disable range are narrower than binary devices in multi-state devices, the effect of floating gate-to-floating gate coupling is of concern for multi-state devices. Therefore, floating gate to floating gate coupling can cause the memory cell to shift from an allowed threshold voltage range to a disabled range. As the memory cell size continues to shrink, the expected natural threshold voltage stylization and erase distribution increases due to short channel effects, large oxide thickness/coupling ratio changes, and larger channel dopant fluctuations. The available separation between adjacent states is thus reduced. This effect of multi-state memory is more pronounced than that of memory using only two states (binary memory). 120932.doc 1335596 In addition, the space between the word lines and the space between the bit lines will also increase the fit between adjacent floating gates. Errors can also occur due to the retrotype effect. In a typical Nand-type flash memory device, the memory cells are programmed in a certain order, where the memory banks adjacent to the source-side selection gates are first programmed. Thereafter, the memory cells on the adjacent word lines are programmed, then the memory cells on the adjacent sub-lines are programmed, and so on, until the memory on the last word line of the gate is selected to be close to the 汲 汲 汲 侧unit. As more memory cells in a NAND string are programmed, the conductivity in the channel region below the unselected-word line will decrease, due to the higher threshold voltage of the programmed memory cell. The threshold voltage of the memory cell in the erased state. This increased channel resistance changes the characteristics of the memory cell. When a particular memory cell is being programmed (and verified), all memory cells above the word line of the selected word line are still erased. Therefore, conduction is excellent in the channel region below their word lines, resulting in a relatively high memory cell current during the actual verify operation. However, all of the memory cells of the NAND string are clamped to their desired state. As most of the memory cells will be programmed into the stylized state (more than 25%) The memory cells will remain erased. The conductivity in the channel region below their word lines is typically reduced. The IV characteristic changes because there will be less current than the previous verification operation during the stylization. The reduced current causes a false offset of the threshold voltage of the memory unit, which can cause errors when reading data. This effect is called the receding effect.

120932, doc 1335596 [Summary of the Invention]. . For the amount of adjacent floating gates, for the specific memory, the early reading process will provide compensation for the adjacent memory cells to reduce the specific memory of the adjacent memory cells. The consumable effect of the body. In order to consider the back-type effect, a first voltage is used during a verify operation of a non-selected word line that has been subjected to a stylized operation, and is used for a non-selected word line that has not been subjected to the method - second Voltage. The combination of these two technologies provides more accurate data storage and retrieval. A specific embodiment includes applying a voltage of a shirt to a particular non-volatile storage element in a group comprising connected non-volatile storage elements; applying: -: - voltage to one of the groups Or a first set of a plurality of non-volatile storage elements; applying a second voltage to one of the group comprising a second set of the plurality of non-volatile storage elements; applying the specific electricity, applying a different The second voltage is one of the groups adjacent to the non-volatile storage element' and the programming of the particular non-volatile storage element is verified based on the particular voltage. The first set of one or more non-volatile storage elements is located on a first side of the particular non-volatile storage element and has been programmed one or more times since the last erase of the group = The first wish is applied in conjunction with the particular voltage. The second set of one or more non-issuous storage elements is located at one of the particular non-volatile storage elements and m has not undergone a stylization process since the last erasure of the group. The second electric grind is applied in conjunction with the particular voltage. The adjacent non-volatile storage element is located on the second side of the particular non-volatile storage element proximate to the particular non-volatile storage element. Self-erase the group to

120932•细 丄: The second non-volatile storage element has not been programmed. The eight-body embodiment includes: applying a specific power to a specific non-volatile storage element in a group containing the connected non-volatile storage elements; = a first - electric dust to one of the groups The first pass of one or more non-volatile storage elements, ginkgo. Since the last erasure of one of the groups, the first set of the plurality of non-volatile storage elements has undergone one or more stylization processes; applying - the second voltage to one of the groups Or a plurality of non-volatile storage 7L pieces of the second set; in combination with applying the specific voltage, applying a different voltage from the second voltage to the adjacent non-volatile storage element of the group, according to the specific voltage To verify the A-form of the particular non-volatile storage element and to read data from the particular non-volatile storage element. The reading includes applying a data dependent electrical condition to the adjacent non-volatile storage element in accordance with one of the conditions of the adjacent non-volatile storage element. The first voltage is applied in conjunction with the particular electromigration. Since the last erasure of the group, the second set of one or more non-volatile storage elements has not undergone a stylization process, and the second electric dust is applied in conjunction with the specific electric power; The volatile storage element is in close proximity to the particular non-volatile storage element. A specific embodiment includes: applying a specific electrical I to - a specific non-volatile storage element in a group comprising connected non-volatile storage elements; applying a first-voltage to the group - or A plurality of non-volatile storage elements 'have-last erased the group' since the one or more non-volatile storage elements have undergone - or multiple stylization processes; applying a second voltage to one of the groups A collection of one or more non-volatile storage elements since the erasure of the group 'the collection of one or more non-volatile storage elements has not been recorded 120932.doc • 11. 5 1335596: a stylized process; Selecting a dependent voltage according to the number of non-volatile storage elements in the set; and applying (with the special::: several miles to - non-volatile needle 1 with voltage) the dependent voltage (4) non-volatile storage element system The particular non-survival 4 neighbor; and sensing the condition regarding the particular non-volatile storage and the particular voltage. In conjunction with the particular voltage, the voltage is applied to the particular voltage and the second voltage is applied. -: An exemplary embodiment includes: a plurality of non-volatile storage elements;

And a logic circuit in communication with the plurality of non-volatile storage elements for performing the processes described herein. [Embodiment] An example of a memory system suitable for implementing the present invention uses a NAND type flash memory structure, # including a plurality of transistors arranged in series between two selected gates. The transistors in series and the select gates are referred to as a NAND string. Figure 1 depicts a top view of a NAND string. Figure 2 shows the equivalent circuit. The NAND string shown in Figures 1 and 2 includes four transistors 100, 102, 104 and 100 sandwiched between a first selected closed pole 120 and a first selected ground 122. The gate 120 is gated to the NAND string connection of bit line 126. The gate 122 is connected to the nand string connection of the source line 128. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 12 CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. The transistors 100, 1〇2, 104, and 106 each have a control gate and a floating gate. The transistor 1 has a control gate 1 CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG. And floating gate 102FG * transistor 104 includes control gate 104CG and floating gate 120932.doc • 12· 1335596 104FG. The transistor i〇6 includes a control gate 1〇6CG and a floating gate 106FG. The control gate i〇OCG is connected to (or is) the word line WL3, the control gate 102CG is connected to the word line WL2, and the control gate 104 (: (3 is connected to the word line WL1, and the control gate i〇6CG) Connected to the word line wl〇^ In one embodiment, the transistors 100, 102, 1〇4, and 106 are all memory cells. In other embodiments, the memory cell can include a plurality of transistors. Or may be different from the memory unit shown in Figures 1 and 2.

The gate 120 is connected to the select line SGD»select gate 122 connected to the select line SGS.

3 is a side view of the NAND string described above. As shown in FIG. 3, the electro-crystalline system of the NAND string is formed in the p-well region 14A. Each of the transistors includes a stacked gate structure consisting of a control gate (1〇〇CG, 1〇2CG, 1〇4CG*106CG) and a floating gate (1〇〇FG, i〇2fg, l〇4FG*1〇6FG). Control gates and floating gates are typically formed by depositing a polysilicon layer. The floating interrogation system is formed on the surface of the p-well on top of an oxide or other dielectric film. The control gate is above the floating gate, and the polysilicon (tetra) dielectric layer separates the control gate from the floating gate. The control cells of the memory cells (1〇〇, 1〇2, 104, and 106) form a word line. The N+ doped diffusion regions 13〇, 132, 134, 136, and 138 are shared between adjacent memory cells, whereby the memory cells are connected in series to each other to form a NAND string. The N+ doped regions form the source and the extremum of each of the memory cells. For example, the drain of 122 and the drain of the source 106 of the transistor 106 and the source 'N+ doped region 130 of the transistor 104 serve as a transistor; the N+ doped region 132 acts as an electric crystal; the N+ doped region 134 acts as the source of the drain of the transistor I20932.doc 13 j 1335596 104 and the source of the transistor 1〇2; the N+ doped region 136 acts as the drain of the transistor 102 and the source of the transistor 100; and the N+ doped region 138 It serves as the drain of the transistor 100 and the source of the transistor 120. N+ doped region 136 is coupled to the bit line of the NAND string, and N+ doped region 138 is coupled to a common source line for a plurality of NAND strings. Note that although Figures 1 through 3 illustrate the presence of four memory cells in the NAND string, the use of four memory cells is provided as an example only. In conjunction with the techniques described herein - the nand string can have fewer than four memory cells or more than four memory cells. For example, some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, and the like. The discussion herein does not limit the number of any particular memory cell in a NAND string. Each memory unit can store data expressed in analog or digital form. When storing bit-bit data, the possible threshold voltage range of the memory cell is divided into two ranges that are assigned as logical data "" and "〇". In NAND-type flash memory - The real shot, the memory voltage after the memory cell is erased is negative and is defined as "]". The threshold voltage after the stylized operation is positive and is definitely ambiguous. When the threshold voltage is negative and an attempt is made to apply the sag to the control gate for reading, the 'memory unit will be turned on to indicate that the remote is being stored.” l, although the threshold voltage is positive and an attempt is made to apply 0. When reading to the control pole, the memory unit is not turned on, indicating that the storage logic "0' memory unit can also be; i J to store multiple states, thereby storing multi-bit digital data. If the storage data is stored in multiple states, the threshold voltage window is divided into 120932.doc • 14· 1335596 dry state. For example, if four states are used, then four threshold voltage ranges will be assigned to the data values "U,|,"1〇", "〇1" and "〇〇". In one example of the Nand type s memory, the threshold voltage after the erase operation is negative and is defined as "11". The positive threshold voltage is used for the state "10" ' "〇1" And ',00,·〇

NAND-type flash memory and related examples of operation thereof are provided in the following U.S. Patent/Patent Application, the entire contents of which are hereby incorporated by reference: U.S. Patent No. 5,570,315; U.S. Patent No. 5,466, 397; U.S. Patent No. 5,386 '422; U.S. Patent No. 6,456,528; and U.S. Patent Publication No. US2003/0002348. Other types of non-volatile memory other than NAND type flash memory can be used in conjunction with the present invention. Another type of memory cell that is useful for flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate for storing charge in a non-volatile manner. March 1987 IEEE Electr〇n Device

Letters, EDL-8, No. 3, pp. 93-95, Chan et al., "A Tru (Single-Transistor Oxide-Nitride-Oxide EEPROM Device'^" describes such a memory cell. The three-layer dielectric formed by bismuth oxide and bismuth oxynitride ("ΟΝΟ") is sandwiched between a conduction control gate and a surface of one of the semiconducting substrates above the memory cell channel. The electrons are injected from the memory cell channel into the nitride (where the electrons are intercepted and stored in the restricted area) to program the memory cell. Then, the stored charge changes the channel of the memory cell in a detectable manner. Part of the threshold voltage. The 120932.doc 15 1335596 memory cell is erased by injecting a thermal hole into the nitride. See also IEEE April of Solid State Circuits, Vol. 26, No. 4, April 1991. 497-501, Nozaki et al., VIII-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application", which describes a similar memory unit of a split-gate configuration, in which a doped complex The gate extends over a portion of the memory cell channel to form a separate select transistor. The two articles mentioned above are incorporated herein by reference. IEEE IEEE 1998 by William D. Brown Stylized techniques are proposed in Section 1.2, edited by Joe E. Brewer, "Nonvolatile Semiconductor Memory Technology", and the description in this section also applies to dielectric charge trapping devices. The described memory cells can also be used in conjunction with the present invention. Therefore, the techniques described herein are also applicable to the coupling between dielectric regions of different memory cells. IEEE Electron Device Letters, Vol. 21, No. 11 of November 2000 154-545, Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", has described another practice of storing two bits in each memory cell. The dielectric layer extends across the source. And the channel between the bungee diffusion. The charge of one data bit is localized in the dielectric layer adjacent to the drain, and the charge of the other data bit is localized in the dielectric layer adjacent to the source. Multiple state data storage is obtained by separately reading the binary states of the spatially separated charge storage regions within the dielectric. The memory unit described in this paragraph can also be used in conjunction with the present invention. 4 illustrates an example of a NAND cell array, such as the NAND cells of 120932.doc -16· 1335596 shown in FIGS. 1 through 3. Along each row, a bit line 206 is coupled to the > and pole select gates for the NAND string 150; and the pole terminal 126. A source line 204 along each column of NAND strings can be connected to the source terminals 128 of the source select gates of all of the NAND strings. Examples of NAND architecture arrays and their operation as part of a memory system are described in U.S. Patent Nos. 5,57,315; 5,774,397; and 6,046,935. The memory cell array is divided into a plurality of memory cell blocks. As with the flash EEPROM system, the block is an erase unit, that is, each block contains a minimum number of memory cells that can be erased together. Each block is typically divided into pages. In one embodiment, one page is a stylized unit. In a specific embodiment, individual pages can be divided into segments, and the segments can include a minimum number of memory cells that are written at a time as a basic stylized operation. One or more pages of data are typically stored in a column of memory cells. One page can store one or more segments (sect〇r). A section includes user data and additional items (overheacj). The additional item data typically includes an error correction code (ECC) that has been calculated from the user profile for that section. A portion of the controller (described below) calculates the ECC when the data is programmed into the array, and also checks the ECC when the data is read from the array. Alternatively, the ECC and/or other additional items may be stored in a different page (or even a different block) than the user data. The user data for a segment is typically 512 bytes, which corresponds to the size of one of the Seetors in the drive. The additional item data is typically an additional 16-20 bytes. A large number of pages form a block, for example, from 8 pages to the most "2, 64, 128 or more [in some embodiments -17-120932.doc 1335596, a column of NAND strings includes a block" In one embodiment, the memory cell is erased by raising the p-well to an erase voltage (eg, 20 volts) for a sufficient period of time and grounding the word line of the selected block while the source The line and bit line are in a floating state. Due to capacitive coupling, the unselected word line, bit line, and select line and source line also rise to a significant fraction of the erase voltage. Reinforcing the electric field to the tunneling oxide layer of the memory cell of the selected block, and electrons emitted from the floating gate are emitted to the substrate 'causing the data of the selected memory cell to be erased' typically by Fowler_Nordheim tunneling Mechanism. As electrons move from the floating gate to the p-well, the threshold voltage of the selected memory cell is reduced. Erasing can be performed on the entire memory array, separate blocks, or other memory unit units. 5 shows an item according to the invention The memory device 296 of the embodiment has read/write circuits for reading and staging a page of memory cells in parallel. The memory device 296 can include one or more memory die 298. The memory die 298 includes a two-dimensional memory cell array 300, a control circuit 310, and a read/write circuit 365. In some embodiments, the memory cells may be three-dimensional. The memory array 300 can be decoded via a column. The device 330 is addressed by a word line and via a row of decoders 36. The read/write circuit 365 includes a plurality of sensing blocks 400 and allows a page of memory to be read or programmed in parallel. A controller 35 is typically included in a memory device 296 (e.g., a removable memory card) that is identical to one or more memory die 298. Commands and data are routed through line 32. Transfer between the host and controller 350, and via line 318 to control

120932.doc -18 · 1335596 Transfer between the controller and one or more memory dies 298. Control circuit 310 cooperates with read/write circuit 365 to perform memory operations with respect to memory array 300. The control circuit 31 includes a state machine 312, an on-chip address decoder 314, and a power control module 310. The state, machine 312 provides wafer level control of memory operations. The on-chip address decoder 314 provides an address interface between the hardware address used by the host or a memory controller and the hardware address used by the decoders 330 and 360. The power φ rate control module 3 16 controls the power and voltage supplied to the word lines and bit lines during memory operation. In some embodiments, some of the components of FIG. 5 can be combined. In various settings. In the tenth, one or more components (single or combined) of the memory cell array 3 图 in FIG. 5 can be regarded as a management circuit. For example, one or more of the management circuits can include any one or combination of the following: control circuit 310, state machine 312, decoder 314/36, power control module 316, sensing block 400, reading / Write circuit 365, controller 35 〇. • FIG. 6 illustrates another configuration of the memory device 296 illustrated in FIG. 5. Access to the memory array 300 by various peripheral circuits is implemented in a symmetrical manner at opposite sides of the array such that the density of access lines and circuits on each side is reduced by a factor of two. Therefore, the column decoder is divided into column decoders 33a and 330] 8' and the row decoder is divided into 360 and 3608. Similarly, the s sell/write circuit is divided into a read/write circuit 365A (which is connected from the bottom of the memory array 300 to the bit line) and a read/write circuit 365B (which is from the top of the memory array). Connected to the bit line) In this way, the density of the read/write module is substantially reduced by a factor of two. The apparatus of Figure 6 can also include a controller, such as 120932.doc • 19· 1335596, with the apparatus of Figure 5 as described above. FIG. 7 is a block diagram of an individual sensing block, which is divided into a core portion (referred to as sensing module 380) and a common portion 390. In one embodiment, there is a separate sensing module 380 for each bit line and a common portion 390 for a plurality of sensing modules 38. In one example, a sensing block will include a common portion 39A and eight sensing modules 380. Each sensing module in a group will be in communication with an associated common portion via a data bus 372. For more information, please refer to US Patent Application No. 11/026,536, filed on December 29, 2004, "Non-Volatile Memory & Method with

Shared Processing for an Aggregate of Sense Amplifiers"> The entire content of this application is incorporated herein by reference. The sensing module 380 includes a sensing circuit 37A that determines whether a conduction current in a line 70 of the connected bit is above or below a predetermined threshold level. Sensing module 380 also includes a one-bit line latch 382 for setting voltage conditions on the connected bit line. For example, a predetermined state latched in bit line latch 382 will cause the connected bit line to be pulled to a specified stylized inhibit state (e.g., Vdd). The same portion of the processor 392, a set of data latches 394, and a "face 396 between the set of data latches 394 and the data bus 32'. Processor 392 performs the operations. For example, the processor does this by determining the data stored in the sensed memory unit and storing the data of the soil determination in the set of data latches. Group information

I20932.doc -20. Latch l § 394 is used to store the data bits determined by processor 392 during a read operation. The set of data latches is also used to store data bits that are imported from the data bus 320 during the stylizing operation. The imported data bit table indicates the written data to be programmed into the memory. The 1/〇 interface 396 provides an interface between the data latch 394 and the data bus 32〇. During the reading and sensing period, the operation of the system is under the control of the state machine M2. The state machine controls the control and the voltage of the pole to the address memory unit. As the various predefined control gate voltages corresponding to the various memory states supported by the memory are progressively passed, the sensing module 380 can sense their voltages - and will sense the data via the data bus. The modulo, and 380 provides - output to the processor 392. At this time, the processor determines the obtained memory state by considering the sensing event of the sensing module and the information about the applied control gate from the state machine via the input line. The 2' processor computes the binary encoding of the memory state and stores the resulting data bits in the data latch 394. In another reckless embodiment of the core portion, the 'bit 70-line latch 382 has a dual purpose as a latch for latching the output of the sense module 380 and also as described above. Meta line latch. • Some implementations will include multiple processors 392. In a particular embodiment, each processor 392 will include an _output line (not shown in Figure 7) such that each output line is wired 〇R together. In some embodiments, the rounds are reversed prior to being connected to the wired-OR line. This configuration enables the rapid determination of the time during which the stylization process has been completed during the stylization verification process. This is because the state machine receiving the wired.OR can determine 120932.doc 21 1335596 All the bits being programmed have reached the desired level. Level. For example, when every bit has reached its desired level, the bit is logically developed to the Wlred-〇R line (or a data "!" is inverted). When the bit outputs a data "〇" (or a data "1" is reversed), the state machine knows to terminate the stylization process. Because each processor communicates with eight sensing modules, the device must read the wired-OR line eight times, or will accumulate the associated bits: the logic of the result of the line is added to the processor 392, Make the state machine only need to read

Line once. Similarly, by properly selecting the logic level, the global state machine can detect when the first bit changes its state and changes the algorithm accordingly. During the stylization or verification, the data to be programmed from the data bus 32 is stored in the data latch 394. Under the control of the state machine, the stylization operation includes a staging voltage pulse applied to the control gate of the addressed memory unit. After each stylized pulse - read back (verify) to determine if the memory cell has been programmed to the desired memory state. The processor 392 monitors the read back memory state relative to the desired memory state. When the two memory states are the same, the processor 392 sets the bit line latch 382 to cause the bit line to be pulled to a specified stylized inhibit state. This prohibits further programming of the memory unit coupled to the bit line even if a stylized pulse appears on the control gate of the memory unit. In other embodiments, during the verification process, the processor loads bit line latch 382 at the beginning and the sensing circuit sets it to a disable value. The data latch stack 394 includes a stack corresponding to the sensing module 120932.doc -22- 1335596

Material latch. In one embodiment, each sensing module 380 has three data latches. In some embodiments, but not necessarily, the data latch is implemented as a shift register such that the parallel data stored therein is converted to the serial data for the data bus 320 and vice versa. In a preferred embodiment, all of the data latches corresponding to the read/write blocks of the m memory cells can be linked together to form a block shift register so that A block transfer is used to input or output a block of data. Specifically, the bank containing r read/write modules is adapted such that each of the group of data latches sequentially moves data into or out of the data bus as if it belonged to a bank. A component of the shift register for the entire read/write block.

For additional information on the structure and/or operation of the specific embodiments of the non-volatile storage device, see: (1) U.S. Patent Application Publication No. 2004/0057287, issued March 25, 2004, entitled "Non-Volatile Memory And Method with Improved Sensing" (2) US Patent Application Publication No. 2004/0109357, published on June 10, 2004, entitled "Non-Volatile Memory And Method with Improved Sensing" (3) Inventor Raul-Adrian Cernea, U.S. Patent Application Serial No. 11/015,199, filed on December 16, 2004, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation"; (4) Inventor US Patent Application No. 11/099, 133, filed on Apr. 5, 2005, entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory"; and (5) Inventors Siu Lung Chan and Raul-Adrian 120932.doc -23- 1335596

U.S. Patent Application Serial No. 11/321,953, filed on December 28, 2005, to "Reference sense Amplifier For Nonvolatile Memory". The entire contents of the five patent documents listed above are incorporated herein by reference. Referring to Figure 7A, an exemplary structure of memory cell array 302 is illustrated. As an example, a NAND flash s memory that is divided into 丨, 〇 24 blocks is described. Other sized arrays can also be used. You can erase the data stored in each block at the same time. In a specific embodiment, the block is the smallest unit of the suffix unit that is simultaneously erased. In this example, each block includes 8,512 lines corresponding to the bit lines B1, BL1, ..., BL85 11. In one embodiment, all of the bit lines of a block can be selected simultaneously during read operations and stylized operations. Memory cells along a common word line and connected to any bit line can be programmed simultaneously. In another implementation, the bit line (4) is divided into odd-numbered lines and even-numbered lines of 70 lines. In an odd/even bit line architecture, a memory unit along a common spring line connected to an odd bit line is programmed once, and a memory along the common word line and connected to the even bit line The unit performs another stylization. Figure 7A illustrates four memory banks connected in series to form a NAND string. Although shown, four memory cells are included in each __NAND string, and = four or more memory cells can be used. (For example, a terminal of Μ, 或 or other number of NAND strings is connected to the corresponding bit line via the "and pole selection idle pole (which is connected to the selection gate and the pole line SGD) and the other terminal is via a source selection pole (which is connected to the selection

120932.doc -24- S 1335596 Gate source line SGS) and connected to the common source line. Figure 8 is a flow chart showing one embodiment of a method for staging a stylized non-volatile memory. In one embodiment, the sibling unit (in blocks or other units) is erased prior to stylization. At step 40 of Figure 8, the "bedding load" command is issued by the controller and received by control circuit 310. In step 4〇2, the address data of the specified page address is input to the decoder 314 from the controller or the host. In step 4〇4, a page of stylized data on the addressed page is entered into the data buffer for programmaticization. The > material is latched in the appropriate set of latches. In step 4〇6, a "stylized" command is issued by the controller to state machine 312. By triggering the "programming" command, the step applied to the appropriate word line as shown in Figure 9 is used. The pulse is controlled by the state machine 3 12 to program the data latched in step 4〇4 into the selected memory unit. In step 4〇8, the programmed voltage Vpgm is initialized to the start pulse (eg, 12 volts or other value) 'and a stylized counter pc maintained by state machine 312 is initialized to 0. At step 410, a first ¥1) 2111 pulse is applied to the selected word line. If stored in a special data The latched H-tape logic "〇" indicates that the corresponding memory cell should be stylized, and the corresponding bit line is grounded. On the other hand, if the logic stored in a particular latch is "丨, Indicates that the corresponding memory unit should maintain its existing data state, and the corresponding bit line is connected to Vdd to prohibit stylization. In step 412, different voltages are used for the word lines to verify the shape of the selected memory cell, which is different from the voltage to the control gate of the memory cell of a NAND string. Detailed details of the verification recovery process are provided below. If 120932.doc •25-1335596 cross-measures - the target threshold voltage of the selected memory unit has reached the appropriate level' then the data stored in the corresponding data latch is changed to logic "1". If it is detected that the target threshold voltage has not reached the proper position, the data stored in the corresponding data latch is not changed. In this manner, the bit of the logical τ is stored in the corresponding data latch. Lines do not need to be stylized. When all data latches are storing logic "", the state machine (via the wired_0R type mechanism described above) knows that all selected memory cells have been programmed. At step 414' check if all data latches are storing logic "丨". If so, since all selected memory cells have been programmed and verified, the stylization process is completed and becomes #. In step 416, report "pass" (PASS) status. In a specific embodiment, the verification of step 4 12 includes providing one or more voltages different from the voltages supplied to the other non-selected memory cells to the memory adjacent to the memory cells being programmed. unit. For example, if the s-resonant cell located on word line WLn is being programmed, the voltage applied to the memory cell on word line WLn+1 will be different than the voltage applied to the non-selected word line. This compensation will be discussed in more detail below with reference to FIG. At step 414, if it is determined that not all of the data latches are storing logic "1", the stylization process continues. At step 418, the stylized limit value PCMAX is compared to check the stylized counter Pc. An example has a program limit of 20; however, other values can be used. If the stylized counter PC is not less than 20, the stylization process has failed and the "Failure" status is reported in step 42. If the stylized counter pC is less than 2 〇, the Vpgm level is incremented by the step size, and the stylized count 120932.doc • 26· is accumulated at step 422 (eg, left and right, more than two groups, etc. ). Figure H) illustrates various sequences during the verification process - for example, if the memory unit is a binary memory unit, the process of Figure 1Q can be performed during the delivery of step 412. If the ticker unit has multiple state units of four states (e.g., 'e, a, b, and C), then the process of Figure 10 is performed three times during the iteration of step 412. - Generally speaking, during a read and verify operation, the selected word line is connected to a voltage, and the level of the voltage is specified for each read and verify operation to determine the threshold voltage of the memory cell involved Has it reached this position? If the word line voltage is applied, the voltage applied to the word line is responded to, and the conduction current of the memory unit is measured to determine whether the memory unit is turned on. If the measured current is greater than a certain i, the memory unit is turned on. And the voltage applied to the word line is greater than the threshold voltage of the memory unit. If the measured conduction current is not greater than the predetermined value, it is assumed that the memory unit is not turned on, and the voltage applied to the word line is not greater than the memory unit. Threshold voltage. There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of the memory cell is measured in accordance with the discharge or charge rate of a dedicated capacitor in the sense amplifier. In one embodiment, a memory array that is threaded using all of the bits can measure the conduction current of the memory cells in accordance with the discharge or charge rate of a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or cannot allow) the NAND string 120932.doc -28 - 1335596 charging rate of the memory cell to measure the conduction current of the memory cell. First, the behavior of the sensing circuit and the memory cell array involving measuring the conduction current of the memory cell by determining whether the bit line has been discharged will be discussed with reference to SGS (B), Selected BL (B), and BLCLAMP (B). . At time t1 of FIG. 10, SGD rises to Vdd (eg, about 3.5 volts), unselected word line WL_unsel_S rises to Vrdl (eg, about 5.5 volts), unselected word line WL_unsel_D rises to Vrd2, bungee The side adjacent word line WLn+Ι rises to VrdX, the selected word line WLn rises to the verify level Vcgv for verify operation (eg, Vva, Vvb or Vvc of FIG. 11), and BLCLAMP (B) rises to a precharge The voltage is precharged with the selected bit line Selected BL(B) (eg, about 0.7 volts). The voltages Vrd1, Vrd2, and VrdX act as pass voltages because the two voltages cause the non-selected memory cells to turn on and act as pass gates. In a specific embodiment, the Vrd2 is about 2.5 to 4 volts less than Vrdl; however, in other embodiments, other values that are lower than Vrdl or higher than Vrdl can also be used for Vrd2. In some embodiments, VrdX is equal to or slightly less than Vrd 1. In some embodiments, VrdX is greater than Vrd2 and less than Vrdl (e.g., about 2.4 to 3 volts less than Vrd 1) to accommodate the data dependent read process described below. Vrd2 less than Vrd 1 is applied to compensate for the back-type effect described above. At time t2, BLCLAMP (B) is lowered to Vss so that the NAND string can control the bit line. Furthermore, at time t2, the source side selection gate is turned on by raising SGS (B) to vdd. This provides a path that consumes the charge on the bit line. If the threshold voltage of the memory cell selected for reading is greater than Vcgr or the verify level applied to the selected word line WLn, then the selected memory 〆120932.doc •30. 1335596 body unit is not turned on and The bit line is not discharged, as indicated by signal line 450. If the threshold voltage of the memory cell selected for reading is lower than Vcgr or lower than the verify level applied to the selected word line WLn, the memory cell selected for reading is turned on (conducted) And the bit line voltage will be consumed as shown by curve 452. At time t2 and at some point prior to time t3 (determined by a particular implementation), the sense amplifier will determine if the bit line has been consumed by a sufficient amount. Between times t2 and t3, BLCLAMP (B) rises to allow the sense amplifier to measure the evaluated bit line voltage and then decrease, as shown in Figure 1A. The signal depicted at time t3' will be reduced to Vss (or another value for standby or recovery). ^ Note that in other embodiments, the timing of some signals may be changed (eg, to apply the neighbors) Signal offset).

Next, reference will be made to SGS (C), Selected BL (C) and BLCLAMP (C) to describe the sensing circuit and memory involved in measuring the conduction current of the memory cell according to the discharge or charging rate of a dedicated capacitor in the sense amplifier. The behavior of the cell array. At time t1 of FIG. 10, SGD rises to Vdd (eg, 'about 3.5 volts'), and the non-selected word lines WL_imsel_S rise to Vrd1, the non-selected word lines WL_unsel_D rise to Vrd2, and the non-selective side adjacent word lines WLn +Ι rises to VrdX 'The selected word line WLn rises to Vcgv for verify operation (eg 'Vva, Vvb or Vvc of Figure 11'), and BLCLAMP (B) rises. In this case, the 'sense amplifier keeps the bit line voltage constant, regardless of the ongoing operation of the NAND string, so that the sense amplifier measures the flow in the case of the bit line "clamp" Current. Therefore, BLCLAMP (C) rises at time t1 and does not change from time t1 to time t3. At a time point after time t1 and before time t3 (as determined by the specific implementation of 120932.doc -31 1335596), the sense amplifier will determine if the capacitor in the sense amplifier has been consumed or charged a sufficient amount. At time t3, the signal drawn will be reduced to Vss (or another value for standby or recovery). Please note that in other embodiments, the timing of some signals can be changed. The read operation is performed in the same manner as described above with respect to Figure 10 except for the following items: applying Vcgr (eg, Vra, Vrb, or Vrc of Figure 11) to WLn, the non-selected word lines (except for 汲The top side adjacent word line will receive Vread (Vread = Vrdl), and the drain side adjacent word line will receive the read voltage dependent on the data described below. Figure 10A illustrates a NAND string and a set of voltages applied to the NAND string during the verify operation shown in Figure 10. The NAND string of FIG. 10A includes eight memory cells 464, 466, 468, 470, 472, 474, 476, and 478 °. Each of the eight memory cells includes a floating gate (FG) and a control gate. (CG). A source/drain region 490 is interposed between each of the floating gates. In some embodiments, there is a P-type substrate (e.g., germanium), an N-well in the substrate, and a P-well in the N-well (not shown in the drawings to make the drawing easier to read). Note that the P-well can include a channel implant, which is typically a P-type implant to determine or help determine the threshold voltage and other characteristics of the memory cell. The source/drain region 490 is formed in an N+ diffusion region in the P well. A gate side selection gate 384 is provided at one end of the NAND string. The drain side select gate 324 connects the NAND string to the corresponding bit line via bit line contact 494. A source select gate 482 is provided at the other end of the NAND string. The source select gate 482 connects the NAND string to the common source line 492. During the verify operation, the selected memory unit 470 receives the verify comparison 120932.doc -32 - 1335596 voltage Vcgv. The non-selected memory cells 464, 466, and 468 located on the source side of the selected memory cell 470 receive Vrdl at their control gates. Since the NAND string of Figure 10A was last erased, memory cells 464, 466, and 468 have undergone one or more stylization processes, potentially resulting in stylizing one or more pages of data stored in their memory cells. . The non-selected memory cells 474, 476 and 478 located on the drain side of the selected memory cell 470 receive Vrd2 at their control gates. In a specific embodiment, the non-selected memory cells 474, 476, and 478 have not experienced one or more stylization processes since the last time the NAND string of FIG. 10A was erased, and thus the non-selected word lines Still in an erased state, this potentially causes one or more pages of data to be stored in their memory cells. Note that receiving Vrdl or Vrd2 is not an act of a stylized process. The drain side adjacent memory unit 472 receives VrdX. Since the NAND string of Figure 10A was last erased, memory cells 472, 474, 476, and 478 have undergone one or more stylization processes, potentially causing one or more of the memory cells to be programmed in their memory cells. Page information. That is, when the verify operation is performed on the memory unit 470, the non-selected memory cells 464, 466, and 468 located on the source side of the selected memory cell 470 may be in state E, A, B, or C. (See Figures 11 through 13). On the other hand, the non-selected memory cells 472, 474, 476 and 478 located on the drain side of the selected memory cell 470 will be in an erased state E (see Figures 11 through 13). The reason that the memory cells 464, 466, and 468 are referred to as being located on the source side of the selected memory cell 470 is that their memory cells are located on the same NAND string as the selected memory cell 470 and are located at the same source. The gate 120932.doc -33 - 1335596 is selected on the same side of the selected memory cell 470 of the pole 482. Although Fig. 1 shows that there are two memory cells on the source side, but one or more memory cells are on the source side. The reason that the memory cells 472, 474, 476, and 478 are referred to as being located on the drain side of the selected memory cell 470 is that their memory cells are located on the same NAND string as the selected memory cell 470 and are located at the same The same side of the selected memory cell 47 of the gate 484 is selected on the drain side. Although FIG. 10A shows four memory cells on the drain side, on the far side

There may be one or more memory cells, or there may be two or more memory cells on the drain side. Figure 10B illustrates the NAND string and a set of voltages applied to the NAND string during a read operation. During the read operation, selected memory cell 47 receives the read compare voltage Vcgr - non-selected memory cells 464, 466, 468, 472, 474 and 476 receive Vread at their control gates. In a specific embodiment, Vread = Vrdl. The drain side proximity memory unit 472 receives VreadX at its control gate.

Figure 10C is a flow chart showing a specific embodiment of the process of programming and reading. In many applications, all word lines of a block are programmed. After this stylization, all data or subsets of data can be read one or more times. In some embodiments, the word lines are programmed from the source side to the bottom side. For example, in step 5, the memory cells connected to a first word line (e.g., 'WLO; see Figure 7A) are programmed. At step 502, the memory unit connected to a second word line (e.g., WLi) is programmed. At step 504, the memory cells connected to a third word line are programmed. And so on, until in step 5〇6, the stylization is connected to the last word 120932.doc 34-1335596 for example? The memory unit of the closed-end word line is selected on the adjacent side. In other embodiments, other stylized passes may be used and used, including the stylized sequence of selecting the closed pole from the source side to the non-polar side. After programming all of the word lines, any one or more of the memory cells associated with the blocks of the word lines can be read. Consider an example of a digital camera that stores a set of images. It is very likely that the pictures are stored across multiple blocks, so that all word lines are programmed first after any read operation. Note that other operational sequences than those shown in Figure 1GC can be implemented. Each word line can go through - or multiple stylizations. For example, a word line can be associated with multiple pages of information. Each stylization process can be used for different pages. That is, the process of Fig. 8 is carried out for each page f material. For example, each of steps 500 through 506 can include multiple stylization processes. In other embodiments, all of the page material associated with a word line can be programmatically together' or a word line can be associated with only one page of material. In one embodiment, the voltage Vrdx depends on the number of unselected word lines that have not yet undergone a stylization process. In a specific embodiment programmed from the source side to the drain side, VrdX is determined by the number of unselected word lines on the drain side of the selected word line. When considering NAND strings or other suitable groups, the value of VrdX is determined using the number of non-selected memories located on the drain side of the selected memory cell. For example, if there is a non-selected word line on the drain side of the selected memory cell, then VrdX=Vrdl-l(X), where X is equal to a small voltage in the range of 0.1 to 0.4 volts, which It is selected according to the simulation and device characteristics. If there are two unselected word lines on the drain side of the selected memory cell, then VrdX = Vrdl - 2(X). If there are three unselected word lines on the drain side of the selected memory 120932.doc -35 - 1335596, then Vrdx = Vrdl_3(x), and so on. Other formulas or mechanisms can also be used. 1DD is a flow chart for describing a method for selecting an appropriate level of Vrdx in accordance with an embodiment in which voltage Vrdx is dependent on non-selected memories located on the drain side of the selected memory cell. The number of body units. In an exemplary embodiment, step 404 of FIG. 1D is performed after step 402 of FIG. 8 and prior to step 4〇4. At step 402A, the block and word line associated with the page address are identified. At step 402B, it is determined that the word line that has not been programmed in the block identified in step 4〇2A is selected in step 4〇2C according to the number of non-selected word lines located on the drain side of the selected word line. The voltage VrdX of the word line is adjacent to the drain side of the selected word line. If applicable, at the end of the successful stylization procedure, the threshold voltage of the memory unit shall be within one or more threshold voltage distributions of the programmed memory unit or a threshold voltage of the erased memory unit Within the distribution. Figure 1 shows an exemplary threshold voltage distribution of a memory cell array when each suffix unit stores two bits of data. Figure U shows the first threshold voltage of the erased memory cell. Distribution E. Stylized memory unit

The three threshold voltage distributions A, B, and Ce. In one embodiment, the threshold voltage of the E distribution + is negative, and the threshold voltage in the A, B*c distribution is positive. Each of the distinct threshold voltage ranges of Figure 11 corresponds to a predetermined value for each set of data bits. The specific relationship between the data programmed in the memory unit and the threshold voltage level of the memory unit depends on the data encoding scheme used by the memory unit. For example, the US patent case =

120932.doc -36- Into S 1335596 6'222,762 and U.S. Patent Application Serial No. 1/461,244, "Tracking Cells For A Memory System" Incorporating herein by reference) describes various data encoding schemes for multi-state flash memory cells. In a specific embodiment, a Gray code assignment is used to assign data values to the threshold voltage ranges such that if a threshold voltage of a floating gate is erroneously shifted to its neighboring physical state ' Then only one bit will be affected. An example of the heart '11' to the limit of electricity waste range E (state E); assign "丨〇" to the threshold voltage range A (state A); assign "〇〇" to the threshold voltage range b (state b); and assign "01" to the threshold voltage range C (state c). However, in other embodiments, the Gray code is not used. Although four states are illustrated, the present invention can also be applied in conjunction with other multi-state structures, including multi-state structures having four or more states. Figure 11 also shows three read reference voltages vra, Vrb and Vrc for reading data from the memory unit. By testing whether the threshold voltage of a given memory cell is less than or below Vra, Vrb, and Vrc, the system can determine the state of the memory cell. FIG. 11 also shows three verification reference voltages Vva, vvb, and Vvc. When the memory unit is programmed to state A, the system will test if the memory unit has a threshold voltage greater than or equal to Vva. When the memory unit is programmed to state B, the system will test if the memory unit has a threshold voltage greater than or equal to Vvb. When the memory unit is programmed to state c, the system will determine if the memory unit has a threshold voltage greater than or equal to Vvc 〇 120932.doc • 37· £ 1335596. In one embodiment, the full sequence is called Stylized to directly program the memory cells from the erased state E to any of the programmed states A, B, or C. For example, a population of memory cells to be programmed can be erased first so that all memory cells in the population are in an erased state. Next, the process shown in Figure 18 (using the control gate voltage sequence shown in Figure 9) is used to program the memory cells directly to state A, B or C. When some memory cells are being programmed from state E to state A, other memory cells are being programmed from state E to state 8 and/or from state E to state c. Compared to the voltage change on the floating gate under WLn when staging from state E to state A or from state E to state b on wLn, when staging from state E to state c on WLn The amount of charge change on the floating gate under WLn is the largest, so the parasitic coupling amount to the adjacent floating gate under WLn-Ι is the largest. The coupling amount from the state to the state B to the adjacent floating gate decreases, but is still significant. When staging from state E to state a, the coupling to the adjacent floating gate is even further reduced. Accordingly, the amount of correction required to subsequently read each state of WLn will vary depending on the state of the adjacent memory cells on WLn. Figure 12 illustrates an example of a two-pass technique for a stylized multi-state memory unit that stores data for two different pages (a lower page and an upper page). The figure shows four states: state E (1丨), state A (10), state B (00), and state C (〇1). For state E, the two pages are stored 1 . For state A, the lower page stores "〇" and the upper page stores "1" ^ for state B, and the two pages store "〇·’. For state c, the lower page stores "丨" and the upper page stores "0". Note that although a particular bit pattern has been assigned 120932.doc -38 - 1335596 to each state, different bit patterns can be assigned. In the first stylization process, # is set to the bit in the lower logical page to set the threshold voltage level of the memory unit. If the bit is a logical "", 贝, ! is in the proper state because it was erased earlier: so the threshold voltage is not changed. However, if the bit to be programmed is a logic then the memory The threshold voltage level of the unit is increased to state A as shown by arrow 530. This causes the first stylization process to terminate. In the second stylization process

Sets the threshold voltage level of the memory unit according to the bit being programmed into the upper logical page. If the upper logical page bit is stored - logical 'be, since the memory cell is in state E or A (depending on the stylization of the lower page bit), the two are

The state contains the upper page bit "", the user is not programmed. If the upper page bit logic "0" ', the threshold voltage is offset. If the first process causes the memory unit Maintained in the erased state E, then in the second phase, the s-resonant unit is programmed such that the threshold voltage is increased to the state C range, as indicated by arrow 534. If the first stylization process results The memory unit has been programmed into state A, and the memory unit is further programmed in the second process such that the threshold voltage is increased to the state B range as shown by arrow 532. The result of the second process is The memory unit is programmed into a data that is designated to cause the upper page to store the logic " and the lower page has not been changed. In Figures 11 and 12, the sway gate to the adjacent bit line The amount of coupling depends on the final state. In a specific embodiment, when a full page of data is filled, 'a system can be set up if the write is sufficient to perform a full sequence of writes. If the data is insufficient to 120932.doc

*: S -39· 1335596 When writing a full page, the stylization process can use the received data to program the next page. When receiving subsequent data, the system will then program the upper page. In another embodiment, the system can begin writing in the mode of the programmed lower page, and if sufficient data is subsequently received, transition to full sequence stylized mode to fill an entire (or large Most) memory cells of the word line. For more information on this specific example, please refer to the inventor.

Sergy Anatolievich Gorobets and Yan Li, U.S. Patent Application Serial No. 11/13,125, filed on December 14, 2004, is entitled "pipenned Programming 〇f Non-Volatile Memories Using Early Data, the entire contents of which are incorporated by reference. Incorporating herein. Figures 13A-C disclose another process for staging non-volatile memory that reduces the effect of floating gate-to-floating gate coupling by: for any particular memory cell, After writing to a previous page of an adjacent memory cell, for a particular page written to that particular memory cell. In an example of an embodiment taught by Figures 13A-C, the non-volatile memory cell is used Four data states store two bits of data per memory unit. For example, assume state E is erased, and states A, B, and C are stylized. State E stores data. a Store data 01. State B stores data 1 (^ status ^ stored data 〇〇. This is an example of a non-Gray code, because the two bits are changed between adjacent states A & B. Other data can be used to the physical data state coding method. Each memory unit stores two pages of data. For reference purposes, their pages will be referred to as the upper page and the lower page; however, other titles may be given. State a of the process of 13A-C, the upper page stores the bit 〇 and the lower 120932.doc -40· 1335596 The page stores the bit 1 » With regard to state B, the upper page stores the bit 丨 and the lower page stores the bit 0. State C 'The two pages store the bit data. Figure 13 The stylized process of AC is a two-stage process. In the first step, the lower page is programmed. If the lower page maintains data 1, the memory unit The state is maintained in state E. If the data is to be stylized as 〇, the threshold voltage of the memory cell is raised, causing the memory cell to be programmed to state B'. Thus, Figure 13A depicts the memory cell from State E is stylized to state B. State B depicted in Figure 13A is transition state B; therefore, the verification point is depicted as Vvb, which is lower than Vvb. In a specific embodiment, the memory unit is State £ program After the state B., then, the page below the adjacent memory cell (WLn+Ι) in the nand string will be stylized. For example, please refer back to Figure 2, in the stylized § memory unit 1 After the lower page of 〇6, the lower page of the memory unit 104 will be programmed. After the stylized memory unit 〇4, if the threshold voltage of the memory unit 104 rises from the state e to the state B, the floating gate The pole-to-floating gate coupling effect will cause the apparent threshold voltage of the memory cells 1〇6 to rise. This will have the effect of widening the threshold voltage distribution of state B to the threshold voltage distribution 550 as depicted in Figure 13B. When the upper page is programmed, the apparent width of the threshold voltage distribution is remedied. Figure 13C depicts the process of stylizing the upper page. If the memory cell is in the erased state E and the upper page is maintained at 丨, the memory cell will remain in state E. If the memory cell is in state E and the upper page is to be programmed to zero, then the threshold voltage of the 5th memory early will rise, causing the memory cell to be in state A. If the memory cell is in the middle threshold voltage distribution 120932.doc -41 - .(s:> 1335596 5 5 0 and the upper page is maintained at 1 A ) 6 the memory cell will be programmed to the final state B If the memory unit 1 is in the middle threshold voltage distribution 550 and the upper page is to become the data 〇, then the threshold voltage of the body 11 will rise, causing the memory unit to be in the skin r - Figure 13A-C The process of poetry reduces the floating gate-to-floating gate coupling effect, because only the upper page of the memory cell stylizes the apparent threshold voltage of the β 疋 memory cell in the w. An example of an alternative state code is the case. When the upper page data is 1, then

The distribution 5 5 0 moves to the state c; and the μ μ plus π — when the field is 0 贫 poor material system 0, then moves to the state Β. Although FIGS. 13A-C provide an example of a data condition and two pages of data, the concept of "η Γ · 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Or less than four data states and implementations that differ from the two pages. 14A-F are diagrams for describing the stylized order of the method ’ shown in Figures u, 12, and 13A-C, in accordance with various embodiments. Figure 14A is a diagram depicting the sequence of staging memory elements along the bit line for all bits. In this embodiment, the block containing four word lines includes four pages (page G_3). The page 〇 is written first, then page 1 is written, then page 2' is written and then page 3 is written. The material in the page 包括 includes the data stored by all the memory cells connected to the word line WL0'. The information in page 1 includes the data stored by the memory unit connected to the word line. The data in page 2 includes the data stored by the memory Z element connected to word line WL2. The information in page 3 includes the data stored by the memory unit connected to the word line. The particular embodiment of Figure 14A employs a full sequence as described above with respect to Figure 11. 120932.doc -42· 1335596 Body Architecture The stylized sequence of the two-stage stylization process according to Figure 12. A block containing four word lines consists of 16 pages, the number of which is programmed in the numerical order of pages (from page 0 to page 15). For the memory cells connected to the even bit lines of the word line w1 ,, the lower page material forms a page and the upper page data forms page 2. For the memory cell unit lower page data forming page 1 connected to the odd bit line of the word line WL0 and the upper page material forming page for the memory cell connected to the even bit line on the word line WL1, the lower page forms page 4 and The upper page forms page 6. The page 5 is formed for the lower page of the memory cell unit connected to the odd bit line of the word line WL, and the upper page forms the page 7. For memory cells connected to even bit lines on word line WL2, the lower page forms page 8 and the upper page forms page 1 〇. For the memory cells connected to the odd bit lines of the word line wl2, the lower page forms page 9 and the upper page forms page 11. For the memory cell unit connected to the even-numbered bit line of the word line WL3, the lower page forms the page 12 and the upper page forms the page 14^ for the memory cell connected to the odd-numbered bit line of the word line WL3, the lower page forms the page I) And the last four pages form page 15. Alternatively, as in the figure me, the upper and lower pages under each word line of the even-numbered 7L line are first programmed, and then the two pages of the odd-numbered bit lines of the same word line are programmed. Figures 14F and 14G depict the sequence of stylizing memory cells using the stylized methods of Figures 13A-C. Figure 14f is an architecture for performing all bit threading. For a memory cell connected to word line WL0, the lower page forms a page and the upper page forms page 2. For the memory cell connected to the word line WL1, the lower page forms page 1 and the upper page forms page 4. For the memory unit connected to the word line WL2, the lower page forms page 3 and the upper page forms page 6. For the connection 120932.doc -44- 1335596 material data are written together with their ECC bits. ECc technology is a technology well known in the art. The ECC process used may include any suitable ECC process known in the art. When reading data from a page, the ECCMa element is used to determine if there are any errors in the data (step 6〇2). The ECC process can be performed by a controller, a state machine, or other device in the system. If there is no error in the material, the data is reported to the user at step 604. For example, the data is communicated to the controller or host via data I/O line 320. If an error is found at step 602, it is determined if the error is correctable (step 606). This error may be due to floating gate to floating gate coupling effects or other reasons. Various ECC methods have the ability to correct a predetermined number of errors in a set of data. If the ECC process can correct the material, the ECC process is used to correct the data at step 608, and the modified data is reported to the user at step 61. If the error cannot be corrected by the ECC process, then a data recovery process is performed in step 620. In some embodiments, an ECC process will be performed after step 620. More detailed details on the data recovery process are provided below. After restoring the data, the data is reported in step 622. Note that the process of Figure 15 can be used in conjunction with the use of all bit threading or odd/even bit threading to program the data. Figure 16 is a flow chart depicting a particular embodiment of a process for performing a read operation for a page (see step 600 of Figure 15). The process of Figure 16 can be performed for - page where one page covers all bit lines of a block, only odd bit lines of a block, only even bit lines of a block, or other bits of a block Line subset. At step 640, the read reference voltage Vra is applied to 12 〇 932.doc • 47· 1335596 associated word line associated with the page. At step 642, a bit line associated with the page is sensed to determine whether the addressed memory cell is turned "on" or "off" depending on the application of Vra to the control closed end of the addressed memory cell. The conductive bit lines indicate that the memory cells are turned on; therefore, the threshold voltage of their memory cells is lower than Vra (e.g., in state E). At step 644, the sensed result of the bit line is stored in the appropriate latch for their bit line. At step 646, the read reference voltage Vrb is applied to the word line associated with the page being read. . At step 648, the bit line is sensed as described above. At step 650, the results are stored in the appropriate latches for their bit lines. At step 652, the read reference voltage Vrc is applied to the word line associated with the page. At step 654, the bit line is sensed to determine the open memory unit, as described above. At step 656, the results from the sensing step are stored in the appropriate latches for their bit lines. At step 658, the data value for each bit line is determined. For example, if the memory cell is traversed by Vra' then the s-resonant cell is in state e. If the memory cell is conducting at Vrb and Vix (rather than Vra), then the memory cell is in state a. If the memory single TL is conducted in Vrc (rather than Vra and Vrb), the memory cell is in state B. If the memory cell does not conduct under Vra, Vrb, and Vrc, then the s-resonant cell is in state C. In one embodiment, processor 392 determines the data value. At step 660, for each bit το line, processor 392 stores the determined data value in the appropriate latch. In other embodiments, various levels of sensing (Vra, Vrb, and may occur in different orders. Steps 640 through 644 include performing Vcgr=Vra and VreadX=Vread to perform Figure 120932.doc • 48· 1335596 ι〇 The operations of steps 646 to 650 include performing the operations shown in FIG. 10 with vcgr=vrb and vreadx=Vread. Steps...to... include performing the operations shown in FIG. 1 at vcgr=Vrc and Vreadx=Vread. The process embodiment of Figure 16 does not include performing any compensation for floating gate to floating gate coupling. In another embodiment, steps 64A, 646 and 652 are VreadX equal to Vread4 (described below) or other values. This is illustrated in Figure 17. Figure 17 is a flow chart illustrating a specific embodiment of the process of restoring data (step 62). The data may include an error due to floating gate to floating gate coupling effects (or other reasons). The process of Figure 17 attempts to read the data while compensating for the floating gate to floating gate coupling effect (or other cause of error). Compensation includes: viewing adjacent word lines; and determining how the floating gate has been caused to float The adjacent word lines of the pole coupling effect are programmed. For example, when reading the data on the word line WLn (eg, FIG. 7A2WL2), the process will also read the word line WLn+Ι (eg, FIG. 7AiWL3). Data ° If the data on word line WLn+Ι has caused an apparent change in the data on word line wLn, then the reading process will compensate for this unintended change. The process illustrated in Figure 17 applies to the above described with respect to Figure 11 Full sequence stylized 'two bits of one logical page are stored in each memory unit and will be read and reported together. If the memory cell on the adjacent word line is in state E, then there is no floating gate Extreme to floating gate coupling effect. If the memory cell on the adjacent word line is in state A, there is a small coupling effect. If the memory cell on the adjacent word line is in state B, there is a medium floating gate to floating gate. Coupling effect. If the memory 120932.doc -49-1335596 body element on the adjacent word line is in state c, there is a large floating gate to floating gate coupling effect. The exact coupling effect due to the adjacent word line will be the image. The embodiment differs and can be determined by the characterization device. Step 670 of circle 17 includes performing a read operation on adjacent word line WLn+1. This includes performing the process of Figure 16 on adjacent word lines. For example, if Reading a page in word line WL1, step 67A includes performing the process of Figure 16 on the word line. In step 672, the result of step 67 is stored in the appropriate latch. In some embodiments, The read operation performed by WLn+1 results in the determination of the actual data stored on WLn+1. In other embodiments, the read operation performed on WLn + 导致 results in the determination of the charge WL ' of WLn+1 ± which may or may not accurately reflect the data stored on WLn+1. When the target is to read the data on WLn, it is not necessary to perform ECC correction on the WLn+1i item, because the bit that is erroneously read is most likely to be at the end of the interference, and is determined to be read. In the process of compensating the amount of memory cells corresponding to WLn, misinterpreting the bits that are erroneously read as belonging to another data state does not cause a major error. For example, when WLn+Ι is read in the absence of coupling compensation (step 670 of FIG. 7) as part of the read process of WLn, slightly over-stylized WLn+1 is intended to be programmed to state B. The memory cell, which subsequently undergoes a capacitive coupling effect during the stylization of WLn+2, is now misinterpreted as being in state C. This misreading is not a problem. The reasons are as follows: (1) the target is not reading the data on WLn+Ι; (2) the apparent state of the memory unit on WLn+Ι is in the c state. The correction applied to the reading of the corresponding memory cell on the WLn is actually better than that applied to the memory cell on the WLn+丨 (ie, the shape 120932.doc -50-1335596 state B). Corrected. This is because all the causes (4) of the memory cells on the state are misinterpreted as being in state c (whether or not the memory cells are first programmed or later from the WLn+2 memory cells) And (4) WLn + 丨 memory unit caused by the (four) combined effect and the WLn memory unit experienced the coupling effect. This stronger constraining effect experienced by the memory cell on WLn may actually be better than applying the correction to the WLn+1 memory cell corresponding to state C (rather than state B). An alternative embodiment includes adding a margin to the read voltage during the read of step 67 of Figure 17. This is the reading of step 67.

Coupling correction is performed on the reading of step 670. However, such an I-body embodiment may not perform coupling correction as during the reading of step 670, as described below. At step 674, a read process is performed for the word line of interest WLn. This includes performing the process of Figure 16 with VreadX = Vreadl. In a specific embodiment, Vreadl = Vread (e.g., '5 5 volts or 6 volts, or other suitable value). Therefore, all non-selected word lines are receiving Vread. Since the compensation is determined by the difference between the Vread value used on the WLn+1 during the current t-buy operation and the ¥ substitute value used during the verification phase of the %-form/verification, the maximum compensation is provided. The compensation value 〇〇111{)(: can be defined as follows: c 〇 mpC = Vreadl - VrdX ^ for a memory cell having its neighbor memory unit WLn + Ι determined (in step 67 )) to be in state c The bit το line stores the result of step 674 in the appropriate latch, thus causing the memory cell that has experienced the highest threshold voltage change for its bungee-side neighbor due to being programmed from state E to state c. make up

120932.doc -51· 1335596

CompC. Note that during the stylization/verification of WLn their neighbors are in state E, but are now in state C. In all cases, between the write time of WLn and the current read time of WLn, the state changes experienced by the neighbors on the WLn+Ι on the drain side must be compensated. For the neighbors whose bungee side are currently being detected, the bit line that is not in state C, the read data of this WLn (using Vreadl on WLn+Ι) will be ignored. At step 678, a read process is performed on WLn. During the read process, the drain side adjacent word line WLn+1 will receive Vread2. That is, VreadX = Vread2, where the value of Vread2 is closer to VrdX used during stylization than Vreadl. In a specific embodiment, Vread2 is 4.9 volts. This implementation is suitable for a small amount of compensation for the memory cells of the state B where the bungee side neighbors are now in state B. The compensation amount for an example is compB=Vread2-VrdX. At step 680, the result of step 678 is stored for a bit line having a memory cell whose neighboring memory cell (e.g., WLn+1) is in state B. Information on other bit lines will be ignored. At step 682, a read process is performed on WLn. During the read process, the drain side adjacent word line WLn+1 will receive Vread3. That is, VreadX = Vread3, where Vread3 is closer to VrdX used during stylization than Vread2. In a specific embodiment, Vread3 is 4.3 volts. This implementation is suitable for a smaller amount of compensation for the memory cells of the state A of the state where the bungee side neighbor is now. The compensation amount for an example is compA=Vread3-VrdX. At step 684, the result of step 682 is stored for bit 120932.doc -52 - 1335596 line ' having a memory cell whose neighboring memory cell (e.g., WLn + Ι) is in state A. Information on other bit lines will be ignored. At step 686, a read process is performed on WLn. During the read process, the non-polar side adjacent word line WLn+1 will receive vread4. which is,

VreadX=Vread4, where Vread4 is equal to VrdX used during stylization, or Vrdx is closer to Vread3 (eg, Vread4=3 7. V). This implementation applies to its bungee side neighbors now in state E. There is no compensation for the memory single t1, because their neighbors are in state E during stylization/verification. At step 688, the result of step 686 is stored for a bit line having a memory cell whose neighboring memory unit (e.g., WLn+1) is in state E. Data for other bit lines will be ignored. During the process of Figure 17, adjacent bit lines will receive four voltages; however, each selected memory cell will be read with only one appropriate voltage. In various embodiments, different values of Vreadl, Vread2, Vread3, and Vread4 can be determined based on device characteristics, experiments, and/or simulations. In the foregoing discussion, the process of Figure 17 is used as the recovery step of Figure 15 . The P knife is executed. In another embodiment, the initial read process performed by the user can be used as a response to a read data. For example, after receiving a request to read data in step 598 of Figure 15, the system will perform a read operation in step 6. In this particular embodiment, step 6 is implemented by performing the process of FIG. A particular embodiment of implementing step 6 using the process of Figure 17 may have no additional data recovery step 620, so if an error is uncorrectable, the system will report the error. Figure 18 is a flow diagram showing the process of performing a data recovery process (except for the last 120932.doc -53 - 1335596 word line) for all of the word lines of a block (the method of Figure 17). For example, if there is an x+1 word line, the recovery process can be used for word lines WLO to WLx-1. Since WLx (e.g., the word line closest to the drain) does not have a neighbor that would cause a floating gate-to-floating gate coupling effect after being programmed, it is not necessary to perform the recovery process for the word line. Although FIG. 8 is depicted in a recovery process, in the above, it may be at an individual time and limited to the specific embodiment described in FIG. 15 for all word lines to be sequentially executed, the ECC error of Xi Xizheng, Perform this recovery process on the word line. Can be corrected. Γ group, 砝jti about the full sequence of two bits of the logical page of one of the storage of Figure 11,

When the data is extracted, the process can be slightly modified. For example, when performing a standard read operation (step 6 of Figure 15), reading the lower page would require applying Vra and VrC to the control gate of the memory cell and sensing at the subsequent read point. To determine whether the information on the lower page is in the status E/C (data 1) or status A/B (data 0). Thus, Figure 16 can be modified by performing only steps 640, 642, 644 and steps 652 through 66A for the lower page read. When the reading of the upper page is performed, the read comparison point Vrb is used to determine whether the upper page data is in the state E/A (data 〇 or state b/c (3⁄4 material 0). Therefore, for the upper page read Only steps 8, 650, 658, and 66 执行 are performed to modify the process of Figure 16. In addition, when the data is restored (step 620), the process will perform the process of Figure 19 to restore the data of the lower page 'and perform Figure 20 The process is to restore the data of the upper page. In step 730 of Figure 19, a read operation is performed on the adjacent word line 20932.doc - 54 · 1335596 WLn+1 in accordance with the method of Figure 16. In some embodiments, The read operation performed by WLn+1 results in determining the actual data stored on WLn+1. In other embodiments, the read operation performed on WLn+Ι results in determining the amount of charge (or other condition) on WLn+Ι, It may or may not accurately reflect the data stored on WLn+Ι. The result of the read operation is stored in the appropriate latch at step 732. At step 734, a read process is performed on the word line of interest WLn, It includes applying Vra to WLn and VreadX=Vread4 to perform Figure 16 The data of the bit line is sensed at step 736. The result is stored in the appropriate latch at step 738. In another embodiment of step 734, the read process is performed with VreadX = Vreadl. In a specific embodiment, the VreadX value in step 734 should be the same as the value used during the verification process. At step 740, the read reference voltage Vrc is applied to word line WLn, and is performed with VreadX=Vreadl for the word line of interest WLn. A read operation. In step 742, the data is sensed as described above. At step 744, the result of sensing step 742 is stored for the bit line associated with the neighboring memory cells storing the data of state C. Step 746, applying a read reference voltage Vrc to the word line WLn, and performing a read operation on the word line of interest WLn with VreadX = Vread2 for WLn + 。. At step 948, the data is sensed as described above. At step 950, the result of step 948 is stored for the bit line associated with the neighboring memory cells storing the data of state B. The data for the other bit lines will be discarded. At step 752, the read reference voltage Vrc is applied to word WLn, and to

120932.doc -55-

VreadX = Vread3 is used for WLn+1 to perform a read operation on word line WLn. At step 754, the data is sensed as described above. At step 756, the result of step 754 is stored for the bit line associated with the neighboring memory unit storing the data of state A. Data from other bit lines will be discarded. At step 758, the read reference voltage Vrc is applied to the word line WLn, and a read operation is performed on the word line WLn with VreadX = Vread4 for WLn+1. At step 760, the data is sensed as described above. At step 762, the result of step 760 is stored for the bit line associated with the neighboring memory unit storing the data of state E. Data from other bit lines will be discarded. At step 764, processor 392 will determine the data value based on the stored data from the sensing step. At step 766, the determined data value from step 764 will be stored in the latch for final communication to the user requesting the read data. In another embodiment, steps 734 through 738 associated with state A can be performed between 762 and 764. The steps of Figure 19 are also performed using other sequences, and the steps of other flow charts can also be used. Note that in the processing procedure described with reference to FIG. 19, the compensation is applied only to Vrc to distinguish between state B and state C. It is assumed that no compensation is required when reading with Vra, although the negative threshold of the erased state is affected by WLn+Ι, but is usually sufficiently far apart from state A, so that no correction is required. Although this is a practical assumption for contemporary memory, it may not be necessary for future generations of memory, and the compensation process described for Vrc can be applied to Vra. When the data value is determined in step 764, if the memory unit responds When Vra is conducted, the data of the lower page is Π1Π. If the memory unit responds to Vra

C 120932.doc •56· 1335596 Not transmitting and responding to Vrc without conduction, the lower page information is also "Γ. If the memory unit responds to Vra and does not conduct but responds to Vrc and transmits, the lower page data is also "0%. The process of Figure 20 is used to read or restore the upper page data. At step 800, a read operation is performed on the adjacent word line WLn+1 using the method of Figure 16. In some embodiments, the read operation performed on WLn+1 results in the determination of the actual data stored on WLn+Ι. In other embodiments, the read operation performed on WLn+Ι results in the determination of the amount of charge on WLn+Ι, which may or may not accurately reflect the data stored on WLn+Ι. At step 802, the result of step 800 is stored in the appropriate latch for each bit line. At step 804, the read reference voltage Vrb is applied to the word line WLn, and a read operation is performed on the word line WLn with VreadX = Vread 1 for WLn+1. At step 806, the data is sensed as described above. At step 808, the result of step 806 is stored for the bit line associated with the neighboring memory unit storing the data of state C. Data from other bit lines will be discarded. At step 810, the read reference voltage Vrb is applied to the word line WLn, and a read operation is performed on the word line WLn with VreadX = Vread2 for WLn + Ι. At step 812, the data is sensed as described above. At step 814, the result of step 812 is stored for the bit line associated with the neighboring memory unit storing the data of state B. Data from other bit lines will be discarded. At step 816, the read reference voltage Vrb is applied to the word line WLn, and a read operation is performed on the word line WLn with VreadX = Vread3 for WLn + Ι. At step 8.1, the data is sensed as described above. At step 820, the result of step 818 is stored for the line 120932.doc - 57 - 1335596 associated with the neighboring memory unit storing the data of state A. Data from other bit lines will be discarded. At step 822, the read reference voltage Vrb is applied to the word line WLn, and a read operation is performed on the word line WLn with VreadX = Vread4 for WLn + Ι. At step 824, the data is sensed as described above. At step 826, the result of step 824 is stored for the bit line 'associated with the neighboring memory unit storing the data of state E. Data from other bit lines will be discarded. At step 828' processor 392 will determine the data value based on the sensed data from the store. If the memory unit is turned on in response to Vrb, the upper page data is π 1 ” ^ If the memory unit is not enabled in response to Vrb, then the upper page data is "0". At step 830, the data value determined by processor 392 is determined. It is stored in the data latch for communication to the user. In another embodiment, the method of FIGS. 19 and 20 is used instead of using the method of FIGS. 19 and 20 to restore the material. The initial data reading is performed in response to a request to read the data. For example, after receiving a request to read the data in step 598 of FIG. 15, the system will perform a read operation in step 6. In this particular embodiment, step 600 is implemented by performing the processes of Figures 19 and/or 2A. A specific embodiment of implementing step 600 using the processes of Figures 19 and/or 2 can have no additional data recovery. Step 620, so if an error is uncorrectable, the system will report the error. Figures 19 and 20 are for reading data programmed using the upper and lower pages of Figure 12. Figure 19 and Figure 19 2G method to read by There are bit threaded or odd/even bit threaded stylized data. When used with all bits threaded, the typical peer reads all 120932.doc -58 - 1335596 bit lines. When interleaved with odd/even bits, the even bit lines are typically read simultaneously at the first time, and typically odd bit lines are simultaneously read at different times. Figure 21-26 shows for reading According to the method associated with the method of Fig. 13A-c, the process of Fig. 21 can be implemented as a whole process for reading information, which is in response to a read request for a specific one or more pages of data. Execution is performed prior to ECC, separately from ECC, and/or in conjunction with ECC. • In other embodiments, the process of Figure 21 can be performed as part of the data recovery step 620 of Figure 15. When reading the process according to Figure 13A-C For stylized data, any disturbances from floating gate to floating gate coupling due to pages below the stylized adjacent memory unit should be corrected when stylizing the upper page of the memory unit being considered Thus, when attempting to compensate for floating gate to floating gate coupling effects from adjacent memory cells, embodiments of the process only need to consider the coupling effects due to staging the top pages of adjacent memory cells. In the step of FIG. 21 • 1〇60, the process reads the data of the upper page of the adjacent word line. If the page above the adjacent word line is not stylized (steps 1〇62), the considered page can be read. There is no need to compensate for the floating gate to floating gate junction effect (steps 1〇64). If the top page of the adjacent word line is programmed (steps 1〇62), then in step 1066 the floating gate should be used. The floating gate coupling effect is compensated to some extent to read the page under consideration. In some embodiments, a read operation on an adjacent word line results in determining the amount of charge on the adjacent word line that may or may not accurately reflect the data stored on the adjacent word line. Furthermore, the selected word line (i.e., WLn) to be read may itself have only the lower page material. This can be sent to 120932.doc •59- 1335596 when the entire block has not been programmed. In this case, it is always ensured that the s-resonance unit on WLn+1 is still in an erased state and thus the hidden body has not yet suffered the coupling effect. This means that no compensation is needed. Therefore, reading the lower page of the word line whose upper page has not been programmed can be performed as usual without any compensation technique. In one embodiment, the memory array implementing the stylization process of Figures 13A-C will retain the set of memory cells for storage - or multiple flags. For example, σ, a row of memory cells can be used to store a flag indicating whether the lower page of the individual column It unit has been programmed, and another row of memory cells can be used for storage to indicate the respective Whether the upper page of the column memory unit has been programmed to be a flag. In some embodiments, a redundant memory unit can be used to store a copy of the flag. By checking the appropriate flag ‘can be judged and whether the page above the adjacent sub-line has been programmed. For more information on this flag and the stylization process, please refer to the article "The United States Patent No. 6,657,891 by " Semic〇nduct〇r Mem〇ry

Device For Storing Multi_Valued Data", the entire contents of which is incorporated herein by reference. Fig. 22 shows a specific embodiment of a processing procedure for extracting page data from an adjacent word line (such as a neighboring word line on the non-polar side) (step ι〇6〇 of Fig. 21). At step 1100, the read reference voltage Vrc is applied to the word line associated with the page being read. At step 11() 2, the bit line is sensed as described above. The result of step 11G2 is stored in the appropriate #latch in step 1104. In step 1106, the system checks the flag for indicating the upper page stylized associated with the page being read. In the specific embodiment, the memory of the flag is stored 120932.doc • 60·

丄JJJ body unit in the flag to ^ ^, ffi, 'breaking settings to store the status of the E information and the flag is not set under the eclipse + " < Beizhu and under the storage state C information Therefore, when step 1102 is sensed, the specific memory is paid in the U.

" single π, if the memory unit conducts (turns on), then the memory A A _ v J ^ 0 , _ non-storage state C data and the flag is not set if the memory unit The value path BI ^ t ^ 〇〇. χ ^ Where there is no conduction, then in step 1106 it is assumed that the memory... is indicating that the upper page has been programmed. In the specific embodiment, 'the flag can be stored in the right side of the byte to store all the bits, then the byte will include a state machine indicating the flag and the makeup state system. The only 8-bit code known to Chuan, such that the 8-code has bits in the following state: at least one bit is in state, at least one bit is in state, and at least one bit is in shape and A bit is in state C. If the upper page has not been in the state of the bit, the byte of the memory cell will store the code if the upper page has been programmed. In a specific example, the step η 〇 6 is performed by checking whether any of the cell units of the byte in which the code is being stored respond to Vrc is not enabled. In another embodiment, 'step 1106 includes Defining and reading the byte of the memory unit that is storing the flag and transmitting the data to the state machine, the state machine will verify whether the code stored in the memory unit matches the code expected by the state machine If yes, the state concludes that the upper page has If the flag has not been set (steps 11〇8), then the process of Figure 22 has not been terminated by the conclusion that the page has not been programmed. If the flag has been set (step 1108), then assume The upper page has been programmed, and at step 1120, a voltage Vrb is applied to the word line associated with the page being read. At f: 5 120932.doc • 61 · 丄 step 1122 '_bit line' as above The result of step 1122 is stored in the appropriate latch at step 1124. At step 1126, the power word Vra is applied to the word line associated with the page being read. At step 1128, the sense is at step (10). 'Storing the result of step 1128 in the appropriate lock. In step 1132, the processor 392 determines each memory file being read based on the results of the three sensing steps 2 1122 and 1128.

兀 The value of the data stored. At step (1) 4, the asset value determined at step 1132 is stored in the data latch for final communication to the user. At step U32' processor 392, based on the selected particular state code, uses the familiar: simple logic technique to determine the value of the upper page and the value of the lower page. For example. For the encoding described in Figure 13, the lower page data is μ* (complementary to the values stored when reading by state), and the upper page data is (4) OR (Vrb AND Vrc*) 一项 in a specific embodiment The process of Figure 22 includes applying Vread to the adjacent word line on the non-polar side. Thus, for the process of Figure 22, Vreadx = Vread.

In another embodiment of the process of Figure 22, VreadX = Vread4. FIG. 23 is a diagram showing the specific implementation of the process for reading data from the floating gate to the oceanic gate of the adjacent word line (see step 1 (4) of FIG. 21). The flow chart of the example. In step 1150, it is determined whether the upper page or the lower page of the word line associated with the consideration is used to perform the reading, and the lower page is read. In step 丄(1), the voltage is applied. Vrb to the word line associated with the page being read. The bit line is sensed in step 54. In step u56, the result of the sensing step 1154 is stored in the appropriate latch. In step (10), the flag is checked. To determine whether the £; 120932.doc -62- 1335596 page contains the upper page data. If there is no flag, then any data is currently in the intermediate state and the Vrb used is not the correct comparison voltage, and the process continues Step 1160. At step 116, vra is applied to the word line, the bit line is re-sensed at step 1162, and the result is stored at step 1164. At step 1166 (after step 1164; or if the flag is set, then at step After 1158), processing The device 392 determines the value of the data to be stored. In a specific embodiment, when the lower page is read, if the memory unit is turned on in response to Vrb (or Vra) being applied to the word line, the lower page data is also &quot ;1"; Otherwise, the lower page data is also "〇,. If the page address is determined to correspond to the upper page (step 丨丨5〇), the upper page reading process is performed at step 1170. In a specific implementation In the example, the upper page reading process of step 1170 includes the same method as described in FIG. 22, which includes reading the flag from an unwritten upper page for addressing or for other reasons. All three states. In one embodiment, the process of Figure 23 includes applying Vread to the drain side adjacent word line. Thus, Vreadx = Vread for the process of Figure 23. Another embodiment of the process of Figure 22 Vreadx = Figure 24 is a flow chart showing a specific embodiment of the process for reading data when compensating for the floating gate to floating gate coupling effect (see step 1066 of Figure 21). Step 12 of 24, the system determines that Use compensation for floating gate to floating gate coupling. This is done separately for each bit line. The appropriate processor 392 will determine the bit line that needs to be compensated based on the data from the adjacent word line. The word line is in state E or B (or has a charge that apparently indicates state E or b) and is being read

120932.doc -63 - 2疋 Word lines do not need to compensate for floating gate to floating gate coupling effects. Assume that if it is in state E, since the current word line is written, <|> | (has moved, so does not contribute to any coupling. If in state B, the shell is converted from B·, and from (1) to (4), small movement and can be viewed. In another embodiment, 'small scale Δ Μ can be applied to compensate for this small movement. In the specific embodiment, step 1200 can be performed in parallel. The process is exemplified with step 0, and FIG. 25 provides a diagram H (four) for explaining whether the execution decision is used for a = fixed word line on the word line to perform a read process. The second step is used to perform a read process. Read, when reading in V ton, if the memory cell is in state 』 and 'then the latch stores "r; if the memory cell is in state A, B 2 C' then the latch is stored" 〇', when reading with Vrb, the latch for the state t will store, T, and for states B and C, the third step of the latch will be followed by the second step including the second step After the inversion result (4), (7) is the result of the job-operation. In the fourth step = two To perform a read. For the state Ε 'Α and Β, latch 1 for state C, the latch stores "〇". In the fifth step = step: the result is a logical touch with the result of step 3. Operation = = means, steps and 4 can be performed as part of Figure 22. The result of executing the firmware 5 by the processor 392 can be stored in the latch, such as step =, 5 steps "1" If compensation is required, the storage "〇compensation" is on WLn+1 of the health state AM, and is read on the WLn that is in the early state of the hidden body. 120932.doc • 64 - 丄W5596 The memory unit needs to be compensated. Compared to some previous methods that require two or more latches to store the full data from WLrm, this approach requires only one latch to determine if WLn is corrected. Step 1202 of Figure 24, determining the upper page of the page being read. Page or lower page. If the page being read is the lower page, then during the delta selling process in step 12〇4, Vrb is applied to the associated On the sub-line WLn of the page being read, and applying Vread4 to the drain side adjacent word line wL n+i. Please ^' state code as described in main intent 13. Reading with Vrb is sufficient to determine the lower page data. In step 1208, the result of step 1206 is stored in the appropriate latch associated with the bit 兀* line. In step 1210, during the read process, Vrb is applied to the word line WLn for the page being read, and the deuteration is applied to 3 to the drain side adjacent word line WLn+Ι (see, for example, The pixel line is sensed at step 1212. At step 1214, for the bit line that was determined to be used for compensation at step 12, the result stored in step 1208 is overwritten using the sensing result of step 1212. If it is determined that a particular bit line does not require the use of compensation, then the data from step 1212 is not stored. At step 1216, processor 392 will determine if the data for the lower page is i or 〇. If the memory. Single 70 responds to Vrb and is opened, the lower page data is "1"; otherwise, the lower page is also ""0". At step 1218, the lower page material is stored in the appropriate lock for communication to the user. If it is determined in step 12〇2 that the page being read is the upper page, then the upper page correction process is performed in step 1220. Figure 26 is a flow chart for describing the upper page correction process. At step 125A of FIG. 26, the read reference voltage Vrc is applied to the word line associated with the page being read, and vread4 to 120932.doc • 65-1335596 is applied to the drain side adjacent word line WLn+1 to As part of the reading process. At step 1252, the bit line is sensed. At step 1254, the result of the sensing step is stored in the appropriate latch. At step 1256, Vrc is applied to the word line associated with the page being read, and Vread3 is applied to the drain side adjacent word line WLn+1 as part of the read process. At step 1258, the bit line is sensed. At step 1260, for any bit lines that need to be compensated (see step 1200), the results of the sensing step 1258 are used to overwrite the results stored in step 1254.

At step 1270, during the read process, Vrb is applied to the word line, and Vread4 is applied to the non-polar side adjacent word line WLn+1. At step 1272, the bit line is sensed. At step 1274, the result of sensing step 1272 is stored. At step 1276, during the read process, Vrb is applied to the word line associated with the page being read, and Vread3 is applied to the drain side adjacent word line WLn+1. At step 1278, the bit line is sensed. At step 1280, for any bit line that needs to be compensated (see step 1200), the result stored in step 1274 is overwritten with the result of step 1278. At step 1282, Vra is applied to the word line associated with the page being read, and Vread4 is applied to the near-side adjacent word line WLn+1 as part of the read process. At step 1284, the bit line is sensed. At step 1286, the result of sensing step 1284 is stored in the appropriate latch. At step 1288, Vra is applied to the word line associated with the page being read, and Vread3 is applied to the drain side adjacent word line WLn+1 as part of the read process. At step 1290, the sense bit line is over step 1282, for any bit line that needs to be compensated (see step 1200), the result stored in step 1286 is overwritten with the result of step 1290, 120932.doc - 66-1335596. At step 1294, processor 392 determines the data value in the manner of another method known in the art described above. At step 1296, the data value determined by processor 392 is stored in the appropriate data latch' for communication to the user. In other embodiments, the read (vrc, Vrb, Vra) order can be changed. - In the previous section on the discussion of the ® 21, it is very likely (but not necessary) that a request to read the data would require reading # multiple pages of information. In a specific embodiment, if the β-taking process of reading the multi-page data is to be accelerated, the reading process is pipelined, so that the state machine will perform the next page sensing when the user is transmitting the previous page data. . In this embodiment, the flag extraction process can interrupt the pipelined read process. In order to avoid this-interruption, the specific embodiment considers reading the flag of the page when reading a predetermined page and causing the s wired_OR integration process to check the flag (rather than reading the flag and sending the flag) Flag to state machine). For example, during step 1060 of Figure 21 (reading adjacent word lines), the process first uses • VrC as the reference voltage to read the data. At this point, if the wired-OR line indicates that each state stores data, then the upper page has not been programmed, so no compensation is required and the system will not compensate for the floating gate to floating gate coupling. Read below (step 卜 64 if • pure - includes a byte per block of data for each state, then if the flag is set, then at least the flag memory unit will have a state C If the wired-OR line indicates that any memory unit has no data in state C, the state machine concludes that the flag has not been set, so the upper page of the adjacent word line has not been stylized, and There is no need for 120932.doc -67- 1335596 to compensate for floating 'gate coupling. For more information on performing pipelined readings, please refer to the US patent application filed by the inventor jian Chen on April 5, 2005. 11/099, No. 133 entitled "C〇mpensating f〇r

Coupling During Read Operations 〇f Non-Volatile Memory", the entire contents of which is incorporated herein by reference. The techniques described above help to undo the floating gate to floating gate coupling effect. Figure 27 illustrates the concept of a floating gate to a floating gate. Figure 27 illustrates adjacent floating gates 13〇2 and 1304 on the same NAND string. Floating gates 1302 and 1304 are located on NAND channel/substrate 1306 having source/drain regions 13A8, 131A and 1312. A control gate 13 14 that is connected to and belongs to a portion of the word line WLn is connected to the floating gate 1302. Control gate 1316 connected to floating gate 1304 and belonging to the portion of word line WLn+1 ^ although floating gate 13〇2 will likely be subjected to a face-up from a plurality of other floating gates, for simplicity 27 shows only the effect from one adjacent memory cell. Specifically, FIG. 27 depicts three light-combining components supplied from the neighbor to the floating gate 1302: ri, r2, and Cr. The component ri is the coupling ratio between the adjacent floating gates (1302 and 1304) and is calculated by dividing the capacitance of the adjacent floating gate by the floating gate 13〇2 to all the capacitances of all other electrodes around it. Coupling sum. The component ^ is the coupling ratio between the floating gate 1302 and the drain side adjacent control gate 13 16 and is calculated by dividing the capacitance of the floating gate 1302 and the control gate 13 16 by the floating gate 1302. The sum of all the capacitances of all other electrodes around it is summed. The component Cr controls the gate coupling ratio and is calculated by dividing the capacitance between the floating gate 1304 and its corresponding control gate 1316 by the floating 120932.doc -68-1335596 moving gate 1302 to all around it. The sum of all capacitive couplings of the other electrodes. In the specific embodiment, the required compensation amount AVread can be calculated as follows: . AVread = (AVTn +1)-1 " i+ - (rl)(C/-) • where ΔνΤη+1 Stylized/verified time and current time at WLn

The root cause of the parasitic coupling effect of the threshold voltage variation ❹ΔνΤη+1 and the H-line to word line of the adjacent memory cell between the φ turns is mitigated by this method. AVread is the compensation needed to deal with this effect. • Compensation for coupling as described herein can be achieved by utilizing the same parasitic capacitance between adjacent floating gates and the capacitance between the floating gate and the adjacent control gate. Since the control gate/floating gate stack is typically etched in one step, the tracking changes in the spacing between the memory cells are compensated. Therefore, the further the two neighbors are apart, the smaller the coupling, and • the smaller the compensation required for this effect. The closer the two neighbors are, the larger the coupling and the greater the compensation. This constitutes a proportional compensation. ‘ The compensation described above also reduces the effect of changes in etch back depth. In some devices, the control gate partially overlaps the floating gate. The amount of overlap is called "etchback". The change in the depth of the return silver can affect the amount of coupling. Using the compensation scheme described above, the compensation effect also varies with the depth of return. As a result of the ability to reduce the floating idle-to-floating effect, the margin between the threshold voltage distributions can be made smaller, or the memory system can be programmed faster.

120932.doc •69- 1335596

Embodiments of the present invention have been presented above for the purposes of illustration and description. The invention is not intended to be exhaustive or to limit the invention. Many modifications and variations are possible in light of the above teachings. The specific embodiments are chosen to best explain the principles of the present invention and the application of the embodiments of the invention, The invention (4) is intended to be defined by the scope of the attached patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a NAND string. Figure 2 shows an equivalent circuit diagram of a NAND string. 3 is a cross-sectional view of a NAND string. 4 is a block diagram of a NAND flash memory cell array. FIG. 5 is a block diagram of a non-volatile memory system. Figure 6 is a block diagram of a non-volatile memory system. 7 is a block diagram of a particular embodiment of a sensing block.

Figure 7A illustrates a block diagram of a memory array. Figure 8 is a flow chart showing the flow of a non-volatile memory unit. Figure 9 is a diagram showing the control thyristor applied to a non-volatile memory unit. & A. Example of Figure 10 is a timing diagram for explaining the read/verify operation. Some Signal Trips During This Figure 10A illustrates a NAND string. Figure 10B shows the NAND string. 120932.doc • 70- FIG. 10C is a flow chart illustrating a specific embodiment of a process for operating a non-volatile storage device. FIG. 10D illustrates a process for selecting a voltage for a word line adjacent to a selected word line. A flow chart of a specific embodiment. 11 illustrates an exemplary set of threshold voltage distributions. FIG. 12 depicts an exemplary set of threshold voltage distributions. Figures 13A-C illustrate various threshold voltage distributions and describe the process for programming non-volatile memory. 14A-G are diagrams showing the sequence of programming non-volatile memory processes in various embodiments. Figure 15 is a flow chart showing a specific embodiment of a process of reading a non-volatile memory. Figure 16 is a flow chart showing a specific embodiment of a process for performing a non-volatile memory read operation. Figure 17 is a flow chart showing a specific embodiment of a process for restoring data. Figure 18 is a flow chart showing a specific embodiment of a process for restoring data from a plurality of word lines. Figure 19 is a flow chart showing a specific embodiment of a process for reading data from a lower page. Figure 20 is a flow chart 9 showing a specific embodiment of a process for reading data from an upper page. Figure 21 is a flow chart showing a specific embodiment of a process for describing data. 0 120932.doc -71- 1335596 Figure 22 is a flow chart showing a specific embodiment of a process for reading data from an upper page. Figure 23 is a flow chart showing a specific embodiment of a process for reading data without using compensation. 24 is a flow chart showing a specific embodiment of a process for reading a word line and compensating for a floating gate to floating gate (or dielectric to dielectric region) coupling. FIG. 25 is a table for describing a process of determining a data value. Figure 26 is a flow chart showing a specific embodiment of a process for reading the upper page material using the correction. Figure 27 is a block diagram showing the capacitive coupling between two adjacent memory cells. [Main component symbol description] 100, 102, 104, 106 Transistor (memory unit) 100CG, 102CG, 104CG, 106CG 100FG, 102FG, 104FG, 106FG 120 120CG 122 122CG 126 128 126 Control gate floating gate first choice Gate control gate second selection gate control gate bit line (Figure 2) Source line (Figure 2) Bungee terminal (Figure 4) /5 120932.doc -72- 1335596

128 source terminal (Fig. 4) 130, 132, 134, Ν+ doped (diffusion) region 136, 138 140 ρ well region 150 NAND string 204 source line 206 bit line 296 memory device 298 memory die 300 Memory cell array 310 control circuit 312 state machine 314 on-chip address decoding 316 power control module 318 line 320 data bus 330, 330 Α, 330 Β column decoder 350 controller 360, 360 Α, 360 Β row decoder 365, 365 Α, 365 Β Read/write circuit 370 sensing circuit 372 data bus 380 sensing module 382 bit line latch · 73 · 120932.doc 1335596

390 Common Section 392 Processor 393 Input Line 394 Data Latch 396 I/O Interface 400 Sensing Blocks 466, 468, 470, Memory Units 472, 474, 476, 478, 600, 602 482 Source Select Gate 484 Bottom side select gate 490 source/" and polar region 492 common source line 494 bit line contact 450 signal line 452 curve 450 signal line 452 signal line 530 threshold voltage level increased to state A 532 Voltage increases to state B range 534 threshold voltage increases to state 550 state B's threshold voltage distribution 1302, 1304 floating gate 1306 NAND channel/substrate 120932.doc •74- 1335596

1308, 1310, 1312 source/drain region 1314, 1316 control gate A, B, C threshold voltage distribution (stylized state) B' transition state BE threshold voltage distribution (erased state) BLCLAMP Analog signal BLO, BL1, ... bit line for setting the value of the bit line when the sense amplifier is charging

BL8511 PC rl, r2, Cr PCMAX Selected BL Stylized Counter Coupling Component Stylized Limit Value Bit line selected for reading/verification

SGD bungee side select gate of gate

SGS Source Vcgr VcgvVpgm Vrdl, Vrd2, VrdX Vra, Vrb, Vrc Vva, Vvb, Vvc Vvb' source side select gate gate memory cell source line read compare voltage verify compare voltage stylized voltage pass voltage read Take the reference voltage verification reference voltage verification point WLn selected for the read/verify word line 120932.doc •75· 1335596 WLn+l

WL unsel S

The non-selected word line of the LD unsel D WLn adjacent to the word line of the adjacent word line is located on the source side of the selected word line, and the non-selected word line on the drain side of the selected word line is adjacent to the left side of the selected word line. External unselected word line

120932.doc -76-

Claims (1)

1335596 Patent Application No. 096117515 'Chinese Patent Application Scope Replacement (99 years 1 month), Patent Application Park: Original I 1. A method of using a non-volatile storage device, comprising: applying a specific voltage to a a specific non-volatile storage element in the group of connected non-volatile storage elements; u-electrical to the group - or - a plurality of non-volatile storage: the first - set of The first collection of - or a plurality of non-volatile storage elements is located on a first side of the particular non-volatile storage element 'and has been subjected to - or multiple stylization processes since the last erase of the group' Cooperating with the specific voltage, applying the first voltage; storing the voltage to the group - or - a plurality of non-volatile first sub-groups of the two sets - the containing - or a plurality of non-volatile storage elements The collection system is located on the second side of one of the specific non-volatile storage elements = and the last voltage of the group has not been subjected to a predetermined voltage, and the second voltage is applied; Applied One of the second electric grinders is electrically connected to one of the group adjacent to the non-volatile storage and stored in the Buzen U-storage element, the adjacent non-winged-side tight/constant non-volatile (four) storage element The second non-volatile material element, self-erasing the group to save the second:: the adjacent non-volatile storage element of the non-volatile storage element has not been programmed; and 2 The method of claim 2, wherein the second voltage is less than the first voltage 120932-991011.doc 1335596. : the voltage different from the second voltage is greater than the second voltage and less than the first voltage. The method of claim 2, wherein: the voltage different from the second voltage is greater than the second voltage and equal to the first voltage. The method of claim 1, wherein: the characteristic voltage is a verification reference voltage; the first voltage is sufficiently high to turn on the first non-volatile storage element set; the second voltage is sufficiently high enough to be turned on The second non-volatile storage element set, and the 6 second voltage is less than the first voltage; and the verification is part of the iteration of the -stylization process. 6. The method of claim 5, wherein: the group comprising the connected non-volatile storage elements is a NAND flash memory device that is part of a NAND string. 7. The method of claim 5, wherein: the first non-volatile storage element set is one of the source sides of the storage element; the non-volatile non-volatile second non-volatile storage element set is located in the storage element a side of the crucible; and the secret side of the adjacent non-volatile storage element. The method is located in the specific non-volatile storage i20932-9910n.doc 8. The method of claim 1, the further comprising: the reading of the specific non-volatile storage element includes applying a common renewal power $ # # A , J °°°—a collection of non-volatile storage elements and the second set of non-volatile components 该 the reading includes applying according to the adjacent non-volatile storage:::::- The method of claim 9, wherein: the multi-state NAND flash memory of the portion of the group of non-volatile storage elements connected to the non-volatile storage element, /, 0亥 疋 疋 voltage to the specific non-volatile storage element a gate; ~ force 亥 first voltage to the first non-volatile storage element set of gates; I 该 add the second voltage to the second non a gate of the set of volatile storage elements; and a wire different from the voltage of the second voltage to one of the adjacent non-volatile storage elements controlling the gate. 10. The method of claim 9, wherein: The second voltage is less than the first voltage; the specific voltage is a verification reference The voltage is sufficiently sufficient to open the first set of non-volatile storage elements; the second voltage is sufficiently high to open the second set of non-volatile storage elements; and 120932-991011.doc 1335596: One of the source side of the non-volatile library component set storage unit; the non-volatile storage ==:: stored: piece _, the specific non- element of the non-polar side I is stored in the specific non- The volatile storage name U. The method of claim 1, wherein the step further comprises: determining, according to the non-volatile storage element in the second set, a value of the voltage of the second electrical device. a non-volatile storage system comprising: a group comprising connected non-volatile storage elements; and a management circuit in communication with the connected non-volatile storage group, the management circuit applying a specific Electricity - ~ L 疋 疋 昼 昼 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该/ one or more non-volatile fruits 0 and applying a second voltage to the group a second set comprising - or a plurality of non-volatile storage elements, a first collection comprising one or more non-volatile storage elements on a first side of the particular non-volatile storage element, and One of the groups has been subjected to a - or multiple stylization process since the last erasure, the second or more of the non-volatile storage elements being located on the second side of one of the particular non-volatile storage elements, and Since the last erasure of the group has not undergone a stylization process, when the specific voltage is applied, the management circuit applies a voltage different from the second voltage to one of the groups adjacent to the non-volatile 120932-991011 .doc -4- Mountain 5596 T王㑩存兀仵_ The low-clay element is located on the first side of the particular non-volatile (four) storage element and immediately adjacent to the particular non-volatile health component, since erasing the group' The adjacent non-volatile memory element immediately adjacent to the particular non-volatile storage element has not been programmed, and the management circuit verifies the particular non-volatile storage stylization based on the particular voltage. The non-volatile storage system of claim 12, wherein: the second voltage is less than the first voltage; and the voltage different from the second voltage is greater than the second voltage and less than the first voltage. The non-volatile storage system of claim 12, wherein: the specific voltage is a verification reference voltage; the first voltage is sufficiently high to turn on the set of non-volatile storage elements; the second voltage is sufficiently high enough Opening the second set of non-volatile storage elements; and the second voltage is less than the first voltage; and the management circuit verifies the particular non-volatile storage element as part of the iterative process. A non-volatile storage system that is privately categorized by a circumstance, wherein: the group comprising the connected non-volatile storage elements is a NAND string. 16. The non-volatile storage system of claim 15, wherein the first non-volatile storage element set is located on a source side of the specific non-volatile 120932-991011.doc storage element; the second non-volatile The set of dislocation elements is located on one of the drain sides of the storage element; and the non-volatile non-volatile storage element is located on the drain side of the element. Non-volatile storage of bamboo rafts 17. The non-volatile storage system of claim 12, wherein the § hai dynasty circuit reads the data from the specific non-supplemental Transmitting the first non-volatile storage element set and the second non-volatile storage element set, the reading comprising applying a data-dependent voltage to the adjacent non-dependency according to the condition of the adjacent non-volatile storage element Volatile storage element. 1 8. The non-volatile storage system of claim 7, wherein: the group comprising the connected non-volatile storage elements - nand string; applied. a specific voltage to one of the specific non-volatile storage elements controlling the gate; applying the first voltage to the control gate of the first non-volatile storage element set; applying the second voltage to the second non-volatile storage element And concentrating the control gate; and applying a voltage different from the second voltage to one of the adjacent non-selective storage elements to control the gate. 19. The non-volatile storage system of claim 18, wherein: the second voltage is less than the first voltage; 120932-9910H.doc 1335596. Hite 疋 voltage system - test ^ Feng Yin card reference voltage; this brother a voltage full set of high; M open the first - non-volatile storage element of the second voltage full set of high; and M open the second non-volatile The second voltage of the storage unit is less than the first voltage; one source side of the first non-volatile storage storage element; and the second non-volatile storage element collection system storage element One of the drain sides, and the non-volatile non-volatile storage side of the non-volatile storage element. The part is located in the far (four) non-volatile storage 2 〇 _ as in the non-volatile storage system of claim 12, wherein The management circuit selects one of the voltages different from the second voltage according to the number of non-volatile storage elements in the second combination, T. 120932-991011.doc 1335596 ' Patent application No. 096117515 Chinese pattern replacement page (October 99) --, Year Month 曰 Correction replacement page flft.tn 12 I 120932-flg-991011.doc