TWI329905B - Integrated circuit structure - Google Patents

Integrated circuit structure Download PDF

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TWI329905B
TWI329905B TW095132551A TW95132551A TWI329905B TW I329905 B TWI329905 B TW I329905B TW 095132551 A TW095132551 A TW 095132551A TW 95132551 A TW95132551 A TW 95132551A TW I329905 B TWI329905 B TW I329905B
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Taiwan
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integrated circuit
conductor
substrate
circuit structure
connection
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TW095132551A
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TW200802700A (en
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Chih Hsiang Yao
Tai Chun Huang
Mong Song Liang
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

1329905 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體技術，特別係關於一種積體 電路結構的内連線及連接結構。 【先前技術】 九第1圖係顯示一習知的積體電路結構400的部分示 意圖。本發明所屬技術領域中具有通常知識者 成於一石夕基底術上的-積體電路裝置4〇4可包含^或 複數個電晶體及/或其他裝置，其中矽基底4〇2包含一上 表面401與一下表面4〇3。一接觸蝕刻停止層4〇5係沿著 一電晶體結構與一氧化物平坦化結構4〇7，而形成於上表 面401上。一金屬化結構4〇6係置於積體電路裴置*⑽ 上，其包含複數個内連線層（例如導線與連接物[via])與複 數個層間介電層。雖然第！圖中僅繪示出—第—金屬層 =1與-第二金屬層M2 ’本發明所屬技術領域中具有^ 常知識者應可瞭解依據裝置的複雜程度，其通常^有更 多的金屬層，例如可形成九個金屬層於積體電路裝置 與保護層/連接結構（未繪示）之間。 ^ 第2圖係顯示積體電路結構4〇0的另—示竟圖，其 係顯示層狀的矽基底4〇2與金屬化結構406。本:二所屬 技術領域中具有通常知識者應當瞭解，第2圖^未繪示 的積體電路裝置404係可嵌於矽基底4〇2的上表面1 = 中或形成於石夕基底402的上表面4()1上。第2圖僅顯示 0503-Α32271 TWF/dwwang 4 1329905 ====線接合结構408或覆晶接合 屬上:並通常穿透-===:中的最上層的金 以低介電常數（low_k ; LK)材料、極低 ΓΓΓΓ4、超齡 ^2：：7"51"χικ^Γ^^ 可欠=的 =匕，構406的層間介電層的好處在於 的電，並因此減少内連線的導線之間的= Γ 2上7分類是基於其介電常數，其中介 = == = =數 2.7〜2·4 為 斜mm 4超低介電常數材 ’.材科為夕孔質、基質為氫化㈣鹽 ▲啊〇職，· HSQ)的材料，為D〇w c〇rning公g ^其介電常數小於2'然而，上述低介電常數材料的= 械強度較低，由例如形成料接合結構彻或前述導體 凸塊時所引發的應力常會使上述低介電常數材料破裂。 另外，上述低介電常數㈣的強度，亦會因為 構傷中的金屬層數目的增加而降低；又因為前述金屬。 層數的增加，而使其連線長度增加，其電阻也因而辦加蜀 而發生較嚴㈣RC延遲（RCdelay)，而降低元件的^度。’ 【發明内容】 有鑑於此，本發明的—目_提供—種積體電路梦 0503-A32271 TWF/dwwang 5 1329905 3 ’可有效改善前述低介電常數材料破裂問題，並解決 :内連線的金屬層數增加所造成㈣低元件速問 ° 4 為達成本發明之上述目的，本發明 電路結構，包含:-基底，其具有-上表面與一下= 上述上表面具有一電路裝置於其上 、 ,Μτ、* 4* μ 硬數個金屬層，電 ! 生連接於上述電路褒置；—連接結構於上述下表面上. 以及一導體内連線結構，貫穿上述基底。 ’ 本發明係又提供一種積體電路結構，包含··一美底， 電路裝 其具有一上表面與一下表面，上 3 置於其上;複數個金屬層，電性連接二=1, 連：二ί複數個層間介電層令的複數個第-導體 ==複ST;-連接結構於上述基底 連接上述連接結構與上述電路^置述導體内連線結構電性 【實施方式】 為讓本發9月$ μ ;十、4 明顯易懂，下文特舉出：佳:二：徵:和優點能更 作詳細說明如下： 1土 η靶例，並配合所附圖式， 明較佳實施例之積體電路結構。 ^ Θ係顯示本發明一較佳實施例之 05O3-A3227JTWF/dwwang 1329905 豆，路結構500，具體而言，銲線接合結構咖係 上表面5〇3(雖然圖中顯示其在基底5(^的 社構5GS I形成於上表面5〇】上。為了幫助銲線接合 :構的形成’導體内連線結構5W的形成，係穿、秀 基底502的而至一電路裝置5〇4(請參考第式、一八 屬=。6。導體内連線結構51。具有複㈣^ 體材料例如鎢、銅，，並在下
^缞接入s連接結^，例如為―銲墊及其所連接的 紅線接合結構508、戋一赴荇姓a & ,, ^ J 構係可與任何必要的保護層起l在構本接結 線接合結構·係形成於㈣丄 上，而非形成於脆弱的金屬化結構5〇勺入〃 弱的低介電常數材料層間介;'匕3讀個脆 薄…密爾㈣，較好為^層二⑷ 内連線結構51〇的深寬比而形成幫助其形L降低㈣ 之積一=圖’係顯示本發明另一較佳實施例 5 0 〇H ，取代第3圖所示的積體電路結構 500。與弟3圖所示的積體電路結構％ :所示=化結構寫分成二個金屬化結構： 2之外’ 4 4圖所示的積體電路結構則A的盆 相同。金屬化結構驗2係形成於基底;〇2; :t=上:而，接合結構 構6A2上、爹考弟3、4圖，本質上可將部分的全屬 化結構(第3圖）自基底5Q2的上表面5 形^ 0503-A32271 TWF/dwwang 7 1329905 於基底502的下表面503上，而成為第4圖所示的積體 電路結構500A。例如假設積體電路結構500A的金屬化 結構共具有9個金屬層，分別編號為Ml〜M9，則金屬化 結構506A,、506A2的可能架構則表列於下列第1表中： 第1表 金屬化結構506A! 金屬化結構506A2 Ml M2 〜M9 Ml 〜M2 M3 〜M9 Ml 〜M3 M4 〜M9 Ml 〜M4 M5 〜M9 Ml 〜M5 M6 〜M9 Ml 〜M6 M7 〜M9 Ml 〜M7 M8 〜M9 Ml 〜M8 M9 另外第4圖中的導體内連線結構510則穿越基底 502，而連接金屬化結構506A,、506A2、電路裝置504、 與銲線接合結構508。 設計者可根據金屬層的數量、金屬化結構506A!、 506A2中的低介電常數材料的強度、或其他條件，來決定 如何選用金屬化結構506A,、506A2的組合。藉由將銲線 接合結構508移至基底502的背面（下表面503)，其形成 時應力就不會作用於基底502的上表面501中的電路裝 0503-A32271 TWF/dwwang 8 1329905 置504。另外，藉由將部分的金屬化結構移至基底502的 背面（下表面503)，具有脆弱的低介電常數材料的金屬化 結構506A,、506A2的厚度均可以得到縮減。如前所述， 層間介電層的穩定度及其抵抗破裂的能力，係與其層數 成反比。 雖未列於第1表中，第3圖係顯示其金屬化結構506 係全部形成於基底502的上表面501上，但是其銲線接 合結構508則形成於下表面503上，藉由導體内連線結 構510將銲線接合結構508連接至金屬化結構506與電 路裝置504。 第5圖為一較詳細的示意圖，係顯示本發明另一較 佳實施例之積體電路結構500B(顯示出其中的第一金屬 層Ml與第二金屬層M2)，其部分的金屬化結構506B係 自電路裝置504的上方移至基底502的下表面503的上 方。基底502較好為矽基底，而亦可使用m-v族的化合 物、或絕緣層上覆石夕（silicon on insulator ; SOI)的基底。 電路裝置504，其包含一電晶體與一複晶矽導線，如習知 技術一般形成於基底502的上表面501上。任何本發明 所屬技術領域中具有通常知識者當可暸解，電路裝置504 可包含一或複數個電晶體，例如為金氧半 (metal-oxide-semiconductor ; MOS)電晶體或其他結構。 電路裝置504的功能可作為記憶體、電源裝置、依特定 用途而設計的積體電路（application specific integrated circuit ; ASIC)、處理器、或其他功能的裝置。第5圖所 0503-A32271 TWF/dwwang 9 1329905 不的基底502,是以上表面向下的方式呈現，因此上表面 5〇1在第5圖令是朝下，而下表面5〇3在第5圖中係朝上。 如同習知技術’一氧化物層52〇與一接觸蝕刻停止層Μ〕 係形成於電路裝置504上。如同前文所述，至少部分I 有低介電常數層間介電層的金屬化結構5_係自氧ς 物層520的另一側，移至基底5〇2的下表面$⑽上。 金屬化結構506Β(其中的第—金屬層M1與第二金屬 層M2)係經由穿透基底5〇2的導體内連線結構“ο,連接 至電路裝置504。導體内連線結構51〇可具有一絕緣層或 阻障層於其側壁’用以關而形成導體内連線結構510 的導通^、與在上料通孔_成導體材㈣技術，可 參考目前已知的技術’在此便予以省略其詳細過程。為 了幫助電路裝置504與金屬化結構5〇6B之間的連接，可 藉由㈣或研磨，將基底5G2薄化至2〜1Q密爾（mu) 度。 金屬化結構506B的形成可藉由傳統的製程技術例 如雙鑲嵌技術’其可參考目前已知的技術，在此便予以 省略其詳細過程。上述形成金屬化結構5〇6β的係必要時 形成複數個阻障層509 ;形成層間介電層5〇7 ;蝕刻出導 通孔512與溝槽514;與以導體材料例如鶴、雀呂、銘銅、 或銅填滿導通孔512與溝槽514。導體材料與低介電常數 介電層的材料的組合例示如下：銅/ LK、銅/ elk、銅 /FSG(摻氟的二氧化矽；flu〇rined〇pedsilicateg⑽)、及 銘/氧化物等等。-承載器基板亦可同時與氧化物層別 0503-A32271 TWF/dwwang 1329905 連接，以維護前述製程步驟中的本發明之積體電路結構 的安全。 如第5圖中所例示，可將所有的金屬化結構506B形 成於基底502的下表面503上，然後形成第3、4下表面 503圖所示的銲線接合結構508。在本實施例中，銲線接 合結構508的形成會對金屬化結構506B施加應力，該應 力不會完全轉移至基底502的上表面501上的電路裝置 504。因此，銲線接合結構508的形成不會對電路裝置504 的功能造成影響。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何本發明所屬技術領域中具有通常知 識者，在不脫離本發明之精神和範圍内，當可作些許之 更動與潤飾，因此本發明之保護範圍當視後附之申請專 利範圍所界定者為準。
0503-A32271 TWF/dwwang 11 1329905 【圖式簡單說明】 第1圖為一示意圖，係顯示一習知的積體電路結構 的架構。 第2圖為第1圖所示的積體電路結構的另一示意 圖，並顯示其銲線結構。 第3圖為一剖面示意圖，係顯示本發明較佳實施例 之積體電路結構。 第4圖為一剖面示意圖，係顯示本發明另一較佳實 施例之積體電路結構。 第5圖為一剖面示意圖，係顯示本發明又另一較佳 實施例之積體電路結構。 【主要元件符號說明】 400〜積體電路結構， 402〜矽基底； 404〜積體電路裝置； 406〜金屬化結構； 408〜銲線接合結構； 500A〜積體電路結構， 501〜上表面； 503〜下表面； 506〜金屬化結構； 506A2〜金屬化結構； 507〜層間介電層； 401〜上表面； 403〜下表面； 405〜接觸蝕刻停止層； 407〜氧化物平坦化結構； 500〜積體電路結構； 500B〜積體電路結構； 502〜基底； 504〜電路裝置； 506A,〜金屬化結構； 506B〜金屬化結構； 508〜銲線接合結構； 0503-A32271TWF/dwwang 1329905 509〜阻障層； 512〜導通孔； 520〜氧化物層； Ml〜第一金屬層； 510〜導體内連線結構； 514〜溝槽； 522〜接觸蝕刻停止層； M2〜第二金屬層。
(|/ 0503-A32271 TWF/dwwang

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  1. I3299Q5 I 修正曰期：99.5.5 第95132551號申請專利範圍修正本 十、申請專利範圍： 1· 一種積體電路結構，包含： -基底’其具有一上表面與一下表面，該上表面且 有一電路裝置於其上； 複數個金屬層，電性連接於該電路裝置； 一連接結構於該下表面上；以及 .-導體内連線結構，包含至少—第—導 ⑻a)貫穿該連接結構正上方之基底， = 接接觸，其中該第一導體 運接…構直 該下表面的接觸面延伸垂直向上的區域内，、 導體連接通道_填滿導體材料。 、第 兮導專利乾圍第1項所述之積體電路結構，1中 3:申:=二連接該連接結構與該電路裝置。 至少邱項所述之積體電路結構，且中 f的該獲數個金屬層係置於該基底的該上表 '面 4·如申請專㈣圍第〗項料 該複數個金屬層包含複數個 電路f構，其中 導體連接通道㈣與複數個導體線電層令的複數個第二 5.如申請專利範圍第4 該複數:層間介電層包含低介電;=電路結構’其中 π t I ’ 。 •如申請翻制第3項 之積體電路結構，其中 0503-A3227lTWF3/jeff 1329905 第95132551號申請專利範圍修正本 ，， :導體内連線結構至少電性連接該些金屬層：=: T 一層。 /、 如申請專利範圍第1項所述之積體電路結構，里中 該連接、纟^構包含至少一銲線接合結構。 =如申4專利範圍第丨項所述之積體電路結構，立中 該基底的厚度為2〜1〇密爾（mil)。 '、 10.—種積體電路結構，包含： -基底，其具有一上表面與一下表面 有一電路裝置於其上； 丄衣面” =數個金制，電性連接於該電路裝置，該些金屬 層包含複數個層間介電層中的複數個第接 (via)與複數個導體線； 一連接結構於該基底的該下表面上；以及 構’包含至少一第二導體連接通道 L接二連接結構正上方之基底’且與該内連線結構 其t該第二導體連接通道係位於該連接結構斑該下 表面的接觸面延伸垂直向上的區域内、 連接通道中填滿導體材料； 弟一導體 其中該導體内連線結構電性連接該連接結構與該電 路裝置。 η.如申請專㈣㈣1G項所述之積體電路結構，其 中該基底的厚度為2〜1〇密爾。 12.如申請專利範圍第1()項所述之積體電路結構，其 0503-A3227 丨 TWF3/jeff 132990^ 第95132551號申請專利範圍修正本 修正日期：99.5.5 中至少部份的該些金屬層係置於該基底的該下表面上。 13. 如申請專利範圍第12項所述之積體電路結構，其 中至少部份的該些金屬層係置於該基底的該上表面上。 14. 如申請專利範圍第1〇項所述之積體電路結構，其 中該些第一、第二導體連接通道包含銅、鎢、或叙。 15. 如申請專利範圍第10項所述之積體電路結構，其 中該連接結構包含至少一銲線接合結構。 16. 如申請專利範圍第10項所述之積體電路結構，其 —— 〇 中該導體内連線結構係電性連接該電路裝置與該 層中的其中之 二隹屬 0503-A32271TWF3/jeff 16
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