TWI329819B - System and method for managing circuit layout files - Google Patents

System and method for managing circuit layout files Download PDF

Info

Publication number
TWI329819B
TWI329819B TW95145826A TW95145826A TWI329819B TW I329819 B TWI329819 B TW I329819B TW 95145826 A TW95145826 A TW 95145826A TW 95145826 A TW95145826 A TW 95145826A TW I329819 B TWI329819 B TW I329819B
Authority
TW
Taiwan
Prior art keywords
line
message
circuit layout
circuit
wiring
Prior art date
Application number
TW95145826A
Other languages
Chinese (zh)
Other versions
TW200825820A (en
Inventor
Christina Yang
Original Assignee
Inventec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inventec Corp filed Critical Inventec Corp
Priority to TW95145826A priority Critical patent/TWI329819B/en
Publication of TW200825820A publication Critical patent/TW200825820A/en
Application granted granted Critical
Publication of TWI329819B publication Critical patent/TWI329819B/en

Links

Description

1329819 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種檔案管理技術,更詳而言之,係 有關力種於電路圖案的佈設過程中對佈線應用程式中 »己錄線路名稱訊息與線路屬性訊息對應關係之電路佈設 檔案進行管理之系統及方法。 【先前技術】 目前,於印刷電路板之佈設過程中,之前要新建線路 屬性,並且對線路屬性進行規則設定,然後根據不同線路 的走線要求選擇相應的線路屬性。如果讀錯線路屬性,那 麼=線路的線寬'線距都會發生錯誤,當該線路以錯誤之 線寬及線距佈設於印刷電路板上後,輕則會影響電氣性 月匕,降低該線路或印刷電路板之品質特性,重則會導致整 個產品的失敗。由此可見,正確地選擇線路屬性對線路之 佈設設計來講係至關重要的。 • 舉例來說,假設有一線路+V3M_LAN,其正確之線路屬 性係為PG爾_2(L5—5复5_5,即該線路之線寬為 2〇mil,線路間之線距為5mil ;倘若於佈線過程中 +V3M_LAN的線路屬性誤讀成defaul t_線路-屬性即線寬 為5mil,線距為5mil ’這樣,導致所佈設之線路之線寬 係為5mil,因該+V3M—LAN係為一電源線,需要盆線寬較 寬,如果線路屬性發生錯讀之情形,即t影響該電源線之 電性傳輸性能。 特別地,在印刷電路板設計過程令,由於佈設工程師 19986(修正本) 6 1329819 =ΓΓ文原理圖,而於修改過程中’很容易影響到預先 二、、、、4屬性,造成線路屬性錯誤。因此為避免這個問 f田目前’於修改原理圖之前’佈設工程師會建立並保存 〜己錄線路與線路屬性之對應關係的電路佈設檔 電子工程師於後續修改原理圖後,當將原理圖中 2與線路屬性之對應_是否與賴存之電路佈設槽 〃線路與線路屬性之對應關係是否一致,且於判斷二者 不一致時’復再將所健存之電路佈設檔案復原回來。 惟,前述習知技術中,因該電路佈設槽案之建立盜保 存,以及於修改完原理圖後進行比對等作業均係透過佈設 =程師以人工方式完成的’故其最Α缺陷在於穩定性較 差,難免會因許多因素,包括作業人員本身之生理、心理 因素及外在環境影響而導致於於作業過程中發生差錯。另 外’由於對原理圖每作一次修改都要求佈設工程師以手動 =式重複上述包括保存及復原等在内之動作,操作比較繁 ^而 常會因為人為之疏,t、而忘記進行對應之操作而 =成線路屬性錯誤。另一方面,操作流程繁複,過多人力 二^斤耗費時間及成本過高’對亟欲尋求生產成本降低以 曰加產品競爭力的製造廠商而言顯然是極不合理的。 因此,如何克服上述習知技術之缺失,進而提供一種 :以自動化方式管理電路佈設檔案的功能,以可於電路圖 f的广設過程中,避免習知技術中因人為操作而造成的錯 、’k幵電路佈設檔案的管理質量,確保電路佈設檔案中 線路名稱訊息與線路屬性訊息對應關係的正確性,且可簡 19986(修正本) 7 1329819 流程及節省作業時間,並提高工作之效率,實為目 月1j亟待解決之問題。 【發明内容】 馨於上述習知技術之缺失’本發明之主要目的係在於 ^ 一種電路佈設檔案之管理系統及方法,俾避免作業過 人爲疏失,可確保電路佈設檔案中線路名稱訊息與 綠路屬性訊息對應關係的正確性。 轉明之另-目的係在於提供—種可簡化操作流程 卽省作業時間之電路佈設檔案之管理系統及方法。 本發明之再-目的係在於提供—種可提高工作效率 之電路佈設檔案之管理系統及方法。 為達上述目的及其他,本發明即提供一種電路佈設樓 案之管理系統及方法。該電路佈設檔案之管理系統係應用 具有儲存單元之電子裝置中,用以辅助一佈線應用程 式製作一印刷電路板(Printed Circuit B〇ard,pcB)之電 路圖案’於該佈線應用程式巾係預設有佈設於該印刷電路 板上的線路名稱訊息及對應之線路屬性訊息,該系統係包 括:偵測模組,係用以於透過該佈線應用程式執行完一反 向標註(back ann〇tati〇n)作業後,偵測該電子裝置之儲 存單元是否儲存有-包含有線路名稱訊息與線路屬性訊 息對應關係的電路佈設檔案,若否,則產生一觸發訊號輸 出;檔案建立模組,係用以於接收到該偵測模組所產生之 觸發訊號時,依據該佈線應用程式預設的線路名稱訊息及 對應之線路屬性訊息’建立一用以記錄線路與線路屬ς對 19986(修正本) 8 關係的電路佈设檔案,並將其儲存至該電子裝置之儲存 單元;比對模組,透過該佈線應用程式依據反向標註作業 •之提不修改該印刷電路板之原理圖,並將修改後之原理圖 導入該佈線應用程式後,比對該修改後之原理圖中線路名 稱訊與線路屬性訊息之對應關係與儲存於該電子裝置 :之儲存單元之電路佈設檔案中線路名稱訊息與線路屬性 ..訊息之對應關係是否一致;以及導入模組,係用以於該比 對模組比對㈣電路佈設財巾線路名龍息與線路屬 性訊息之對應關係不-致時,將該儲存單元所儲存之電路 佈設檔案重新導入該佈線應用程式,俾供該佈線應用程式 進行佈線作業。 上述該反向標註(back ann〇tat i〇n)作業係將該印刷 電路板之電路圖案佈設中所涉及之各元件之資料反標回 原理圖、,俾原理圖與電路圖案佈設中的資料保持一致性。 上述該線路屬性訊息係'至少包括有所欲佈設線路之 •層面訊息、線寬、同一線路屬性間之線距以及不同線路屬 性間之線距。 本發明復提供-電路佈設檔案之管理方法,係一且有 儲存單元之電子裝置中,用以輔助一佈線應用程式製;乍一 印刷電路板之電路圖案’於該佈線應用程式中係預設有佈 设於該印刷電路板上的線路名稱訊息及對應之線路屬性 該方法係包括以下步驟:⑴透過該佈線應用程 \订完一反向標註作業後,谓測該電子裝置之儲存單元 中是否儲存有-包含有線路名稱訊息與線路屬性訊息對 9 19986(修正本) 1329819 應關係的電路佈設檔案,若是,則進至步驟(4),若否, ,進至步驟(2) ; (2)依據該佈線應用程式預設的線路 %訊息及對應之線路屬性訊息建立-用以記錄線路盘 線路屬性對應關係的電路佈設檔案,並將該電路佈設權案 儲存至該電子裝置之儲存單元;接著進至步驟(3) ; (f) :透過該佈線應隸式依據反向標註作業之提示修改該印 、刷電路板之原理圖,並將修改後之原理圖導入該佈線應用 程式;接著’進至步驟(4) ; (4)比對該修改後之原理 圖中線路名稱訊息與線路屬性訊息之對應關係、與儲存於 該電子裝置之儲存單元之電路佈設檔案中線路名稱訊自 j路^訊息之對應關係是否—致,若是,則結束步驟 矛若否則進至步驟(5);以及(5)將該電子裝置 ^儲存單摘儲存之電路佈設㈣導U料線應用程 式。 本發明之電路佈設播案之管理系統及方法,係於電路 眷°案的佈設過程中’當㈣該電子裝置並無儲存有-包含 有:路名稱訊息與線路屬性訊息對應關係的電路佈設檔 案時’自動建立-用以記錄線路與線路屬性對應關係的電 路佈设檔案,並於電子工程師將修改後之原理圖導入該佈 ,應用程式並比對該修改後之原理圖中線路名稱訊息與 、’、路屬f生訊心之對應關係與所健存之電路佈設樓案中線 路名稱訊息與線路屬性訊息之對應關經比對係不二致· 可將該所儲存之電路佈設檔案重新導入該佈線應用程 式’俾供該佈線應用程式進行佈線作業。藉以解決習知技 19986(修正本) 10 .街之人工作業過程中由於人爲疏忽而導致佈線應用程式 中線路名稱訊息與線路屬性訊息對應關係產生錯誤的問 、 卜相較於習知技術,以自動化處理替代習知技術 人工作業,可簡化操作流程及節省作業時間,並有效 提高工作效率。 【實施方式】 _ 以下藉由特定的具體實施例說明本發明之實施方 式,熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用,本說明書中的各項細節亦 可基於不同的觀點與應用,在不悖離本發明之精神下進行 各種修飾與變更。 β月參閱第1圖’其係為本發明之電路佈設檔案之管理 系統的基本架構示意圖。該電路佈設檔案之管理系統玉 係應用於一具有儲存單元20之電子裝置2中,用以辅助 鲁一佈線應用程式製作一印刷電路板之電路圖案,於該佈線 . 應用程式中係預設有佈設於該印刷電路板上的線路名稱 — 訊息及對應之線路屬性訊息。於本實施例中,該線路屬性 訊息係至少包括線路之層面訊息、線寬、同一線路屬性間 之線距以及不同線路屬性間之線距。 如圖所示’本發明之電路佈設檔案之管理系統1係包 括4貞測柄組10、槽案建立桓組12、比對模組14以及導入 模組16。 偵測模組10係用以於透過該佈線應用程式執行完一 11 19986(修正本) 1329819 反向標註作業後,偵測該電子裝置2之儲存單元 儲存有-包含有線路名稱訊息與線^ 的電,案’若否’則產生一觸發訊號 =中,該反向標註作業係將該印刷電路板之電路圖= 所涉及之各兀件之資料反標回原理圖,俾原理圖盥電 =:Γ的資料保持一致性,因該反向標註部分係為 業界所熟知之習知技術’故於此不再另行贅述。 檔案建立模組12係用以於接收到該制模組10之觸 發訊號時’依據該佈線應用程式預設的線路名稱訊息及對 應之線路>1性m立記料路與祕屬性對應 關係的電路佈設檔案,並將其儲存至該電子装置2之儲存 單元20。於本實施例中,該電路佈設檔案係以列表形式 來顯示線路與線路屬性之對應關係,但並不以此為限,其 亦可採例如圖表之顯示形式。 比對模組14係用以於電子工程師依據反向標註作業 籲之提示修改該印刷電路板之原理圖,並將修改後之原理圖 . 導入該佈線應用程式後,比對該修改後之原理圖中線路名 ' 稱訊息與線路屬性訊息之對應關係與儲存於該電子裝置 2之儲存單元20之電路佈設檔案中線路名稱訊息與線路 屬性訊息之對應關係予以比對,以比對二者是否一致。於 本實施例中’該原理圖之修改係可包括例如修改元件封 裝、增加網路連接和標號以及增加器件等動作,因修改原 理圖之作業流程係為習知技藝’為業界所熟知且並非本案 之重點,故於此並不再另行贅述。 19986(修正本) 12 1329819 導入模組16係用以於該比對模組14比對得到二者不 -致時’將該儲存單元2G所儲存之電路佈設檔案重新導 入該佈線應驗^ ’俾供該佈線制程行佈線作業。 透過本發明之電路佈設檔案之管理系統1執行本發 明之電路佈設檔案之管理方法流程係如第2圖所示,本發 明之電路佈設檔案之管理方法係包括以下詳細實施步 驟·首先’於步驟S200,透過偵測模組1〇於該佈線應用 ,式執行完-反向標註作業後,偵測該電子裝置2之儲存 早7L 20中是讀存有—包含有線路名稱訊息與線路屬性 ^息對應關係的電路佈設檔案,若是,則進至步驟S 2 〇 4 ; 若否’則進至步驟S2〇2。 。於步驟S202’透過檔案建立模组12依據該佈線應用 程式預》又的線路名稱訊息及對應之線路屬性訊息建立一 用以兄錄線路與線路屬十生對應關係的電路佈設檔案,並將 其儲存至該電子裝置2之儲存單元2()。接著,進至步驟 S204。 於步驟S204 ’電子工程師依據反向標註作業之提示 修改該印刷電路板之原理®,並將修改後之原理圖導入該 佈線應用程式。接著,進至步驟S2〇6。 人 於步驟S206 ’透過比對模組丨4比對該修改後之原理 圖中線路名稱訊息與線路屬性訊息之對應關係與儲存於 該電子裝置2之儲存單元2〇之電路佈設檔案中線路名稱 訊息與線路屬性訊息之對應關係是否一致,若 該步驟流程;若否,則進至步驟漏。 13 19986(修正本) 丄:529819 . 於步驟S2〇8’透過導入模組16將該電子裝置2之儲 存單元2G所儲存之電路佈設檔案導人至該佈線應用程 弋俾供該佈線應用程式進行佈線作業以可避免發生線 路所選擇的線路屬性係為錯誤的情形,確保佈線應用程式 所佈設之線路的正確性。 : 綜上所述,本發明之電路佈設檔案之管理系統及方 法,主要係於電路圖案的佈設過程中,於執行完一反向標 鲁註作業後且偵測該電子裝置並無儲存有一包含有線路名 %訊息與線路屬性訊息對應關係的電路佈設檔案時,自動 建立一用以記錄線路與線路屬性對應關係的電路佈設檔 案,判斷得到沒有電路佈設檔案時,自動建立一用以記錄 2路與線路屬性對應關係的電路佈設檔案,並於後續比對 仔到修改後之原理圖中線路與線路屬性之對應關係與所 儲存之電路佈設檔案中線路與線路屬性之對應關係係為 不一致時,自動將所儲存之電路佈設檔案復原,以供佈設 鲁工程師依據該電路佈設檔案以對修改後之原理圖作相應 .·· 之修正並於電子工程師將修改後之原理圖導入該佈線應 ..用程式並比對該修改後之原理圖中線路名稱訊息與線路 屬性訊息之對應關係與所儲存之電路佈設檔案中線路名 稱訊息與線路屬性訊息之對應關經比對係不一致時,可將 該所儲存之電路佈設檔案重新導入該佈線應用程式俾供 該佈線應用程式進行佈線作業,以可避免習知技術之人工 作業過程中因人爲疏忽而導致佈線應用程式中線路名稱 訊息與線路屬性訊息對應關係產生錯誤情形,確保佈線應 14 19986(修正本) 用私式所佈設之線路的正確性 只费攸 崎性並減少電路圖案佈線後之 汉復修改。另外,本發明之雷玖 ^ , 乃之電路佈设檔案之管理系統及方 法,相較於習知技術之人工作鞏, H ± 讣系了間化刼作流程及節省 作業時間,並有效提高工作效率。 上述實施例#為例示性說明本發明之原理及里功 效’而非用於限制本發明,亦即,本發明事實上仍可 他改變。因此,任何熟習此項技藝之人 發明之精神及料下,對上述 耵上迷貫細•例進行修改。因此本發 明之權利保護範圍,應如後述之申請專利範圍所列。 【圖式簡單說明】 第1圖係顯示本發明之電路佈設檔案之管理系統之 基本架構示意圖;以及 第2圖係顯示本發明之電路佈設檔案之管理方法之 流程示意圖。 【主要元件符號說明】 1 電路佈設檔案之管理系統 10 偵測模組 12 檔案建立模組 14 比對模組 16 導入模組1329819 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a file management technique, and more particularly to the name of a circuit in a wiring application during the laying process of a circuit pattern. A system and method for managing a circuit layout file corresponding to a message and a line attribute message. [Prior Art] At present, in the process of laying out a printed circuit board, a new line attribute is newly created, and the line attributes are regularly set, and then the corresponding line attributes are selected according to the routing requirements of different lines. If the wrong line attribute is read, then the line width 'line distance of the line will be wrong. When the line is laid on the printed circuit board with the wrong line width and line spacing, it will affect the electrical crescent and reduce the line. Or the quality characteristics of printed circuit boards, which will lead to the failure of the entire product. It can be seen that the correct choice of line attributes is critical to the layout of the line. • For example, suppose there is a line +V3M_LAN, the correct line attribute is PG er_2 (L5-5 complex 5_5, that is, the line width of the line is 2 mil, the line spacing between lines is 5 mil; if During the wiring process, the line attribute of +V3M_LAN is misinterpreted as defaul t_ line-attribute, that is, the line width is 5 mil, and the line spacing is 5 mil'. This results in a line width of 5 mils for the route being laid, because the +V3M-LAN system is A power cord requires a wide line width. If the line attribute is misread, t affects the electrical transmission performance of the power line. In particular, the printed circuit board design process is due to the layout engineer 19986 (Revised 6 1329819 = ΓΓ文 schematic diagram, and in the process of modification, it is easy to affect the pre-second, ,, and 4 attributes, causing line attribute errors. Therefore, in order to avoid this question, the field is currently 'before modifying the schematic diagram' The circuit layout file will be established and saved to the corresponding relationship between the recorded line and the line attribute. After the subsequent modification of the schematic diagram, the correspondence between the 2 and the line attributes in the schematic diagram is set to whether or not the circuit is laid on the circuit. Whether the correspondence relationship with the line attribute is consistent, and when it is judged that the two are inconsistent, the circuit layout file of the stored circuit is restored again. However, in the above-mentioned prior art, the establishment of the slot is saved by the circuit, and After the modification of the schematic diagram, the comparison and other operations are performed manually by the layout = programmer. Therefore, the most serious defect is that the stability is poor, which is inevitably due to many factors, including the physiological and psychological factors of the operators themselves. The external environmental influence causes errors in the operation process. In addition, each time the modification of the schematic diagram requires the layout engineer to manually repeat the above actions including saving and restoring, the operation is more complicated and often Because of the artificial sparseness, t, and forget to carry out the corresponding operation = the line attribute is wrong. On the other hand, the operation process is complicated, too much manpower is too time-consuming and costly to 'seek to seek to reduce production costs to increase It is obviously unreasonable for manufacturers of product competitiveness. Therefore, how to overcome the lack of the above-mentioned prior art, and then mention For one kind: to manage the function of circuit layout file in an automated way, in the process of widening the circuit diagram f, avoiding the error caused by human operation in the prior art, the management quality of the 'k幵 circuit layout file, ensuring the circuit layout The correctness of the correspondence between the line name message and the line attribute message in the file can be simplified and the work time can be saved and the work efficiency can be improved. 】 Xin is missing from the above-mentioned prior art. The main purpose of the present invention is to provide a management system and method for circuit layout files, which avoids manual errors and ensures line name information and green road attribute information in circuit layout files. The correctness of the correspondence. The other purpose is to provide a management system and method for simplifying the operation process and saving the operation time of the circuit layout file. A further object of the present invention is to provide a management system and method for a circuit layout file that can improve work efficiency. To achieve the above objects and others, the present invention provides a management system and method for a circuit layout project. The management system for the circuit layout file is applied to an electronic device having a storage unit for assisting a wiring application to fabricate a printed circuit board (Printed Circuit B〇ard, pcB) circuit pattern in the wiring application system. Having a line name message and a corresponding line attribute message disposed on the printed circuit board, the system includes: a detecting module for performing a reverse labeling through the wiring application (back ann〇tati 〇n) after the operation, detecting whether the storage unit of the electronic device stores a circuit layout file containing a correspondence between the line name message and the line attribute message, and if not, generating a trigger signal output; the file creation module is For receiving the trigger signal generated by the detection module, according to the line name message preset by the wiring application and the corresponding line attribute message 'establish a record line and line attribute pair 19986 (corrected version) 8) the circuit layout file is stored and stored in the storage unit of the electronic device; the comparison module is passed through the wiring application According to the reverse labeling operation, the schematic diagram of the printed circuit board is not modified, and the modified schematic diagram is imported into the wiring application, corresponding to the line name information and the line attribute information in the modified schematic diagram. Relationship between the line name message and the line attribute: the correspondence between the information in the circuit layout file of the storage unit of the electronic device: and the import module is used for comparing the comparison module (4) circuit layout When the correspondence between the financial line name and the line attribute information is not correct, the circuit layout file stored in the storage unit is re-imported into the wiring application for the wiring application to perform the wiring operation. The back annotation (back ann〇tat i〇n) operation is to reverse the data of each component involved in the circuit pattern layout of the printed circuit board back to the schematic diagram, the data in the schematic diagram and the circuit pattern layout. Maintain consistency. The above-mentioned line attribute message 'includes at least the layer information of the line to be laid, the line width, the line spacing between the attributes of the same line, and the line spacing between the different line attributes. The method for managing a circuit layout file is provided in an electronic device having a storage unit for assisting a wiring application system; a circuit pattern of a printed circuit board is preset in the wiring application The line name message and the corresponding line attribute disposed on the printed circuit board include the following steps: (1) after the reverse labeling operation is completed through the wiring application, the storage unit of the electronic device is referred to Is there a circuit layout file containing the line name message and the line attribute message pair 9 19986 (Revised) 1329819, if yes, go to step (4), if no, go to step (2); 2) establishing, according to the line % message preset by the wiring application and the corresponding line attribute message, a circuit layout file for recording the correspondence relationship of the line circuit attribute, and storing the circuit layout right to the storage unit of the electronic device Then proceed to step (3); (f): modify the schematic of the printed and brushed circuit board according to the prompt of the reverse marking operation through the wiring, and modify the schematic The schematic diagram is imported into the wiring application; then 'go to step (4); (4) the correspondence between the line name message and the line attribute message in the modified schematic diagram, and the storage unit stored in the electronic device Whether the correspondence between the line name and the message in the circuit layout file is - if, if so, the step of the step ends if the step (5) is entered; and (5) the circuit of the electronic device is stored and stored separately Layout (4) Guide U line application. The management system and method for circuit layout of the present invention is in the process of laying out the circuit '° 'When the electronic device is not stored - the circuit layout file containing the correspondence between the road name message and the line attribute message When 'automatically establishes--the circuit layout file for recording the correspondence between the line and the line attribute, and the electronic engineer introduces the modified schematic diagram into the cloth, and the application compares the line name message in the modified schematic diagram with The correspondence between the line name message and the line attribute message in the circuit layout of the circuit is the same as that of the line circuit. The stored circuit layout file can be re-created. Import the wiring application '俾 for the wiring application to perform routing work. In order to solve the problem that the correspondence between the line name message and the line attribute message in the wiring application is wrong due to human inadvertence during the manual operation of the street. Manual processing instead of conventional technology with automated processing simplifies the operation process and saves time and increases work efficiency. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. Refer to Fig. 1 for the month of the present invention, which is a schematic diagram of the basic structure of the management system for the circuit layout file of the present invention. The management system of the circuit layout file is applied to an electronic device 2 having a storage unit 20 for assisting the Luyi wiring application to fabricate a circuit pattern of the printed circuit board, and the circuit is pre-configured in the application. The name of the line that is placed on the printed circuit board - the message and the corresponding line attribute message. In this embodiment, the line attribute message includes at least the layer information of the line, the line width, the line spacing between the attributes of the same line, and the line spacing between different line attributes. As shown in the figure, the management system 1 for the circuit layout file of the present invention includes a 4-handle handle set 10, a groove set-up group 12, a comparison module 14, and an introduction module 16. The detection module 10 is configured to perform a reverse marking operation after the 11 199819 (Revision) 1329819 operation through the wiring application, and detect that the storage unit of the electronic device 2 stores - contains the line name message and the line ^ The electricity, the case 'if no' generates a trigger signal = medium, the reverse labeling operation is to reverse the circuit diagram of the printed circuit board = the data of the various components involved back to the schematic diagram, 俾 schematic diagram 盥 = : The data of Γ is consistent, and the reverse labeling part is a well-known technique known in the art, and therefore will not be further described herein. The file creation module 12 is configured to: when receiving the trigger signal of the module 10, 'correspond to the line name message preset by the wiring application and the corresponding line>1; The circuit layout file is stored and stored in the storage unit 20 of the electronic device 2. In this embodiment, the circuit layout file displays the correspondence between the line and the line attributes in a list form, but is not limited thereto, and may also be, for example, a display form of a chart. The comparison module 14 is used to modify the schematic diagram of the printed circuit board by the electronic engineer according to the prompt of the reverse marking operation, and the modified schematic diagram is introduced into the wiring application, and the modified principle is compared. Corresponding relationship between the line name 'name message and the line attribute message in the figure and the corresponding relationship between the line name message and the line attribute message in the circuit layout file stored in the storage unit 20 of the electronic device 2 are compared to compare whether the two Consistent. In the present embodiment, the modification of the schematic diagram may include, for example, modifying the component package, adding network connections and labels, and adding devices, etc., since the operation flow of modifying the schematic diagram is a well-known technique is well known in the industry and is not The focus of this case is therefore not repeated here. 19986 (Revised) 12 1329819 The introduction module 16 is used to compare the comparison module 14 to obtain the two-in-one 're-introduction of the circuit layout file stored in the storage unit 2G into the wiring inspection ^ '俾For the wiring process wiring work. The management method for the circuit layout file of the present invention is performed by the management system 1 for the circuit layout file of the present invention. As shown in FIG. 2, the management method of the circuit layout file of the present invention includes the following detailed implementation steps. S200, after the detection module 1 is used in the wiring application, after the execution-reverse labeling operation, detecting that the storage of the electronic device 2 is early 7L 20 is stored in the presence--containing the line name message and the line attribute ^ The circuit layout file of the correspondence relationship, if yes, proceeds to step S 2 〇 4; if not, then proceeds to step S2 〇 2 . . In step S202, a circuit layout file for the relationship between the brother line and the line is established by the file creation module 12 according to the line name message of the wiring application program and the corresponding line attribute message, and Stored in the storage unit 2 () of the electronic device 2. Next, the process proceeds to step S204. In step S204, the electronic engineer modifies the principle of the printed circuit board according to the prompt of the reverse labeling operation, and introduces the modified schematic diagram into the wiring application. Next, the process proceeds to step S2〇6. In step S206, the correspondence between the line name message and the line attribute message in the modified schematic diagram is compared with the line name in the circuit layout file stored in the storage unit 2 of the electronic device 2 through the comparison module 丨4. Whether the correspondence between the message and the line attribute message is consistent, if the step is the flow; if not, the step is leaked. 13 19986 (Revised) 丄: 529819. In step S2〇8', the circuit layout file stored in the storage unit 2G of the electronic device 2 is guided to the wiring application through the import module 16 for the wiring application. The wiring operation is performed to avoid the occurrence of an error in the line attribute selected by the line, and to ensure the correctness of the route laid by the wiring application. In summary, the management system and method for the circuit layout file of the present invention are mainly used in the process of laying out the circuit pattern, and after detecting a reverse labeling operation, detecting that the electronic device does not store an included When a circuit layout file having a line name % message and a line attribute message is associated, a circuit layout file for recording the correspondence between the line and the line attribute is automatically established, and when it is determined that there is no circuit layout file, a record 2 is automatically created. The circuit layout file corresponding to the line attribute, and in the subsequent comparison, the corresponding relationship between the line and the line attribute in the modified schematic diagram and the corresponding relationship between the line and the line attribute in the stored circuit layout file are inconsistent, The stored circuit layout file is automatically restored, so that the layout engineer can make a corresponding correction to the modified schematic according to the circuit layout file, and the electronic engineer will introduce the modified schematic diagram into the wiring. The program compares the correspondence between the line name message and the line attribute message in the modified schematic diagram. When the corresponding relationship between the line name message and the line attribute information in the stored circuit layout file is inconsistent, the stored circuit layout file may be re-imported into the wiring application for the wiring application to perform wiring work, It can avoid the human error caused by the inadvertent technique in the prior art, which causes the line name message and the line attribute information in the wiring application to generate an error condition, and ensure that the wiring should be 14 19986 (amendment). Correctness is only a matter of expense and reduces the modification of the circuit pattern wiring. In addition, the management system and method of the circuit layout file of the present invention are compared with the work of the prior art, and the H± system is used to improve the process and save time, and effectively improve Work efficiency. The above-described embodiment # is illustrative of the principles and functions of the present invention and is not intended to limit the invention, that is, the invention may in fact be changed. Therefore, any person who is familiar with the art can modify the above-mentioned details. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application described below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the basic structure of a management system for a circuit layout file of the present invention; and Fig. 2 is a flow chart showing a management method of a circuit layout file of the present invention. [Main component symbol description] 1 Circuit layout file management system 10 Detection module 12 File creation module 14 Comparison module 16 Import module

電子裝置 儲存單元 S200〜S208步驟 19986(修正本) 15Electronic device storage unit S200~S208 steps 19986 (amendment) 15

Claims (1)

、申請專利範圍: 一種電路佈設檔案之管理系統,係應用於一具有儲存 早兀之電子裝置中,用以輔助一佈線應用程式製作一 P 刷電路板(Printed Circuit Board ’ PCB)之電路圖 案,於該佈線應用程式中係預設有佈設於該印刷電路 板上的線路名稱訊息及對應之線路屬性訊息,該電路 佈設檔案之管理系統係包括: 偵測模組,係用以於透過該佈線應用程式執行完 一反向標註(back annotation)作業後,偵測該電子 裝置之儲存單元是否儲存有一包含有線路名稱訊息 與線路屬性訊息對應關係的電路佈設檔案,若否,則 產生一觸發訊號輸出; 檔案建立模組,係用以於接收到該偵測模組所產 生之觸發訊號時,依據該佈線應用程式預設的線路名 稱訊息及對應之線路屬性訊息,建立一用以記錄線路 與線路屬性對應關係的電路佈設檔案,並將其儲存至 該電子裝置之儲存單元; 比對模組,透過該佈線應用程式依據反向標註作 業之提示修改該印刷電路板之原理圖,並將修改後之 原理圖導入該佈線應用程式後,比對該修改後之原理 圖中線路名稱訊息與線路屬性訊息之對應關係與儲 存於該電子裝置之儲存單元之電路佈設檔案中線路 名稱訊息與線路屬性訊息之對應關係是否一致;以及 ‘入杈組,係用以於該比對模組比對出該電路佈 19986(修正本) 16 設檔案中線路名稱訊息與線路屬性訊息之對 :一致時,將該儲存單元所館存之電路佈設槽、宰:新 =該佈誠、歸式,俾供料職、㈣式進行佈線 2. 如中請專利範圍第!項之電路佈設槽案之管理系統, 其中’該反向標註(back annotation)作業係將 刷電路板之電路圖案佈設中所涉及之各 反標回原理圖。 貝枓 3. 如申請專利範圍第!項之電路佈設槽案之管理方法, 其中’該電路佈設檔案係為列表或圖表之其中—者來 顯示線路名稱訊息與線路屬性訊息之對應關係。 4. 如申請專利範圍第丨項之電路佈設檔案之管理方法, 其中,該線路屬性訊息係至少包括有所欲佈設線路之 層面訊息、線丸、同一線路屬性間之線距以及不同線 路屬性間之線距。 φ 5. —種電路佈設檔案之管理方法,係一具有儲存單元之 電子裝置中,用以辅助一佈線應用程式製作一印刷電 路板之電路圖案,於該佈線應用程式中係預設有佈設 於該印刷電路板上的線路名稱訊息及對應之線路屬 性訊息,該電路佈設檔案之管理方法至少包括以下步 (1)透過該佈線應用程式執行完一反向標註作 業後’彳貞測該電子裝置之儲存單元中是否儲存有一包 含有線路名稱訊息與線路屬性訊息對應關係的電路 17 19986(修正本) 1329819 佈設檔案,若是’則進至步驟⑷,药,則進至 步驟(2); (2) 依據該佈線應用程式預設的線路名稱訊息 及對應之線路屬性訊息建立一用以記錄線路與線路 屬性對應關㈣電路佈設財,並將該電路佈設播案 儲存至該電子裝置之儲存單元;接著進至步驟㈠),· (3) 透過該佈線應用程式依據反向標註作業之 提不修改該印刷電路板之原理圖,並將修改後之原理 圖導入該佈線應用程式;接著,進至步驟(4); (4) 比對該修改後之原理圖中線路名稱訊息與 線路屬性訊息之對應關係與儲存於該電子裝置之^諸、 存單元之電路佈設檔案中線路名稱訊息與線路屬性 訊息之對應關係是否m 若否,則進至步驟(5 );以及 (5) 將該電子裝置之儲存單元所儲存之電路佈 設槽案導入至該佈線應用程式。 6·如申請專利範圍第5項之電路佈設檔案之管理方法, 其中,該反向標註作業係將電路圖案佈設中所涉及之 各元件之資料反標回原理圖。 7·如申請專利範圍第5項之電路佈設檔案之管理方法, 其中,該電路佈設檔案係為列表或圖表之其中一者來 顯示線路與線路屬性之對應關係。 8.如申請專利範圍第5項之電路佈設檔案之管理方法, 其中,該線路屬性訊息係至少包括線路之層面訊阜、 19986(修正本) 18 1329819 線寬、同一線路屬性間之線距以及不同線路屬性間之 線距。Patent application scope: A management system for circuit layout files, which is applied to an electronic device having a storage device for assisting a wiring application to fabricate a circuit pattern of a Printed Circuit Board (PCB). In the wiring application, a line name message and a corresponding line attribute message disposed on the printed circuit board are pre-configured, and the circuit management system includes: a detecting module for transmitting the wiring After the application performs a back annotation operation, it detects whether the storage unit of the electronic device stores a circuit layout file including a correspondence between the line name message and the line attribute message, and if not, generates a trigger signal. The file creation module is configured to, when receiving the trigger signal generated by the detection module, establish a line for recording according to the line name message preset by the wiring application and the corresponding line attribute message. a circuit layout file corresponding to the line attribute and storing it in the storage of the electronic device a unit; a matching module, modifying the schematic of the printed circuit board according to the prompt of the reverse labeling operation by the wiring application, and importing the modified schematic diagram into the wiring application, comparing the modified schematic diagram Whether the correspondence between the line name message and the line attribute message is consistent with the correspondence between the line name message and the line attribute message in the circuit layout file of the storage unit of the electronic device; and the 'input group is used for the ratio Compare the module with the circuit board 19986 (Revised) 16 Set the pair of line name information and line attribute information in the file: When the data is consistent, the circuit stored in the storage unit is slotted, slaughtered: New = The Bucheng , categorization, 俾 supply job, (4) type wiring 2. If the patent scope is the first! The circuit of the item is arranged in a management system for the slot, wherein the 'back annotation' operation is to return the back-to-back schematic diagram involved in the circuit pattern layout of the brush circuit board. Bessie 3. If you apply for a patent range! The management method of the circuit layout slot of the item, wherein the circuit layout file is a list or a chart to display the correspondence between the line name message and the line attribute message. 4. The method for managing a circuit layout file according to the scope of the patent application, wherein the line attribute message includes at least a layer information of the line to be laid, a line pill, a line spacing between the same line attributes, and a different line attribute. Line spacing. Φ 5. A method for managing a circuit layout file, which is an electronic device having a storage unit for assisting a wiring application to create a circuit pattern of a printed circuit board, and the wiring application is pre-arranged in the wiring application The line name message on the printed circuit board and the corresponding line attribute message, the method for managing the circuit layout file includes at least the following steps: (1) performing a reverse labeling operation through the wiring application program Is there a circuit 171998 (Revised) 1329819 for storing the correspondence between the line name message and the line attribute information in the storage unit, if it is 'to proceed to step (4), the medicine proceeds to step (2); And establishing, according to the line name message preset by the wiring application and the corresponding line attribute message, a circuit for collecting the line and the line attribute (4), and storing the circuit layout to the storage unit of the electronic device; Then proceed to step (1)), (3) through the wiring application, according to the reverse labeling operation, the printing is not modified. Brush the schematic of the board and import the modified schematic into the wiring application; then, proceed to step (4); (4) Correspond to the line name message and the line attribute message in the modified schematic Corresponding relationship between the line name message and the line attribute information in the circuit layout file stored in the storage unit of the electronic device is m, if not, proceeding to step (5); and (5) the electronic device The circuit layout slot stored in the storage unit is imported into the wiring application. 6. The management method of the circuit layout file according to item 5 of the patent application scope, wherein the reverse labeling operation reverses the data of each component involved in the circuit pattern layout back to the schematic diagram. 7. The method for managing a circuit layout file according to item 5 of the patent application scope, wherein the circuit layout file system is one of a list or a chart to display a correspondence between the line and the line attribute. 8. The method for managing circuit layout files according to item 5 of the patent application scope, wherein the line attribute information includes at least a line level signal, 19986 (amendment) 18 1329819 line width, line spacing between the same line attributes, and The line spacing between different line attributes. 19 19986(修正本)19 19986 (amendment)
TW95145826A 2006-12-07 2006-12-07 System and method for managing circuit layout files TWI329819B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95145826A TWI329819B (en) 2006-12-07 2006-12-07 System and method for managing circuit layout files

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95145826A TWI329819B (en) 2006-12-07 2006-12-07 System and method for managing circuit layout files

Publications (2)

Publication Number Publication Date
TW200825820A TW200825820A (en) 2008-06-16
TWI329819B true TWI329819B (en) 2010-09-01

Family

ID=44772145

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95145826A TWI329819B (en) 2006-12-07 2006-12-07 System and method for managing circuit layout files

Country Status (1)

Country Link
TW (1) TWI329819B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402710B (en) * 2009-12-16 2013-07-21 Zhen Ding Technology Co Ltd System and method for designing manufacture of printed circuit board
TWI646440B (en) * 2017-07-03 2019-01-01 和碩聯合科技股份有限公司 Circuit comparison method and electronic device
CN114528798A (en) * 2022-02-18 2022-05-24 环荣电子(惠州)有限公司 Printed circuit board element inspection method and system thereof

Also Published As

Publication number Publication date
TW200825820A (en) 2008-06-16

Similar Documents

Publication Publication Date Title
CN103914315B (en) Configuration method of drivers
US7430729B2 (en) Design rule report utility
CN102682166B (en) SMT (Surface Mounted Technology) equipment rapid processing system and method
US8578346B2 (en) System and method to validate and repair process flow drawings
CN108228119A (en) Method of printing, terminal device and storage medium based on HXML
CN110222381B (en) Method, system, medium and terminal for generating dynamic installation guide file for PCB assembly
CN107766040A (en) A kind of method, apparatus and computer-readable recording medium for generating interface document
CN104091161A (en) Schematic circuit diagram netlist comparison method
CN108536915B (en) Method and device for designing bonding pad in PCB design drawing of printed circuit board
TWI329819B (en) System and method for managing circuit layout files
CN105701317A (en) Method and system for correcting signal missing in schematic diagram designing
CN110134596A (en) The generation method and terminal device of test document
CN103208087A (en) Power distribution network data checking method based on international electrotechnical commission (IEC) 61968 standard
CN102707958A (en) Open-platform-based interface generation checking method and equipment
KR20080052368A (en) Cad apparatus and computer readable recording medium having cad program recorded
CN110020414A (en) A kind of electronic contract document creation method, system
CN108287720A (en) software compilation method, device, equipment and storage medium
CN109325221B (en) Method and device for merging table files
Walker Microsoft® office visio® 2007 inside out
CN101201866A (en) System and method for managing circuit laying document
JP2013161370A (en) Edition and verification system for whole product electric specification
CN114565355B (en) Material station table synthesis method, system, equipment and storage medium
JPH11282895A (en) Electric system cad net data verifying method and medium in which electric system cad net data verification program is recorded
CN108875224A (en) The control methods of brd file, device, equipment and the storage medium of correcting and master PCB
JP2004171365A (en) Drawing verification system

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees