1325289 九、發明說明： •「【發明所屬之技術領域】 V —種電路板結構及其形成斷路點之方法 路板電鍍製程中之形成斷路點製程。 尤袪—種电 -【先前技術】 —目前以各種方式封裝完成的積體電路，壯 較内含Β Η夕诿且I ^ m封裝_體邊長 曰’或封裝體的面積是内含 曰曰片面積的Μ倍以内，稱之為晶 、'内：1325289 IX. Description of invention: • "Technical field to which the invention belongs" V - Circuit board structure and method of forming a break point. Forming a break point process in a plate plating process. 尤 袪 - seed type - [prior art] - At present, the integrated circuit is packaged in various ways, and the area of the package is Μ Η 诿 and the area of the package is Μ times the area of the enamel, which is called Crystal, 'inside:
Package Chip Slze Package, CSP) 〇 ? 體的Π裝結構不但體積小，厚度也㈣，晶片到散敎 祖的路徨縮短，而可有效散熱，藉以 政一 -作後之可素洚.v成* 知升日日片在長時間運 聶度，又線路阻抗顯著減小，晶 .幅度提升，進而提升電氣性能與 、&隨之大 有效縮短了信號的傳導距離，其HU夕，⑽封裝 小、容sp封裝之產品體積更 而成^ 熱效果更佳，系統穩定性強， 機封裝技術，特別是應用於手機及數位相 微导輕碍紐小型的電子產品。 教個：ΓΡ封裝用的電路板’係於整片的版面上形成有複 數個矩陣排列的線路單又 接至一 Jt、s 合调線路早兀係稭由排線連 線路軍1導線上’而可藉由該電鐘導線以在該些 、·’ 兀之毛性連接墊上形成如鎳/金之金屬層。 或斷過:中，難免因外在因素造成短路 的叚疵，再加上電路板不斷朝高密度、細 5 19568(修正版） 1325289 • ^層久的方向次進，若未能及時將不良板篩檢出 其流人製程中，勢必造成更多的成本浪費。因此 衣％控制的改善外，提高測試的技術也是可以為電路 Γ造者提供降低報廢率讀升產品㈣轉決方案。在 3子產品的生產過程中，因瑕U造 、個階段都有不_程度，越早發現則補救的成本越低在各 …然而習知CSP電路板於製作完成後，由於電路板表面 兩形成綠漆作為保護層，故不易將 • ^ y π 电路板的共通之電 精確對位切割成為各別獨立的線路，使其上之各個 =路厂仍電性連接在㈣導線上，使得各料路單元之 二仍Λ、“呆持電性連接關係，無法成為獨立的電路，亦不能 :面=電性測試’而採用全面自動光學檢測(Aut0Package Chip Slze Package, CSP) The armor structure of the body is not only small in size, but also in thickness (4). The chip is shortened to the ancestors, and it can be effectively dissipated, so that it can be effectively cooled. * Knowing that the Japanese film is used for a long time, the line impedance is significantly reduced, and the crystal amplitude is increased, which in turn improves the electrical performance, and the large and effective shortening of the signal transmission distance, its HU Xi, (10) package Small, capacitive sp-packaged products are more compact. The thermal effect is better, the system stability is strong, and the machine packaging technology, especially for mobile phones and digital phase micro-guides, is a small electronic product. Teach: The circuit board used for packaging is formed on the entire layout of the board with a plurality of matrix arrays connected to a Jt, s joint line, early stalks, and the line is connected to the line 1 'With the electric bell wire, a metal layer such as nickel/gold can be formed on the bristle connection pads of the . Or break: In the middle, it is inevitable that the short circuit will be caused by external factors, and the circuit board will continue to move toward the high density, fine 5 19568 (corrected version) 1325289 • ^ layer long direction, if not timely, will be bad When the board screen is inspected for its inflow process, it will inevitably result in more waste of costs. Therefore, in addition to the improvement of the % control of the garment, the technology for improving the test can also provide the circuit maker with a plan to reduce the scrap rate and read the product (4). In the production process of 3 sub-products, because of the U-making and the stage, there is no degree. The earlier the discovery, the lower the cost of remediation. However, the conventional CSP board is finished after the production, due to the surface of the board. The green lacquer is formed as a protective layer, so it is not easy to cut the common electrical power of the ^^y π circuit board into separate lines, so that each of the above-mentioned road factories is still electrically connected to the (four) wires, so that each The second element of the material path unit is still "staying in electrical connection, cannot be an independent circuit, nor can it be: surface = electrical test" and adopts full automatic optical inspection (Aut0
Inspe_ 但A0I全檢對#站生產負擔非 V ’且產品檢驗所f耗㈣間亦相當長，間接影響其他 產品之生產時間。 為解決電路板於製造完成後，將各個線路單元與共通 的電鍍導線切斷，使各個線路單元 平70成為獨立線路以供電性 測试，而另如弟1八至1D所示之習知製法。 士如第Μ圖所示，提供-電路板10，於該電路板 之衣面具有複數係如焊墊(bond finger)或球塾㈣之 電性連接心2,且該電性連接墊12係藉由導電線路 性連接至-電鐘導線U,並於該電路板1〇之表面形成有 :焊層广且該防焊層15形成有第一開孔i5i以露出該 电性遷料！2,又該防焊層15形成有第二開孔⑸以露 ]9568(修正版） 6 .出該導電線路】3之部份。 :如第1B圖所示，接著於該電路叛】 •:化阻層16， 冉心成一圖案 而僅路出該第一開孔151中之電 而可於該電性達接執 Μ接塾】2 ’ ^ 银一 12表面-电錄形成金屬保護層1 7。 .如* 1C圖所*，然後移除該阻層 孔152令之部份的導電線路13。 路出該弟二開 中之Si圖：示，最後_製程移除該第二開孔I” '性連接，且確保得而Λ利於後續該電性連接墊12進行電 侵立確保不發生電性短路。 與加程需施加及移除阻層16’導致製程步驟 J日加，使製程時間延長。 /评 為解決上述習知技術之缺失， 夹凼專利弟 6,660,559 政用阻層即可移除導線之製程，如第 至2C圓所示。 々如弟2Α 請參閱第2Α圖，提供一兩枚4 fF, jl ^ ，、电路板2〇 ,於該電路板2〇 具有複數電性連接塾22，且該電性連接塾Μ係藉 甴導包線路23電性連接至一電 曰 20 ^ , 电鍍筝線24，並於該電路板 之表面形成有防焊層25，且兮 ,ςι ^ 且該防焊層25形成有第一開 孔251，俾以路出該電性連接墊22。 請爹閱第2Β圖，接箸，於該 中的電性連接墊22表面電^^25<卜開孔251 〜 ρ ®私鎮形成-金屬保護層26，而可 藉由該防焊層25保護該此導命φ 金屬保護層。 …線…面不被電錢形成 請參閱第2C圖，該防焊層以係為雷射光束可炼化之 19568(修正版) 7 1325289 材質；又於該防焊層25表面位於導電線路23之上方預留 V—欲形成開孔之區域，得以雷射光束在該區域進行移除， 而在該防焊層25形成第二開孔252，並且切斷位在該防焊 層25下方之部分導電線路23，俾使該電性連接墊22獨立 .以確保不發生電性短路。 上述之習知製程雖可免除使用阻層所引起的製程步 驟增加、時間增長之缺失；然而，藉由雷射移除部分防焊 層及覆蓋其下之部分導電線路，容易導致切斷處有銅渣及 -高溫碳化物殘留，此類殘留物在產品進行AEI(Auto Electrical Inspection) 測試時容易導致線路微短路 (Micro-short)。 因此，如何提出一種避免習知採用阻層導致製程步驟 /增加、時間增長，或以雷射移除防焊層及覆蓋其下之電鍍 導線所引起的銅渣及碳化物殘留等缺失，實以成爲目前業 界亟待克服之難題。 【發明内容】 鑒於上述習知技術之種種缺點，本發明之主要目的在 於提供一種電路板結構及其形成斷路點之方法，得以清除 雷射製程殘留於電路板上之殘渣，藉以避免後續電路板之 電性測試製程中發生線路之微短路（micro-short)的情況。 本發明之再一目的在於提供一種電路板結構及其形 成斷路點之方法，得以降低製程成本，並縮短製程時間。 為達上述及其他目的，本發明提出一種電路板結構形 成斷路點之方法，主要係包括：提供至少一表面形成有圖 8 19568(修正版)Inspe_ However, the A0I full inspection pair #站 production burden is not V ’ and the product inspection f consumption (4) is also quite long, which indirectly affects the production time of other products. In order to solve the problem that the circuit board is completely cut after the completion of the manufacture, the circuit unit is cut off from the common electroplating wire, so that each line unit 70 becomes an independent line for power supply test, and the other is a conventional method as shown in the brothers 18 to 1D. . As shown in the figure, a circuit board 10 is provided, and a plurality of electrical connection cores 2 such as bond fingers or ball joints (4) are provided on the clothing surface of the circuit board, and the electrical connection pads 12 are The conductive layer is connected to the electric bell wire U, and the surface of the circuit board 1 is formed with a wide solder layer and the solder resist layer 15 is formed with a first opening i5i to expose the electric retentive material! 2, the solder resist layer 15 is formed with a second opening (5) to expose the portion of the conductive line 3 of the 9486 (revision). : as shown in FIG. 1B, following the circuit rebellion: • the resistive layer 16 is formed into a pattern and only the electricity in the first opening 151 is taken out, and the electrical connection can be connected. 】 2 ' ^ Silver - 12 surface - lithography to form a metal protective layer 17 . As shown in Fig. 1C, the conductive line 13 of the resist hole 152 is removed. The Si diagram of the second opening of the brother is shown: the last_process removes the second opening I" 'sexual connection, and ensures that the electrical connection pad 12 is subsequently electrically intruded to ensure that no electricity occurs. Slight short circuit. The addition and removal of the resist layer 16' with the addition process leads to a J-day addition of the process step, which prolongs the process time. /Improved the lack of the above-mentioned conventional technology, and the patented resistance of the patented brother 6,660,559 can be moved. Except for the wire manufacturing process, as shown in the 2nd to the 2nd circle. 々如弟2Α Please refer to the 2nd drawing, providing one or two 4 fF, jl ^ , and the circuit board 2〇, which has multiple electrical connections on the circuit board 2〇塾22, and the electrical connection is electrically connected to the electric circuit 20^ by the guiding package line 23, the electroplating kite wire 24 is formed, and the solder resist layer 25 is formed on the surface of the circuit board, and 兮, ςι ^ The solder resist layer 25 is formed with a first opening 251 for routing the electrical connection pad 22. Please refer to the second drawing, and the surface of the electrical connection pad 22 is electrically ^^25< The opening 251 ~ ρ ® is formed into a metal protective layer 26, and the conductive metal layer can be protected by the solder resist layer 25. The surface is not formed by the electric money. Please refer to FIG. 2C. The solder resist layer is made of 19568 (revision) 7 1325289 which can be refining the laser beam; and the surface of the solder resist 25 is located above the conductive line 23. Retaining V—the area where the opening is to be formed, the laser beam is removed in the area, and the second opening 252 is formed in the solder resist layer 25, and a part of the conductive line under the solder resist 25 is cut. 23. The electrical connection pad 22 is made independent to ensure that no electrical short circuit occurs. The above-mentioned conventional process can eliminate the increase of the process steps and the lack of time increase caused by the use of the resist layer; however, by the laser shift In addition to the partial solder mask and some of the conductive traces underneath it, it is easy to cause copper slag and high-temperature carbide residue at the cut-off. Such residues are likely to cause short-circuits on the line when the product is tested by AEI (Auto Electrical Inspection). Micro-short. Therefore, how to avoid the copper slag and carbide residue caused by the conventional use of the resist layer to cause the process steps/increase, time increase, or laser removal of the solder resist and the underlying plating wires Missing In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a circuit board structure and a method for forming a circuit breaker point, which can remove the laser process residue. Residue on the circuit board to avoid micro-short of the circuit in the subsequent electrical test process of the circuit board. A further object of the present invention is to provide a circuit board structure and a method for forming a circuit breaker point, To reduce the process cost and shorten the process time. To achieve the above and other objects, the present invention provides a method for forming a circuit breaker structure to form a break point, which mainly comprises: providing at least one surface formed with FIG. 8 19568 (revision)
案化線路；J •;八 θ心艰戟板，而該線路層係由複數電鍍導線縱橫 ^割成複數趣_狀祕單元，且該⑽單元藉由複 ·:=線，接該電鐵導線，並於該承载板之表面線路層形成 成|知層，以雷射光束（Laser beam )於該防焊層上形 在開孔，並持續以雷射光束切斷該排線，使該排線 .、支汗孔中形成近完全分斷而仍帶有排線殘邊的斷·點；以及 排線殘潰’以使該斷點完全分斷，且使該排 / 王成對之微蝕側壁，該成對之微蝕側壁所對庫之 ^層㈣的下緣隸料於該成狀微侧壁之上= 相對距離。 〜丄缘的 t述清理該開孔與排線殘渣之製程係以蝕刻溶液 進行微M (Mic⑺Etch—)製程俾 、王*除開孔中於雷射㈣及切割製程所產生的殘逢。 該承載板係為兩層或多層電路板之其中—者， 电路板係可為-CSP電路板，且該線路層係為鋼材料 板製法，復提供—種電路板結構，係包括承載 戒乂有圖茱化之線路層，而該線路層係由複數電鑛導線 縱核W成複數個矩陣排列之線路單元，且該 2 以排線連接該電料線；以及防焊層，係形成於該承= 之表面線路層上，該料層形成有上寬下窄且呈 狀之開孔’又該開孔下之排線已切斷而該斷點口:上:下 :側Γ=斷點經觸程清理該開孔而呈成對二 ，’：成對之微卿所對應之防焊層開 二 從係小於竣成對之微蝕側壁之上緣的相對距離。Ί 】9568(修正版) 9 •以干^之包路板結構及其形成斷路點之方法’主要係 ·.:·斷二複i直接在防焊層上形成閑孔並持續以雷射光束切 習知使用阻層之缺失，並可簡化製程步 刻故该:衣程時間；此外，本發0㈣於雷射製程後藉由姓 除殘留於該電路板之電錢導線材料及碳化物進 。避免後績電性測試時發生線路短路。 【實施方式】 二下係藉由特定的具體實施例說明本發明之實施方 式’熟悉此技蔽夕X丨γ μ μ 、.、 .瞭解本發明明書所揭示之内容輕易地 S月之其他優點與功效。 I構及第'AW圖所示’係為本發明之電路板 形成斷路點之方法之上視及製程剖面示意圖。 ^參閲第3圖及4Α圖，首先提供—至少—表面形成 夕:Γ化線路層〕2之承栽板3〇，該承載板30係為兩層或 :::路板’其中該電路板係可為一 csp電路板，而該線 曰係，鋼材料製成丨又該線路層32係由複數電鍍導 2a縱秩分割成複數個矩陣排列之線路單元32b，且該 2路早兀32b藉由複數排線32c連接該電鍍導線32a，且 ^ X承载板之表面線路層形成一防焊層33，於本實施例 ^該防焊層33係以印刷、旋塗及貼合之任—方式將該防 叶s 33塗覆於該承載板表面。 印苓閱第4B圖，以t射光東（Laser beam )於該防焊 ^ 乂上形成至少一開孔33()，該開孔”。係呈雷射燒灼 八並持續以雷射光束切斷該排線32c，使該排線32c在 19568(修正版) 10 1325289 開孔330中形成近完全分斷而仍帶有排線殘潰仏的斷點。 *；.而在形成該開孔33〇後，於該開孔330中殘留有殘渣 ‘/33a，該殘渣33&係為上述雷射製程中切斷排線32c時之排 線材=(齡）及該防焊層33經高溫f射形成的碳化物。 •請參閱第4C ®，最後進行微#製程，藉祕刻溶液 .(etching solution )如硫酸雙氧水溶液清除該開孔33〇與 其中之排線殘渣33a，以使該斷點完全分斷，並且使該排 線32C之斷點呈成對之微蝕侧壁32cl，該成對之微蝕侧壁 32cl所對應之防焊層閛孔33〇的下緣孔徑係小於該成對之 微蝕側壁32cl之上緣酌相對距離，以避免殘留的殘渣造成 微短路而影響電性測武，俾使該電鍍導線32a與線路單元 32b分開，且使該線略單元32b成為獨立單元，以利後續 -進行電性測試。 依上述之製法，本發明復揭露一種電路板結構，包 括.具有圖案化之線路層32的承載板30，而該線路層32 係由複數電鐘導線32a縱橫分割成複數個矩陣排列之線路 早元32b ’且該線路豕元32b以排線32c連接該電鍍導線 32a;以及防焊層33，係形成於該承載板30表面之線路層 32上’該防焊層33形成有上寬下窄之開孔330，於該開孔 330下之排線32c係經雷射先束切斷而該斷點口係上寬下 窄，且該排線32c之斷點經徵蝕製程清理開孔330而呈成 對之微钱側壁32cl，該成對之微蝕側壁32cl所對應之防 焊層開孔330的下緣扎徑係小於該成對之微蝕側壁32cl 之上緣的相對距離。 11 19568(修正版) 1325289 • •該承載板30係為一絕緣板或具有線路之電路板，i .该電路板係為- CSP電路板，而該線 ㈣ Ϊ料製成。 吩尽知為銅材 ^於習知技術’本發明之電路板結構及其形成斷路 =射==光束直接在防烊層形成開孔，並 1、射先束㈣該用以電性連接電链導線及線 :的排線’以免㈣知技術必須上阻層之缺失，而 =程步驟、縮短製程時I此外，本發 ^ .==溶液清除殘留於該電路板之電鑛導線材：： 、而可避免後續電性測試時發生微短路的缺失。 上述實施例僅為例示性說明本發明之原理及^苴 :二=於限制本發明。任何熟習此項技藝之人士均； 之不逐$本發明之瀚神及範疇 盥鐵仆。円μ· . ^ 了上这貫鉍例進行修飾 直二匕Θ此’本發明之權利保護範圍，應如後 寻vj乾圍所列。 月 【圖式簡單說明】 第1入至1D圖普為習知切斷電性連接塾與 間的導電線路的製衰上視圖； “ ;x 第2A至2CaH系為美國專利第6,66〇,5 視圖； 5此心衣征上 第3圖係為本發明之電·結構上視示意圖；以及 力a之剖面不意圖。 【主要元件符號說明】 19568(修正版) 12 1325289 10 ' 20 電路板 '•12、22 電性連接墊 -·;_13、23 導電線路 14 、 24 、 32a f鍍導線 • 15、25、33 防焊層 151 、 251 零 第一開孔 152 ' 252 第二開孔 16 限層 17、26 金屬保護層 30 禾載板 32 象路層 / 32b 象路單元 32c 排線 32cl 敬蝕側壁 330 閑孔 33a 幾:渣 13 ]9568(修正版)Case circuit; J •; eight θ heart hard board, and the circuit layer is cut from a plurality of electroplated wires into a plurality of interesting elements, and the (10) unit is connected to the electric iron by a complex:== line And forming a conductive layer on the surface circuit layer of the carrier plate, forming a laser beam on the solder resist layer to form an opening, and continuously cutting the cable with a laser beam, so that the wire Cable, the formation of a nearly complete break in the sweat hole and still with the broken edge of the line; and the line collapse 'to make the break point completely broken, and make the row / Wang paired The micro-etched sidewalls, the pair of micro-etched sidewalls, the lower edge of the layer (4) of the library are placed above the formed micro-walls = relative distance.丄 的 的 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理 清理The carrier board is one of two or more layers of circuit boards, and the circuit board can be a -CSP circuit board, and the circuit layer is made of a steel material plate method, and the circuit board structure is provided, including a load ring. a circuit layer having a circuitized layer, wherein the circuit layer is a line unit in which a plurality of electric ore wires longitudinal nucleus W are arranged in a plurality of matrixes, and the 2 is connected to the electric material line by a wire; and the solder resist layer is formed on the On the surface circuit layer of the substrate, the material layer is formed with an opening having a width and a narrow upper and lower shape, and the cable under the opening has been cut off and the break point is: upper: bottom: side Γ = broken The point is cleaned by the contact to form the pair of holes, and the pair of the solder resist layer corresponding to the pair is less than the relative distance of the upper edge of the micro-etched side wall of the pair. Ί 】 9568 (Revised Edition) 9 • The structure of the road board with dry ^ and its method of forming a break point 'main system ·.: · 断二复i directly forming a free hole on the solder resist layer and continuing the laser beam It is customary to use the absence of the barrier layer, and can simplify the process steps: the clothing time; in addition, the hair 0 (4) after the laser process by the surname in addition to the remaining money on the circuit board wire material and carbide into . Avoid short circuit when the post-test electrical test is performed. [Embodiment] The following describes an embodiment of the present invention by a specific embodiment. 'Familiar with this technique X 丨 γ μ μ , . , . Advantages and effects. The I structure and the 'AW diagram' are schematic diagrams of the above-mentioned method and the process profile for forming a circuit breaker point of the circuit board of the present invention. ^ Referring to Figures 3 and 4, firstly, at least - a surface forming layer: a siliconization circuit layer 2, a carrier board 3 is provided, the carrier board 30 is a two layer or::: a road board 'where the circuit The board system can be a csp circuit board, and the line is made of a steel material, and the circuit layer 32 is divided into a plurality of matrix line units 32b by a plurality of vertical plating guides 2a, and the two lines are early. 32b is connected to the plated wire 32a by a plurality of wires 32c, and the surface circuit layer of the X-loading plate forms a solder resist layer 33. In the embodiment, the solder resist layer 33 is printed, spin-coated and bonded. - The method applies the leaf guard s 33 to the surface of the carrier plate. Referring to FIG. 4B, at least one opening 33 () is formed on the solder resist by a Laser beam, which is laser-burned and continuously cut by a laser beam. The wire 32c causes the wire 32c to form a break point in the opening of the 19568 (revision) 10 1325289 hole 330 which is nearly completely broken and still has a wire breakage. *; After the crucible, a residue '/33a remains in the opening 330, and the residue 33& is the wire rod (the age) when the wire 32c is cut in the above laser process, and the solder resist layer 33 is irradiated by the high temperature f Carbide formed. • Refer to 4C®, and finally perform the micro-process, and remove the opening 33〇 and the wire residue 33a therein by using an etching solution such as an aqueous solution of sulfuric acid to make the break point. Fully broken, and the break point of the wire 32C is paired with the micro-etched sidewall 32cl, and the lower edge of the solder resist pupil 33〇 corresponding to the pair of micro-etched sidewalls 32cl is smaller than the diameter The relative distance between the upper edge of the micro-etching sidewall 32cl is avoided to avoid the micro-short circuit caused by the residual residue, which affects the electrical measurement, so that the plated wire 32a and the wire are The circuit unit 32b is separated, and the line unit 32b is made into a separate unit for subsequent electrical testing. According to the above method, the present invention discloses a circuit board structure including: a carrier having a patterned circuit layer 32. The circuit board 32 is divided into a plurality of matrix-arranged line early elements 32b' by a plurality of electric clock wires 32a, and the circuit unit 32b is connected to the plated wires 32a by a wire 32c; and a solder resist layer 33, The soldering layer 33 is formed on the circuit layer 32 on the surface of the carrier plate 30. The solder resist layer 33 is formed with an upper opening and a narrow opening 330. The cable 32c under the opening 330 is cut by a laser beam. The break point is wide and narrow, and the break point of the wire 32c is formed by the etch process cleaning hole 330 to form a pair of micro-money side walls 32cl, and the pair of micro-etching sidewalls 32cl correspond to the solder resist layer The lower edge of the hole 330 is smaller than the relative distance of the upper edge of the pair of microetched side walls 32cl. 11 19568 (Revised) 1325289 • The carrier plate 30 is an insulating board or a circuit board having a line, i The board is made of - CSP board, and the line (4) is made of tantalum. Copper material according to the prior art 'the circuit board structure of the invention and its formation open circuit = shot == beam directly forms an opening in the anti-mite layer, and 1, the first beam (four) is used to electrically connect the electric chain wire and the wire : The wiring line 'to avoid (four) knowing that the technology must be missing the resist layer, and = step, shorten the process I. In addition, the hair ^.== solution removes the electric ore wire remaining on the circuit board:: The absence of a micro-short circuit occurs during subsequent electrical testing. The above-described embodiments are merely illustrative of the principles of the invention and the following: Anyone who is familiar with this skill will not be able to pay for the invention and the scope of the invention.円μ· . ^ This is a modification of the example. The scope of protection of this invention should be as follows. Month [Simple description of the diagram] The first entry to the 1D map is a conventional view of the fading of the electrically conductive lines connecting the electrical connections; "x" 2A to 2CaH is US Patent No. 6,66 5 views; 5 This is the top view of the electrical and structural diagram of the present invention; and the profile of the force a is not intended. [Main component symbol description] 19568 (revision) 12 1325289 10 ' 20 circuit Board '•12, 22 Electrical connection pad-·;_13, 23 Conductive line 14, 24, 32a f plated wire • 15, 25, 33 solder mask 151, 251 zero first opening 152 ' 252 second opening 16 limited layer 17, 26 metal protective layer 30 and carrier board 32 image layer / 32b image unit 32c line 32cl eroded side wall 330 idle hole 33a several: slag 13 ] 9568 (revision)