TWI413199B - Dummy substrate strip for testing - Google Patents
Dummy substrate strip for testing Download PDFInfo
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- TWI413199B TWI413199B TW97146833A TW97146833A TWI413199B TW I413199 B TWI413199 B TW I413199B TW 97146833 A TW97146833 A TW 97146833A TW 97146833 A TW97146833 A TW 97146833A TW I413199 B TWI413199 B TW I413199B
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- substrate strip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
本發明係有關於半導體裝置之基板條，特別係有關於一種測試用空白基板條。The present invention relates to a substrate strip for a semiconductor device, and more particularly to a blank substrate strip for testing.
按，在半導體(積體電路)封裝構造之完整製程中應經過多個製造程序，例如黏晶(Die Bond)、打線(Wire Bond)以及封膠(Molding Compound)等製程，而這些製程均需要專業的半導體封裝機台設備，才能將半導體晶片製成為半導體封裝構造。除了封裝類型的多樣化，每一封裝廠區所使用的半導體封裝機台與封裝材料也不盡相同，故為確定產品設計完整度能與廠內半導體封裝機台與現用的封裝材料達到完美匹配，應針對封裝類型調整各個製程中所使用半導體封裝機台的參數設定，例如黏晶製程的參數設定、打線製程的參數設定以及封膠製程的參數設定。然而目前的方式為使用設計完成的實際基板條進行半導體封裝機台的參數設定，以使產品能符合高產生率的量產要求。就實際基板條而言，須依照欲製造之封裝類型，加以設計基板條上打線接墊的形成位置以及線路層的配置圖樣，故在封裝製程之模擬測試中一般具有特殊線路結構之實際基板條無法達到共用性之要求。並且，由基板製造廠製出實際基板條並運輸到封裝廠需要一段時間，又進入到封裝廠之後到排入製造行程的間隔亦不一定有足夠的時間來作機台參數的調整與設定。Press, in the complete process of semiconductor (integrated circuit) package structure, there should be a number of manufacturing processes, such as Die Bond, Wire Bond, and Molding Compound, which are required for these processes. Professional semiconductor packaging machine equipment can make semiconductor wafers into semiconductor package construction. In addition to the variety of package types, the semiconductor packaging machine and packaging materials used in each package site are not the same, so to determine the product design integrity can be perfectly matched with the in-house semiconductor packaging machine and the current packaging materials. The parameter settings of the semiconductor packaging machine used in each process should be adjusted for the package type, such as the parameter setting of the die bonding process, the parameter setting of the wire bonding process, and the parameter setting of the sealing process. However, the current method is to use the actual substrate strip designed to perform the parameter setting of the semiconductor packaging machine, so that the product can meet the high production rate mass production requirements. In terms of the actual substrate strip, the formation position of the wire bonding pad on the substrate strip and the layout pattern of the circuit layer must be designed according to the type of package to be manufactured, so the actual substrate strip having a special wiring structure is generally included in the simulation test of the packaging process. Unable to meet the requirements for sharing. Moreover, it takes a certain period of time for the substrate manufacturer to produce the actual substrate strip and transport it to the packaging factory, and the interval between the entry into the packaging factory and the discharge into the manufacturing process does not necessarily have sufficient time for the adjustment and setting of the machine parameters.
為了解決上述之問題，本發明之主要目的係在於提供一種測試用空白基板條，能取代實際基板條以模擬在各式半導體封裝或是模組構造之製程，以降低模擬測試之成本。由於該測試用空白基板條具有共用性，能在實際基板條進廠之前可以預先進行封裝機台之參數調整與設定。In order to solve the above problems, the main object of the present invention is to provide a test blank substrate strip which can replace the actual substrate strip to simulate various semiconductor package or module construction processes to reduce the cost of the simulation test. Since the test blank substrate strip has the common property, the parameter adjustment and setting of the packaging machine can be performed in advance before the actual substrate strip enters the factory.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種測試用空白基板條，主要包含一基板核心層、一導電層、一防焊層以及一鍍金層。該基板核心層係具有一表面。該導電層係形成於該基板核心層之該表面。該防焊層係形成於該基板核心層上，該防焊層係具有一第一開口，以使該導電層之對應顯露部位模擬為一模封區，其中該導電層係完全鋪滿該模封區，以使該基板核心層不外露於該模封區。該鍍金層係形成於該導電層顯露於該第一開口內的部位。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a blank substrate strip for testing, which mainly comprises a substrate core layer, a conductive layer, a solder mask layer and a gold plating layer. The substrate core layer has a surface. The conductive layer is formed on the surface of the core layer of the substrate. The solder resist layer is formed on the core layer of the substrate, the solder resist layer has a first opening, so that the corresponding exposed portion of the conductive layer is simulated as a mold sealing region, wherein the conductive layer completely covers the mold The sealing zone is such that the substrate core layer is not exposed to the molding zone. The gold plating layer is formed on a portion of the conductive layer that is exposed in the first opening.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述的測試用空白基板條中，該鍍金層係可概為該基板核心層之該表面三分之一。In the foregoing test blank substrate strip, the gold plating layer may be substantially one third of the surface of the substrate core layer.
在前述的測試用空白基板條中，該導電層係可為一銅箔。In the foregoing test blank substrate strip, the conductive layer may be a copper foil.
在前述的測試用空白基板條中，該導電層係可概呈矩形並全面覆蓋該基板核心層之該表面。In the aforementioned test blank substrate strip, the conductive layer may be substantially rectangular and completely cover the surface of the substrate core layer.
在前述的測試用空白基板條中，該導電層係可缺乏線路，以使該測試用空白基板條為無電性功能之虛基板條。In the foregoing test blank substrate strip, the conductive layer may lack a line, so that the test blank substrate strip is a virtual substrate strip having no electrical function.
在前述的測試用空白基板條中，該防焊層係可更具有複數個第二開口，係排列鄰近於該基板核心層之一長側邊，以使該導電層之對應顯露部位模擬為複數個注澆口。In the foregoing test blank substrate strip, the solder resist layer may further have a plurality of second openings arranged adjacent to one of the long sides of the substrate core layer, so that the corresponding exposed portions of the conductive layer are simulated as plural A note gate.
在前述的測試用空白基板條中，該防焊層係可更具有一開槽，係連接該些第二開口，以使該導電層之顯露部位形成為梳狀。In the foregoing test blank substrate strip, the solder resist layer may further have a slit for connecting the second openings so that the exposed portion of the conductive layer is formed into a comb shape.
在前述的測試用空白基板條中，該防焊層係可更具有複數個第三開口，係排列於該基板核心層之該表面之周邊，以使該導電層之對應顯露部位模擬為複數個晶片定位標記。In the foregoing test blank substrate strip, the solder resist layer may further have a plurality of third openings arranged around the surface of the substrate core layer to simulate a corresponding exposed portion of the conductive layer into a plurality of Wafer positioning mark.
在前述的測試用空白基板條中，該第一開口係可為封閉狀，以使該鍍金層不延伸到該基板核心層之該表面之周邊。In the foregoing test blank substrate strip, the first opening may be closed such that the gold plating layer does not extend to the periphery of the surface of the substrate core layer.
在前述的測試用空白基板條中，可另包含有至少一空白晶粒，係設置於該鍍金層上。In the foregoing test blank substrate strip, at least one blank crystal grain may be further included on the gold plating layer.
在前述的測試用空白基板條中，該空白晶粒係可為一鋁晶粒。In the foregoing test blank substrate strip, the blank crystal grain may be an aluminum crystal grain.
由以上技術方案可以看出，本發明之測試用空白基板條，具有以下優點與功效：It can be seen from the above technical solutions that the blank substrate strip for testing of the present invention has the following advantages and effects:
一、利用測試用空白基板條之防焊層、導電層與鍍金層之形成位置關係，能使測試用空白基板條模擬以取代實際基板條運用於各式半導體封裝構造或模組構造之製程，以進行機台參數之調整與設定，故能降低模擬測試之成本。並由於該測試用空白基板條具有共用性，能在實際基板條進廠之前可以預先進行封裝機台之參數調整與設定，使調機時間更有彈性。1. Using the positional relationship between the solder resist layer of the blank substrate strip for testing and the conductive layer and the gold plating layer, the test blank substrate strip can be simulated to replace the actual substrate strip for the various semiconductor package structures or module construction processes. In order to adjust and set the parameters of the machine, the cost of the simulation test can be reduced. And because the test blank substrate strip has the common property, the parameter adjustment and setting of the packaging machine can be performed in advance before the actual substrate strip enters the factory, so that the tuning time is more flexible.
二、由於鍍金層覆蓋由防焊層定義之模封區，並可如同實際基板條之複數個位於特定位置的接墊，在模擬製程中銲線能接合在鍍金層之任意部位，使測試用空白基板條具有共用性。2. Since the gold plating layer covers the molding area defined by the solder resist layer, and can be used as a plurality of pads of the actual substrate strip at a specific position, the soldering wire can be bonded to any part of the gold plating layer in the simulation process for testing. Blank substrate strips have commonality.
三、由於測試用空白基板條不需設置複雜的線路，故能降低其設計成本，並可簡化其製程。Third, since the blank substrate strip for testing does not need to be provided with complicated wiring, the design cost can be reduced, and the manufacturing process can be simplified.
四、由於空白晶粒用以模擬一般的晶片，且空白晶粒用以與銲線接合的表面為一鋁面，如同一般晶片上之複數個鋁墊，銲線能接合在空白晶粒的鋁面之任意部位，故設置於鍍金層上的空白晶粒具有共用性。4. Since the blank die is used to simulate a general wafer, and the surface on which the blank die is bonded to the bonding wire is an aluminum surface, like a plurality of aluminum pads on a general wafer, the bonding wire can be bonded to the aluminum of the blank die. Since any part of the surface, the blank crystal grains provided on the gold plating layer have commonality.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之一具體實施例，一種測試用空白基板條舉例說明於第1圖之表面示意圖以及第2、3圖之截面示意圖。該測試用空白基板條100主要包含一基板核心層110、一導電層120、一防焊層130以及一鍍金層140。該測試用空白基板條100係作為半導體封裝或模組製程中之晶片承載件，所製成之各式半導體封裝構造並不需要有實際的電性功能，其主要目的在於模擬實際基板條在各個製程的參數設定。該基板核心層110係具有一表面111。通常該表面111係為該基板核心層110進行製程處理之表面。通常該基板核心層110係由介電材料所組成，例如FR-3、FR-4之玻璃纖維布含浸樹脂或聚亞醯胺(PI)。According to an embodiment of the present invention, a test blank substrate strip is exemplified in a schematic view of the surface of Fig. 1 and a schematic cross-sectional view of Figs. 2 and 3. The test blank substrate strip 100 mainly comprises a substrate core layer 110, a conductive layer 120, a solder resist layer 130 and a gold plating layer 140. The test blank substrate strip 100 is used as a wafer carrier in a semiconductor package or a module process, and various semiconductor package structures are not required to have actual electrical functions, and the main purpose thereof is to simulate actual substrate strips in each Parameter setting of the process. The substrate core layer 110 has a surface 111. Typically, the surface 111 is the surface on which the substrate core layer 110 is subjected to a process. Typically, the substrate core layer 110 is composed of a dielectric material such as FR-3, FR-4 glass fiber cloth impregnated resin or polyamidamine (PI).
請參閱第2及3圖所示，該導電層120係形成於該基板核心層110之該表面111。該導電層120係可採用壓合(laminating)、電鍍(plating)、塗層(coating)等技術形成。在本實施例中，該導電層120係可為一銅箔。該導電層120係可概呈矩形並全面覆蓋該基板核心層110之該表面111。較佳地，該導電層120係可缺乏線路，以使該測試用空白基板條100為無電性功能之虛基板條，故該測試用空白基板條100在製造上不需要形成線路結構的蝕刻步驟，藉此減少該測試用空白基板條100之成本並使其具有通用性。Referring to FIGS. 2 and 3, the conductive layer 120 is formed on the surface 111 of the substrate core layer 110. The conductive layer 120 can be formed by techniques such as laminating, plating, coating, and the like. In this embodiment, the conductive layer 120 can be a copper foil. The conductive layer 120 can be substantially rectangular and completely cover the surface 111 of the substrate core layer 110. Preferably, the conductive layer 120 lacks a line, so that the blank substrate strip 100 for testing is a virtual substrate strip having no electrical function, so the blank substrate strip 100 for testing does not need to be formed into an etching step of the wiring structure. Thereby, the cost of the test blank substrate strip 100 is reduced and made versatile.
請參閱第2圖所示，該防焊層130係形成於該基板核心層110上。當該導電層120為全面覆蓋之結構時，該防焊層130係覆蓋於該導電層120上。當該導電層120為局部覆蓋之結構時，該防焊層130係同時覆蓋於該導電層120與該基板核心層110上。該防焊層130係可以塗佈、印刷或貼覆等方式形成。該防焊層130之材質可為感光高分子的絕緣材料，例如綠漆。請參閱第1圖所示，該防焊層130係具有一第一開口131，以使該導電層120之對應顯露部位模擬為一模封區。換言之，該模封區之大小是由該防焊層130之第一開口131所定義。而該模封區係為在半導體封裝或模組製程中被一封膠體模封覆蓋的區域。通常在該模封區內會先設置複數個晶片並以銲線連接晶片與該測試用空白基板條100，再進行壓模作業以使封膠體密封晶片與銲線。Referring to FIG. 2, the solder resist layer 130 is formed on the substrate core layer 110. When the conductive layer 120 is a fully covered structure, the solder resist layer 130 covers the conductive layer 120. When the conductive layer 120 is partially covered, the solder resist layer 130 covers the conductive layer 120 and the substrate core layer 110 at the same time. The solder resist layer 130 can be formed by coating, printing, or laminating. The material of the solder resist layer 130 may be an insulating material of a photosensitive polymer, such as green paint. Referring to FIG. 1 , the solder resist layer 130 has a first opening 131 to simulate a corresponding exposed portion of the conductive layer 120 as a mold sealing region. In other words, the size of the die seal region is defined by the first opening 131 of the solder resist layer 130. The encapsulation region is an area covered by a gelatinous encapsulation in a semiconductor package or module process. Usually, a plurality of wafers are first disposed in the mold sealing region, and the wafer and the blank substrate strip 100 for testing are connected by wire bonding, and then a molding operation is performed to seal the wafer and the bonding wire.
此外，請參閱第2及3圖所示，該導電層120係完全鋪滿該模封區，以使該基板核心層110不外露於該模封區，以供在該模封區進行電鍍。在本實施例中，該第一開口131係可為矩形。請參閱第1圖所示，該防焊層130係可更具有複數個第二開口132，係排列鄰近於該基板核心層110之一長側邊112，以使該導電層120之對應顯露部位模擬為複數個注澆口121。該導電層120可具有顯露於該些第二開口132之部位。在壓模注膠之過程中，封膠體係由該些注澆口121注入，並覆蓋該模封區(即該第一開口131)。該些注澆口121係為等距排列，以使多注入管道之封膠體在該測試用空白基板條100上具有較為一致之流速。在本實施例中，該些第二開口132係為指狀並連通至該長側邊112，以形成開放式之開口。在本實施例中，該防焊層130係可更具有一開槽133，係連接該些第二開口132，以使該導電層120之顯露部位形成為梳狀。該開槽133係可為長條狀以串接該些第二開口132，並且該開槽133的延伸方向係與鄰近之該長側邊112為平行。請參閱第1圖所示，該導電層120對應該開槽133之部位係為顯露，並可形成一連接條122。故該連接條122係與該長側邊112為平行，並連接該些注澆口121，故能維持較為平衡的模流速度，並有助於脫模。請參閱第1圖所示，該防焊層130係可更具有複數個第三開口134，係排列於該基板核心層110之該表面111之周邊，以使該導電層120之對應顯露部位模擬為複數個晶片定位標記。在黏晶過程中，黏晶機台設備係藉由該些晶片定位標記之定位與引導將晶片設置於該測試用空白基板條100在該模封區內之適當位置。較佳地，該些開口131、132與134與該開槽133係可以曝光與顯影該防焊層130方式同時完成。In addition, as shown in FIGS. 2 and 3, the conductive layer 120 completely covers the mold region so that the substrate core layer 110 is not exposed to the mold region for plating in the mold region. In this embodiment, the first opening 131 can be rectangular. As shown in FIG. 1 , the solder resist layer 130 further has a plurality of second openings 132 arranged adjacent to one of the long sides 112 of the substrate core layer 110 such that corresponding portions of the conductive layer 120 are exposed. The simulation is a plurality of gates 121. The conductive layer 120 can have a portion exposed to the second openings 132. During the molding of the molding, the sealing system is injected from the gates 121 and covers the molding region (ie, the first opening 131). The gates 121 are arranged equidistantly such that the sealant of the multi-injection tube has a relatively uniform flow rate on the test blank substrate strip 100. In this embodiment, the second openings 132 are finger-shaped and communicate with the long sides 112 to form an open opening. In this embodiment, the solder resist layer 130 may further have a slit 133 connecting the second openings 132 such that the exposed portion of the conductive layer 120 is formed into a comb shape. The slot 133 can be elongated to connect the second openings 132 in series, and the slot 133 extends in a direction parallel to the long side 112 adjacent thereto. Referring to FIG. 1 , the conductive layer 120 is exposed to the portion where the groove 133 is to be formed, and a connecting strip 122 may be formed. Therefore, the connecting strip 122 is parallel to the long side 112 and is connected to the gates 121, so that a relatively balanced mold flow speed can be maintained and the mold release can be facilitated. As shown in FIG. 1 , the solder resist layer 130 may further have a plurality of third openings 134 arranged around the surface 111 of the substrate core layer 110 to simulate a corresponding exposed portion of the conductive layer 120 . Positioning markers for a plurality of wafers. In the die bonding process, the die bonding machine device positions the wafer in the proper position of the test blank substrate strip 100 in the molding region by positioning and guiding the wafer positioning marks. Preferably, the openings 131, 132 and 134 and the slot 133 can be completed simultaneously by exposing and developing the solder resist layer 130.
請參閱第2及3圖，該鍍金層140係形成於該導電層120顯露於該第一開口131內的部位，即是位於該模封區內。該鍍金層140係可被打線接合，以使該鍍金層140可以模擬複數個位置可任意變化之基板條接墊，以提供任意的打線接合位置。此外，該鍍金層140是一薄金層，可用以防止該導電層120之氧化。Referring to FIGS. 2 and 3, the gold plating layer 140 is formed in a portion of the conductive layer 120 exposed in the first opening 131, that is, in the mold sealing region. The gold plating layer 140 can be wire bonded so that the gold plating layer 140 can simulate a plurality of substrate strips that can be arbitrarily changed to provide any wire bonding position. In addition, the gold plating layer 140 is a thin gold layer that can be used to prevent oxidation of the conductive layer 120.
因此，該測試用空白基板條100具有共用性。在本實施例中，當實際基板條具有三個(或多個)模封區時，該測試用空白基板條100可具有單一個模封區，使得該鍍金層140係可概為該基板核心層110之該表面111三分之一，能節省該鍍金層140的形成面積。晶片與銲線之接合皆可在該鍍金層140上。因此，本發明僅需一個模封區便可完成模擬實際基板條在各個製程的參數設定，能縮短模擬的時間以及降低成本。請參閱第1及2圖所示，更具體地，該第一開口131係可為封閉狀，以使該鍍金層140不延伸到該基板核心層110之該表面111之周邊。Therefore, the test blank substrate strip 100 has commonality. In this embodiment, when the actual substrate strip has three (or more) molding regions, the test blank substrate strip 100 may have a single molding region, such that the gold plating layer 140 can be substantially the substrate core. One third of the surface 111 of the layer 110 can save the formation area of the gold plating layer 140. Bonding of the wafer to the bonding wire can be performed on the gold plating layer 140. Therefore, the present invention only needs one mold sealing zone to complete the parameter setting of the actual substrate strip in each process, which can shorten the simulation time and reduce the cost. Referring to FIGS. 1 and 2 , more specifically, the first opening 131 may be closed such that the gold plating layer 140 does not extend to the periphery of the surface 111 of the substrate core layer 110 .
請參閱第4及5圖所示，該測試用空白基板條100可另包含有至少一空白晶粒150，係利用一黏晶材料160之黏貼設置於該鍍金層140上，用以模擬實際晶粒在基板條上的黏晶參數設定。該空白晶粒150係用以模擬一記憶體晶片之尺寸但可不具有積體電路或其它主動元件。較佳地，該空白晶粒150係可為一鋁晶粒，即在矽片上鋪設一整面鋁層，以使該空白晶粒150具有一鋁質金屬面151。而該鋁質金屬面151係作為該空白晶粒150被銲線連接之一表面。因此，該鋁質金屬面151可供打線接合點為任意位置，該鋁質金屬面151可模擬實際晶片之複數個鋁墊，以使該空白晶粒150具有共用性。較佳地，該空白晶粒150係可由鋁晶圓切割形成，故能提供任意尺寸或厚度之空白晶粒150。As shown in FIGS. 4 and 5, the test blank substrate strip 100 may further include at least one blank die 150 disposed on the gold plating layer 140 by a bonding of a die bonding material 160 for simulating the actual crystal. The grain size parameter of the grain on the substrate strip is set. The blank die 150 is used to simulate the size of a memory chip but may not have integrated circuitry or other active components. Preferably, the blank die 150 can be an aluminum die, that is, a full-face aluminum layer is laid on the die, so that the blank die 150 has an aluminum metal face 151. The aluminum metal surface 151 is used as a surface on which the blank crystal grains 150 are joined by a bonding wire. Therefore, the aluminum metal surface 151 can be used for any position of the wire bonding joint, and the aluminum metal surface 151 can simulate a plurality of aluminum pads of the actual wafer to make the blank crystal grains 150 have commonality. Preferably, the blank die 150 is formed by cutting from an aluminum wafer, so that blank die 150 of any size or thickness can be provided.
由於銲線之一端可打線連接在該空白晶粒150之該鋁質金屬面151之任意部位，又銲線之另一端可打線連接在該測試用空白基板條100之該鍍金層140之任意部位。故由銲線形成之銲線配置圖案可為任意。故藉由該鍍金層140與該空白晶粒150可模擬多種不同的實際打線，以調整打線機台的參數設定。請參閱第6圖所示，在第一種銲線配置圖案中，複數個銲線210係由該空白晶粒150之兩相對側邊連接至該鍍金層140。請參閱第7圖所示，在第二種銲線配置圖案中，複數個銲線220係由該空白晶粒150之四周邊連接至該鍍金層140。此外，使用本發明之該測試用空白基板條100可在封膠製程中檢測該些銲線210或220的偏移情形。請參閱第8圖所示，在封膠時，一封膠體230係由該些注澆口121注入，並形成於該測試用空白基板條100上，以密封該空白晶粒150以及該些銲線210。Since one end of the bonding wire can be wire-bonded to any portion of the aluminum metal surface 151 of the blank die 150, and the other end of the bonding wire can be wire-bonded to any portion of the gold plating layer 140 of the test blank substrate strip 100. . Therefore, the wire bonding pattern formed by the bonding wires can be any. Therefore, the gold plating layer 140 and the blank die 150 can simulate a plurality of different actual wire bonding to adjust the parameter setting of the wire bonding machine. Referring to FIG. 6, in the first bonding wire arrangement pattern, a plurality of bonding wires 210 are connected to the gold plating layer 140 from opposite sides of the blank die 150. Referring to FIG. 7 , in the second wire bonding pattern, a plurality of bonding wires 220 are connected to the gold plating layer 140 from the periphery of the blank die 150 . In addition, the use of the blank substrate strip 100 for testing of the present invention can detect the offset of the bonding wires 210 or 220 during the encapsulation process. Referring to FIG. 8 , a seal 230 is injected from the gates 121 and formed on the test blank substrate strip 100 to seal the blank die 150 and the solders. Line 210.
因此，該測試用空白基板條100可模擬實際基板條在半導體封裝構造或模組構造之各個製程的參數設定，例如晶片設置、打線連接以及封膠等，以便於實際基板條進來時，可以直接排入製程以節省調機時間。此外，可藉由該測試用空白基板條100之該鍍金層140以取代實際基板條之複數個位於特定位置之接墊，使該些銲線210或220能接合在該鍍金層140之任意部分，故可滿足多種半導體封裝構造或模組構造中銲線與基板條之間的打線接合位置，不需另外設計特定線路結構的基板條，故能降低測試時所需的基板成本。並且，該空白晶粒150之該鋁質金屬面151可以取代實際晶片上之複數個鋁墊，使得該些銲線210或220能接合在該鋁質金屬面151之任意部分，故可滿足多種半導體封裝構造或模組構造中銲線與晶片之間的打線接合位置，而不需另外設計特定的晶片，故能降低調整與設定機台測試時所需的成本。Therefore, the test blank substrate strip 100 can simulate the parameter setting of the actual substrate strip in each process of the semiconductor package structure or the module structure, such as wafer setting, wire bonding, and sealing, so that when the actual substrate strip comes in, it can directly Discharge into the process to save time. In addition, the bonding wires 210 or 220 can be bonded to any portion of the gold plating layer 140 by the gold plating layer 140 of the blank substrate strip 100 of the test to replace the plurality of pads of the actual substrate strip at a specific position. Therefore, the wire bonding position between the bonding wire and the substrate strip in a plurality of semiconductor package structures or module structures can be satisfied, and the substrate strip of the specific wiring structure is not required to be additionally designed, thereby reducing the substrate cost required for testing. Moreover, the aluminum metal surface 151 of the blank die 150 can replace a plurality of aluminum pads on the actual wafer, so that the bonding wires 210 or 220 can be bonded to any part of the aluminum metal surface 151, so that various types can be satisfied. The wire bonding position between the bonding wire and the wafer in the semiconductor package structure or the module structure can reduce the cost required for the adjustment and setting of the machine test without separately designing a specific wafer.
由上述可知，該測試用空白基板條100可模擬實際基板條進行在各式半導體封裝構造或模組構造之製程，以節省調機時間，並且在測試時該鍍金層140能滿足不同的打線形成位置之需要，而不需另外設計特定線路結構的基板條或使用到實際基板條。It can be seen from the above that the test blank substrate strip 100 can simulate the actual substrate strip to be processed in various semiconductor package structures or module configurations to save the tuning time, and the gold plating layer 140 can meet different wire formation during testing. The position is required without the need to additionally design a substrate strip of a particular wiring structure or to use an actual substrate strip.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
100．．．測試用空白基板條100. . . Blank substrate strip for testing
110．．．基板核心層110. . . Substrate core layer
111．．．表面111. . . surface
112．．．長側邊112. . . Long side
120．．．導電層120. . . Conductive layer
121．．．注澆口121. . . Gate gate
122．．．連接條122. . . Connecting strip
130．．．防焊層130. . . Solder mask
131．．．第一開口131. . . First opening
132．．．第二開口132. . . Second opening
133．．．開槽133. . . Slotting
134．．．第三開口134. . . Third opening
140．．．鍍金層140. . . Gold plating
150．．．空白晶粒150. . . Blank grain
151．．．鋁質金屬面151. . . Aluminum metal surface
160．．．黏晶材料160. . . Clay material
210．．．銲線210. . . Welding wire
220．．．銲線220. . . Welding wire
230．．．封膠體230. . . Sealant
第1圖：為依據本發明之一具體實施例的一種測試用空白基板條之表面示意圖。Figure 1 is a schematic view showing the surface of a test blank substrate strip in accordance with an embodiment of the present invention.
第2圖：為依據本發明之一具體實施例的測試用空白基板條沿第1圖2-2剖切線之截面示意圖。Fig. 2 is a cross-sectional view showing a blank substrate strip for testing according to an embodiment of the present invention taken along line 2-2 of Fig. 1;
第3圖：為依據本發明之一具體實施例的測試用空白基板條沿第1圖3-3剖切線之截面示意圖。Figure 3 is a cross-sectional view of a test blank substrate strip taken along line 1 - 3-3 of Figure 1 in accordance with an embodiment of the present invention.
第4圖：為依據本發明之一具體實施例的測試用空白基板條上設有空白晶粒之表面示意圖。Figure 4 is a schematic view showing the surface of a blank substrate for testing on a blank substrate strip according to an embodiment of the present invention.
第5圖：為依據本發明之一具體實施例的測試用空白基板條上設有空白晶粒之截面示意圖。Fig. 5 is a schematic cross-sectional view showing the provision of blank crystal grains on a test blank substrate strip according to an embodiment of the present invention.
第6圖：為依據本發明之一具體實施例的測試用空白基板條在製程中形成第一種銲線配置圖案並在封膠前之表面示意圖。Fig. 6 is a schematic view showing the surface of a first type of bonding wire in a process for forming a first bonding wire arrangement pattern in a process according to an embodiment of the present invention.
第7圖：為依據本發明之一具體實施例的測試用空白基板條在製程中形成第二種銲線配置圖案並在封膠前之表面示意圖。Figure 7 is a schematic view showing the surface of the test blank blank in the process of forming a second wire bonding pattern in the process according to an embodiment of the present invention.
第8圖：為依據本發明之一具體實施例的測試用空白基板條在製程中形成第一種銲線配置圖案並在封膠後之截面示意圖。Figure 8 is a cross-sectional view showing the first type of bonding wire arrangement pattern in the process of the blank substrate strip for testing according to an embodiment of the present invention and after sealing.
100．．．測試用空白基板條100. . . Blank substrate strip for testing
110．．．基板核心層110. . . Substrate core layer
112．．．長側邊112. . . Long side
120．．．導電層120. . . Conductive layer
121．．．注澆口121. . . Gate gate
122．．．連接條122. . . Connecting strip
130．．．防焊層130. . . Solder mask
131．．．第一開口131. . . First opening
132．．．第二開口132. . . Second opening
133．．．開槽133. . . Slotting
134．．．第三開口134. . . Third opening
140．．．鍍金層140. . . Gold plating
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| TW200810636A (en) * | 2006-08-08 | 2008-02-16 | Phoenix Prec Technology Corp | Printed circuit board structure and method for forming broken circuit point |
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2008
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200810636A (en) * | 2006-08-08 | 2008-02-16 | Phoenix Prec Technology Corp | Printed circuit board structure and method for forming broken circuit point |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201023283A (en) | 2010-06-16 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |