TWM556409U - Substrate structure - Google Patents

Abstract

A substrate structure includes a wafer bonding area, a board edge area, at least one first metal stop structure and at least one first metal peripheral structure. The wafer bonding area is used for at least one semiconductor wafer to be disposed thereon. The board edge area includes a glue injection area and a stamping area. The glue injection area is adjacent to and surrounds the wafer bonding area, and is used for forming an encapsulation material thereon. The die area surrounds the glue injection area and is used for pressing the lower surface of one of the glue filling molds onto it. The first metal stop structure is adjacent to a first surface of the board edge area, and substantially completely surrounds the wafer bonding area. The first metal stop structure is located in the die area. The first metal peripheral structure is adjacent to the first surface of the board edge region and surrounds the first metal stop structure.

Description

Substrate structure

The present invention relates to a substrate structure, and more particularly to a substrate structure for a semiconductor package element.

A substrate for a semiconductor package structure usually includes a central die bonding area and a side rail area located around the die bonding area. The board edge area is mainly to assist the substrate to be stably placed on the carrier during subsequent processes (such as die bonding, wire bonding, molding, and cutting) to avoid operations During the process, a problem occurs in that components (such as wafers, wires, and molding compounds, etc.) cannot be accurately placed on the substrate due to the substrate position shift. Therefore, the board edge area of the substrate will be designed with a plurality of pin holes that can be provided by the positioning pins of the bearing platform, so that when the substrate is moved to the bearing platform, the positioning of the board edge area can be used. The holes correspond to the positioning pins of the carrier to achieve the positioning effect. It is worth noting that because the board edge area has a supporting function, the outermost two sides (upper side and bottom side) need to be covered with a certain amount of copper to help strengthen / support the structure of the entire substrate. In addition to the above functions, the setting of copper in the edge area of the board can also be used to reduce the degree of warpage and deformation of the substrate after baking (that is, an appropriate copper residual rate can adjust the degree of warpage and deformation of the substrate). In addition, when there is an electrical connection relationship between the copper in the board edge area and the wafer bonding area, the copper in the board edge area can also assist the plating operation of the upper / lower surface of the substrate. It should be noted that the board edge area will be cut off after the packaging process is completed, so it only appears at the stage before the packaging process.

In one or more embodiments, a substrate structure includes a die bonding area, a side rail area, at least one first metal stop structure and at least one first metal peripheral structure. The wafer bonding area is used for at least one semiconductor wafer to be disposed thereon. The board edge area includes a glue injection area and a stamping area. The glue injection area is adjacent to and surrounds the wafer bonding area, and is used for forming an encapsulation material thereon. The die area surrounds the glue injection area and is used for pressing the lower surface of one of the glue filling molds onto it. The first metal stop structure is adjacent to a first surface of the board edge area, and substantially completely surrounds the wafer bonding area. The first metal stop structure is located in the die area. The first metal peripheral structure is adjacent to the first surface of the board edge region and surrounds the first metal stop structure.

The copper distribution design of the board edge area of the substrate may have three forms: a full copper type, a mesh type, and an L-shaped bar (L bar). The first all-copper distribution is a copper metal layer or a large area copper metal layer in the board edge area. However, because the copper layer is a dielectric layer (that is, the copper layer is formed and located on the dielectric layer), and the thermal expansion coefficient (CTE) of the copper metal and the dielectric layer is very different, during the baking process Under the effect of the heat rise, the larger the copper design, the easier it is to delaminate with the dielectric layer of the substrate. That is, the copper layer is easily separated from the dielectric layer (this is because there is too much stress and no space can eliminate the stress). Once the delamination occurs, it will cause failure in subsequent plating (because it will affect the stability of the plating fixture in contact with the plating grip), or it will affect the support strength when the board edge area actually provides support functions. Therefore, the occurrence of delamination will affect the structural strength and electrical function of the board edge area. The second type of network distribution is to form a plurality of copper metal line segments crossing each other in the edge area of the board to form at least one network structure. Compared with the above all-copper design, the mesh design has enough space to disperse the stress of copper and avoid delamination. However, due to the excessive space, the substrate may be subjected to subsequent molding. The encapsulating gel will flow directly from the gap between the independent net and the net to the outermost edge of the board edge area to form a bleed out. After that, the overflow of the glue at the outermost edge of the board edge area needs to be handled separately to avoid causing jamming of the subsequent machine, which will reduce the overall process efficiency. The third type of L-shaped stripe distribution is to form a complex array of L-shaped stripe copper metals in the edge area of the plate. Each group is a generally rectangular shape formed by two L-shaped stripe copper metals corresponding to each other. A generally rectangular shape has a curved gap. In this distribution, although the proportion of copper metal and space is between the above two distributions, because the shape of the L-shaped strip copper metal is designed to be asymmetric, the stress cannot be averaged by space during thermal expansion. It is dispersed, so there is still a risk of delamination between the copper metal and the dielectric layer, and during the molding process, the encapsulant often flows to the side edge of the substrate through the gap between adjacent generally rectangular shapes. Furthermore, there is also a problem of stress concentration at the corners of a single L-shaped strip-shaped copper metal. The manufacturing method of the substrate structure and the semiconductor package component discussed below uses a metal stop structure to reduce the problem of overflowing glue. FIG. 1 depicts a schematic top view of an example of a substrate structure 1 according to some embodiments of the present invention, in which a first solder resist layer and a first surface treatment layer are omitted. FIG. 2 depicts an enlarged schematic view of an area A in the substrate structure 1 according to FIG. 1. The substrate structure 1 includes a first portion (eg, a die bonding area 2), a second portion (eg, a side rail area 3), at least one first metal stop structure 4, At least one first metal peripheral structure 5, at least one first metal inner peripheral structure 7, and a plurality of positioning holes 103. As shown in FIG. 1, the substrate structure 1 may be a strip type substrate structure. In other embodiments, the substrate structure 1 may also be a panel type substrate structure. The first part (for example, the wafer bonding area 2) is used for mounting at least one semiconductor wafer 24 (FIG. 12) thereon. As shown in FIG. 1, the first part (for example, the wafer bonding area 2) includes a plurality of (for example, 2 * 8 = 16) unit areas 21. Each area unit 21 is defined by a plurality of intersecting first boundary lines 20, and is used for at least one semiconductor wafer 24 (FIG. 12) disposed therein. In one embodiment, the first dividing lines 20 are imaginary cutting lines. It should be noted that in some embodiments, the first dividing lines 20 may be solid lines, that is, they may be actual line segments. Each area unit 21 has a first circuit layer 12 therein. The first circuit layer 12 is adjacent to a first surface 101 (FIG. 3) of the first portion (for example, the wafer bonding area 2). The first circuit layer 12 includes a plurality of conductive traces 121, a plurality of conductive pads 122, and a plurality of conductive fingers 123. It can be understood that the layouts of the first circuit layers 12 in all such regional units 21 may be consistent with each other. In addition, after the subsequent molding process, a cutting process can be performed along the first boundary lines 20, so each area unit 21 will remain in each final product (ie, the semiconductor package component 11 (Figure 19)) in. The second part (for example: the board edge area 3) surrounds / encloses the first part (for example: the wafer bonding area 2). That is, the first part (for example, the wafer bonding area 2) is located at the middle position of the substrate structure 1, and the second part (for example: the board edge area 3) is located at the peripheral position of the substrate structure 1. The second part (for example, the board edge area 3) includes a glue injection area 31 and a stamping area 32. As shown in FIG. 1, in an embodiment, the injection area 31 and the stamping area 32 are distinguished by a second boundary line 30, and the second boundary line 30 and the first boundary line 20 are the outermost. The circles are substantially parallel, and the second boundary line 30 surrounds / encloses the outermost circle of the first boundary line 20. The injection area 31 is located between the second boundary line 30 and the outermost circle of the first boundary line 20, and the stamping area 32 is located at the outermost side of the second boundary line 30 and the substrate structure 1. Between the edges. It should be noted that, in some embodiments, the second boundary line 30 may be an imaginary line; however, the second boundary line 30 may also be a solid line, that is, it may be an actual line. The glue injection area 31 is adjacent to and surrounds / encloses the first part (for example, the wafer bonding area 2), and is used for forming an encapsulating material 28 (FIG. 14) on the subsequent molding process. It can be understood that the first part (for example, the wafer bonding area 2) can also be used for forming the encapsulating material 28 (FIG. 14) thereon during the molding process. Therefore, after the molding process, the second boundary line 30 is the boundary line (that is, the outer contour line) of the encapsulant 28 (FIG. 14). In other words, the area surrounded by the second dividing line 30 will be filled with the encapsulation material 28 (FIG. 14) (the encapsulation material 28 will cover the injection area 31 and the first part (for example, the wafer bonding area 2 )), And there is no encapsulant 28 outside the second boundary 30. The die area 32 surrounds the injection area 31, that is, the die area 32 is farther from the first part than the injection area 31 (eg, the wafer bonding area 2). The molding area 32 is used for pressing a lower surface 901 of a glue mold 90 (FIG. 13) onto the molding area before the molding process. In other words, the lower surface 901 of the potting mold 90 is pressed / covered on the stamping area 32, and the cavity 902 of the potting mold 90 corresponds to / accommodates the potting area 31 and the first portion (for example, : The wafer land 2). The first metal stop structure 4 is adjacent to a first surface 101 (FIG. 3) of the second portion (for example, the board edge region 3), and substantially completely surrounds / encloses the first portion (for example, the wafer bonding). Zone 2). That is, the first metal stop structure 4 is a continuous ring structure; or, the first metal stop structure 4 may have a small gap in some places to form a discontinuous ring structure. In one embodiment, the first metal stop structure 4 is located in the die area 32 and is very close to the second boundary line 30. The first metal stop structure 4 is substantially parallel to the second boundary line 30, and the first metal stop structure 4 surrounds / encloses the second boundary line 30. Alternatively, in an embodiment, the second boundary line 30 is located on the inner side of the first metal stop structure 4 (or on the inner side of the solder resist layer covering the first metal stop structure 4 side). Therefore, during the molding process, the entire first metal stop structure 4 is pressed by the potting mold 90 (FIG. 13), so that the cavity 902 of the potting mold 90 forms a closed space. In one embodiment, the injection port of the injection mold 90 may be located on a small section of the first metal stop structure 4. After that, the encapsulating material 28 (FIG. 14) will not overflow to the stamping area 32 after filling the cavity 902, but will only be located in the injection area 31 and the first part (for example, the wafer bonding area 2 ). As shown in FIG. 2, the first metal stop structure 4 is a strip-shaped structure and has a substantially single width W ₁ . The width W ₁ is between 0.05 mm and 0.5 mm, between 0.1 mm and 0.4 mm, or between 0.2 mm and 0.3 mm. The first metal peripheral structure 5 is adjacent to the first surface 101 (FIG. 3) of the second portion (for example, the board edge region 3), and surrounds / encloses the first metal stop structure 4. In one embodiment, the first metal peripheral structure 5 and the first metal stop structure 4 are located on the same layer, and the materials are all made of copper and formed at the same time. The first metal peripheral structure 5 is located in the die area 32 to balance the copper residual rate and stress of the substrate structure 1 as a whole. The first metal peripheral structure 5 includes a plurality of first peripheral metal blocks 51 and a plurality of first peripheral metal connecting sections 52. The first peripheral metal blocks 51 are spaced apart from each other (eg, arrayed), and surround / enclose the first metal stop structure 4. In the embodiment of FIGS. 1 and 2, the first metal peripheral structure 5 includes a plurality of rows (for example, six rows) of the first peripheral metal blocks 51, and the positions of the first peripheral metal blocks 51 of adjacent rows are aligned with each other. Each of these first peripheral metal blocks 51 is a convex polygon including at least three sides (eg, triangle, square, rectangle, convex pentagon or convex hexagon, etc.), a circle or an ellipse, The shape of the first peripheral metal block 51 can avoid the problem of stress concentration. The first peripheral metal connecting sections 52 are connected to the first peripheral metal blocks 51, and can be connected to the first peripheral metal blocks 51 and the first metal stop structure 4, and can be connected to the first metal stop Structure 4 and the first metal inner surrounding structure 7. As shown in FIG. 2, in an embodiment, the minimum distance G between any two of the first peripheral metal blocks 51 adjacent to each other is between 0.1 mm and 0.3 mm. This gap G has enough space to disperse the stress of copper and avoid delamination. The maximum width W ₂ of the first peripheral metal block 51 is between 0.2 mm and 0.4 mm. The maximum width W ₃ of the first peripheral metal connecting section 52 is less than or equal to 0.3 mm, less than or equal to 0.2 mm, or less than or equal to 0.1 mm. The first metal peripheral structure 5 may further include at least one first meshed metal structure 53 and a plurality of first plating pinch points 55. The first mesh metal structure 53 is formed by a plurality of copper metal line segments crossing each other. The pattern of the first mesh metal structure 53 is different from the patterns of the first peripheral metal blocks 51, both of which are located on the same layer, and the material is both copper and formed at the same time. Therefore, the first mesh metal structure 53 can also be used to balance the copper residual rate and stress of the substrate structure 1 as a whole. The first plating clamping points 55 are used to clamp the plating chuck of a plating device during the plating process, so that the current of the plating device can enter the substrate structure 1 through the first plating clamping points 55. In one embodiment, the first plating pinches 55 are electrically connected to the first circuit layer 12. For example, the first plating pinch 55 may be electrically connected via the first peripheral metal connection section 52, the first peripheral metal block 51, the first metal stop structure 4 and the first metal inner structure 7. Connected to the first circuit layer 12. The first metal inner structure 7 is adjacent to the first surface 101 (FIG. 3) of the second part (for example, the board edge region 3), and the first metal stop structure 4 and the first part (for example: Between the wafer lands 2). That is, the first metal inner surrounding structure 7 is located in the injection area 31 and between the second boundary line 30 and the outermost circle of the first boundary line 20, and surrounds / encloses the first portion (for example, : The wafer land 2). In one embodiment, the first metal inner peripheral structure 7, the first metal peripheral structure 5, the first metal stop structure 4 and the first circuit layer 12 are located on the same layer, and the materials are all copper, and at the same time form. The first metal inner peripheral structure 7 can also be used to balance the residual copper rate and stress of the substrate structure 1 as a whole. In one embodiment, the first metal inner periphery structure 7 includes a plurality of first inner periphery metal blocks 71 and a plurality of first inner periphery metal connecting sections 72. The first inner metal blocks 71 are spaced apart from each other (eg, arranged in a row), and surround / enclose the first portion (eg, the wafer bonding area 2). Each of these first inner metal blocks 71 is a convex polygon including at least three sides (eg, triangle, square, rectangle, convex pentagon or convex hexagon, etc.), a circle or an oval The above-mentioned shape of the first inner metal block 71 can avoid the problem of stress concentration. In one embodiment, the shape and size of the first inner metal block 71 are substantially the same as the shape and size of the first outer metal block 51. The first inner metal connecting sections 72 are connected to the first inner metal block 71 and the first metal stop structure 4, and can be connected to the first inner metal block 71 and the first circuit layer 12. In one embodiment, the width of the first inner metal connection segment 72 is substantially the same as the width of the first outer metal connection segment 52. The positioning holes 103 pass through the substrate structure 1 and are located outside the substrate structure 1, and are used for positioning. The positioning holes 103 are for the position pins of the machine to pass through, so that when the substrate structure 1 is placed on the machine, the position on the horizontal plane is fixed, and no horizontal displacement will occur. 3 is a schematic cross-sectional view taken along line II according to FIG. 2, and further includes a first solder resist layer 15, a second solder resist layer 17, a first surface treatment layer 191, and a second surface treatment layer 192. As shown in FIG. 3, the substrate structure 1 further includes a substrate body 10, at least one second metal stop structure 8, at least one second metal peripheral structure 6, at least one second metal inner structure 9, and a second circuit. Layer 14, at least one outer conductive channel 16, at least one inner conductive channel 18, a first solder resist layer 15 and a second solder resist layer 17. The material of the substrate body 10 is usually a dielectric material, which may include a glass-reinforced epoxy material (such as FR4), bismaleimide triazine (BT), epoxy resin, silicon, and a printed circuit board. (PCB) material, glass, ceramic or photoimageable dielectric (PID) material. The substrate body 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. The first surface 101 of the substrate body 10 includes the first surface 101 of the first portion (for example, the wafer bonding area 2) and the first surface 101 of the second portion (for example, the board edge area 3), and the substrate body The second surface 102 of 10 includes the second surface 102 of the first portion (for example: the wafer bonding area 2) and the second surface 102 of the second portion (for example: the board edge area 3). In one embodiment, the first circuit layer 12, the first metal inner structure 7, the first metal stop structure 4 and the first metal peripheral structure 5 are located on the same layer, and are all located on the substrate body 10. On the first surface 101. An upper surface 41 of one of the first metal stop structures 4 is higher than or equal to one of upper surfaces 54 of the first metal peripheral structure 5, that is, a thickness of the first metal stop structure 4 is greater than or equal to The thickness of the first metal peripheral structure 5, whereby the first metal blocking structure 4 can produce a better blocking effect. In one embodiment, the conductive finger 123 of the first circuit layer 12 has a first surface finish layer 191, such as a gold plating layer or a tin plating layer. The second circuit layer 14, the second metal inner structure 9, the second metal stop structure 8 and the second metal peripheral structure 6 are located on the same layer and are all adjacent to the second surface 102 of the substrate body 10. . For example, the second circuit layer 14, the second metal inner structure 9, the second metal stop structure 8, and the second metal peripheral structure 6 are all embedded in the second surface 102 of the substrate body 10, and The lower surface of the second circuit layer 14, the lower surface of the second metal inner structure 9, the lower surface of the second metal stop structure 8, and the lower surface of the second metal peripheral structure 6 are substantially the same as the substrate body 10. The second surface 102 is coplanar. However, it can be understood that the second circuit layer 14, the second metal inner structure 9, the second metal stop structure 8 and the second metal peripheral structure 6 may also be located on the second surface of the substrate body 10. 102 on. The second circuit layer 14 is adjacent to the second surface 102 of the first portion (for example, the wafer bonding area 2). The second circuit layer 14 has at least a plurality of conductive pads, and their positions correspond to the conductive pads of the first circuit layer 12. For example, the conductive pads of the second circuit layer 14 are located on the first circuit layer 12. Directly below the conductive pad. It can be understood that the wiring of the second circuit layer 14 and the wiring of the first circuit layer 12 may be the same or different. In one embodiment, the first circuit layer 12 is electrically connected to the second circuit layer 14 through the inner conductive channel 18. That is, the inner conductive channel 18 penetrates the substrate body 10 and is used to electrically connect the first circuit layer 12 and the second circuit layer 14. In one embodiment, the first circuit layer 12 and the inner conductive channel 18 are simultaneously formed. In one embodiment, a lower surface of the conductive pad of the second circuit layer 14 has a second surface treatment layer 192, such as an electroplated gold layer or an electroplated tin layer. The second metal stop structure 8 is adjacent to the second surface 102 of the second portion (for example, the plate edge region 3). In an embodiment, the shape and size of the second metal stop structure 8 are substantially the same as the shape and size of the first metal stop structure 4, and the second metal stop structure 8 is located on the first metal The stop structure 4 is directly below. The second metal peripheral structure 6 is adjacent to the second surface 102 of the second portion (for example, the board edge region 3), and surrounds / encloses the second metal stop structure 8. In one embodiment, the second metal peripheral structure 6 and the second metal stop structure 8 are located on the same layer, and the materials are all made of copper and formed at the same time. The position of the second metal peripheral structure 6 corresponds to the position of the first metal peripheral structure 5. For example, the second metal peripheral structure 6 is located directly below the first metal peripheral structure 5 (that is, it is located in the stamper). Area 32) is used to balance the copper residual rate and stress of the substrate structure 1 as a whole. The second metal peripheral structure 6 includes a plurality of second peripheral metal blocks 61 and a plurality of second peripheral metal connecting sections (not shown). The second peripheral metal blocks 61 are spaced apart from each other (eg, arrayed), and surround / enclose the second metal stop structure 8. Each of the second peripheral metal blocks 61 is a polygon, including a triangle, a square, a rectangle, a convex pentagon or a convex hexagon, including at least three sides, a circle or an oval. The second peripheral metal connecting sections can be connected to the second peripheral metal blocks 61, and can be connected to the second peripheral metal blocks 61 and the second metal stop structure 8, and can be connected to the second metal stop Structure 8 and the second metal inner surrounding structure 9. In one embodiment, the second peripheral metal connecting sections may be omitted. In an embodiment, the shape and size of the second peripheral metal block 61 are the same as the shape and size of the first peripheral metal block 51, and one of the second patterns arranged by the second peripheral metal blocks 61 is the same. A first pattern is arranged on the first peripheral metal blocks 51. However, in other embodiments, the shape and size of the second peripheral metal block 61 and the shape and size of the first peripheral metal block 51 may be different, and the second pattern arranged by the second peripheral metal blocks 61 is different. It is different from the first pattern arranged by the first peripheral metal blocks 51. In one embodiment, the second metal peripheral structure 6 is electrically connected to the first metal peripheral structure 5 through the outer conductive channel 16. That is, the outer conductive channel 16 penetrates the substrate body 10 and is used to electrically connect the second metal peripheral structure 6 and the first metal peripheral structure 5. In one embodiment, the first metal peripheral structure 5 and the outer conductive channel 16 are formed at the same time. The second metal peripheral structure 6 may further include at least one second mesh metal structure (not shown) and a plurality of second plating pinches 65. The second mesh metal structure is formed by a plurality of copper metal line segments crossing each other, and corresponds to the first mesh metal structure 53. The pattern of the second mesh metal structure is different from the patterns of the second peripheral metal blocks 61, both of which are located on the same layer, and the material of which is both copper and formed at the same time. Therefore, the second mesh metal structure can also be used to balance the residual copper ratio and stress of the substrate structure 1 as a whole. The second electroplating nips 65 are used to clamp the electroplating chuck of an electroplating device during the electroplating process, so that the current of the electroplating device can enter the substrate structure 1 through the second electroplating nips 65. In one embodiment, the second plating pinches 65 are electrically connected to the first circuit layer 12. For example, in one embodiment, the second plating pinch 65 is electrically connected to the first plating pinch 55 through the outer conductive channel 16, and then is electrically connected to the first circuit layer 12. That is, the outer conductive channel 16 can be used to electrically connect the second plating pinch 65 and the first plating pinch 55. In one embodiment, the first plating pinch 55 and the outer conductive channel 16 are formed at the same time. The second metal inner structure 9 is adjacent to the second surface 102 of the second portion (for example, the board edge region 3), and the second metal stop structure 8 is bonded to the first portion (for example, the wafer) Zone 2). That is, the second metal inner periphery structure 9 is located in the injection area 31 (and is located directly below the first metal inner periphery structure 7). In one embodiment, the second metal inner structure 9, the second metal peripheral structure 6, the second metal stop structure 8 and the second circuit layer 14 are located on the same layer, and the materials are all copper, and at the same time form. The second metal inner structure 9 can also be used to balance the copper residual rate and stress of the substrate structure 1 as a whole. In one embodiment, the second metal inner periphery structure 9 includes a plurality of second inner periphery metal blocks 91 and a plurality of second inner periphery metal connecting sections (not shown). In an embodiment, the shape and size of the second inner metal block 91 are substantially the same as the shape and size of the second outer metal block 61. The second inner metal connecting sections can be connected to the second inner metal block 91 and the second metal stop structure 8, or can be connected to the second inner metal block 91 and the second circuit layer 14. In one embodiment, the width of the second inner metal connection segment is substantially the same as the width of the second outer metal connection segment. The first solder mask layer 15 covers the first surface 101 of the first portion (for example, the wafer bonding area 2) and the first circuit layer 12 thereon, but does not cover the conductive fingers 123 of the first circuit layer 12 The first surface treatment layer 191, that is, the first surface treatment layer 191 is exposed outside the first solder resist layer 15. At the same time, the first solder mask layer 15 covers the first surface 101 of the second portion (for example, the board edge region 3) and the first metal inner surrounding structure 7, the first metal blocking structure 4 and the The first metal peripheral structure 5 does not cover the first plating pinch 55. In addition, the second solder mask layer 17 covers the second surface 102 of the first portion (for example, the wafer bonding area 2) and the second circuit layer 14 thereon, but does not cover the conductive connection of the second circuit layer 14垫上 第二 表面 处理 层 192. The second surface treatment layer 192 on the pad. That is, the second surface treatment layer 192 is exposed outside the second solder resist layer 17. At the same time, the second solder mask layer 17 covers the second surface 102 of the second portion (for example, the board edge region 3) and the second metal inner surrounding structure 9, the second metal blocking structure 8 and the The second metal peripheral structure 6 does not cover the second plating pinch 65. FIG. 4 depicts a partially enlarged schematic diagram of an example of a substrate structure 1a according to some embodiments of the present invention, wherein the first solder resist layer and the first surface treatment layer are omitted. The substrate structure 1a of this embodiment is similar to the substrate structure 1 illustrated in FIGS. 1 to 3, and the differences are as follows. In the substrate structure 1a, the first metal stop structure 4a includes a plurality of first stop metal blocks 42 and a plurality of first stop metal connecting sections 43, wherein a width W of each first stop metal block 42 ₄ is larger than the width W _{5 of} each first stop metal connecting section 43. The first stop metal blocks 42 are spaced from each other, and the first stop metal connecting sections 43 are connected to the first stop metal blocks 42. 4, the first stop 42 of the metal block width W is equal to the first peripheral line ₄ the maximum width W ₂ of the metal block 51, the first stopper metal connection line width W ₅ of the second section 43 is larger than A maximum width W _{3 of} a peripheral metal connecting section 52, and a distance between the first stop metal blocks 42 is equal to a minimum distance G between any two of the first peripheral metal blocks 51 adjacent to each other. However, in other embodiments, the first stop 42 of the metal block width W ₄ may be less than or greater than the first metal block 51 of the peripheral maximum width W _2, the first metal connection stopper section 43 of width W ₅ May be equal to or smaller than the maximum width W _{3 of} the first peripheral metal connecting section 52, and the distance between the first stop metal blocks 42 may be smaller than or greater than any two adjacent to the first peripheral metal block 51 Minimum spacing G. FIG. 5 depicts a partially enlarged schematic diagram of an example of a substrate structure 1b according to some embodiments of the present invention, wherein the first solder resist layer and the first surface treatment layer are omitted. FIG. 6 is a schematic cross-sectional view taken along line II-II according to FIG. 5, and further includes a first solder resist layer 15, a second solder resist layer 17, a first surface treatment layer 191, and a second surface treatment layer 192. The substrate structure 1b of the embodiment of FIG. 5 and FIG. 6 is similar to the substrate structure 1 described in FIGS. 1 to 3, and the differences are as follows. In the substrate structure 1b, each of the second peripheral metal blocks 61 is not aligned with each of the first peripheral metal blocks 51, that is, each of the second peripheral metal blocks 61 is not located in each of the first Directly below the peripheral metal block 51. As shown in FIG. 6, the center of each of the second peripheral metal blocks 61 and the center of each of the first peripheral metal blocks 51 have an offset S. FIG. 7 depicts a partially enlarged schematic diagram of an example of a substrate structure 1c according to some embodiments of the present invention, wherein the first solder resist layer and the first surface treatment layer are omitted. The substrate structure 1 c of the embodiment of FIG. 7 is similar to the substrate structure 1 described in FIGS. 1 to 3, and the differences are as follows. In the substrate structure 1c, the positions of the first peripheral metal blocks 51 in adjacent rows are not aligned with each other, that is, the positions of the first peripheral metal blocks 51 in adjacent rows are staggered with each other. In other words, the center points of the first peripheral metal blocks 51 adjacent to the left and right are not located on the same straight line. FIG. 8 depicts a partially enlarged schematic diagram of an example of a substrate structure 1d according to some embodiments of the present invention, wherein the first solder resist layer and the first surface treatment layer are omitted. FIG. 9 is a schematic partial perspective view of FIG. 8. The substrate structure 1d of the embodiment of FIGS. 8 and 9 is similar to the substrate structure 1 illustrated in FIGS. 1 to 3, and the differences are as follows. In the substrate structure 1d, the first metal stop structure 4b includes a plurality of first stop metal blocks 44 and a plurality of first stop metal connecting sections 45, wherein a width W of each first stop metal block 44 ₆ is larger than the width W _{7 of} each first stop metal connecting section 45. The first blocking metal blocks 44 are spaced apart from each other, and the two first blocking metal blocks 44 are connected by two first blocking metal connecting sections 45. As shown in FIGS. 8 and 9, the width W ₆ of the first stop metal block 44 is equal to the maximum width W _{2 of} the first peripheral metal block 51, and the width W ₇ of the first stop metal connecting section 45 is Is equal to the maximum width W ₃ of the first peripheral metal connecting section 52, and the distance g between the first blocking metal blocks 44 is equal to the minimum distance G between any two of the first peripheral metal blocks 51 adjacent to each other. . However, in other embodiments, the first stop 44 of the metal block width W ₆ may be less than or greater than the first metal block 51 of the peripheral maximum width W _2, the first stop connected to metal segment 45 of a width W ₇ May be less than or greater than the maximum width W _{3 of} the first peripheral metal connecting section 52, and the distance g between the first stop metal blocks 45 may be less than or greater than any two adjacent to the first peripheral metal blocks 51. The minimum distance G. FIGS. 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19 illustrate a method of manufacturing a semiconductor package element according to some embodiments of the present invention. 10, a carrier 22 is provided. In one embodiment, the carrier 22 is a metal, such as copper. Then, a second circuit layer 14, at least one second metal inner structure 9, at least one second metal stop structure 8, and at least one second metal peripheral structure 6 are formed on the carrier 22. In one embodiment, the second circuit layer 14, the second metal inner structure 9, the second metal stop structure 8 and the second metal peripheral structure 6 are the same layer and are formed in the same step. Referring to FIG. 11, a substrate body 10 is formed on the carrier 22 to cover the second circuit layer 14, the second metal inner structure 9, the second metal stop structure 8, and the second metal peripheral structure 6. Next, the first circuit layer 12, the first metal inner peripheral structure 7, the first metal stop structure 4, the first metal peripheral structure 5, at least one outer conductive channel 16, at least one inner conductive channel 18 and A plurality of positioning holes 103 are formed on the substrate body 10 to form a substrate structure 1. In an embodiment, the first circuit layer 12, the first metal inner structure 7, the first metal stop structure 4 and the first metal peripheral structure 5 are the same layer and are formed in the same step. It should be noted that the substrate structure 1 at this stage is substantially the same as the substrate structure 1 shown in FIGS. 1 to 3, except that the second solder resist layer 17 and the second surface treatment layer 192 have not been formed. The substrate body 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. The substrate structure 1 includes a first portion (for example, a wafer bonding area 2), a second portion (for example, a board edge area 3), the first metal stop structure 4, the first metal peripheral structure 5, and the first The metal inner periphery structure 7, the positioning holes 103, the second circuit layer 14, the second metal inner periphery structure 9 and the second metal stop structure 8. The substrate structure 1 may be a strip-type substrate structure. In other embodiments, the substrate structure 1 may be a panel-type substrate structure. The first part (for example, the wafer bonding area 2) includes a plurality of area units 21. The first circuit layer 12 is disposed in each of the regional units 21. The first circuit layer 12 is located on the first surface 101 of the first portion (for example, the wafer bonding area 2). The first circuit layer 12 includes a plurality of conductive traces 121, a plurality of conductive pads 122, and a plurality of conductive fingers 123 (FIG. 2). The second part (for example: the board edge area 3) surrounds / encloses the first part (for example: the wafer bonding area 2). The second part (for example, the board edge area 3) includes a glue injection area 31 and a stamping area 32. The injection region 31 is adjacent to and surrounds / encloses the first portion (eg, the wafer bonding region 2). The die area 32 surrounds the injection area 31, that is, the die area 32 is farther from the first part than the injection area 31 (eg, the wafer bonding area 2). The first metal stop structure 4 is adjacent to a first surface 101 (for example, located on the first surface 101) of the second part (for example, the board edge region 3), and substantially completely surrounds / around the first surface 101. A part (for example, the wafer bonding area 2) (as shown in FIG. 1 and FIG. 2). In one embodiment, the first metal stop structure 4 is located in the die area 32 and is very close to the second boundary line 30. An upper surface 41 of one of the first metal stop structures 4 is higher than or equal to one of upper surfaces 54 of the first metal peripheral structure 5, that is, a thickness of the first metal stop structure 4 is greater than or equal to The thickness of the first metal peripheral structure 5, whereby the first metal blocking structure 4 can produce a better blocking effect. In one embodiment, the conductive fingers of the first circuit layer 12 have a first surface treatment layer 191, such as an electroplated gold layer or an electroplated tin layer. The first metal peripheral structure 5 is adjacent to the first surface 101 of the second portion (for example, the board edge region 3), and surrounds / encloses the first metal stop structure 4. The first metal peripheral structure 5 is located in the die area 32 to balance the copper residual rate and stress of the substrate structure 1 as a whole. The first metal peripheral structure 5 includes a plurality of first peripheral metal blocks 51 and a plurality of first peripheral metal connecting sections 52, at least one first mesh metal structure 53 and a plurality of first electroplating clamping points 55 (as shown in FIG. 1 and Figure 2). The first plating clamping points 55 are used to clamp the plating chuck of a plating device during the plating process, so that the current of the plating device can enter the substrate structure 1 through the first plating clamping points 55. In one embodiment, the first plating pinches 55 are electrically connected to the first circuit layer 12. The first metal inner peripheral structure 7 is adjacent to the first surface 101 of the second portion (for example, the board edge region 3), and the first metal stop structure 4 is bonded to the first portion (for example, the wafer) Zone 2). That is, the first metal inner surrounding structure 7 is located in the glue injection area 31. In one embodiment, the first metal inner periphery structure 7 includes a plurality of first inner periphery metal blocks 71 and a plurality of first inner periphery metal connecting sections 72 (as shown in FIGS. 1 and 2). The positioning holes 103 (FIG. 1) pass through the substrate structure 1 and are located outside the periphery of the substrate structure 1, and are used for positioning. The second circuit layer 14, the second metal inner structure 9, the second metal stop structure 8 and the second metal peripheral structure 6 are all embedded in the second surface 102 of the substrate body 10, and the second circuit The lower surface of the layer 14, the lower surface of the second metal inner structure 9, the lower surface of the second metal stop structure 8 and the lower surface of the second metal peripheral structure 6 are substantially the same as the second surface of the substrate body 10 102 coplanar. The second circuit layer 14 is adjacent to the second surface 102 of the first portion (for example, the wafer bonding area 2). The second circuit layer 14 has at least a plurality of conductive pads, and its position is corresponding to the conductive pads 122 of the first circuit layer 12, for example, the conductive pads of the second circuit layer 14 are located on the first circuit layer 12 Directly below the conductive pad 122. In one embodiment, the first circuit layer 12 is electrically connected to the second circuit layer 14 through the inner conductive channel 18. That is, the inner conductive channel 18 penetrates the substrate body 10 and is used to electrically connect the first circuit layer 12 and the second circuit layer 14. In one embodiment, the first circuit layer 12 and the inner conductive channel 18 are simultaneously formed. The second metal stop structure 8 is adjacent to the second surface 102 of the second portion (for example, the plate edge region 3). The shape and size of the second metal stop structure 8 are substantially the same as the shape and size of the first metal stop structure 4. The second metal peripheral structure 6 is adjacent to the second surface 102 of the second portion (for example, the board edge region 3), and surrounds / encloses the second metal stop structure 8. The position of the second metal peripheral structure 6 corresponds to the position of the first metal peripheral structure 5. The second metal peripheral structure 6 includes a plurality of second peripheral metal blocks 61 (as shown in FIG. 1 and FIG. 2) and a plurality of second peripheral metal connecting sections (not shown in the figure). In one embodiment, the second metal peripheral structure 6 is electrically connected to the first metal peripheral structure 5 through the outer conductive channel 16. That is, the outer conductive channel 16 penetrates the substrate body 10 and is used to electrically connect the second metal peripheral structure 6 and the first metal peripheral structure 5. In one embodiment, the first metal peripheral structure 5 and the outer conductive channel 16 are formed at the same time. The second metal peripheral structure 6 may further include at least one second mesh metal structure (not shown) and a plurality of second plating pinches 65. The second electroplating nips 65 are used to clamp the electroplating chuck of an electroplating device during the electroplating process, so that the current of the electroplating device can enter the substrate structure 1 through the second electroplating nips 65. In one embodiment, the second plating pinches 65 are electrically connected to the first circuit layer 12. For example, in one embodiment, the second plating pinch 65 is electrically connected to the first plating pinch 55 through the outer conductive channel 16, and then is electrically connected to the first circuit layer 12. The second metal inner structure 9 is adjacent to the second surface 102 of the second part (for example, the board edge area 3), and the second metal stop structure 8 and the first part (for example, the wafer bonding area) 2) Between. That is, the second metal inner periphery structure 9 is located in the injection area 31 (and is located directly below the first metal inner periphery structure 7). In one embodiment, the second metal inner periphery structure 9 includes a plurality of second inner periphery metal blocks 91 and a plurality of second inner periphery metal connecting sections (not shown). Next, a first solder mask layer 15 is formed to cover the first surface 101 of the substrate body 10 and all components thereon, but a portion of the conductive fingers of the first circuit layer 12 and the first plating pinch 55 are exposed. . Next, an exposed portion of the first surface treatment layer 191 on the conductive finger is formed. Referring to FIG. 12, at least one semiconductor wafer 24 is electrically connected to the first portion of the substrate structure 1 (for example, the wafer bonding area 2). In one embodiment, the semiconductor wafer 24 is adhered to the first solder mask layer 15 on the first surface 101 of the substrate body 10 with an adhesive layer 23, and the semiconductor wafer 24 is electrically charged through at least one wire 26. The first surface treatment layer 191 is electrically connected to the conductive finger 123. Next, a glue mold 90 is provided. The glue mold 90 has a lower surface 901 and a cavity 902. The cavity 902 has a side surface 903, and the side surface 903 of the cavity 902 substantially corresponds to the second boundary line 30. Referring to FIG. 13, the lower surface 901 of the potting mold 90 is pressed against the molding area 32 of the substrate structure 1, that is, the position of the first metal stop structure 4 corresponds to the bottom of the potting mold 90. The surface 901, and the first portion of the substrate structure 1 (for example, the wafer bonding area 2), the at least one semiconductor wafer 24, and the injection area 31 are positioned corresponding to the mold cavity 902 (for example, located in the mold cavity 902 ). In other words, the entire first metal stop structure 4 and the first solder resist 15 on its upper surface 41 are tightly pressed by the lower surface 901 of the potting mold 90, so that the mold of the potting mold 90 The cavity 902 forms a closed space. In one embodiment, the side surface 903 of the cavity 902 is substantially coplanar with the second boundary line 30. Therefore, after the encapsulation material 28 (FIG. 14) fills the cavity 902, it will not overflow to the stamping area 32, but will only be located in the injection area 31 and the first part (for example, the wafer bonding area 2). . It can be understood that if the first solder resist 15 is not provided, the lower surface 901 of the potting mold 90 will press the first metal stop structure 4. Referring to FIG. 14 and FIG. 15, FIG. 15 is an overall plan view of FIG. 14. Forming an encapsulation material 28 to cover all the components on the first part of the substrate structure 1 (eg, the wafer bonding area 2), the at least one semiconductor wafer 24, the wires 26, and the glue injection area 31 element. Due to the blocking effect of the first metal blocking structure 4, there is no encapsulating material 28 outside the second dividing line 30. That is, the second boundary line 30 is a boundary line (ie, a contour line of the periphery) of the encapsulation material 28, and the encapsulation material 28 does not overflow to the stamper area 32. Then, the film is removed. That is, the glue mold 90 is removed. Referring to FIG. 16, the carrier 22 is thinned from the lower surface of the carrier 22. In one embodiment, the carrier 22 is copper, and a de-oxidation process is used to remove the oxide on the lower surface of the copper. Referring to FIG. 17, the carrier 22 is removed to expose the second surface 102 of the substrate body 10 and the second circuit layer 14, the second metal inner structure 9, the second metal stop structure 8, and the second metal. Peripheral structure 6. In one embodiment, the carrier 22 is copper, and an etching process is used to remove the entire carrier 22. Referring to FIG. 18, a second surface treatment layer 192 is formed on a portion of the second circuit layer 14. In an embodiment, the first plating clamping points 55 and / or the second plating clamping points 65 are used to clamp a plating chuck of a plating device during the plating process, so that the current of the plating device can be Enter the first circuit layer 12 and the second circuit layer 14 of the substrate structure 1 through the first plating pinch 55 and / or the second plating pinch 65 to form a second surface treatment layer 192 On the conductive pads of the second circuit layer 14. Next, a second solder mask layer 17 is formed to cover the second surface 102 of the first portion (for example, the wafer bonding region 2) and the second circuit layer 14 thereon, but not to cover the second circuit layer 14. The second surface treatment layer 192 on the conductive pad. That is, the second surface treatment layer 192 is exposed outside the second solder resist layer 17. At the same time, the second solder mask layer 17 covers the second surface 102 of the second portion (for example, the board edge region 3) and the second metal inner surrounding structure 9, the second metal blocking structure 8 and the The second metal peripheral structure 6 does not cover the second plating pinch 65. In other embodiments, the second solder mask layer 17 may cover the second plating pinch 65. Referring to FIG. 19, the second portion (for example, the board edge region 3) of the substrate structure 1 is cut along the first boundary line 20 to form a plurality of semiconductor package components 11. That is, each semiconductor package element 11 corresponds to a region unit 21 of the first portion (for example, the wafer bonding region 2) described above. Unless otherwise specified, such as "above", "below", "up", "left", "right", "down", "top", "bottom", "vertical", "horizontal", "side" , "Higher", "lower", "upper", "upper", "lower" and other spatial descriptions indicate the orientation shown in the figure. It should be understood that the space description used in this article is for the purpose of illustration only, and the actual implementation of the structure described in this article can be spatially configured in any orientation or manner. The limitation is that the advantages of the embodiments of the new model are not Configuration is biased. As used herein, the terms "substantially", "substantially", "substantially" and "about" are used to describe and consider small variations. When used in conjunction with an event or situation, the term can refer to a situation in which the event or situation occurs explicitly and a situation in which the event or situation closely resembles. For example, when used in conjunction with numerical values, these terms may refer to a range of variation that is less than or equal to ± 10% of the value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, Less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, if the difference between two values is less than or equal to ± 10% of the average of the values (such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than Or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%), the two values can be considered to be "substantially" the same. The term "substantially coplanar" may refer to two of several micrometers (μm) along the same plane (such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane). Surface. In addition, quantities, ratios, and other numerical values are sometimes presented in a range format herein. It should be understood that such range formats are used for convenience and brevity, and should be interpreted flexibly to include not only values explicitly designated as range limits, but also all individual values or subranges encompassed within that range, as Explicitly specify each value and subrange in general. In the description of some embodiments, providing one of the components "on" another component may cover the situation where the former component is directly on the latter component (e.g., in physical contact with the latter component) and one or more A condition in which an intervening component is located between a previous component and a subsequent component. Although the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations do not limit the invention. Those skilled in the art should understand that various changes can be made and equivalents can be substituted without departing from the true spirit and scope of the new model as defined by the scope of the attached patent application. Instructions need not be drawn to scale. Due to manufacturing procedures and tolerances, there may be a difference between the artistic reproduction in this new model and the actual equipment. There may be other embodiments of the present invention that are not explicitly described. This specification and drawings are to be regarded as illustrative rather than restrictive. Modifications can be made to adapt specific situations, materials, material compositions, methods, or processes to the objectives, spirit, and scope of the new model. All such modifications are intended to be within the scope of the patentable applications attached hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that such operations may be combined, subdivided, or reordered to form equivalents without departing from the teachings of the new model. method. Therefore, unless explicitly indicated herein, the order and grouping of operations is not a limitation of the new model.

G‧‧‧Pitch
W ₁ ‧‧‧Width
W ₂ ‧‧‧Width
W3‧‧‧Width
W ₄ ‧‧‧Width
W ₅ ‧‧‧Width
W ₆ ‧‧‧Width
W ₇ ‧‧‧Width
g‧‧‧ pitch
1‧‧‧ substrate structure
1a‧‧‧ substrate structure
1b‧‧‧ substrate structure
1c‧‧‧ substrate structure
1d‧‧‧ substrate structure
2‧‧‧ Wafer Land
3‧‧‧board edge
4‧‧‧The first metal stop structure
4a‧‧‧First metal stop structure
4b‧‧‧First metal stop structure
5‧‧‧First metal peripheral structure
6‧‧‧Second metal peripheral structure
7‧‧‧The first metal inner structure
8‧‧‧Second metal stop structure
9‧‧‧Second metal inner structure
10‧‧‧ substrate body
11‧‧‧Semiconductor Package Components
12‧‧‧First circuit layer
14‧‧‧Second circuit layer
15‧‧‧First solder resist
16‧‧‧ Outer conductive channel
17‧‧‧Second solder mask
18‧‧‧ Internal conductive channel
20‧‧‧ first dividing line
21‧‧‧ regional unit
22‧‧‧ carrier
23‧‧‧ Adhesive layer
24‧‧‧Semiconductor wafer
26‧‧‧Wire
28‧‧‧sealing plastic
30‧‧‧Second dividing line
31‧‧‧gel injection area
32‧‧‧Compression zone
41‧‧‧ Upper surface of the first metal stop structure
42‧‧‧First stop metal block
43‧‧‧First stop metal connection
44‧‧‧First stop metal block
45‧‧‧First stop metal connection
51‧‧‧The first peripheral metal block
52‧‧‧The first peripheral metal connecting section
53‧‧‧The first mesh metal structure
54‧‧‧ Upper surface of the first metal peripheral structure
55‧‧‧The first plating pinch
61‧‧‧Second peripheral metal block
65‧‧‧Second plating pinch
71‧‧‧The first inner wall metal block
72‧‧‧The first inner wall metal connecting section
90‧‧‧Pouring mold
91‧‧‧Second inner block
101‧‧‧ the first surface of the substrate body
102‧‧‧ the second surface of the substrate body
103‧‧‧ Positioning hole
121‧‧‧ conductive trace
122‧‧‧Conductive pad
123‧‧‧Conductive finger
191‧‧‧The first surface treatment layer
192‧‧‧Second surface treatment layer
901‧‧‧ under the mold
902‧‧‧mould cavity
903‧‧‧Side surface of mold cavity

FIG. 1 depicts a schematic top view of an example of a substrate structure according to some embodiments of the present invention, in which a first solder resist layer and a first surface treatment layer are omitted. FIG. 2 depicts an enlarged schematic view of an area A in the substrate structure 1 according to FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line I-I according to FIG. 2, and further includes a first solder resist layer, a second solder resist layer, a first surface treatment layer, and a second surface treatment layer. FIG. 4 depicts a partially enlarged schematic diagram of an example of a substrate structure according to some embodiments of the present invention, wherein the first solder resist layer and the first surface treatment layer are omitted. FIG. 5 depicts a partially enlarged schematic diagram of an example of a substrate structure according to some embodiments of the present invention, wherein the first solder resist layer and the first surface treatment layer are omitted. FIG. 6 is a schematic cross-sectional view taken along line II-II according to FIG. 5, which further includes a first solder resist layer, a second solder resist layer, a first surface treatment layer, and a second surface treatment layer. FIG. 7 depicts a partially enlarged schematic diagram of an example of a substrate structure according to some embodiments of the present invention, wherein the first solder resist layer and the first surface treatment layer are omitted. FIG. 8 depicts a partially enlarged schematic diagram of an example of a substrate structure according to some embodiments of the present invention, in which the first solder resist layer and the first surface treatment layer are omitted. FIG. 9 is a schematic partial perspective view of FIG. 8. FIGS. 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19 illustrate a method of manufacturing a semiconductor package element according to some embodiments of the present invention.

1‧‧‧ substrate structure

2‧‧‧ Wafer Land

3‧‧‧board edge

4‧‧‧The first metal stop structure

5‧‧‧First metal peripheral structure

7‧‧‧The first metal inner structure

12‧‧‧First circuit layer

20‧‧‧ first dividing line

21‧‧‧ regional unit

30‧‧‧Second dividing line

31‧‧‧gel injection area

32‧‧‧Compression zone

51‧‧‧The first peripheral metal block

53‧‧‧The first mesh metal structure

55‧‧‧The first plating pinch

71‧‧‧The first inner wall metal block

72‧‧‧The first inner wall metal connecting section

103‧‧‧ Positioning hole

Claims (27)

A substrate structure includes: a die bonding area for at least one semiconductor wafer to be disposed thereon; a side rail area including a glue injection area and a die area, the glue The injection area is adjacent to and surrounds the wafer bonding area for forming an encapsulating plastic material thereon; the stamping area surrounds the adhesive injection area for pressing a lower surface of an injection mold on it; at least one The first metal stop structure is adjacent to a first surface of the edge area of the board and substantially completely surrounds the wafer bonding area, and the first metal stop structure is located in the stamper area; and at least one first metal The peripheral structure is adjacent to the first surface of the board edge region and surrounds the first metal stop structure. The substrate structure according to item 1 of the patent application scope, wherein the first metal stop structure is a continuous ring structure. The substrate structure according to item 2 of the scope of the patent application, wherein the first metal stop structure is a strip structure and has a single width. The substrate structure according to item 2 of the scope of the patent application, wherein the first metal stop structure includes a plurality of first stop metal blocks and a plurality of first stop metal connecting sections. The width is greater than the width of each first stop metal connecting section, the first stop metal blocks are spaced from each other, and the first stop metal connecting sections are connected to the first stop metal blocks. The substrate structure according to item 1 of the scope of patent application, wherein the first metal peripheral structure and the first metal stop structure are located on the same layer. The substrate structure described in item 1 of the patent application scope further includes a first circuit layer adjacent to a first surface of the wafer bonding area, and the first metal peripheral structure includes a plurality of first plating pinches, It is electrically connected to the first circuit layer. The substrate structure according to item 1 of the patent application scope, wherein the first metal peripheral structure includes a plurality of first peripheral metal blocks, and the first peripheral metal blocks are spaced apart from each other and surround the first metal stop structure. The substrate structure according to item 7 of the scope of patent application, wherein the first peripheral metal block is a convex polygon, a circle or an ellipse including at least three sides. The substrate structure according to item 7 of the scope of patent application, wherein the minimum distance between any two of the first peripheral metal blocks adjacent to each other is between 0.1 mm and 0.3 mm. The substrate structure according to item 7 of the scope of patent application, wherein the maximum width of the first peripheral metal block is between 0.2 mm and 0.4 mm. The substrate structure according to item 7 of the scope of the patent application, wherein the first metal peripheral structure further includes a plurality of first peripheral metal connecting sections to connect the first peripheral metal blocks. The substrate structure according to item 11 of the scope of the patent application, wherein the maximum width of the first peripheral metal connection segment is less than or equal to 0.1 mm. The substrate structure described in item 1 of the patent application scope further includes at least one second metal peripheral structure adjacent to a second surface of the board edge region. The substrate structure according to item 13 of the patent application scope further includes at least one outer conductive channel for electrically connecting the first metal peripheral structure and the second metal peripheral structure. The substrate structure according to item 13 of the application, wherein the first metal peripheral structure includes a plurality of first peripheral metal blocks, and the second metal peripheral structure includes a plurality of second peripheral metal blocks. The substrate structure according to item 15 of the scope of patent application, further comprising a first circuit layer adjacent to a first surface of the wafer bonding area, and the second metal peripheral structure further includes a plurality of second plating pinches, It is electrically connected to the first circuit layer. The substrate structure according to item 15 of the scope of the patent application, wherein the center of each of the second peripheral metal blocks and the center of each of the first peripheral metal blocks have an offset. The substrate structure according to item 15 of the scope of patent application, wherein the second peripheral metal block is a convex polygon, a circle or an ellipse including at least three sides. The substrate structure according to item 15 of the scope of patent application, wherein a second pattern arranged by the second peripheral metal blocks is different from a first pattern arranged by the first peripheral metal blocks. The substrate structure according to item 1 of the patent application scope, wherein the first metal peripheral structure includes a plurality of rows of first peripheral metal blocks, and the positions of the first peripheral metal blocks of adjacent rows are aligned with each other. The substrate structure according to item 1 of the patent application scope, wherein the first metal peripheral structure includes a plurality of rows of first peripheral metal blocks, and the positions of the first peripheral metal blocks of adjacent rows are staggered with each other. The substrate structure according to item 1 of the patent application scope, wherein the first metal peripheral structure includes at least one first mesh metal structure. The substrate structure according to item 1 of the scope of patent application, wherein an upper surface of one of the first metal stop structures is higher than or equal to an upper surface of one of the first metal peripheral structures. The substrate structure described in item 1 of the patent application scope further includes at least a first metal inner peripheral structure, which is adjacent to the first surface of the board edge area, and is located between the first metal stop structure and the wafer bonding area. between. The substrate structure according to item 24 of the scope of the patent application, wherein the first metal inner structure includes at least one first inner metal connection section, which is connected to the first metal stop structure and is located in one of the wafer bonding areas. One line layer. The substrate structure according to item 1 of the patent application scope further includes: a first circuit layer adjacent to a first surface of the wafer bonding area; a second circuit layer adjacent to one of the wafer bonding areas A second surface; at least one inner conductive channel electrically connected to the first circuit layer and the second circuit layer; and at least one first metal peripheral structure adjacent to the first surface of the board edge region and electrically connected To the first circuit layer. The substrate structure described in item 1 of the patent application scope further includes a first solder resist layer covering a first surface of the wafer bonding area, the first surface of the board edge area, and the first metal stop structure.