TWI321850B - - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device and a semiconductor device manufacturing method having structures having different heights in a plurality of active regions. The semiconductor device is a MOS transistor including a non-electric memory cell having a floating gate and a logic circuit. [Prior Art 3] In the semiconductor integrated circuit device (1C), the logic circuit is to reduce power consumption, and a complementary MOS having an n-channel MOS (NMOS) transistor and a p-channel m〇s (PMOS) transistor (CMOS) circuit formation. With the demand for high integration and high speed of the semiconductor integrated circuit device (ic), the transistor which is an IC component is gradually miniaturized. When the scale rule is fined, the operating speed of the transistor is increased and the operating voltage is lowered.

The element isolation region of the LOCOS (l〇cal oxidation of silicon) forms an unnecessary area which narrows the active area from the bird's mouth portion whose thickness is gradually reduced from the target, and hinders the increase in the degree of integration. Therefore, STI (shallow trench isolation) is widely used. The element isolation area of sti is as follows. The surface of the broken substrate is thermally vaporized to form a buffered yttria film on which a nitriding film is deposited by chemical vapor deposition (CVD). A photoresist pattern having an opening pattern corresponding to the element isolation region is formed, and the tantalum nitride film or the hafnium oxide film is etched. The element isolation trench is formed by forming a patterned nitride film as a photomask "dream substrate (4)". After the surface of the active trench is separated by the element isolation trench, the surface of the trench is thermally oxidized by a high-density «HDP CVD or the like to embed the component isolation trench. The yttrium oxide film on the tantalum nitride film is removed by chemical mechanical polishing (CMP). Here, tantalum nitride has a function as a stopper for CMP. The wafer surface after CMp is flattened. The exposed tantalum nitride film is removed by hot phosphoric acid, and the hafnium oxide film is removed by etching with dilute hydrofluoric acid to expose the surface of the active region. After the formation of the STI, the surface of the active region is thermally oxidized to form a cerium oxide film for ion implantation, which is used for forming a well for each crystal, for blocking a channel, and for adjusting a threshold. After the implant is implanted, the aged oxide oxide film is etched away. The active region is thermally oxidized again to form a cerium oxide film. When a gate oxide film of different thickness is formed, a part of the gate oxide film is removed to form a new gate oxide film. A gate electrode layer such as a germanium is deposited on the gate oxide film, and a pattern is formed by etching using a photoresist mask. The surface of the element isolation region of the STI is higher than the surface of the active region. In the buffering of the oxidized oxide film, when the excessive residue is performed, the STI oxide film is also left, so that the STI yttrium oxide film around the exposed active region retreats, and at the same time, the concave portion which is recessed downward from the surface of the active region is formed. . When the steps of thermal oxidation and thermal oxidization of the ruthenium film are repeated, the STI ruthenium oxide film around the active region is further retracted, and at the same time, the concave portion recessed downward from the surface of the active region is deeper. When the distribution density of the element isolation regions on the wafer is different, in the region where the density is low, concave distortion occurs during CMP. When a concave twist is generated, the amount of protrusion of the STI protruding from the surface of the substrate in the region is reduced.

Japanese Patent Laid-Open Publication No. 2003-297950 discloses that in an integrated circuit device including a DRAM memory cell and a peripheral circuit region, when an STI is formed, a concave distortion occurs in a peripheral circuit region due to a difference in pattern density, and yttrium oxide is formed. The film has a height difference. In the peripheral circuit region, when the STI height is 20 nm with respect to the surface of the germanium substrate, the defect density of the gate insulating film is the smallest, and in the region of the delta memory cell, when the height of sti is 〇 In nm, the defect density of the gate insulating film is the smallest, so it is proposed that after the CMP of the STI yttrium oxide film, the peripheral circuit region is covered with a photomask, and the memory cell region is engraved to make it lower than the STI of the peripheral circuit region. About 20nm. By this selective etching, the amount of protrusion of the STI from the surface of the lingual region is about 2 〇 nm in the peripheral circuit region and about 〇 nm in the memory cell region, and the above-described optimum STI height can be achieved. Japanese Patent Laid-Open Publication No. 2006-32700 indicates that in the DRAM memory cell region and the peripheral circuit region, when the amount of protrusion of the STI with respect to the surface of the ruthenium substrate is poor, the range of the photo lithography technique is reduced, and it is proposed to form 811. Further, in the step of implanting ions in each active region, ions are implanted into the memory cell region using the same mask, and the STI of the memory cells is etched to average the STI protrusion amounts in all the wafer regions. When the memory cell region of the peripheral circuit region is selectively etched, the amount of protrusion of the STI is uniformized. In Japanese Patent Laid-Open Publication No. 2003-297950, the STI of the memory cell is also etched to reduce the amount of protrusion, but the purpose, the etching time, and the etching amount are different. These proposals are related to the adjustment of the STI protrusion amount when the DRAM memory cell is integrated with the peripheral circuit area. A logic semiconductor device in which a rewritable non-electrical semiconductor memory device is mixed is formed into a product division called a CPLD (complex programmable logic devic e) or an FPGA (field programmable gate array), and is developed to form by a programmable feature. Big market. A typical example of the rewritable non-electrical semiconductor memory is to replace the insulating gate structure formed by the gate insulating film of the NMOS transistor and the dummy electrode thereon with a laminated channel insulating film, a sub-closed electrode, and a gate. A flash memory cell of an insulating film and a gate electrode of a control gate. Since the floating gate electrode writes/deletes the f-charge, or the voltage of the control electrode is controlled by the floating gate electrode, the operating voltage is increased. In a logic semiconductor device in which a non-electrical memory is mixed, in addition to (4) minus _ yuan, a high voltage transistor for controlling (4) memory cells and a low voltage transistor for high performance logic circuits are stacked on each other. On the same semiconductor wafer. Forming a transistor with a low threshold and a transistor with a high threshold requires changing the conditions for ion implantation of the threshold adjustment. When independent ion implantation is performed in the area p § area and pM OS area, 4 pieces of reticle and 8 times of ion implantation are required for high voltage operation (4 电S, low voltage operation CMOS 4 kinds of transistors) International Patent Publication No. WO2004/093192 discloses that in addition to forming a flash memory, an NMOS transistor and a PMOS transistor having a high threshold and a low threshold with high voltage operation and low voltage operation and a medium voltage N 外部 for an external input signal are formed. The 0 S transistor and the P Μ 0 S transistor have a total of the steps of the transistor. It is proposed to use three kinds of photomasks and four times of ion implantation for three kinds of 1 <^1〇8 (or PMOS) transistors. Method for ion implantation: forming a plurality of kinds of closed insulating defects having different thicknesses in a region of a transistor having different operating voltages. To form a thick gate oxide film and a thin gate oxide film, a thick gate oxide film is formed on the surface of all tongue regions. Selectively remove the thick gate yttrium oxide film in the region where the thin gate yttrium oxide is formed. Thereafter, the thin gate oxidized oxide film is formed to form a 3 freshness 卩 化 频 验 验 2 & & & & & & & & & Gate yttria film formation step. When the ruthenium oxide film is etched, over-etching is performed, and the ruthenium oxide film of the element isolation region around the active region is also etched. When the ruthenium oxide film is repeatedly etched, the element isolation region has a recess that cannot be ignored at the boundary with the active region. The gate electrode of the flash memory has a structure in which a gate is controlled by a 〇N〇 film (the oxidized stone film/nitridium film/oxidized stone film) on the floating gate. The floating gate is a gate that is electrically floating. The electrode is generally formed by polyfluorene, and is patterned by a second etching step. The contact of the polycrystalline layer covering the surface with the ruthenium film is not necessarily easy. The periphery of the active region is surrounded by a STI having a concave portion or a protrusion, and is formed on the inclined surface. The pattern increases the difficulty. Since the control gate electrode of the flash memory is formed on the floating gate, the surface is higher than the gate electrode of the MOS transistor of the surrounding circuit. The semiconductor of the flash memory region and the logic circuit region is integrated. The device has a problem that is different from a semiconductor device in which a DRAM memory cell region and a logic circuit region are integrated. Patent Document 1: Japanese Patent Laid-Open Publication No. 2003-297950 Patent Document 2: PCT Patent Publication No. 2006-032700 Patent Document 3: International Publication No. WO2004/093192 SUMMARY OF INVENTION Summary of the Invention A new solution is required for a new problem. It is an object of the present invention to provide a new solution A semiconductor device and a method of manufacturing a semiconductor device. 1321850 Another object of the present invention is to provide a semiconductor device with high yield and a method for manufacturing the semiconductor device. Still another object of the present invention is to provide a range of photolithography processes. A semiconductor device and a method of manufacturing a semiconductor device. Further, another object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device which can prevent a problem of generation of a residue of a conductive material. According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate having a first region and a second region, an element isolation trench formed in the semiconductor substrate, and an insulating film shape embedded in the element isolation trench 10 And forming an STI element isolation region of the plurality of active regions of the first region and the second region, and forming an STI element isolation region on the active region of the first region to a surrounding STI element isolation region, and having a first structure having a first height And a second structure formed on the active region of the second region to the surrounding STI element isolation region and having a second height lower than the first height; and a surface of the STI element isolation region of the first 15 region It is lower than the surface of the STI element isolation region of the second region. According to another aspect of the present invention, a method of fabricating a semiconductor device comprising the steps of: (a) forming an element isolation region having a plurality of active regions of 20 divisions in a semiconductor substrate having a first region and a second region; (b) etching the semiconductor substrate as the etching mask to form an element isolation trench for separating the plurality of active regions; (c) embedding the component isolation Ditch, deposition element isolation material film; 10 1321850 (d) The aforementioned element isolation material film is chemically mechanically polished to form an element isolation region while exposing the reticle insulating film pattern; (e) after the aforementioned step (d), Forming a photoresist pattern covering the second region, etching the element isolation region of the first region to remove a portion of the thickness of the 5 active regions; (f) removing the light after the step (e) a cover insulating film pattern; (g) after the foregoing step (1), forming the aforementioned element isolation region extending from the active region of the first region to the periphery thereof a first structure having a first height; 10 (h) after the step (f), forming the element isolation region extending from the active region of the second region to the periphery thereof and having a lower height than the first height The second structure of the second height. Can solve new problems. Patterning on a non-flat surface can be suppressed. 15 can suppress the residue of etching. It can reduce the height difference and expand the range of the photolithography process. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1-1]/[1-2th]/[1-3]/[1-4th] 1A-II, 1K shows the present invention Fig. 20 is a cross-sectional view showing the process of the semiconductor device of the embodiment. Fig. 1J is a plan view showing the arrangement of the gate electrodes. [Fig. 2-1] / [2-2] / [2-3] Fig. 2A - Fig. 2F are cross-sectional views showing the process of the semiconductor device of the second embodiment of the present invention. [Fig. 3] Figs. 3A and 3B are cross-sectional views showing the process of the semiconductor device according to the third embodiment of the present invention. 11 1321850 Application No. 95123911 Amendment Page 'Monthly Cut Repair (No Correct Replacement y [Fig. 4] Fig. 4 is a cross-sectional view of a semiconductor device having a transistor of a specific embodiment. [5- 1]][5-2]/[5-3]/[5th-4]; |/[5·5] 5th-8th - 5th shows the semiconductor device process shown in FIG. Fig. 5 [Fig. 6-1] / [6-2] 7 [6-3] Fig. 6 - Fig. 6 shows a semiconductor integrated circuit device in which a flash memory and a logic circuit are mixed. A cross-sectional view of the new topic.

C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 1 First, a method of manufacturing an integrated circuit including a flash memory and a logic circuit according to the prior art will be described with reference to Figs. 6-8 to 6G. As shown in Fig. 6A, the surface of the tantalum substrate is thermally oxidized to form a tantalum oxide film 2, on which a tantalum nitride film 3 is deposited by chemical vapor deposition (CVD). The nitride film 3 and the oxidized stone film are patterned by using a resist pattern, and the oxidized stone film 2 and the nitrided film 3 covering the shape of the active region B region are retained. The nitriding film of the nitriding stone is used as a money mask. The stone slab substrate is engraved to form an element isolation trench. After the surface of the element isolation trench is oxidized, the oxidized fragmentation film 4 is buried by high-density plasma (HDp) CVD. Chemical mechanical polishing (CMP) is performed from the surface of the oxidized stone film 4, and the ruthenium oxide film 4 is formed on the surface of the surface of the nitriding film 3. As shown in Fig. 6B, the nitriding stone is removed by hot phosphoric acid. The exposed buffered oxidized stone was removed by dilute hydrofluoric acid. In addition, STI's oxidized stone film: slightly _. * Around the STi_(4) area where the bulge can be obtained, the surface of the active area is thermally oxidized to form an emulsified stone film for ion implantation, and the active area is used for the formation of a channel for the well formation, and the threshold value is used for control. Ion implantation. After the ions are implanted, the sacrificial oxidized oxide film is removed. The step of the STI (the portion having the non-flat surface) around the active region is expanded to the outside. As shown in Fig. 6C, the surface of the active region is thermally oxidized to form a channel oxidized particle 6 for a flash memory. Also shown is a state in which a concave portion is formed in the STI around the active region by repeating the oxidized oxide film. As shown in Fig. 6D, the channel oxide film 6 is covered, and the polyimide film 7 is deposited by CVD, and etching is performed using a photoresist pattern to form a pattern in the gate width direction (the horizontal direction in the drawing). It is not easy to vertically and completely etch the polyimide film 7 at the step formed at the peripheral portion of the STI. As shown in Fig. 6E, a ruthenium film 8 covering the ruthenium film 7 is formed. For example, the polysilicon film 7 is covered, and after the yttrium oxide film and the nitriding film are deposited by CVD, the surface of the tantalum nitride film is thermally oxidized to form a yttrium oxide film. A photoresist pattern RP41 having an opening is formed on the active region to perform ion implantation for threshold control of the logic circuit region. Thereafter, the photoresist pattern RP41 is removed. As shown in Fig. 6F, a photoresist pattern RP42 having an opening is formed in a region where the ruthenium film 8 is removed, and the exposed ruthenium film is etched and removed. By this etching step, the STI outside the flash memory region is etched to lower the surface. Thereafter, the photoresist pattern RP42 is removed. As shown in FIG. 6G, the polysilicon film for forming the gate electrode is deposited by CVD to 9° to cover the peripheral circuit region, and the etching of the photoresist pattern having the shape of the gate electrode in the flash memory region is used to form the control gate. The pattern, the % of the pattern, also forms the pattern of the 0 Ν 0 film 8 and the floating gate 7. Ion implantation is performed to form the secret/secret area of the flash memory. The photoresist layer covering the _marking area and having the free electrode shape in the peripheral circuit region forms a pattern of the electrodes of the logic circuit. In the secret circuit, the ion is implanted, _ into the source / light pole area. 5 The correction system outlines the plane I of the shape of the electrode of the MOS transistor of the flash memory and the peripheral circuit. In the flash memory shown on the left side, the floating gate FG is arranged under the control CG. In the figure, the upper and lower sides are patterned according to the upper side of the control gate CG. Before the engraving, the floating fg is patterned in the width direction of the gate, and in the other regions such as the control gate (7), the floating layer 1 〇 layer, the enamel film, and the control gate layer are stacked. # When the silver gate is not completely isolated, the short circuit occurs. However, since the thickness of the ruthenium film on the sidewall of the gate is increased in the vertical direction, it is not easy to completely remove the ruthenium. Fig. 6 is a view showing a state in which the όνο film is not completely removed, the wall is left, and the polysilicon film 7 having the floating gate is left. When the floating gate adjacent to the polysilicon film 7 is short-circuited 15, a defective memory is generated. Even if only the ruthenium film 8 remains, the thin-walled ruthenium film can be a source of garbage generation. The control gate of the flash memory cell is placed on the floating gate and is at the highest STI present in the higher active region. On the other hand, the STI surface outside the flash memory region is reduced after the engraving step of the ΟΝΟ臈 and channel oxygen 20 fossil film shown in FIG. 6F, and there is no floating gate under the gate electrode. The lowest portion of the surface of the electrode layer is also much lower than the highest portion of the flash memory region. That is, the entire flash memory region is higher than the logic region, and the flash memory region forms a region such as a trapezoid when viewing the entire semiconductor wafer. An insulating film is formed on the substrate having such a height difference, and a contact hole, a 14 1321850 metal wiring or the like is formed to form a multilayer wiring structure, and only a difference in this step leads to a reduction in the focus of the multilayer wiring forming step. Hereinafter, a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to Figs. 1A to 1K. Fig. 1A - Fig. II are sectional views showing the main process, and Fig. 1J is a plan view showing the shape of the gate electrode. Fig. 1K is a sectional view of the control gate. As shown in Fig. 1, the surface of the tantalum substrate 1 is thermally oxidized to form a buffered hafnium oxide film 2 having a thickness of 1 μm, and a niobium nitride film 3 having a thickness of u〇nm is deposited thereon by CVD. The photoresist pattern 3 is used to form the nitride film 3 and the hafnium oxide film 2 in the form of FIG. 10, and the photomask insulating film formed by laminating the oxide oxide film 2 and the nitride film 3 is formed in a shape covering the active region. Pattern. The tantalum nitride film 3 is used as a masking mask to form a component isolation trench with a depth of 300 nm. The oxide (4) was deposited by HDPCVD to a thickness of 55 Gnm, and the element isolation trench was buried. The ruthenium oxide film 4 on the surface of the surface of the tantalum nitride film 3 is removed by CMP from the surface of the tantalum oxide film 4. • As shown in Fig. 1B, the photoresist 矽臈4 having the open area of the flash memory is formed to protrude, and the concave portion of the ruthenium oxide film 4 which has been etched by the rice is covered. Law

The pattern is then etched by HDPCVD to the surface of the active area: ] about 4 〇 nm. In the flash memory region, the tantalum nitride film 3 is etched away, and the tantalum nitride film 3 is etched away by hot phosphoric acid. It is removed by etching with a thin buffered yttrium oxide film 2. STI also eclipses 15 1321850 ^51239〗 No. 1 application description '^^~ 98. Engraved

______jU is obtained in the logic circuit area where the swelled STI surrounds the active area. Then, the surface of the inert region is thermally oxidized to form an oxygen-cut membrane for ion implantation, and the active regions are used for silk assisting, channel blocking layer formation, and ion-controlled ion implantation. After the ions are implanted, the sacrificial oxidized oxide film is removed. The oxidation of the milk is also _, and the recess around the active area is deepened. The surface of the active region is thermally oxidized to form a flash memory dragon element with a thickness of about 101 nm. In the (4) (4) region, in the step of Figure 1B, the STI surface is degraded by _, and the STI surface is stepped down due to the oxidation of the surname. If the removal of the area around the active area of the recess around the active area is small, the difference will be small. As shown in Fig. 1D, the oxidized stone film 6 was covered, and a concentrating film 7 having a thickness of 9 〇 was deposited by CVD, and a pattern was formed in the inter-width direction (horizontal direction in the drawing) by using a photoresist pattern. Since the STi surface of the flash memory region is lowered and the step is small, it is easy to vertically and completely etch the polyimide film 7. 15 As shown in FIG. 1E, a tantalum film covering the polysilicon film 7 is formed by, for example, covering the polysilicon film 7 and depositing a tantalum nitride film having a thickness of about 1 nm on the wafer by CVD. The surface is thermally oxidized to form a hafnium oxide film having a thickness of about 5 nm. The thickness of the entire ruthenium film 8 is about 15 nm. A photoresist pattern RP12 having an opening is formed on the active region to perform ion implantation for controlling the threshold value of the logic circuit region. Thereafter, the photoresist pattern RP12 is removed.

As shown in Fig. 1F, a photoresist pattern RP13 having an opening is formed in a region where the 〇N ◦ film 8 is removed, and the exposed ruthenium film 8 is etched away. Further, the exposed channel yttrium oxide film 6 is etched and removed. By this etching, the STI other than the flash memory region is also removed, and the surface thereof is lowered. However, the STI 16 1321850 surface height of the logic region is higher than the STI surface height of the flash memory region. Thereafter, the photoresist pattern RP13 is removed. As shown in Fig. 1G, a gate oxide insulating film G1 of yttrium oxide is formed by thermal oxidation on the surface of the active region of the logic region. When three kinds of gate insulating germanium are formed, 5 thermal oxidation and selective thermal oxidation etching are repeated twice, and then thermally oxidized, and a thin tantalum oxide film is sequentially formed from the thick tantalum oxide film. Therefore, the STI surface of the logic region is lowered, and the STI surface of the flash memory region is also high. Moreover, even if the flash memory area is low, the difference is reduced as compared with the prior art. The recess around the active area is deepened. 10, as shown in FIG. 1, the polysilicon film 9' deposited by CVD to form a gate electrode is etched using a photoresist pattern RP14 covering the logic region and having a gate electrode shape in the flash memory region, Further, the ruthenium film 'floating gate 7' is also etched to pattern the gate electrode of the flash memory. At this stage, the logic circuit region is covered by the photoresist pattern RP14 without being etched. Ion implantation is performed to form the source/drain regions of the flash memory. Thereafter, the photoresist pattern RP14 is removed. The oxidation of the side surface of the gate electrode is performed to form a flash memory structure. As shown in Fig. II, a photoresist pattern RP15 covering the flash memory region and having the gate electrode shape of the logic circuit region is newly formed, and the gate film 9 is etched to pattern the gate electrode of the logic circuit region. Thereafter, ion implantation of the logic circuit is performed to form a source/drain region. Thereafter, the photoresist pattern RP15 is removed. 〇 The 1J diagram schematically shows a plan view of the gate electrodes of the flash memory and the MOS transistor. The elongated active area AR is arranged in the longitudinal direction in the figure. 17 In the logic circuit, the gate electrode g of the MOS transistor extends across the active region AR and extends over the isolation region of the sti element. In the flash memory, the floating gate FG and the control gate CG extend across the active region and extend over the STI element isolation region. In the region between the control gates CG, the floating gate FG and the control gate CG are completely etched, and 5 there is no residue. The residue of the 0N0 film 8 and the polysilicon film 7 shown in Fig. 6H is not expected. Since the STI segment difference between the active region and the periphery is small in the flash memory region, the surname of the residue remaining can be easily performed. The 1K figure shows a cross-sectional view of the area between the control gates CG along the χ2_χ2 line of the 丨j diagram. Since the step difference of the surface of the base layer is small, the control gate and the floating gate 10 are completely easy to touch, which prevents the floating gate. Short circuit. In addition, Fig. U is a cross-sectional view taken along the line X1-X1. Thereafter, electrode formation, formation of an insulating film, formation of a multilayer wiring, and the like are performed. The STI surface of the flash memory region is lowered, and the surface level of the gate electrode surface of the logic region is within the distribution of the surface level of the gate electrode surface of the flash memory region. In the steps of FIG. 1H and FIG. The height difference of 9 is less than that of the prior art, so the focus of the photolithography technology is reduced. When the process of lowering the surface of the flash memory region is performed, a step is formed between the flash memory region and the logic region, and the film formation and removal on the step portion may cause a problem. The method of manufacturing the semiconductor device of the second embodiment will be described with reference to the second embodiment of Fig. 2 and the second embodiment, which is different from the first embodiment. . Figure 2A is the same as Figure 1A. After the surface of the stone substrate i is thermally oxidized to form the buffer yttrium oxide film 2, the tantalum nitride film 3 is deposited thereon by CVD. Using the photoresist pattern, the nitride (4) 3 and the oxide oxide 2 are patterned, and the nitride film 3 18 is used as a money mask to engrave the stone substrate to form an element isolation trench. The oxidation 11 is deposited by HDP CVD, and the components are buried. The oxidized stone film 4 on the surface of the surface of the nitride film 3 is removed by CMP' from the surface of the oxidized film 4. As shown in Fig. 2B, a gap is left in the periphery to form a photoresist pattern RP21 which opens the area of the flash memory 5, and the HDPCVD oxide film 4 is etched to the middle of the thickness on the surface of the active region. The STI surface of the flash memory region is lowered to form a step 5 at the position of the active region retreating from the flash δ hexon region. Thereafter, the photoresist pattern RP21 is removed, and the tantalum nitride film 3 and the buffered hafnium oxide film 2 are removed by etching in the same manner as in the third embodiment. The exposed active region is thermally oxygenated to form a channel oxidized oxide film for the flash memory region. As shown in Fig. 2C, the channel oxide film 6 is covered, the polysilicon film 7 is deposited, and the photoresist pattern is etched to form a pattern in the gate width direction. Here, the dummy body 7d is left as the step portion 5 is covered. Since the step portion 5 is formed away from the active region of the flash memory region, the gap 7 15 can be easily patterned with the separated dummy body 7d. As shown in Fig. 2D, the ruthenium film 8 covering the ruthenium film 7 is formed. A photoresist pattern RP23 having an opening is formed on the active region to perform ion implantation for threshold control of the logic circuit region. A region covering the flash memory region is formed, and the step of the polysilicon film 7 over the step portion 5 reaches the flat portion of the photoresist pattern RP23, and the exposed film is etched and removed. Further, the exposed channel yttria film 6 is etched away. Although it is the same step as the etching step shown in Fig. 1F, the etching of the tantalum film is performed on a flat surface which does not include a step formed between the flash memory region and the logical memory region, so etching can be easily performed. Thereafter, the photoresist pattern RP23 is removed. A gate insulating film is formed on the surface of the active region by thermal oxidation in the logic region 19 1321850. A polysilicon film of a gate electrode is deposited by CVD. As shown in Fig. 2E, the pattern of the control gate is provided in the flash memory region, and the photoresist pattern RP 5 24 covering the polyimide layer 7 and the germanium film 8 is formed in the step portion. The logic circuit area is covered by the photoresist pattern Rp24. The gate is patterned by the etch of the photoresist pattern RP24, and further, the όνο film 8 and the floating gate 7 are patterned. In the step portion 5, the polysilicon film 9 is patterned to cover the shape of the polysilicon layer 7 and the ruthenium film 8. Ion implantation is performed to form the source/drain regions of the flash memory. Thereafter, the photoresist pattern RP24 is removed. 10 As shown in FIG. 2F, a photoresist pattern Rp25 covering the flash memory region and the step portion and having the gate electrode shape of the logic circuit region is newly formed, and the polyimide film 9 is etched to form the gate electrode of the logic circuit region. pattern. Thereafter, ion implantation of the logic circuit is performed to form a source/drain region. According to the present embodiment, the step portion between the flash memory region and the logic region formed when the STI surface 15 of the flash memory region is lowered is actively placed, and the polysilicon film and the ruthenium film for the floating gate are actively left. The ruthenium film is used to control the gate, and the 〇N〇 film is in the shape of a concentrating film. It can prevent the όνο film from being scratched/checked and peeled off, reducing the possibility of garbage generation. The STI part of the flash memory area for flash memory can be used with other 2-step masks. The manufacturing method of the third embodiment will be described with reference to Figs. 3 and 3D. . The third map is the same as the first one. After the surface of the tantalum substrate is thermally oxidized to form a buffered hafnium oxide film 2, the tantalum nitride film 3 is deposited thereon by CVD. Using the photoresist pattern, the tantalum nitride film 3 and the tantalum oxide film 2 are patterned, and the tantalum nitride film 3 20 1321850 is used as the surname mask to form the element isolation trench. The oxidized stone film 4 was deposited by the CVD into the element isolation trench. The oxidized stone film 4 on the surface of the surface of the oxidized film 3 was removed by CMP from the surface of the oxidized stone film 4. As shown in Fig. 3B, a photoresist pattern RP31 which opens the flash memory region is formed. This photoresist pattern RP31 is used as a mask to perform ion implantation for threshold control of the active region of the flash memory. The same photoresist pattern Rp^ is used as an etching mask, and the HDPCVD yttrium oxide film 4 is etched to the middle of the thickness on the surface of the active region. Thereafter, the photoresist pattern RP31 is removed. The other steps are the same as in the first embodiment. By using both the ion implantation mask and the etching mask, the number of 10 masks can be suppressed. Hereinafter, specific embodiments of the present invention will be described. The main logic circuit is composed of a low-voltage CMOS transistor operating at 12 V, and the input/output circuit is composed of a voltage CMOS transistor operating from 2 5 ¥ to 3.3 V. The non-electric memory control circuit is operated at a high voltage of 5 V and 10 V. CMOS transistor construction. Low-voltage electric 15 crystal and high-voltage transistors have high threshold and low threshold, respectively. "A total of 11 kinds of transistors are used including non-electrical memory. As shown in Fig. 4, n-type wells 8〇, 84, 88 and Ρ-type wells 82 and 86 are formed on the semiconductor substrate 1 to form a p-type well 78 in the n-type well 80. A flash cell (Flash cell), a η pass-through high voltage low threshold transistor (N-HV Low Vt), and an n-channel high voltage high-interval transistor (high-voltage operation) are formed in the p-type well 78 ( N-HVHigh Vt). Is it formed at a high voltage in the n-type well 80? Channel high voltage low threshold transistor (P-HV Low Vt) and ρ channel high voltage high threshold transistor (P-HVHigh Vt). In the p-type well 82 and the n-type well 84, a voltage transistor (N-MV) in the n-channel and a 21-piezoelectric crystal (P-MV) in the pit channel are formed. An n-channel low-voltage high-threshold (N-LVHigh Vt) and an n-channel low-voltage low-threshold transistor (N-LV Low Vt) operating at a low voltage are formed in the p-type well 86 to form a p-channel in the n-type well 88. Low-voltage high-threshold transistor (P-LV HighV) and ρ-channel low-voltage low-threshold transistor (P-LV Low Vt) » η-channel voltage-transistor (n-MV) and ρ-channel voltage-transistor (P- MV) is a transistor that constitutes an input/output circuit, and is a transistor of 2.5V operation or 3_3V operation. The 2.5V operation and the 3.3V operation mean that the thickness of the gate insulating film, the threshold voltage control condition, and the LDD condition are different from each other, and it is not necessary to carry both of them at the same time, and only one of them is a general case. Hereinafter, a method of manufacturing the semiconductor device shown in Fig. 4 will be described. As shown in Fig. 5A, the pattern of the hafnium oxide film 12 and the tantalum nitride film 14 is formed on the tantalum substrate 1 by the steps described in the third embodiment, and the tantalum substrate 1 is etched to form a germanium isolation trench, and then buried. Into the ruthenium oxide film. The ruthenium oxide film on the level of the tantalum nitride film 14 is removed by CMP. An STI element isolation region 22 is formed. In this state, the photoresist pattern 15 exposing the memory region is formed on the substrate. The resist pattern was used as a mask to implant the threshold control ions at an acceleration energy of 4 〇 keV and a dose of 6×1 〇 13 cm 2 to form a p-type region 54. The photoresist pattern 15 was used as a surname mask, and the STI oxidized stone film 22 was removed by 40 nm. The surface of the milk cerium oxide film in the memory region is lowered to form a step difference of 20. The photoresist pattern 15 is removed, and the nitride film 14 and the oxidized stone film 12 are removed in all areas. The steps after this last name step are basically the same as the old one. In order to simplify the drawing, the step difference 20 is omitted and displayed. As shown in Fig. 5B, the active region is separated by the STI yttrium oxide film 22. A cerium oxide sacrificial film is formed by thermal oxidation. The n-type buried impurity layer 28 is formed in a flash cell formation region and an n-channel high-voltage piezoelectric crystal (N-HV) formation region. The n-type buried 5 impurity layer 28 is formed by implanting phosphorus (ρ+) ions at an acceleration energy of 2 MeV and a dose of 2xl013c m·2. The p-type well impurity layers 32, 34 are formed in a flash cell formation region, an n-channel transistor (N-HV, N-MV, N-LV) formation region. The p-type well impurity layer 32 is formed by implanting boron (Β+) ions at an acceleration energy of 400 keV and a dose of 1.5 x 1013 cm-2. The p-type well impurity layer 34 is formed by implanting boron ions at an acceleration energy of 100 keV, a dose of 2 >< 1012 cm_2. Forming a p-type well in a n-channel high-voltage high-threshold transistor (N-HV High Vt) formation region, a η channel voltage transistor (N-MV) formation region, and an η channel low voltage formation region (N-LV) formation region The impurity layer 40 is used. The p-type well impurity layer 40 is formed by implanting boron ions at an acceleration energy of 1 00 keV and a dose of 6 χ 1012 cm·2. An n-type well impurity layer 44 is formed in the p-channel transistor (P-HV, P-MV, P-LV) formation region. The n-type well impurity layer 44 is formed by implanting phosphorus ions at an acceleration energy of 600 keV and a dose of 3 x 1013 cm·2. Under this condition, a ρ channel high voltage low threshold transistor with a threshold voltage of about -0.2 V can be obtained (P-HVLow).

Vt). Forming a threshold voltage control impurity diffusion layer 48 in a p-channel high voltage high threshold transistor (P-HV High Vt) formation region, a voltage transistor (Ρ-MV) formation region in the p channel, and a P channel low voltage transistor ( The P-LV) formation region forms a channel barrier layer 50. The threshold voltage control impurity layer 48 and the channel block 23 layer 50 are formed by implanting phosphorus ions at an acceleration energy of 24 〇 keV and a dose of 5 x 1 〇 i 2 cm 2 . Under this condition, a threshold voltage of about _〇6Vip channel high voltage high threshold transistor (P-HVHigh Vt) can be obtained. After the ion implantation is completed, the cerium oxide sacrificial film is removed. 5 As shown in Fig. 5C, thermal oxidation was carried out for 30 minutes at a temperature of 900 to 1050 ° C to form a channel yttrium oxide film 56 having a film thickness of 1 〇 11111 on the active region. The channel yttrium oxide film 56 was covered, and a ruthenium-doped polyfluorene film having a film thickness of 90 nm was grown on the substrate by a CVD method. The phosphor-doped polyfluorene film is patterned by photolithography and dry etching, and a floating gate 58 formed of a 10 phosphorus-doped polyfluorene film is formed in a flash memory cell (Flash cdl) formation region. On the substrate of the floating gate 58, a cerium oxide film having a thickness of 5 nm and a tantalum nitride film having a thickness of 10 nm were grown by a CVD method. The surface of the tantalum nitride film is thermally oxidized at % 〇 ° C for 90 minutes to grow an oxide film having a thickness of about 5 nm on the surface to form a ruthenium film having a total thickness of about 15 nm (yttrium oxide film / tantalum nitride film 15 / oxidation) Diaphragm) 60. As shown in Fig. 5D, the threshold control ion implantation is performed in the transistor region to obtain the desired threshold. The threshold voltage control impurity layer 64 is formed in the voltage transistor (N_MV) formation region in the η channel. The threshold voltage control impurity layer 64 is formed by implanting shed ions at an acceleration energy of 3 〇 keV and a dose of 5 x 1012 cm -2 to obtain a threshold voltage of about +0.3 to +0.4 V. The impurity voltage layer 68 for threshold voltage control is formed in the p-channel forming region of the piezoelectric film (P-MV). The threshold voltage control impurity layer 68 is formed by implanting arsenic (As+) ions at an acceleration energy of 15 OkeV and a dose of 3 x 1012 cm 2 to obtain a threshold voltage of about _〇.3 - 0.4. 24 1321850 An impurity layer 72 for threshold voltage control is formed in the n-channel low-voltage high-threshold transistor (N-LV High) formation region. The threshold voltage control impurity 72 is formed by implanting boron ions at an acceleration energy of 10 keV and an amount of 5 x 1012 cm -2 to obtain a threshold voltage of about +0.2 V. The threshold voltage control impurity layer 76 is formed in the p-channel low voltage high threshold 5 transistor (P-LVHigh Vt) formation region. The threshold voltage control impurity layer 76 is formed by implanting arsenic ions at an acceleration energy of 100 keV and a dose of 5 x 1012 cm 2 , and a threshold voltage of about 〇 2 V can be obtained. Next, the light lithography technique is used to form a photoresist film 92 covering the flash memory cell forming region and exposing other regions. The photoresist film 92 is used as a mask by dry etching, and the ruthenium film 60 is etched to remove the ruthenium film 60 other than the region in which the flash memory cells are formed. Then, the photoresist film 92 is used as a mask by wet etching using a hydrofluoric acid aqueous solution, and the channel oxide film 56 is etched to remove the channel oxide oxide outside the flash memory cell formation region. After the film 56^, the photoresist film 92 is removed by ashing. As shown in Fig. 5E, thermal oxidation was carried out at a temperature of 850 ° C to form a hafnium oxide film 94 having a film thickness of 13 nm on the active region. A photoresist film 96 covering a flash cell and a high voltage transistor (Ν·Ην, ρ·Ην) region and exposing other regions is formed. The photo-resist film 96 is used as a mask by wet etching using a hydrofluoric acid aqueous solution to etch the hafnium oxide film 94, and the medium voltage transistor (Ν _MV, P-MV) formation region and the low voltage transistor (N-LV) are removed. , P-LV) forms a yttrium oxide film 94 in the region. After that, the photoresist is removed by ashing. As shown in Fig. 5F, thermal oxidation is performed at a temperature of 85 (rc), and a region is formed in a medium voltage transistor (Ν·ΜV, Ρ·ΜV) and a low voltage transistor (N_LV, 25 P-LV). A ruthenium oxide film 98 having a film thickness of 45 nm is formed on the active region. Further, in this thermal oxidation step, the film thickness of the ruthenium oxide film 94 is also increased. The light lithography technique is used to form a covered flash memory cell (Flash cell) Formation region, 焉 voltage transistor (N-HV, Ρ-HV) formation region, medium voltage transistor (N-MV 'P-MV) formation region and exposed low voltage transistor (n-LV, P-LV) The photoresist of the formation region is 〇0. The photoresist film 100 is used as a mask to etch the ruthenium oxide film 98 by wet etching using a hydrofluoric acid aqueous solution, and the low voltage transistor (N-LV, P-LV) is removed. A region of the ruthenium oxide film 98 is formed. Thereafter, the photoresist film 100 is removed by ashing. As shown in FIG. 5G, thermal oxidation is performed at a temperature of 850 ° C, and at a low voltage transistor (N-LV, P-LV). a gate insulating film 102 formed of a ruthenium oxide film having a film thickness of 2.2 nm is formed on the active region of the formation region. Further, in the thermal oxidation step, the film thickness of the ruthenium oxide films 94 and 98 is also increased. In the high voltage transistor (N-HV, P-HV) forming region, a gate insulating film having a film thickness of i6 nm is formed, and a film thickness of 5.5 nm is formed in a region where a medium voltage transistor (N-MV, P-MV) is formed. The gate insulating film is grown by a CVD method to form a polyimide film 1〇8 having a film thickness of i8 μm. Then, a tantalum nitride film 110 having a film thickness of 30 nm is grown on the polyimide film 1〇8 by a plasma CVD method. When the tantalum nitride film is a reflection preventing and etching mask that forms a pattern of the lower polysilicon film 108, the protective logic portion is also provided when the gate electrode side of the flash memory cell described later is oxidized. The function of the gate electrode is formed by photolithography and dry etching to form the yttrium oxide film 110, the polysilicon film 1〇8, the ruthenium film 60 and the floating gate 58 1321850 in the flash cell formation region. a pattern is formed to form a gate electrode 112 of a flash memory cell. As shown in FIG. 5H, the side surface of the gate electrode 112 of the flash memory cell is thermally oxidized by about 10 nm. Ion implantation in the source/drain region is performed. The side of the gate electrode 112 is thermally oxidized by about 1 Onm. Then, the nitridation is performed by thermal 5 CVD. After the film is deposited, the tantalum nitride film and the tantalum nitride film 110 are etched, and the sidewall insulating film 116 made of a tantalum nitride film is formed on the sidewall portion of the gate electrode 112, and the surface of the polyimide film 108 is exposed. Next, a high voltage transistor (N-HV, P-HV) formation region, a medium voltage transistor (N-MV, P-MV) formation region, and a low voltage transistor are formed by photolithography and dry etching (N- The 10 LV, P-LV) formation region of the polyimide film 1 〇 8 is patterned to form the gate electrode 118 composed of the polyimide film 108. As shown in Fig. 51, the source/drain S/D of each transistor of the logic circuit is formed. An extension of the source/drain region of the p-channel low voltage transistor (Ρ-LV) is formed. For example, boron ions are ion implanted at an acceleration energy of 55 keV, a dose of 3.6×10 15 15 4 rrT2, and an arsenic ion at an acceleration energy of 8 〇 keV, a dose of 6.5×10 12 cm −2 , and a tilt of 28 degrees from the substrate normal. It is formed as an extension of the attached pocket. An extension of the source/drain region of the n-channel low voltage transistor (N-LV) is formed. For example, the arsenic ion is tilted by 28 degrees from the substrate normal at an acceleration energy of 3 keV, a dose of l.lxl15 cm-2, and a boron fluoride ion (BF2+) at an acceleration energy of 35 ke 20 v and a dose of 9.5 x 1012 cm 2 . It is formed by ion implantation and serves as an extension of the attached pocket. An extension region of the source/drain region of the voltage transistor (P-MV) in the p-channel is formed. For example, boron fluoride ions are formed by implanting under conditions of an acceleration energy of 1 〇 keV and a dose of 7 x 10 13 cm 2 . Forming an extension region of the source/secret region of the voltage transistor (N-27 MV) in the n-channel, for example, by correcting the ion to accelerate the energy lOkeV, the dose of 2 χΐπ13 Λ -2 ^ 2 10 cm, and the phosphorus ion The acceleration energy is formed by ion implantation by the conditions of eV and dose 3x1QlW. An example of the extension of the source/nomogram region of the P-channel high voltage transistor (p_HV) is formed. It will be formed by implanting a butterfly ion to accelerate the break of eV and a dose of 45 χΐ〇 cm. Forming an n-channel high-voltage transistor (the extension region of the source/drain region between N_. For example, the hetero-ion is formed by ion implantation at an acceleration energy of 35 keV and a dose of 4 χ 10% -2. The thermal CVD method is used to cut the wire, and the sidewall insulating film 144 composed of the yttrium oxide film is formed on the sidewall portion of the gate electrode. The photoresist film is used as a mask to perform ion implantation to form a flash. The memory cell (Flash cell) and the source/drain region of the n-channel transistor, whereby the ion-implanted 'flash memory cell and the η channel's electrodeless electrode are doped into an n-type. Source/汲The polar region is formed by implanting the ions at an acceleration energy of 1 〇 keV, a dose of 6 < 1015 cm · 2. The source/drain region of the P-channel transistor is formed. By ion implantation, p-channel The gate electrode of the transistor is doped p-type. The source/drain region 152 is formed by implanting boron ions at an acceleration energy of 5 keV and a dose of 4xl 〇i5 cm·2. The metal-lithium alloy process automatically aligns the fragmentation electrode on the gate electrode and the source/no-pole. 1〇1 transistor is completed. An insulating film 154 is deposited on the substrate 10 on which the transistor is formed, a contact hole is formed, and a conductive plug 158 is buried to form a second layer metal wiring 160 on the insulating film 154. As shown in FIG. 5J, the deposition of the insulating film, the wiring, and the like are repeated to form the multilayer wiring layer 162 of the desired number of layers. The insulating film 164 is deposited on the multilayer wiring layer 162 to form a contact hole, and the conductive plug 168 is buried. A passivation film 174 is formed on the insulating film 164 on which the wiring layer 170' pad electrode 172 or the like is formed, and the pad electrode is opened. Thus, the semiconductor device is completed. Further, the flash memory cell, the logic transistor, For the process of the multilayer wiring, a well-known process can be used. For example, it can be referred to the "Best Form for Carrying Out the Invention" of Japanese Patent Laid-Open Publication No. Hei. No. 5-142362. The semiconductor device of the flash memory is not limited thereto. The type of the transistor can be appropriately increased or decreased. The memory is not limited to the flash memory. The present invention has been described based on the above embodiments, and the present invention does not It can be widely used when forming a pattern on a plurality of active regions separated by STI element isolation regions to form a pattern having a height of not the same. It is described that the gate electrodes of the flash memory and the MOS transistor are used as structures having different heights. It is effective to construct an electric conductor having a different number of layers, for example, a single-layer structure and a laminated structure. Further, the manufacturer should be able to select various circuits, and various other modifications, improvements, combinations, etc. can be performed. A semiconductor integrated circuit suitable for forming structures having different heights on a plurality of active regions separated by an STI element isolation region, and is applicable to a semiconductor device including a non-electrical memory having a floating gate. [闽 style simple description 3

[Fig. 1-1] / [1-2] / [1-3] / [1-4] Fig. 1A - II 29 1321850 Fig. 1K shows the first embodiment of the present invention A cross-sectional view of a semiconductor device process. Fig. 1J is a plan view showing the arrangement of the gate electrodes. [Fig. 2-1] / [2-2] / [2-3] Fig. 2A and Fig. 2F are cross-sectional views showing the process of the semiconductor device of the second embodiment of the present invention. [Fig. 3] Figs. 3A and 3B are cross-sectional views showing the process of the semiconductor device of the third embodiment of the present invention. [Fig. 4] Fig. 4 is a cross-sectional view showing a semiconductor device having 11 kinds of transistors in a specific embodiment. [Fig. 5-1] / [5-2] / [5-3] / [5-4] / [5-5] 5A Fig. 10 - Fig. 5J shows Fig. 4 A cross-sectional view of the illustrated semiconductor device process. [Fig. 6-1] / [6-2] / [6-3] Fig. 6A, Fig. 6H is a cross section showing a new subject of a semiconductor integrated circuit device in which a flash memory and a logic circuit are mixed. Figure. [Main component symbol description] 1 夕 substrate 2.. buffered yttrium oxide film 3.. yttrium nitride film 4.. yttrium oxide film 5.. . Step difference 6.. . Channel oxidized stone film 7.. Polythene film 7d...Simulation body 8..ΟΝΟ Film 9.. Polyimide film 10.. Substrate 12... Cerium oxide film 14.. Tantalum nitride film 15... Resistive pattern 20.. Step difference 22.. 5.I. Element isolation region 28 ... η type buried impurity layer 32.. ρ type well impurity layer 34.. ρ type well impurity layer 40.. ρ type well impurity Layer 44.. η type well impurity layer 48.·Thickness voltage control impurity layer 30 1321850 50... channel barrier layer 152... source/drain region 54...p-type region 154...insulation film 56 ... channel yttrium oxide film 158... conductive plug 58... floating gate 160... first layer metal wiring 60. "ΟΝΟ film 162...multilayer wiring layer 64... threshold voltage control Impurity layer 164, insulating film 68...threshold voltage control impurity layer 168...conductive plug 72...threshold voltage control impurity layer 170...wiring layer 76...threshold voltage control impurity Layer 172... pad electrode 78···p type well 174...passivation film 80... n type well RP11...resist pattern 82 _·.ρ-type well RP12...resist pattern 84··. η-type well RP13...resist pattern 86···ρ-type well RP14...resist pattern 88... η-type well RP15. .. photoresist pattern 92... photoresist film RP21... photoresist pattern 94... ruthenium oxide film RP23... photoresist pattern 96... photoresist film RP24... photoresist pattern 98... ruthenium oxide film RP25. .. photoresist pattern 100... photoresist film RP31... photoresist pattern 102... gate insulating film RP41... photoresist pattern 108... polysilicon film RP42... photoresist pattern 110.. . The tantalum nitride film G... gate electrode 112... gate electrode CG... control gate 116... sidewall insulating film FG... floating gate 118.. gate electrode 144.. sidewall insulating film AR. ..active area 31

Claims (1)

X. Patent application scope: ^~-- 1. A semiconductor device comprising: 1321850 semiconductor substrate, having the first region and the second region. The STI device isolation region is formed after the semiconductor chip. The isolation trench and the insulating film embedded in the element isolation trench are formed, and the plurality of active regions separating the first region and the second region are formed; and the first structure is formed on the active region of the second region to φ The surrounding STI element isolation region has a first height; and the second structure is formed on the active region of the second region to the surrounding STI element isolation region, and has a second lower than the first height Further, the surface of the STI element isolation region of the first region is lower than the surface of the STI element isolation region of the second region, and the first region is a memory cell region, and the second region is logic In the circuit area, the STI surface height of the memory cell region is substantially equal to the surface height of the active Φ region. 2. The semiconductor device of claim 4, wherein the first and second structures comprise electrical conductors having different numbers of layers. The semiconductor device of claim 1, which has a gate insulating film formed on a surface of a plurality of active regions and having different thicknesses, and a region which is formed in a region apart from a boundary of each of the aforementioned impurity regions The device is a gate electrode having a floating gate and a cattle conductor device, wherein the first structure gate insulating film and the control gate are non-electrical memory 32 1321850 and the second structure is a gate electrode of the MOS transistor. 5. The semiconductor device of claim 4, wherein the STI element isolation region has a step difference between a boundary region of the memory cell region and the logic circuit region, and the semiconductor device includes a step covering the aforementioned step A virtual floating gate formed by the same material as the aforementioned floating gate. 6. The semiconductor device of claim 5, further comprising: a dummy inter-gate insulating film formed on the dummy floating gate and formed of the same material as the gate insulating film; and formed in the dummy A dummy control gate formed on the inter-gate insulating film and the dummy floating gate and formed of the same material as the aforementioned control gate. A semiconductor device comprising a memory cell region and a logic circuit region having gate insulating films having different thicknesses from each other, wherein the memory cell region and the logic circuit region are formed by a trench formed by embedding in the semiconductor substrate The element isolation film is separated, and the element isolation film has a concave portion at a boundary with the active region, and the height of the element isolation film of the memory cell region is lower than the height of the element isolation film of the logic circuit region. 8. A method of manufacturing a semiconductor device comprising the steps of: (a) forming a mask insulating film shape having an opening of an element isolation region for separating a plurality of active regions in a semiconductor substrate having a first region and a second region; (b) using the reticle insulating film pattern as a mask, and engraving the semiconductor substrate to form an element isolation trench for separating the plurality of active regions; (c) embedding the component isolation trench to deposit the device (d) forming the element isolation material film into a 33 1321850 element isolation region by chemical mechanical polishing, and exposing the cover insulating film pattern; (e) after the step (d), forming the second region a photoresist pattern, wherein the element isolation region of the first region is etched to remove a portion of the thickness of the active region; (1) after the step (e), removing the mask insulating film pattern; (g) After the step (1), forming a first structure having a first height from the element isolation region extending from the active region of the first region to the periphery thereof; (h) after the step (1), forming a second structure having a second height lower than the first height from the element isolation region extending from the active region of the second region to the periphery thereof, and the second structure The 1 region is a memory cell region, the second region is a logic circuit region, and the STI surface height of the memory cell region is substantially equal to the surface height of the active region. 9. The method of fabricating a semiconductor device according to claim 8, wherein the steps (g) and (h) form a conductor having a different number of layers. 10. The method of manufacturing a semiconductor device according to claim 8, further comprising the steps of: (1) forming a memory cell gate insulating film on the plurality of active regions before the step (g); (1) removing the foregoing a gate insulating film for the memory cell in the second region; and (k) a gate insulating film for the MOS transistor formed on the active region of the second region. The method of manufacturing a semiconductor device according to claim 10, further comprising the steps of: (1) performing ion implantation for threshold control in the first region using the photoresist pattern of the above step (e). 12. The method of manufacturing a semiconductor device according to claim 10, wherein the step (g) comprises the steps of: (g-Ι) covering the memory cell insulating film for the memory cell to form a floating gate layer (g-2) a pattern in which the floating gate layer is formed in the gate width direction; (g-3) a floating gate layer covering the gate width direction to form a pattern, and a gate insulating film is formed on the semiconductor substrate; (g-4) a gate insulating film is patterned; (g-5) covering the previously patterned gate insulating film to form a gate electrode layer on the substrate; (g-6) forming the gate electrode layer into a pattern and in the gate length direction The gate insulating film and the floating layer are patterned in the upper portion. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the step (h) comprises the steps of: (h-1) and the aforementioned step (g-5) - in the foregoing second region in the aforementioned MOS A gate electrode layer is formed on the gate insulating film for a crystal; (h-2) the gate electrode layer is patterned in the second region. 14. The method of fabricating a semiconductor device according to claim 12, wherein the foregoing step (e) forms a step difference in the element isolation region, and the step (g-2) retains a dummy floating gate on a step difference of the element isolation region. . 15. The method of manufacturing a semiconductor device according to claim 14, wherein the step (g-4) retains a dummy inter-gate insulating film on a portion of the surface of the dummy floating gate, and the foregoing step (g-6) A dummy gate is left on the dummy floating gate and the aforementioned dummy gate insulating film. 36