TWI317523B - Output driving device - Google Patents

Output driving device Download PDF

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TWI317523B
TWI317523B TW095123921A TW95123921A TWI317523B TW I317523 B TWI317523 B TW I317523B TW 095123921 A TW095123921 A TW 095123921A TW 95123921 A TW95123921 A TW 95123921A TW I317523 B TWI317523 B TW I317523B
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pull
control signal
node
signal
output
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TW095123921A
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Chinese (zh)
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TW200713318A (en
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Kee-Teok Park
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Description

U17523 九、發明說明： 【發明所屬之技術領域】 本發明《於一種用⑤一半導體記憶冑t 4中之輸出驅 動裳置，且更明確地說’係關於一種用於藉由改良一轉換 率⑽W論)來保護-有效資料週期之一邊緣的輪出驅動 震置。 【先前技術】 通々，一推挽型驅動器廣泛用作一輸出驅動裝置。關於 挽型輸出驅動器之控制’轉換率的控制已成為一問題： 轉換與-輸出訊號之電壓位準變化多快有關。將轉換率 界定為一展示-電壓位準變化與一單位時間之間之比例的 斜率。 可將轉換率分類為兩種類型：一上升轉換率及—下降轉 換率。上升轉換率指示一自一低位準至一高位準變化之輸 出訊號之電壓位準的斜率。下降轉換率指示一自一高位準 至一低位準變化之輸出訊號之電壓位準的斜率。在任一情 況下，轉換率愈大，輸出訊號之斜率愈陡。換言之，輸出 §fl號之電壓位準在一短時間内變化。 ’ 圖1係一用於一半導體記憶體裝置中之習知輸出驅動器 的示意電路圖。 習知輸出驅動器包括一上拉驅動器PM1，其用於響應於 上拉驅動5凡號PU 一 CTR而上拉驅動一輸出驅動器；及一下 拉驅動器NM1，其用於響應於—下拉驅動訊號PD—CTR而下 拉驅動該輸出驅動器。 112659.doc 1317523 詳言之，上拉驅動器PM 1係一連接於一驅動電壓VDDQ 與輸出節點之間的p型金屬氧化物半導體（PM〇s)電晶體。 PMOS電晶體之一閘極接收上拉驅動訊號pu_CTR。下拉驅 動器NM1係一連接於輸出節點與一接地電壓VSSq之間的n 型金屬氡化物半導體（NMOS)電晶體^ NMOS電晶體之一閘 極接收下拉驅動訊號pd__ctr。 圖2係描繪習知輸出驅動器之一操作的波形圖。 參看圖2’用於上拉驅動操作之上拉驅動訊號pu—ctr具 有比下拉驅動訊號PD—CTR更長之啟動週期。此由一包括 於習知輸出驅動器中之元件之一特性而引起。換言之， PMOS电晶體pMl之驅動強度及轉換率小於電晶體 NM1之驅動強度及轉換率。 因此，為了保護對於輸出資料之邏輯位準“H”及“l” 相同的有效資料窗，PM〇s電晶體pM1經設計以具有一較大 寸一…、而右增大PMOS電晶體pM1之尺寸，則輸出訊號 更易又雜訊之衫響。另外，因為增大輸出節點之電容，所 以輸入特性可在輸入/輸出雙向資料期間降等。上述問題 在一高速操作期間更為嚴重。 【發明内容】 本發明之一目標係提梃一 率來保護一有效資料週期之一邊緣U17523 IX. Description of the Invention: [Technical Field of the Invention] The present invention "drives the output in an output using a semiconductor memory 胄t 4, and more specifically" is used to improve a conversion rate. (10) W)) to protect - the wheel drive drive at the edge of one of the valid data cycles. [Prior Art] A push-pull type driver is widely used as an output driving device. Regarding the control of the pull-type output driver, the control of the slew rate has become a problem: how fast the conversion and the voltage level of the output signal change is related. The conversion rate is defined as the slope of the ratio between the display-voltage level change and a unit time. The conversion rate can be categorized into two types: a rising conversion rate and a falling conversion rate. The rising slew rate indicates the slope of the voltage level of the output signal from a low level to a high level change. The falling slew rate indicates the slope of the voltage level of the output signal from a high level to a low level change. In either case, the greater the conversion rate, the steeper the slope of the output signal. In other words, the voltage level of the output §fl changes in a short period of time. Figure 1 is a schematic circuit diagram of a conventional output driver for use in a semiconductor memory device. The conventional output driver includes a pull-up driver PM1 for pulling up an output driver in response to the pull-up driver 5, and a pull-down driver NM1 for responding to the pull-down driver signal PD. The output driver is pulled down by CTR. 112659.doc 1317523 In detail, the pull-up driver PM 1 is a p-type metal oxide semiconductor (PM 〇s) transistor connected between a driving voltage VDDQ and an output node. One of the gates of the PMOS transistor receives the pull-up drive signal pu_CTR. The pull-down driver NM1 is a n-type metal-telluride semiconductor (NMOS) transistor connected to the ground node VSSq and receives a pull-down driving signal pd__ctr. Figure 2 is a waveform diagram depicting the operation of one of the conventional output drivers. Referring to Figure 2' for the pull-up drive operation, the pull-up drive signal pu-ctr has a longer start-up period than the pull-down drive signal PD-CTR. This is caused by a characteristic of one of the components included in the conventional output driver. In other words, the driving strength and conversion rate of the PMOS transistor pM1 are smaller than the driving strength and conversion ratio of the transistor NM1. Therefore, in order to protect the same valid data window for the logic levels "H" and "l" of the output data, the PM〇s transistor pM1 is designed to have a larger inch... and increase the PMOS transistor pM1 to the right. Size, the output signal is easier and the noise of the shirt is ringing. In addition, because the capacitance of the output node is increased, the input characteristics can be reduced during the input/output bidirectional data. The above problems are more serious during a high speed operation. SUMMARY OF THE INVENTION One object of the present invention is to improve the rate of protection of one of the edges of an active data period.

112659.doc 係挺供一種用於藉由改良一轉換 之一邊緣的輸出驅動器。 提供一種輸出驅動裝置，其包括： 丨應於一上拉控制訊號而上拉驅動 '器，其祕響應於一下拉控制訊 1317523 號而下拉驅動該輸出節點；及—第—n型金屬氧化物半導體 (NMOS)包aa體’其用於響應於—預上拉控制訊號而上拉驅 動該輸出節點。 根據本發明之另_態樣，提供一種輸出驅動裝置，其包 上拉驅動器’其用於響應於—上拉控制訊號而上拉 驅動-輸出節，點；-下拉驅動器，其用於響應於一下拉控 制訊號而下拉驅動該輸出節，點；一第一NM0S電曰曰曰體，其用 於響應於一預上拉控制訊號而上拉驅動該輸出節點；及一 第-PMOS電晶體，其用於響應於一預下拉控制訊號而下拉 驅動該輸出節點。 根據本發明之另一態樣，提供一種半導體裝置，其包括： -第-上拉驅動單元，其用於響應於—第—上拉控制訊號 而將-輸出節點上拉至一上拉電壓；一上拉位準偏移電 路’其用於響應於一預上拉訊號而產生一第二上拉控制訊 號，其中該第二上拉控制訊號之位準高力第一上拉控制訊 號之位準；及一第二上拉驅動單元，其目於響應於第二上 拉控制sfl號而將輸出節點上拉至上拉電壓。 根據本發明之另一態樣，提供一種半導體裝置，其包括： -第-下拉驅動單元用於響應於一第一上拉控制訊號 而將一輸出節點下拉至一下拉電壓；一上拉位準偏移電 路’其用於響應於一預下拉訊號而產生一第二下拉控制訊 號，其中該第二下拉控制訊號之位準高於第一下拉控制訊 號之位準；及一第二下拉驅動單元，其用於響應於第二下 拉控制訊號而將輸出節點下拉至下拉電壓。 112659.doc 1317523 邏輯低位準，所以下拉位準轉換單元200減小預下拉增強訊 號PD_PRE_EMP之電壓位準，使得預下拉增強訊號 PD—PRE—EMP之電壓低於接地電壓VSSQ，且然後將已減小 的訊號作為預下拉控制訊號PD_BB予以輸出。因此，當啟 動下拉驅動器NM2時，亦啟動第一PM0S電晶體pM3，以用 下拉驅動器NM2來下拉驅動該輸出節點。112659.doc is an output driver for one of the edges by improving a conversion. An output driving device is provided, comprising: a pull-up driving device on a pull-up control signal, the secret pull-down driving the output node in response to pulling the control signal 1317523; and - the -n-type metal oxide The semiconductor (NMOS) package aa body 'is used to pull up the output node in response to the pre-pull control signal. According to another aspect of the present invention, an output driving device is provided which includes a pull-up driver for pulling up a drive-output node in response to a pull-up control signal, and a dot-down drive for responding to Pulling down the control signal to pull down the output node, a point; a first NM0S body for pulling up to drive the output node in response to a pre-pull control signal; and a first PMOS transistor, It is used to pull down the output node in response to a pre-pull control signal. According to another aspect of the present invention, a semiconductor device is provided, comprising: a first-pull-up driving unit for pulling up an output node to a pull-up voltage in response to a first-up pull-up control signal; a pull-up level shifting circuit for generating a second pull-up control signal in response to a pre-pull signal, wherein the second pull-up control signal has a high level of power and a first pull-up control signal And a second pull-up driving unit, wherein the output node is pulled up to the pull-up voltage in response to the second pull-up control sfl number. According to another aspect of the present invention, a semiconductor device is provided, comprising: - a pull-down driving unit for pulling down an output node to a pull-down voltage in response to a first pull-up control signal; The offset circuit is configured to generate a second pull-down control signal in response to a pre-pull-down signal, wherein the second pull-down control signal has a higher level than the first pull-down control signal; and a second pull-down driver a unit for pulling down the output node to the pull-down voltage in response to the second pull-down control signal. 112659.doc 1317523 logic low level, so the pull-down level quasi-conversion unit 200 reduces the voltage level of the pre-pull-up enhancement signal PD_PRE_EMP, so that the voltage of the pre-pull-up enhancement signal PD_PRE_EMP is lower than the ground voltage VSSQ, and then will be reduced The small signal is output as a pre-down pull control signal PD_BB. Therefore, when the pull-down driver NM2 is activated, the first PMOS transistor pM3 is also activated to pull down the driver node with the pull-down driver NM2.

儘官圖6中展示預上拉增強訊號pu一pRE—EMp及上拉控 制訊號pu同時啟動，且預下拉增強訊號pD—pRE_EMp及下 拉控制訊號PD同時啟動，但預上拉增強訊號州―赃―EMp 及預下拉増強訊號PD—PRE_EMP可分別早於或遲於上一拉控 制訊號PU及下拉控制訊號PD而啟動。 圖7係展示一通用M〇s電晶體之一特性的圖式。 如所展不，一 NMOS電晶體之轉換率在初始操作時比一 PMOS電aa體之轉換率更好。另外，亦展示電晶體可 比NMOS電晶體輸送—更高電壓位準。 根據本發明之較佳實施例，因為額外包括一nm〇s電晶體 以便上拉驅動-輸出節點，所以可補充—上拉驅動器（意 即，一 PMOS電晶體）之轉換率特性。 因此才艮據本务明之較佳實施例的驅動輸出装置可藉由 改良一轉換率而保護—有效資料週期収夠邊緣。 本申請案含有與分別於·5年9月29日及屬 日在韓國專利局申請之韓國專利申請案第2005-9 i 669號及 第2005-133958唬有關的主題，該等專利申請案之全部内容 以引用的方式併入本文中。 112659.doc 12 【圖式簡單說明】The pre-pull enhancement signal pu-pRE-EMp and the pull-up control signal pu are simultaneously activated, and the pre-pull-up enhancement signal pD-pRE_EMp and the pull-down control signal PD are simultaneously activated, but the pre-pull enhancement signal state-赃The EMp and pre-down pull-up signal PD-PRE_EMP can be started earlier or later than the last pull control signal PU and the pull-down control signal PD. Figure 7 is a diagram showing one of the characteristics of a general-purpose M〇s transistor. As shown, the conversion rate of an NMOS transistor is better than that of a PMOS aa body during initial operation. In addition, it is also shown that the transistor can be delivered at a higher voltage level than the NMOS transistor. In accordance with a preferred embodiment of the present invention, the conversion rate characteristic of the pull-up driver (i.e., a PMOS transistor) can be supplemented because an additional nm 〇s transistor is additionally included to pull up the drive-output node. Therefore, the drive output device according to the preferred embodiment of the present invention can be protected by improving a conversion rate - the effective data period is sufficient for the edge. The present application contains the subject matter related to Korean Patent Application Nos. 2005-9 i 669 and 2005-133958, respectively, filed on Sep. 29, the Japanese Patent Office, and the Japanese Patent Application, respectively. The entire content is incorporated herein by reference. 112659.doc 12 [Simple description]

1317523 广已關於特定實施例描述了本發明，但熟習此項技術 者將易瞭解在Μ離下文之中料㈣时所界定的本發 明之精神及料的情況下可作出各種變化及修改。 圖1係一用於—半導體記憶體裝置中之習知輸出驅動器 的示意電路圖； 圖2係習知輸出驅動器之一操作的波形圖； 圖3係根據本發明之較佳實施例之用於—半導體記㈣ 裝置中之輸出驅動裝置的示意電路圖； 圖4係圖3中所展示之上拉位準轉換單元的示意電路圖； 圖5係圖3中所展示之下拉位準轉換單元的示意電路圖； 圖6係圖3中所展示之輸出驅動裝置之一操作的波形 圖；及 圖7係展示一通用MOS電晶體之一特性的圖。 【主要元件符號說明】 100 上拉位準轉換單元 200 下拉位準轉換單元 11 第一反轉器 12 第二反轉器 ΝΜ1、ΝΜ2 下拉驅動器/NMOS電晶體 ΝΜ3 第一 η型金屬氧化物半導體（NMOS)電 晶體 ΝΜ4 第二NMOS電晶體 NM5 第三NMOS電晶體 112659.doc • 13· 1317523The present invention has been described with respect to the specific embodiments thereof, and it will be apparent to those skilled in the art that various changes and modifications can be made in the present invention without departing from the spirit and scope of the invention. 1 is a schematic circuit diagram of a conventional output driver for use in a semiconductor memory device; FIG. 2 is a waveform diagram of one of the operations of a conventional output driver; FIG. 3 is for use in accordance with a preferred embodiment of the present invention - BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4 is a schematic circuit diagram of a pull-up level conversion unit shown in FIG. 3; FIG. 5 is a schematic circuit diagram of a pull-level level conversion unit shown in FIG. Figure 6 is a waveform diagram showing the operation of one of the output driving devices shown in Figure 3; and Figure 7 is a diagram showing one of the characteristics of a general-purpose MOS transistor. [Main component symbol description] 100 pull-up level conversion unit 200 pull-down level conversion unit 11 first inverter 12 second inverter ΝΜ1, ΝΜ2 pull-down driver/NMOS transistor ΝΜ3 first n-type metal oxide semiconductor ( NMOS) transistor ΝΜ 4 second NMOS transistor NM5 third NMOS transistor 112659.doc • 13· 1317523

NM6 第四NMOS電晶體 NM7 第五NMOS電晶體 PM1、PM2 上拉驅動器/PMOS電晶體 PM3 第一 p型金屬氧化物半導體（PMOS)電 晶體 PM4 第二PMOS電晶體 PM5 第三PMOS電晶體 PM6 第四PMOS電晶體 PM7 第五PMOS電晶體NM6 Fourth NMOS transistor NM7 Fifth NMOS transistor PM1, PM2 Pull-up driver / PMOS transistor PM3 First p-type metal oxide semiconductor (PMOS) transistor PM4 Second PMOS transistor PM5 Third PMOS transistor PM6 Four PMOS transistor PM7 fifth PMOS transistor

112659.doc - 14-112659.doc - 14-

Claims (1)

D 17¾)¾ 123921號專利中請案 _______ . 中文申請專利範圍替換本(98年7月） 阶年9月Π日修正夺 十、申請專利範圍： -二-- i 一種輸出驅動裝置，其包含： 一上拉驅動器’其用於響應於一上拉控制訊號而上拉 驅動一輸出節點； 一下拉驅動器，其用於響應於一下拉控制訊號而下拉 驅動該輸出節點；一第一 n型金屬氧化物半導體（NM〇s) 電晶體，其用於響應於一預上拉控制訊號而上拉驅動該 輸出節點；及 一上拉位準轉換單元，該上拉位準轉換單元用於藉由 增大一預上拉增強訊號之一啟動電壓位準而產生該預上 拉控制§fl號，使得該預上拉增強訊號的該啟動電壓位準 高於一驅動電壓。 2.如請求項1之輸出驅動裝置，其中在該上拉控制訊號之一 啟動之前、之後或期間的一段預定時間啟動該預上拉控 制訊號。 Φ；) 3.如明求項2之輸出驅動裝置，其中該第一 NMOS電晶體· • 及極源極路徑連接於該驅動電壓與該輸出節點之間 且該第一 NM0S電晶體之一閉極接收該預上拉控制訊號 .4·如請求項3之輸岀驅動裝置，其中該上拉驅動器包括一 一 P型金屬氧化物半導體（PM〇s)電晶體，其中該第 PMOS電晶體之—没極_源極路徑連接於該驅動電壓與] 輸出節點之間，且該第—讀⑽電晶體之—閘極接收該 拉控制訊號。 5·如請求項4之輸出驅動裝置’其中該下拉驅動器包括一: 112659-980717.doc 1317523 二NMOS電晶體，其中該第二NMOS電晶體之一汲極-源極 路徑連接於一接地電壓與該輸出節點之間，且該第二 NMOS電晶體之一閘極接收該下拉控制訊號。 6_如請求項5之輸出驅動裝置，其中該上拉位準轉換單元包 括： 一第三NMOS電晶體，其汲極-源極路徑連接於一第一 節點與該接地電壓之間，且其閘極接收該預上拉增強訊 號； 一反轉器，其用於將該預上拉增強訊號反轉； 一第四NMOS電晶體，其汲極-源極路徑連接於一第二 節點與該接地電壓之間，且其閘極接收該反轉器之一輸 出； 一第二PMOS電晶體，其汲極-源極路徑連接於該第一 節點與一高電壓之間，且其閘極耦接至該第二節點，其 中該高電壓高於該驅動電壓；及 一第三PMOS電晶體，其汲極-源極路徑連接於該第二 節點與該高電壓之間，且其閘極耦接至該第一節點。 7. —種輸出驅動裝置，其包含： 一上拉驅動器，其用於響應於一上拉控制訊號而上拉 驅動一輸出節點； 一下拉驅動器，其用於響應於一下拉控制訊號而下拉 驅動該輸出節點； 一第一 NMOS電晶體，其用於響應於一預上拉控制訊號 而上拉驅動該輸出節點； 112659-980717.doc 1317523 ::- m〇s電晶體，其用於響應於一預下拉控制訊號 而下拉驅動s玄輸出節點；及 一上拉位準轉換單元，其用於藉由增大_預上拉增強訊 一啟動錢位準而產生該預上拉控制訊號，使得該預 上拉增強訊號之該啟動職位準高於—驅動電塵。 8.如請求項7之輸出驅動裝置，其進—步包含： 下拉位準轉換單元，其用於藉由減小-預下拉增強 訊號之-啟動電墨位準而產生該預下拉控制訊號，使得 _下拉增強訊號之該啟動„位準低於—接地電塵。 9.如請求則之輸出驅動裝置，其中在該上拉控制訊號之一 啟動之別、之後或期間的一段預定時間啟動該預上拉控 制訊號’且在該下拉控制訊號之—啟動之前、之後或期 間的一段預定時間啟彰該預下拉控制訊號。 W如請求項9之輪出驅動裝置’其中該第一雇⑽電晶體之 一沒極-源極路徑連接於該驅動㈣與該輸出節點之間， 且該第NMOS電晶體之一閘極接收該預上拉控制訊號。 η·如請求項i〇之輸出驅動裝置，其中該第_綱_晶體之 、極源極路彳：連接於該接地電屋與該輸出節點之間， 且該第PMOS電晶體之一閘極接收該預下拉控制訊號。 請求項以輸出驅動裝置，其中該上拉驅動器包括一 第二PMOS電晶體，其中該第二pM〇s電晶體之一汲極-源 極路徑連接於該驅動電磨舆該輸出節點之間，且該第二 P廳S電晶體之—閘極接收該上拉控制訊號；且該下拉驅 L括第—NMOS電曰曰曰體，其中該第二NM〇s電晶體 112659-980717.doc 1317523 間，且該第二1^%〇8電晶體之一閘極接收該下拉控 號。 ^ 之—汲極-源極路徑連接於該接地電壓與該輸出節點之 制訊 包括： η.如請求項12之輸出驅動裝置，其中該上拉位準轉換單元 …一第三NMOS電晶體，其汲極_源極路徑連接於一第 強訊 即點與該接地電壓之間，且其閘極接收該預上拉增 號； S -第-反轉器’其用於將該預上拉增強訊號反轉丨 〜一第四NMOS電晶體，其汲極·源極路徑連接於一第二 節點與該接地電懕之Η H甘q 电塋之間，且其閘極接收該反轉器之一輸 出； -第三PMOS電晶體’纽極源極路徑連接於該第一 節點與-高電壓之間，且其間極輕接至該第二節點，其 中該高電壓高於該驅動電壓；及 鲁 第四PMQS $晶體，其沒極·源極路徑連接於該第二 f點與該高電壓之間，且其閘極耦接至該m 14.如請求項13之輸出驅動梦署 免 . %動裝置，其中該下拉位準轉換單元 包括： -第五PMQS1：晶體，其没極_源極路徑連接於一第三 節點與該驅動電壓之間，且其閉極接收該預下拉增強訊 號； —— 第一反轉器’其用於將該預下拉增強訊號反轉； 第八PMOS包曰曰體，其没極-源極路徑連接於一第四 112659-980717.doc • 4 · 1317523 節點與該驅動電壓之間 間且其閘極接收該第二反轉器之 一輸出； -第五NMOS電晶體，其沒極·源極路徑連接於該第四節 點與㈣電壓之間’且其閑極輕接至該第三節點；及 帛，、NMGS電晶體，其祕_祕路徑連接於該第四 節點與該體電麼之間，且其閘極耗接至該第四節點。 15· —種半導體裝置，其包含： -第-上拉驅動單元，其用於響應於一第一上拉控制 訊號而將一輸出節點上拉至一上拉電壓； -上拉位準偏移電路’其用於#應於—預上拉訊號而 產生-第二上拉控制訊號，其中該第二上拉控制訊號之 一位準尚於該第一上拉控制訊號之位準；及 -第二上拉驅動單元，其用於響應於該第二上拉控制 訊號而將該輪出節點上拉至該上拉電壓。 16. 如請求項15之半導體裝置，其中該預上拉訊縣、以-對 應於該第-絲㈣訊號之—啟料序的預定時序而啟 動。 17. —種半導體襞置，其包含： 一第一下拉驅動單元，其用於響應於一第一下拉控制 訊號而將一輸出節點下拉至一下拉電壓； -下拉位準偏移電路，其用於響應於一預下拉訊號而 產生一第二下拉控制訊號，其中該第二下拉控制訊號之 一位準低於該第一下拉控制訊號之位準；及 一第二下拉驅動單元，其用於響應於該第二下拉控制 112659-980717.doc -5- 1317523 訊號而將該輸出節點下拉至該下拉電壓。 18·如#求項17之半導體裝置，其中該預下拉訊號係以一對 應於°亥第下拉控制訊號之一啟動時序的預定時序予以 啟動。 19. 一種半導體裝置，其包含： 一第一上拉驅動單元，其用於響應於一第一上拉控制 訊號而將—輸出節點上拉至一上拉電壓； -上拉位準偏移電路’其用於響應於一預上拉訊號而 產生一第二上拉控制訊號，其中該第二上拉控制訊號之 一位準尚於該第一上拉控制訊號之位準； 一第一上拉驅動單元，其用於響應於該第二上拉控制 訊號而將該輸出節點上拉至該上拉電壓； 一第一下拉驅動單元，其用於響應於一第一下拉控制 訊號而將一輪出節點下拉至一下拉電壓； -下拉位準偏移電路’其用於響應於一預下拉訊號而 產生-第二下拉控制訊號’其中該第二下拉控制訊號之 一位準低於該第一下拉控制訊號之位準；及 一第二下拉驅動g，其帛於響應於該第三下拉控制 訊號而將該輸出節點下拉至該下拉電壓。 20. 如請求項19之半導體裝置，其中該預上拉訊號係以一對 應於該第-上拉控制之一啟動時序的預冑時序予以 啟動。 •如請求項20之半導體裝置，其中該預下拉訊號係以一對 應於該第-下拉控制訊號之_啟動時序的預定時序予以 112659-980717.doc -6- 1317523 啟動。 22. _ 23.D 173⁄4) 3⁄4 Patent No. 123921 Request _______ . Chinese patent application scope replacement (July 1998) The first day of September is revised to 10, the scope of patent application: - 2 - i an output drive device The method includes: a pull-up driver for pulling up an output node in response to a pull-up control signal; a pull-down driver for driving down the output node in response to a pull-down control signal; a first n-type a metal oxide semiconductor (NM〇s) transistor for driving up the output node in response to a pre-pull control signal; and a pull-up level conversion unit for borrowing The pre-pull control §fl is generated by increasing a startup voltage level of one of the pre-pulsation enhancement signals such that the startup voltage level of the pre-pull enhancement signal is higher than a driving voltage. 2. The output driving device of claim 1, wherein the pre-pulling control signal is activated for a predetermined period of time before, after or during the start of one of the pull-up control signals. Φ;) The output driving device of claim 2, wherein the first NMOS transistor and the source path are connected between the driving voltage and the output node and one of the first NMOS transistors is closed The pole receives the pre-pull control signal. The apparatus of claim 3, wherein the pull-up driver comprises a P-type metal oxide semiconductor (PM〇s) transistor, wherein the PMOS transistor The immersive _ source path is connected between the driving voltage and the output node, and the gate of the first read (10) transistor receives the pull control signal. 5. The output driver of claim 4, wherein the pull-down driver comprises: 112659-980717.doc 1317523 two NMOS transistors, wherein one of the second NMOS transistors has a drain-source path connected to a ground voltage and Between the output nodes, and one of the gates of the second NMOS transistor receives the pull-down control signal. 6) The output driving device of claim 5, wherein the pull-up level conversion unit comprises: a third NMOS transistor having a drain-source path connected between a first node and the ground voltage, and The gate receives the pre-pull enhancement signal; an inverter for inverting the pre-pulse enhancement signal; a fourth NMOS transistor whose drain-source path is connected to a second node and the Between the ground voltages, and the gate thereof receives an output of the inverter; a second PMOS transistor whose drain-source path is connected between the first node and a high voltage, and the gate coupling Connecting to the second node, wherein the high voltage is higher than the driving voltage; and a third PMOS transistor having a drain-source path connected between the second node and the high voltage, and a gate coupling thereof Connect to the first node. 7. An output driving device comprising: a pull-up driver for pulling up an output node in response to a pull-up control signal; a pull-down driver for pulling down the driver in response to a pull-down control signal The output node; a first NMOS transistor for pulling up and driving the output node in response to a pre-pull control signal; 112659-980717.doc 1317523:-- m〇s transistor for responding to a pre-pull control signal is pulled down to drive the sinput output node; and a pull-up level conversion unit is configured to generate the pre-pull control signal by increasing the _ pre-pull-up enhancement signal to activate the money level The starting position of the pre-pull-up enhancement signal is higher than that of driving the electric dust. 8. The output driving device of claim 7, further comprising: a pull-down level conversion unit for generating the pre-down pull control signal by reducing a pre-pull-up enhancement signal-initiating ink level, The activation of the _ pulldown enhancement signal is lower than the grounding dust. 9. If requested, the output driver is activated, wherein the predetermined time is started after, during or after the start of one of the pullup control signals The pre-pull control signal 'and the predetermined pre-down pull control signal before, after or during the start of the pull-down control signal. W. The turn-out drive device of claim 9 wherein the first hire (10) One of the crystal has a pole-source path connected between the driving (four) and the output node, and one of the gates of the first NMOS transistor receives the pre-pulling control signal. η · The output driver of the request item i Wherein the first source of the crystal is connected between the grounded electrical house and the output node, and one of the gates of the first PMOS transistor receives the pre-down pull control signal. Drive unit The pull-up driver includes a second PMOS transistor, wherein a drain-source path of the second pM〇s transistor is connected between the output electrode and the output node, and the second P hall S The gate of the transistor receives the pull-up control signal; and the pull-down driver L includes a first-NMOS electrical body, wherein the second NM〇s transistor 112659-980717.doc 1317523, and the second one One of the gates of the ^%〇8 transistor receives the pull-down control number. ^ The drain-source path is connected to the ground voltage and the output node of the output node includes: η. The output driver of claim 12, Wherein the pull-up level conversion unit is a third NMOS transistor whose drain-source path is connected between a first strong signal and the ground voltage, and the gate receives the pre-pull-up sign; The S-first-inverter is configured to invert the pre-pulse enhancement signal to a fourth NMOS transistor, and the drain-source path is connected to a second node and the ground electrode Between the electric 茔, and its gate receives one of the outputs of the inverter; - the third PMOS transistor 'new pole a source path is connected between the first node and the -high voltage, and is extremely lightly connected to the second node, wherein the high voltage is higher than the driving voltage; and the fourth PMQS$ crystal, the poleless source a pole path is connected between the second f-point and the high voltage, and a gate thereof is coupled to the m 14. The output of the request item 13 drives the dream device, wherein the pull-down level conversion unit comprises : - a fifth PMQS1: crystal, the immersive _ source path is connected between a third node and the driving voltage, and the closed end receives the pre-down pull-up enhancement signal; - the first inverter "is used for Inverting the pre-down pull-up signal; the eighth PMOS packet body, the pole-source path is connected to a fourth 112659-980717.doc • 4 · 1317523 node and the driving voltage between the gate Receiving an output of the second inverter; a fifth NMOS transistor having a immersed source path connected between the fourth node and the (IV) voltage and having its idle pole connected to the third node;帛,, NMGS transistor, its secret _ secret path is connected to the fourth node and the body Between the two, and its gate is consumed to the fourth node. A semiconductor device comprising: - a first pull-up driving unit for pulling up an output node to a pull-up voltage in response to a first pull-up control signal; - a pull-up level shift The circuit 'is used for the pre-pull signal to generate a second pull-up control signal, wherein one of the second pull-up control signals is at the level of the first pull-up control signal; and And a second pull-up driving unit, configured to pull up the round-trip node to the pull-up voltage in response to the second pull-up control signal. 16. The semiconductor device of claim 15, wherein the pre-Laer-Xun County is activated with a predetermined timing corresponding to the pre-order of the first-wire (four) signal. 17. A semiconductor device, comprising: a first pull-down driving unit for pulling an output node to a pull-down voltage in response to a first pull-down control signal; - a pull-down level shift circuit, The second pull-down control signal is generated in response to a pre-pull-down signal, wherein one of the second pull-down control signals is lower than the level of the first pull-down control signal; and a second pull-down driving unit, It is used to pull the output node down to the pull-down voltage in response to the second pull-down control 112659-980717.doc -5-1317523 signal. 18. The semiconductor device of claim 17, wherein the pre-pull-down signal is initiated by a predetermined timing of a start timing of one of the pull-down control signals. 19. A semiconductor device, comprising: a first pull-up driving unit for pulling up an output node to a pull-up voltage in response to a first pull-up control signal; - a pull-up level shift circuit The second pull-up control signal is generated in response to a pre-pull signal, wherein one of the second pull-up control signals is at a level of the first pull-up control signal; a pull driving unit, configured to pull up the output node to the pull-up voltage in response to the second pull-up control signal; a first pull-down driving unit configured to respond to a first pull-down control signal Pulling a round out node to pull down the voltage; - Pulling down the level shifting circuit 'which is used to generate a second pulldown control signal in response to a pre-pull-down signal', wherein one of the second pull-down control signals is lower than the a level of the first pull-down control signal; and a second pull-down driver g, wherein the output node is pulled down to the pull-down voltage in response to the third pull-down control signal. 20. The semiconductor device of claim 19, wherein the pre-pull signal is initiated with a pair of pre-set timings that are one of the start-up timings of the first pull-up control. The semiconductor device of claim 20, wherein the pre-pull-down signal is initiated by a predetermined timing of a start-up sequence of the first-pull control signal to be 112659-980717.doc -6-1317523. 22. _ 23. 一種半導體裝置，其包含： 驅動器，其用於響應於一上拉控制訊號而上拉 驅動—輪出節點；拉驅動，其用於響應於一下拉控制訊號而下拉 驅動該輸出節點；及 驅動單7L，其用於響應於一控制訊號而用一經判定 之位準來驅動該輸出節點， '、不S啟動忒上拉控制訊號及該下拉控制訊號，皆 啟動該控制訊號。 如請求項22之半導體裝置，其進一步包含一位準轉換單 7L，其用於將一預上拉增強訊號及一預下拉增強訊號分別轉換為一預上拉控制訊號及一預下拉控制訊號，其中。衾預上拉增強訊號之一位準低於該預上拉控制訊號之一 位準且該預下拉増強訊號之一位準高於該預下拉控制訊 號的一位準。 112659-980717.doc I317^d23921號專利申請案 中文圖式替換頁(97年11月） J· 們日修正替換頁 VDOQ VDOQA semiconductor device comprising: a driver for pulling up a driving-wheeling node in response to a pull-up control signal; a pull driving for pulling down the output node in response to a pull-down control signal; and driving a single 7L is configured to drive the output node with a determined level in response to a control signal, and the control signal is activated by starting the pull-up control signal and the pull-down control signal. The semiconductor device of claim 22, further comprising a quasi-conversion unit 7L for converting a pre-pulse enhancement signal and a pre-pull enhancement signal into a pre-pull control signal and a pre-pull control signal, respectively. among them.之一 One of the pre-pull enhancement signals is lower than one of the pre-pull control signals and one of the pre-down pull signals is higher than the pre-pull control signal. 112659-980717.doc Patent application No. I317^d23921 Chinese pattern replacement page (November 1997) J· 日日修正 replacement page VDOQ VDOQ PU.PREJMPPU.PREJMP 112659.doc 2-112659.doc 2-
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KR20210144074A (en) * 2020-05-21 2021-11-30 에스케이하이닉스 주식회사 Transmitter circuit

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KR20070036571A (en) 2007-04-03

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