CN1941195A - Output driving device - Google Patents
Output driving device Download PDFInfo
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- CN1941195A CN1941195A CNA2006101263565A CN200610126356A CN1941195A CN 1941195 A CN1941195 A CN 1941195A CN A2006101263565 A CNA2006101263565 A CN A2006101263565A CN 200610126356 A CN200610126356 A CN 200610126356A CN 1941195 A CN1941195 A CN 1941195A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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Abstract
An output driving device includes: a pull-up driver for pull-up driving an output node in response to a pull-up control signal; a pull-down driver for pull-down driving the output node in response to a pull-down control signal; and a first n-type metal oxide semiconductor (NMOS) transistor for pull-up driving the output node in response to a pre-pull-up control signal.
Description
Technical field
The present invention relates to a kind of output driving device that is used for semiconductor memory system, and more particularly, relate to a kind of output driving device that is used for guaranteeing the nargin (margin) in valid data cycle by raising conversion ratio (slew rate).
Background technology
Usually, the push-pull type driver is widely used as output driving device.About the control of push-pull type output driver, the control of conversion ratio has become problem.
Change how soon relevant with the voltage level change of output signal.Conversion ratio is defined as the slope of showing voltage level change and the ratio between the unit interval.
Conversion ratio can be categorized as two types: rising conversion ratio and decline conversion ratio.The slope of rising conversion ratio indication voltage level of output signal from low level to the high level variation.The slope of decline conversion ratio indication voltage level of output signal from high level to the low level variation.In either case, conversion ratio is bigger, and the slope of output signal is steeper.In other words, the voltage level of output signal changed in a short time.
Fig. 1 is the schematic circuit diagram that is used for traditional output driver of semiconductor memory system.
Traditional output driver comprises and draws driver PM1, its be used in response on draw drive signal PU_CTR and on draw the driving output driver; And pull-down driver NM1, it is used for this output driver of drop-down driving in response to drop-down drive signal PD_CTR.
Specifically, drawing driver PM1 on is p type metal oxide semiconductor (PMOS) transistor that is connected between driving voltage VDDQ and the output node.The transistorized grid of PMOS receives and draws drive signal PU_CTR.Pull-down driver NM1 is n type metal oxide semiconductor (NMOS) transistor that is connected between output node and the ground voltage VSSQ.The grid of nmos pass transistor receives drop-down drive signal PD_CTR.
Fig. 2 is an oscillogram of describing the operation of traditional output driver.
Referring to Fig. 2, be used for drawing drive operation on draw drive signal PU_CTR to have a start-up period longer than drop-down drive signal PD_CTR.This is caused by the characteristic that is included in the element in traditional output driver.In other words, the drive strength of PMOS transistor PM1 and conversion ratio are less than drive strength and the conversion ratio of nmos pass transistor NM1.
Therefore, reach " L " identical valid data window in order to ensure the logic level " H " for output data, PMOS transistor PM1 is designed to be has large scale.Yet if increase the size of PMOS transistor PM1, output signal more is subject to The noise.In addition, because increase the electric capacity of output node, so input characteristics can be demoted during the I/O bi-directional data.The problems referred to above are even more serious during high speed operation.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of output driver that is used for guaranteeing the nargin in valid data cycle by the raising conversion ratio.
According to an aspect of the present invention, provide a kind of output driving device, it comprises: on draw driver, its be used in response on draw control signal and on draw the driving output node; Pull-down driver, it is used for this output node of drop-down driving in response to drop-down control signal; And n type metal oxide semiconductor (NMOS) transistor, draw on it is used in response to drawing control signal on pre-and drive this output node.
According to a further aspect in the invention, provide a kind of output driving device, it comprises: on draw driver, its be used in response on draw control signal and on draw the driving output node; Pull-down driver, it is used for this output node of drop-down driving in response to drop-down control signal; First nmos pass transistor draws on it is used in response to drawing control signal on pre-and drives this output node; And a PMOS transistor, it is used for this output node of drop-down driving in response to pre-drop-down control signal.
According to a further aspect in the invention, provide a kind of semiconductor device, it comprises: draw driver element on first, it is used for being pulled in response to drawing control signal on first and with output node and draws voltage; On draw level shift circuit, it is used for producing in response to drawing signal on pre-and draws control signal on second, wherein this draws the level of control signal to be higher than the level that draws control signal on first on second; And drawing driver element on second, it is used for being pulled in response to drawing control signal on second and with output node and draws voltage.
According to a further aspect in the invention, provide a kind of semiconductor device, it comprises: the first drop-down driver element, and it is used in response to the first drop-down control signal output node being pulled down to actuation voltage; On draw level shift circuit, it is used for producing the second drop-down control signal in response to pre-pulldown signal, wherein the level of this second drop-down control signal is higher than the level of the first drop-down control signal; And the second drop-down driver element, it is used in response to the second drop-down control signal output node being pulled down to actuation voltage.
According to a further aspect in the invention, provide a kind of semiconductor device, it comprises: draw driver element on first, it is used for being pulled in response to drawing control signal on first and with output node and draws voltage; On draw level shift circuit, it is used for producing in response to drawing signal on pre-and draws control signal on second, wherein this draws the level of control signal to be higher than the level that draws control signal on first on second; Draw driver element on second, it is used for being pulled in response to drawing control signal on second and with output node and draws voltage; The first drop-down driver element, it is used in response to the first drop-down control signal output node being pulled down to actuation voltage; On draw level shift circuit, it is used for producing the second drop-down control signal in response to pre-pulldown signal, wherein the level of this second drop-down control signal is higher than the level of the first drop-down control signal; And the second drop-down driver element, it is used in response to the second drop-down control signal output node being pulled down to actuation voltage.
Description of drawings
According to the description of following preferred embodiment and in conjunction with the accompanying drawings, above-mentioned and other purpose and advantage of the present invention will become clear, in the accompanying drawings:
Fig. 1 is the schematic circuit diagram that is used for traditional output driver of semiconductor memory system;
Fig. 2 is the oscillogram of the operation of traditional output driver;
Fig. 3 is the schematic circuit diagram of the output driving device that is used for semiconductor memory system according to a preferred embodiment of the invention;
Draw the schematic circuit diagram of level conversion unit on shown in Fig. 4 Fig. 3;
Fig. 5 is the schematic circuit diagram of the drop-down level conversion unit shown in Fig. 3;
Fig. 6 is the oscillogram of the operation of the output driving device shown in Fig. 3; And
Fig. 7 is the figure that shows the characteristic of general MOS transistor.
[main element symbol description]
Draw level conversion unit 200 drop-down level conversion units on 100
The I1 first phase inverter I2 second phase inverter
NM1, NM2 pull-down driver/nmos pass transistor
NM3 the one n type metal oxide semiconductor (NMOS) transistor
NM4 second nmos pass transistor
NM5 the 3rd nmos pass transistor
NM6 the 4th nmos pass transistor
NM7 the 5th nmos pass transistor
Draw driver/PMOS transistor on PM1, the PM2
PM3 the one p type metal oxide semiconductor (PMOS) transistor
PM4 the 2nd PMOS transistor
PM5 the 3rd PMOS transistor
PM6 the 4th PMOS transistor
PM7 the 5th PMOS transistor
Embodiment
Hereinafter, will describe in detail according to output driving device of the present invention referring to accompanying drawing.
Fig. 3 is the schematic circuit diagram of the output driving device that is used for semiconductor memory system according to a preferred embodiment of the invention.
As shown in, output driving device comprises: on draw driver PM2, its be used in response on draw control signal PU and on draw the driving output node; Pull-down driver NM2, it is used for this output node of drop-down driving in response to drop-down control signal PD; On draw level conversion unit 100, it is used for the initiation voltage level of drawing enhancing signal PU_PRE_EMP on pre-by increasing, and produces to draw control signal PU_PP on pre-, makes initiation voltage level greater than drive voltage level; And n type metal oxide semiconductor (NMOS) transistor NM3, draw on it is used in response to drawing control signal PU_PP on pre-and drive this output node.
Output driving device further comprises a drop-down level conversion unit 200 and p type metal oxide semiconductor (PMOS) transistor PM3.
Drop-down level conversion unit 200 is by reducing the voltage level of pre-drop-down control signal PD_BB, produce pre-drop-down control signal PD_BB, make that the voltage level of pre-drop-down control signal PD_BB is lower than ground voltage VSSQ when the pre-drop-down enhancing signal PD_PRE_EMP of startup.The one PMOS transistor PM3 receives pre-drop-down control signal PD_BB (it is lower than ground voltage VSSQ), with this output node of drop-down driving.
Specifically, the first nmos pass transistor NM3 is connected between driving voltage VDDQ and the output node, and draws control signal PU_PP in the grid reception in advance via the first nmos pass transistor NM3.The one PMOS transistor PM3 is connected between output node and the ground voltage VSSQ, and receives pre-drop-down control signal PD_BB via the grid of a PMOS transistor PM3.
On to draw driver PM2 be the PMOS transistor that is connected between driving voltage VDDQ and the output node, and its grid via PMOS transistor PM2 receives and draws control signal PU_CTR.Pull-down driver NM2 is the nmos pass transistor that is connected between output node and the ground voltage VSSQ, and its grid via nmos pass transistor NM2 receives drop-down control signal PD.
Draw the schematic circuit diagram of level conversion unit 100 on shown in Fig. 4 Fig. 3.
As shown in, on draw level conversion unit 100 to comprise: second and third PMOS transistor PM4 and PM5, second and third NOMS transistor NM4 and NM5 and the first phase inverter I1.
Drain electrode-source path of the second nmos pass transistor NM4 is connected between node A and the ground voltage VSSQ, and draws enhancing signal PU_PRE_EMP in the reception in advance of the grid of the second nmos pass transistor NM4.The first phase inverter I1 is used for drawing enhancing signal PU_PRE_EMP anti-phase on pre-.Drain electrode-source path of the 3rd nmos pass transistor NM5 is connected between Node B and the ground voltage VSSQ, and the grid of the 3rd nmos pass transistor NM5 receives the output of the first phase inverter I1.
Drain electrode-source path of the 2nd PMOS transistor PM4 is connected between high voltage VPP and the node A, and the gate coupled of the 2nd PMOS transistor PM4 is to Node B.Similarly, drain electrode-source path of the 3rd PMOS transistor PM5 is connected between high voltage VPP and the Node B, and the gate coupled of the 3rd PMOS transistor PM5 is to node A.The voltage level of high voltage VPP is higher than the voltage level of driving voltage VDDQ.Draw control signal PU_PP on being output as the voltage that is loaded on the Node B in advance.High voltage VPP is higher than driving voltage VDDQ.
Fig. 5 is the schematic circuit diagram of the drop-down level conversion unit 200 shown in Fig. 3.
As shown in, drop-down level conversion unit 200 comprises: the 4th and the 5th PMOS transistor PM6 and PM7, the 4th and the 5th nmos pass transistor NM6 and NM7 and the second phase inverter I2.
Drain electrode-source path of the 4th PMOS transistor PM6 is connected between driving voltage VDDQ and the node C, and the grid of the 4th PMOS transistor PM6 receives pre-drop-down enhancing signal PD_PRE_EMP.The second phase inverter I2 is anti-phase with pre-drop-down enhancing signal PD_PRE_EMP.Drain electrode-source path of the 5th PMOS transistor PM7 is connected between driving voltage VDDQ and the node D, and the grid of the 5th PMOS transistor PM7 receives the output of the second phase inverter I2.
Drain electrode-source path of the 5th nmos pass transistor NM7 is connected between node D and the bulk voltage VBB, and the gate coupled of the 5th nmos pass transistor NM7 is to node C.Drain electrode-source path of the 4th nmos pass transistor NM6 is connected between node C and the bulk voltage VBB, and the gate coupled of the 4th nmos pass transistor NM6 is to node D.The voltage that is loaded on the node D is output as pre-drop-down control signal PD_BB.Bulk voltage VBB is lower than ground voltage VSSQ.
Fig. 6 is the oscillogram of the operation of the output driving device shown in Fig. 3.
Referring to Fig. 3 to Fig. 6, the operation of output driving device is described hereinafter.
When on when drawing control signal PU to start to logic low, draw in the startup driver PM2 and on draw and drive this output node.At this moment, because draw enhancing signal PU_PRE_EMP also to be started as logic high on pre-, more than draw level conversion unit 100 to increase the voltage level that draws enhancing signal PU_PRE_EMP on pre-, the voltage level that draws enhancing signal PU_PRE_EMP on making in advance is greater than driving voltage VDDQ, and the signal that will increase then is as drawing control signal PU_PP output on pre-.Therefore, when drawing driver PM2 on starting, the first nmos pass transistor NM3 also starts, and drives this output node to use to draw to draw on the driver PM2.
Simultaneously, when drop-down control signal PD starts to logic high, start pull-down driver NM1 and this output node of drop-down driving.Because also will pre-drop-down enhancing signal PD_PRE_EMP when starting drop-down control signal PD starting is logic low, so drop-down level conversion unit 200 reduces the voltage level of pre-drop-down enhancing signal PD_PRE_EMP, make the voltage of pre-drop-down enhancing signal PD_PRE_EMP be lower than ground voltage VSSQ, the signal that will reduce is as pre-drop-down control signal PD_BB output then.Therefore, when starting pull-down driver NM2, a PMOS transistor PM3 also starts, to come this output node of drop-down driving with pull-down driver NM2.
Draw control signal PU to start simultaneously although draw enhancing signal PU_PRE_EMP to reach on having illustrated in advance among Fig. 6, and pre-drop-down enhancing signal PD_PRE_EMP and drop-down control signal PD start simultaneously, but draw on pre-enhancing signal PU_PRE_EMP and pre-drop-down enhancing signal PD_PRE_EMP can be respectively early than or be later than and draw control signal PU and drop-down control signal PD and start.
Fig. 7 is the figure that the characteristic of general MOS transistor is shown.
As shown in, the conversion ratio of nmos pass transistor is better than the transistorized conversion ratio of PMOS when initial operation.In addition, also demonstrate the comparable nmos pass transistor of PMOS transistor and carry more high-voltage level.
According to a preferred embodiment of the invention because additionally comprised nmos pass transistor so as on draw the driving output node, so can replenish the conversion ratio characteristic of drawing driver (being the PMOS transistor).
Therefore, driving output unit according to a preferred embodiment of the invention can be guaranteed the enough nargin in valid data cycle by improving conversion ratio.
The application contains and korean patent application 2005-91669 number and 2005-133958 number relevant theme of submitting in Korean Patent office respectively on September 29th, 2005 and on Dec 29th, 2005, and the full content of these patented claims is incorporated herein by reference.
Though described the present invention about specific embodiment, it will be apparent to one skilled in the art that under the situation that does not break away from defined spirit of the present invention of claim and scope, can make various variations and modification.
Claims (24)
1. output driving device, it comprises:
On draw driver, its be used in response on draw control signal and on draw the driving output node;
Pull-down driver, it is used for this output node of drop-down driving in response to drop-down control signal; And
The one n type metal oxide semiconductor nmos pass transistor draws on it is used in response to drawing control signal on pre-and drives this output node.
2. output driving device as claimed in claim 1, it also comprises and draws level conversion unit, draw level conversion unit to be used on being somebody's turn to do by drawing the initiation voltage level of enhancing signal on increasing in advance, generation is drawn control signal on being somebody's turn to do in advance, makes this draw the initiation voltage level of enhancing signal to be higher than driving voltage on pre-.
3. output driving device as claimed in claim 2, wherein on this, draw before the startup of control signal, afterwards or during one period schedule time start and draw control signal on should be pre-.
4. output driving device as claimed in claim 3, wherein drain electrode-the source path of this first nmos pass transistor is connected between this driving voltage and this output node, and the grid of this first nmos pass transistor receives and to draw control signal on should be pre-.
5. output driving device as claimed in claim 4, draw driver to comprise a p type metal oxide semiconductor PMOS transistor on wherein being somebody's turn to do, wherein a PMOS transistor drain-source path is connected between this driving voltage and this output node, and the transistorized grid of a PMOS receive should on draw control signal.
6. output driving device as claimed in claim 5, wherein this pull-down driver comprises second nmos pass transistor, wherein drain electrode-the source path of this second nmos pass transistor is connected between ground voltage and this output node, and the grid of this second nmos pass transistor receives this drop-down control signal.
7. output driving device as claimed in claim 6, wherein be somebody's turn to do and draw level conversion unit to comprise:
The 3rd nmos pass transistor, its drain electrode-source path are connected between first node and this ground voltage, and its grid receives and draws enhancing signal on should be pre-;
Phase inverter, it is used for this drawing enhancing signal anti-phase on pre-;
The 4th nmos pass transistor, its drain electrode-source path are connected between Section Point and this ground voltage, and its grid receives the output of this phase inverter;
The 2nd PMOS transistor, its drain electrode-source path is connected between this first node and the high voltage, and its gate coupled is to this Section Point, and wherein this high voltage is higher than this driving voltage; And
The 3rd PMOS transistor, its drain electrode-source path are connected between this Section Point and this high voltage, and its gate coupled is to this first node.
8. output driving device, it comprises:
On draw driver, its be used in response on draw control signal and on draw the driving output node;
Pull-down driver, it is used for this output node of drop-down driving in response to drop-down control signal;
First nmos pass transistor draws on it is used in response to drawing control signal on pre-and drives this output node; And
The one PMOS transistor, it is used for this output node of drop-down driving in response to pre-drop-down control signal.
9. output driving device as claimed in claim 8, it also comprises:
On draw level conversion unit, it is used for the initiation voltage level of drawing enhancing signal on pre-by increasing, and produces to draw control signal on should be pre-, makes this draw this initiation voltage level of enhancing signal to be higher than driving voltage on pre-; And
Drop-down level conversion unit, it is used for producing this pre-drop-down control signal by the initiation voltage level that reduces pre-drop-down enhancing signal, makes this initiation voltage level of this pre-drop-down enhancing signal be lower than ground voltage.
10. output driving device as claimed in claim 9, wherein on this, draw before the startup of control signal, afterwards or during one period schedule time start and draw control signal on should be pre-, and before the startup of this drop-down control signal, afterwards or during one period schedule time start this pre-drop-down control signal.
11. output driving device as claimed in claim 10, wherein drain electrode-the source path of this first nmos pass transistor is connected between this driving voltage and this output node, and the grid of this first nmos pass transistor receives and to draw control signal on should be pre-.
12. output driving device as claimed in claim 11, wherein a PMOS transistor drain-source path is connected between this ground voltage and this output node, and the transistorized grid of a PMOS receives this pre-drop-down control signal.
13. output driving device as claimed in claim 12, draw driver to comprise the 2nd PMOS transistor on wherein being somebody's turn to do, wherein the 2nd PMOS transistor drain-source path is connected between this driving voltage and this output node, and the transistorized grid of the 2nd PMOS receive should on draw control signal; And this pull-down driver comprises second nmos pass transistor, and wherein drain electrode-the source path of this second nmos pass transistor is connected between this ground voltage and this output node, and the grid of this second nmos pass transistor receives this drop-down control signal.
14. output driving device as claimed in claim 13 wherein is somebody's turn to do and draws level conversion unit to comprise:
The 3rd nmos pass transistor, its drain electrode-source path are connected between first node and this ground voltage, and its grid receives and draws enhancing signal on should be pre-;
First phase inverter, it is used for this drawing enhancing signal anti-phase on pre-;
The 4th nmos pass transistor, its drain electrode-source path are connected between Section Point and this ground voltage, and its grid receives the output of this phase inverter;
The 3rd PMOS transistor, its drain electrode-source path is connected between this first node and the high voltage, and its gate coupled is to this Section Point, and wherein this high voltage is higher than this driving voltage; And
The 4th PMOS transistor, its drain electrode-source path are connected between this Section Point and this high voltage, and its gate coupled is to this first node.
15. output driving device as claimed in claim 14, wherein this drop-down level conversion unit comprises:
The 5th PMOS transistor, its drain electrode-source path are connected between the 3rd node and this driving voltage, and its grid receives this pre-drop-down enhancing signal;
Second phase inverter, it is used for this pre-drop-down enhancing signal anti-phase;
The 6th PMOS transistor, its drain electrode-source path are connected between the 4th node and this driving voltage, and its grid receives the output of this second phase inverter;
The 5th nmos pass transistor, its drain electrode-source path are connected between the 4th node and this ground voltage, and its gate coupled is to the 3rd node; And
The 6th nmos pass transistor, its drain electrode-source path are connected between the 4th node and this ground voltage, and its gate coupled is to the 4th node.
16. a semiconductor device, it comprises:
Draw driver element on first, it is used for being pulled in response to drawing control signal on first and with output node and draws voltage;
On draw level shift circuit, it is used for producing in response to drawing signal on pre-and draws control signal on second, wherein this draws on second the level of control signal to be higher than the level that this draws control signal on first; And
Draw driver element on second, it is used for drawing control signal on second and this output node being pulled in response to this drawing voltage on this.
17. semiconductor device as claimed in claim 16 draws on wherein should be pre-signal drawing the startup predetermined timing regularly of control signal to be activated corresponding to this on first.
18. a semiconductor device, it comprises:
The first drop-down driver element, it is used in response to the first drop-down control signal output node being pulled down to actuation voltage;
On draw level shift circuit, it is used for producing the second drop-down control signal in response to pre-pulldown signal, wherein the level of this second drop-down control signal is higher than the level of this first drop-down control signal; And
The second drop-down driver element, it is used in response to this second drop-down control signal this output node being pulled down to this actuation voltage.
19. semiconductor device as claimed in claim 16, wherein this pre-pulldown signal is activated in the startup predetermined timing regularly corresponding to this first drop-down control signal.
20. a semiconductor device, it comprises:
Draw driver element on first, it is used for being pulled in response to drawing control signal on first and with output node and draws voltage;
On draw level shift circuit, it is used for producing in response to drawing signal on pre-and draws control signal on second, wherein this draws on second the level of control signal to be higher than the level that this draws control signal on first;
Draw driver element on second, it is used for drawing control signal on second and this output node being pulled in response to this drawing voltage on this;
The first drop-down driver element, it is used in response to the first drop-down control signal output node being pulled down to actuation voltage;
On draw level shift circuit, it is used for producing the second drop-down control signal in response to pre-pulldown signal, wherein the level of this second drop-down control signal is higher than the level of this first drop-down control signal; And
The second drop-down driver element, it is used in response to this second drop-down control signal this output node being pulled down to this actuation voltage.
21. semiconductor device as claimed in claim 20 draws on wherein should be pre-signal drawing the startup predetermined timing regularly of control signal to be activated corresponding to this on first.
22. semiconductor device as claimed in claim 21, wherein this pre-pulldown signal is activated in the startup predetermined timing regularly corresponding to this first drop-down control signal.
23. a semiconductor device, it comprises:
On draw driver, its be used in response on draw control signal and on draw the driving output node;
Pull-down driver, it is used for this output node of drop-down driving in response to drop-down control signal; And
Driver element, it is used for driving this output node in response to control signal with the level of determining,
Wherein, all start this control signal no matter draw the startup of control signal and this drop-down control signal on being somebody's turn to do.
24. semiconductor device as claimed in claim 23, it also comprises level conversion unit, it is used for and will draws control signal and pre-drop-down control signal to be converted to respectively on pre-to draw on this control signal and this drop-down control signal, draws the level of control signal and this pre-drop-down control signal to be lower than the level that draws control signal and this drop-down control signal on this respectively on wherein should be in advance.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR91669/05 | 2005-09-29 | ||
| KR20050091669 | 2005-09-29 | ||
| KR1020050133958A KR100753123B1 (en) | 2005-09-29 | 2005-12-29 | Output driving device |
| KR133958/05 | 2005-12-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941195A true CN1941195A (en) | 2007-04-04 |
| CN1941195B CN1941195B (en) | 2012-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101263565A Active CN1941195B (en) | 2005-09-29 | 2006-08-30 | Output driving device |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100753123B1 (en) |
| CN (1) | CN1941195B (en) |
| TW (1) | TWI317523B (en) |
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| CN107959492A (en) * | 2016-10-17 | 2018-04-24 | 英飞凌科技股份有限公司 | For driving the method and drive circuit and electrical fuse circuit of electronic switch |
| CN113708755A (en) * | 2020-05-21 | 2021-11-26 | 爱思开海力士有限公司 | Emphasis circuit and transmitter including the same |
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| KR101045071B1 (en) | 2009-11-30 | 2011-06-29 | 주식회사 하이닉스반도체 | Data output circuit |
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| KR100753404B1 (en) * | 2001-06-28 | 2007-08-30 | 주식회사 하이닉스반도체 | Data output buffer |
| KR100410556B1 (en) * | 2001-06-30 | 2003-12-18 | 주식회사 하이닉스반도체 | Driving method of I/O driver for reducing noise |
| KR100469374B1 (en) * | 2001-12-28 | 2005-02-02 | 매그나칩 반도체 유한회사 | Circuit for Buffering Output |
-
2005
- 2005-12-29 KR KR1020050133958A patent/KR100753123B1/en active IP Right Grant
-
2006
- 2006-06-30 TW TW095123921A patent/TWI317523B/en active
- 2006-08-30 CN CN2006101263565A patent/CN1941195B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104348341A (en) * | 2013-08-02 | 2015-02-11 | 亚德诺半导体集团 | Anti-ringing technique for switching power stage |
| CN107959492A (en) * | 2016-10-17 | 2018-04-24 | 英飞凌科技股份有限公司 | For driving the method and drive circuit and electrical fuse circuit of electronic switch |
| CN107959492B (en) * | 2016-10-17 | 2021-03-05 | 英飞凌科技股份有限公司 | Method and drive circuit for driving an electronic switch and electronic fuse circuit |
| CN113708755A (en) * | 2020-05-21 | 2021-11-26 | 爱思开海力士有限公司 | Emphasis circuit and transmitter including the same |
| CN113708755B (en) * | 2020-05-21 | 2024-03-29 | 爱思开海力士有限公司 | Weighting circuit and transmitter comprising same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070036571A (en) | 2007-04-03 |
| TWI317523B (en) | 2009-11-21 |
| KR100753123B1 (en) | 2007-08-29 |
| CN1941195B (en) | 2012-07-11 |
| TW200713318A (en) | 2007-04-01 |
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