CN101079325A - Shift register circuit - Google Patents
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- CN101079325A CN101079325A CNA2006100898246A CN200610089824A CN101079325A CN 101079325 A CN101079325 A CN 101079325A CN A2006100898246 A CNA2006100898246 A CN A2006100898246A CN 200610089824 A CN200610089824 A CN 200610089824A CN 101079325 A CN101079325 A CN 101079325A
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Abstract
The invention discloses a displacement register circuit, which is serially connected by multiple groups of displacement register units, wherein each group of displacement register unit contains first transistor, second transistor, third transistor and inverter; the first source/drain end of the first transistor receives the input signal; the grid end receives the inverse clock signal; the first source/drain end of the second transistor receives the clock signal; the grid end couples the second source/drain end of the first transistor; the second source/drain end of the second transistor outputs an output signal; the first source/drain end of the third transistor couples the second source/drain end of the second transistor; the second source/drain end of the third transistor couples the ground; the input end of the inverter couples the second source/drain end of the first transistor; the output end couples the grid end of the third transistor.
Description
Technical field
The present invention relates to a kind of shift register, particularly a kind ofly can reduce number of transistors purpose shift-register circuit.
Background technology
Please refer to Fig. 1, it illustrates is in the prior art, a kind of low temperature compound crystal silicon (LowTemperature Ploy Silicon that is applied to, LTPS) technology and be implemented in CMOS shift-register circuit on the glass substrate, this shift-register circuit mainly is to be cascadedly combined by multistage latch cicuit 101 and logical circuit 103.Wherein, each grade latch cicuit 101 needs six transistors to constitute, therefore each level logic circuit 103 is four transistors of needs then, and when latch cicuit 101 that this shift-register circuit was connected in series and logical circuit 103 the more the time, its needed layout area is also bigger.
And in order to reduce the required layout area of circuit, therefore constantly there is new design circuit mode to propose, please refer to Fig. 2, it illustrates is in the prior art, and another kind of shift-register circuit, this shift-register circuit are that the multistage shift register cell of serial connection is formed equally, as shown in FIG., in this shift-register circuit, the internal circuit diagram of one-level shift register cell wherein, and this shift register cell only needs four MOS transistor and one group of phase inverter promptly can carry out work.
Wherein, the gate terminal of MOS transistor Q1 receives an inversion clock signal XCK, and first source/drain electrode end is coupled to output terminal (N-1) OUT of previous stage shift register cell.And first source of MOS transistor Q2/drain electrode end receive clock signal CK, second source/draw end is output terminal (N) OUT of this shift register cell, in order to export self the essential output signal that export of institute.In addition, the gate terminal of MOS transistor Q4 then is output terminal (N+1) OUT that is coupled to the next stage shift register cell.
When inversion clock signal XCK is high-voltage level, transistor Q1 is a conducting state, if this moment, the output signal of previous stage was a high-voltage level, then this high-voltage level can be sent to the gate terminal of transistor Q2 by transistor Q1, therefore, the level of output terminal (N) OUT meeting this moment clock signal CK is to the shift register cell of next stage.In addition, whether transistor Q4 can decide conducting by the output signal of next stage shift register cell, is under the state of conducting as transistor Q4, and output terminal (N) OUT then can the output LOW voltage level.In addition, the input end of phase inverter 201 is coupled to output terminal (N-1) OUT of previous stage shift register cell, when output terminal (N-1) OUT is low voltage level, the output terminal meeting output HIGH voltage level of phase inverter 201 is with turn-on transistor Q3, so that output terminal (N) OUT can remain on the state of low voltage level.
Please refer to Fig. 3, it illustrates is the work clock figure of the signal in the shift register cell of Fig. 2.Wherein, the OUT1-OUT3 in the diagram represents output terminal (N-1) OUT, (N) OUT respectively, and (N+1) signal of OUT changes.When transistor Q1 conducting, terminal A and output signal OUT1 be (because the voltage of terminal A also must be considered the Vth effect of transistor Q1) much at one, and when inversion clock signal XCK is low voltage level, transistor Q1 is a closing state, this moment, the voltage of terminal A was unsteady high-voltage level state, and via the signal of capacitor C feedback clock signal CK, the increase that the voltage of terminal A can continue also makes (N) voltage signal OUT2 that OUT exported can continue to push away and is held in high-voltage level.
By above narration as can be known, the shift-register circuit of this kind design, after its each grade shift register cell can postpone input signal on a clock, transmit signals to again among the next stage shift register cell, to reach the function that signal transmits, and each grade shift register cell only needs 6 transistors (phase inverter 201 needs two transistors to form), 4 transistors have been used though lacked in the prior art than Fig. 1, if but this shift-register circuit is must will be connected in series the multi-stage shift register unit time, still dislike a bit too much, when adding in this way design circuit, each grade shift register cell also must feed back output terminal (N+1) the OUT signal of next stage shift register cell again to circuit, can move normally, this will increase the complexity of circuit layout design.
Summary of the invention
Purpose of the present invention just provides a kind of shift-register circuit, and each the group shift register cell in this shift-register circuit can utilize number of transistors still less, carries out identical functions.
The present invention proposes a kind of shift-register circuit, and this shift-register circuit is that the most group of serial connection shift register cell is formed, and wherein, each group shift register cell all receives identical clock signal and inversion clock signal.Each group shift register cell comprises the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, and phase inverter.
Wherein, first source of above-mentioned the first transistor/drain electrode end receiving inputted signal, and its gate terminal receives the inversion clock signal.First source of above-mentioned transistor seconds/drain electrode end receive clock signal, and its gate terminal is coupled to the second source/drain electrode end of the first transistor, in addition, second source of transistor seconds/drain electrode end is exported an output signal.The 3rd above-mentioned transistorized first source/drain electrode end is coupled to the second source/drain electrode end of transistor seconds, and the 3rd transistorized second source/drain electrode end is coupled to Vcc (power end).The input end of above-mentioned phase inverter is coupled to the second source/drain electrode end of the first transistor, and its output terminal is coupled to the 3rd transistorized gate terminal.
Described according to preferred embodiment of the present invention, more comprise an electric capacity in the above-mentioned shift-register circuit, first end of this electric capacity is coupled to the first source/drain electrode end of transistor seconds, and second end then is coupled to the gate terminal of transistor seconds.
Described according to preferred embodiment of the present invention, the first transistor in the above-mentioned shift-register circuit～the 5th transistor can be a MOS transistor.Wherein, the first transistor～the 3rd transistor can be P type MOS transistor and N type MOS transistor the two one of.
Described according to preferred embodiment of the present invention, if above-mentioned shift register cell in the transistor seconds MOS transistor time, above-mentioned electric capacity can be in the transistor seconds, the grid source electrode stray capacitance between the grid source electrode.
Described according to preferred embodiment of the present invention, the phase inverter in the above-mentioned shift-register circuit comprises the 4th transistor AND gate the 5th transistor.Wherein, the aforesaid the 4th transistorized first source/drain electrode end and gate terminal are coupled to power supply, and the 4th transistorized second source/drain electrode end is then exported above-mentioned mentioned output signal.The 5th above-mentioned transistorized first source/drain electrode end is coupled to the 4th transistorized second source/drain electrode end, and the 5th transistorized gate terminal then receives above-mentioned mentioned input signal, and the 5th transistorized second source/drain electrode end is coupled to ground.
Displacement of the present invention is device unit, position temporarily, the transistorized number of its inner each grade, than circuit of the prior art still less, therefore when the essential serial connection of shift-register circuit multi-stage shift register unit, the transistor size of its inner body also can significantly reduce, so the layout area of integrated circuit can also relatively dwindle more.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates in the prior art, a kind of internal circuit diagram of shift register of CMOS structure.
Fig. 2 illustrates in the prior art, the internal circuit diagram of another kind of shift-register circuit.
Fig. 3 illustrates the work clock figure into the signal in the shift-register circuit among Fig. 2.
It is according in the shift-register circuit proposed by the invention that Fig. 4 illustrates, wherein the internal circuit diagram of one-level shift register cell.
It is according in the shift-register circuit proposed by the invention that Fig. 5 A illustrates, wherein the internal circuit diagram of the phase inverter in the one-level shift register cell.
It is according in the shift-register circuit proposed by the invention that Fig. 5 B illustrates, the circuit diagram of the phase inverter in the another kind of shift register cell.
It is according in the shift-register circuit proposed by the invention that Fig. 6 illustrates, the internal circuit diagram of serial connection two-stage shift register cell.
Fig. 7 illustrates the clock variation diagram of the signal that is the shift register cell among Fig. 6.
It is according in the shift-register circuit proposed by the invention that Fig. 8 illustrates, the internal circuit diagram of the shift register cell of being made up of N type MOS transistor.
It is to utilize in the shift-register circuit proposed by the invention that Fig. 9 illustrates, the circuit diagram of the signal generator that serial connection multi-stage shift register unit is formed.
The reference numeral explanation
101: latch cicuit
103: logical circuit
201,407: phase inverter
400,600: shift register cell
401-405,501,503, Q1-Q4: transistor
501,503:N type MOS transistor
505,507:P type MOS transistor
A, VX, VY: end-point voltage
C: electric capacity
CK: clock signal
IN: input signal
V
DD, V
CC: power end
OUT1-OUT4: output signal
XCK: inversion clock signal
OUT, (N-1) OUT, (N) OUT, (N+1) OUT: output terminal
Embodiment
Shift-register circuit proposed by the invention, its maximum is characterised in that each grade shift register cell in this shift-register circuit, its needed transistor size still less, therefore after shift-register circuit is being connected in series the multi-stage shift register unit, the transistor size of circuit whole interior can significantly reduce, the area of layout can relatively be dwindled, lower the complexity of topological design simultaneously.
Please refer to Fig. 4, it illustrates is according in the shift-register circuit proposed by the invention, wherein the internal circuit diagram of one-level shift register cell.As shown in FIG., this shift register cell 400 comprises the first transistor 401, transistor seconds 403, the 3rd transistor 405, phase inverter 407 and decompression capacitor C.
Wherein, first source of the first transistor 401/drain electrode end receives an input signal IN, and when this shift register cell 400 was the first order in shift-register circuit, this first source/drain electrode end system received the data-signal of being imported by the outside.And when this first transistor 401 was not the first order in this shift-register circuit, this first source/drain electrode end received the signal of being exported by the upper level shift register cell.In addition, the gate terminal of the first transistor 401 receives an inversion clock signal XCK.
In the present embodiment, first source of transistor seconds 403/drain electrode end receives a clock signal CK, and gate terminal is coupled to the second source/drain electrode end of the first transistor 401, and second source of this transistor seconds 403/drain electrode end is exported an output signal OUT.Wherein, when this shift register cell 400 is afterbody in shift-register circuit, the output signal OUT that second source of this transistor seconds 403/drain electrode end is exported promptly is the last signal of exporting of this shift-register circuit, and when this shift register cell 400 is not the first order in this shift-register circuit, the output signal OUT that second source of this transistor seconds 403/drain electrode end is exported, the then input signal that is received for the next stage shift register cell.
In addition, in this embodiment, first source of the 3rd transistor 405/drain electrode end is coupled to the second source/drain electrode end of transistor seconds 403, and second source/drain electrode end is coupled to ground.First end of decompression capacitor C is coupled to the first source/drain electrode end of transistor seconds 403, and second end is coupled to the gate terminal of transistor seconds 403.And the phase inverter 407 in circuit, its input end is coupled to the second source/drain electrode end of the first transistor 401, and output terminal is coupled to the gate terminal of the 3rd transistor 405.
As shown in Fig. 5 A, it illustrates is according in the shift-register circuit proposed by the invention, wherein the circuit diagram of the phase inverter in the one-level shift register cell.As shown in FIG., this phase inverter is by two group transistors, and the 4th transistor 501 and the 5th transistor 503 are formed, and in the present embodiment, the 4th transistor 501 and the 5th transistor 503 are N type MOS transistor.
Wherein, first source of the 4th transistor 501/drain electrode end and gate terminal are coupled to power supply V
DD, second source/drain electrode end then is coupled to the gate terminal of above-mentioned illustrated the 3rd transistor 405.And first source of the 5th transistor 503/drain electrode end is coupled to the second source/drain electrode end of the 4th transistor 501, gate terminal then is the second source/drain electrode end that is coupled to above-mentioned illustrated the first transistor 401, and second source of the 5th transistor 503/drain electrode end is coupled to ground.When the signal of VX end was high-voltage level, the output signal of VY end was a low voltage level then, and vice versa.
In addition, as shown in Fig. 5 B, it illustrates is according in the shift-register circuit proposed by the invention, the circuit diagram of the phase inverter in the another kind of shift register cell.As shown in FIG., this phase inverter also is by two group transistors, and the 6th transistor 505 and the 7th transistor 507 are formed, and in the present embodiment, the 6th transistor 505 and the 7th transistor 507 are P type MOS transistor.
Wherein, first source of the 6th transistor 505/drain electrode end is coupled to power supply V
DD, and gate terminal is coupled to the second source/drain electrode end of above-mentioned illustrated the first transistor 401, second source/drain electrode end then is coupled to the gate terminal of above-mentioned illustrated the 3rd transistor 405.And first source of the 7th transistor 507/drain electrode end is coupled to the second source/drain electrode end of the 6th transistor 505, and gate terminal then is the second source/drain electrode end that is coupled to the 7th transistor 507, and second source of the 7th transistor 507/drain electrode end is coupled to ground.
Same, when the signal of VX end was high-voltage level, the output signal of VY end was a low voltage level then, vice versa.Because in the present embodiment, this phase inverter 407 aims to provide an inversion signal, and therefore except aforementioned illustrated circuit, the inverter circuit that can also use other any pattern to form replaces.
In addition, in the present embodiment, above-mentioned mentioned the first transistor 401, transistor seconds 403 and the 3rd transistor 405, it is P type MOS transistor, and when the transistor seconds in this shift register cell 403 is MOS transistor, above-mentioned illustrated decompression capacitor C except can using lump (Lump) electric capacity that adds, also can utilize the grid source electrode stray capacitance Cgd in the transistor seconds 403 to replace.
Please refer to Fig. 6, it illustrates is according in the shift-register circuit proposed by the invention, the internal circuit diagram after the multi-stage shift register unit serial connection.As shown in Figure 6, illustrate the two groups of shift register cells 400 and 600 the situation that is connected in series among this figure, though and only show the serial connection mode of two groups of shift register cells in this diagram, but shift-register circuit proposed by the invention can be according to the specification requirement of dissimilar circuit, according to being connected in series more multistage shift register cell as the mode that is illustrated among Fig. 6.
Please refer to Fig. 7, it illustrates is the clock variation diagram of the signal in the shift register cell 400 and 600 among Fig. 6, below cooperates the circuit that is illustrated among Fig. 6 to describe.As shown in Figure 6, in this shift-register circuit, each grade shift register cell all is coupled to identical clock signal C K and inversion clock signal XCK, wherein, clock signal C K is the opposite clock signal of clock with inversion clock signal XCK, below is divided into the change procedure that three cycles describe signal in detail.
In cycle A, inversion clock signal XCK is low voltage level (Low), clock signal C K is high-voltage level (High), and input signal IN1 transition is low voltage level (Low), because the first transistor 401a is a conducting state, the low voltage level of input signal IN1 can be sent to second source/drain electrode end by first source/drain electrode end of the first transistor 401a, therefore the voltage VX1 of second source/drain electrode end can be pulled to a relative low voltage level (Low+Vth), cause transistor seconds 403a also can be conducting state, at this moment, the high-voltage level of clock signal C K can be sent to second source/drain electrode end by first source/drain electrode end of transistor seconds 403a.And because the input terminal voltage VX1 of phase inverter 407 is low voltage levels, so the terminal voltage VY1 of its output terminal can transition be a high-voltage level, make that the gate terminal of the 3rd transistor 403a is high-voltage level equally, therefore the 3rd transistor 403a can be closing state, and the signal that the output terminal OUT1 of last shift register cell 400 is exported can be a high-voltage level.
In cycle B, input signal IN1 is returned to normal high-voltage level, because also transition simultaneously of the inversion clock signal XCK that gate terminal received of the first transistor 401a, so the first transistor 401a is a closing state.But transistor seconds 403a is owing to be coupled to a decompression capacitor C in addition between source-grid, in this cycle B, the clock signal C K that first source of transistor seconds 403a/drain electrode end received is a low voltage level, cause the voltage VX1 of gate terminal can be pulled low to lower low voltage level (Low+Vth-Δ V) again, wherein, the value of Δ V is the ratio that the height voltage difference of clock signal C K is multiplied by decompression capacitor C and adjacent each transistor parasitic capacitance again, and the computing formula of this Δ V is as follows
C in the following formula
EqBe meant all equivalent capacitys (comprising decompression capacitor C) of seeing away to right-hand member from end-point voltage VX.
The gate terminal of the transistor seconds 403a of this moment still is a low voltage level, this also makes in cycle B, transistor seconds 403a still maintains conducting state, so the low voltage level of clock signal C K can be sent to second source/drain electrode end by first source/drain electrode end of transistor seconds 403a, therefore between this cycle B, the output terminal output LOW voltage level of shift register cell 400 is to next stage register cell 600.
As previously mentioned, because in this embodiment, transistor seconds 403a is a MOS transistor, so above-mentioned mentioned decompression capacitor C can be the grid source electrode stray capacitance Cgd in the MOS transistor.Generally speaking, transistor is under conducting and closing state, the capacitance of its grid source electrode stray capacitance Cgd also can be different, and in cycle B, because transistor seconds 403a just is the state of conducting, so the appearance value of Cgd is bigger, the gate terminal voltage VX1 of transistor seconds 403a can be pulled low to lower voltage, so that transistor seconds can continue to maintain conducting state.Therefore, when using shift-register circuit proposed by the invention, when being MOS transistor, can utilize in the MOS transistor as if the transistor in the circuit, the characteristic of this grid source electrode stray capacitance Cgd replaces decompression capacitor C, needs otherwise designed to add the puzzlement of electric capacity to exempt again.
And in cycle C, clock signal C K and inversion clock signal XCK are because be the cycle variation of repetition, so the state at cycle C is identical with cycle A, but the input signal IN1 of this moment has been a high-voltage level, so the high-voltage level of input signal IN1 can be sent to second source/drain electrode end by first source/drain electrode end of the first transistor 401a, also make the gate terminal transition simultaneously of transistor seconds 403a become high-voltage level, form closing state.In addition, this moment, the output end voltage VY1 of phase inverter 407 was a low voltage level, so the 3rd transistor 405 is a conducting state, the output terminal OUT1 of shift register cell then can export a high-voltage level to next stage shift register cell 600.
By learning in the above-mentioned explanation, the low voltage level of input signal IN1 can postpone the one-period time, just be sent among the shift register cell 600 by the output terminal OUT1 of shift register cell 400, and the internal circuit configuration of shift register cell 600 is identical with aforesaid shift register cell 400, unique difference is that the first transistor 401b is coupled to clock signal C K, and transistor seconds 403b is coupled to the inversion clock signal, but its inner signal change procedure is also identical with shift register 400, at this not at repeated description.And the variation situation of the voltage signal VX2 of shift register cell 600 inner terminals and VY2 is also as shown in Fig. 7, and its output terminal OUT2 equally also can postpone the one-period time, just the signal of output LOW voltage level news.By above explanation as can be known, this shift-register circuit promptly is via inner each grade shift register cell, reach the transmission of inhibit signal, and this shift-register circuit can also be according to different demand, be connected in series the shift register cell of different numbers, to reach different usefulness.
Please refer to Fig. 8, it illustrates the shift register cell of being made up of N type MOS transistor.In aforesaid explanation, be to describe with P type MOS transistor, certainly, be familiar with this skill person, grade shift register cell of each in the shift-register circuit can also be designed by N type MOS transistor.
Please refer to Fig. 9, it illustrates is to utilize in the shift-register circuit proposed by the invention, the circuit diagram of the signal generator that serial connection multi-stage shift register unit forms, as shown in FIG., in this shift-register circuit, the first transistor 401 in the shift register cell of two adjacent groups is opposite with inversion clock signal XCK with the clock signal C K that transistor seconds 403 is coupled to.This signal generator can be applied to the horizontal driver (scanner driver) of the flat-panel screens (Flat Display) of any pattern, use producing the pixel circuit write signal, perhaps also can be used for vertical driver (data driver) and use generation data sampling signal.
In sum, in shift-register circuit of the present invention, the required transistor size of its inner each grade shift register cell, only need 5 transistors (phase inverter needs 2 transistors), than circuit of the prior art still less, therefore when shift-register circuit must be connected in series multistage shift register cell, the transistor size of its whole interior can significantly reduce, adding each grade shift register cell does not need to feed back the output signal of next stage shift register again, so the layout area of integrated circuit can also relatively dwindle more.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (21)
1. a shift-register circuit is composed in series by a plurality of shift register cells, and each those shift register cell receives a clock signal and an inversion clock signal, and each those shift register cell comprises:
One the first transistor, first source of this first transistor/drain electrode end receives an input signal, the gate terminal of this first transistor receive this clock signal and this inversion clock signal the two one of;
One transistor seconds, first source of this transistor seconds/drain electrode end receive this clock signal and this inversion clock signal the two one of, the gate terminal of this transistor seconds is coupled to the second source/drain electrode end of this first transistor, second source of this transistor seconds/draw end to export an output signal;
One the 3rd transistor, the 3rd transistorized first source/drain electrode end is coupled to the second source/drain electrode end of this transistor seconds, and the 3rd transistorized second source/drain electrode end is coupled to a power end; And
One phase inverter, the input end of this phase inverter is coupled to second source of this first transistor/drain electrode end, and the output terminal of this phase inverter is coupled to the 3rd transistorized gate terminal.
Wherein, this the first transistor in each a little shift register cell is different with the clock signal that this transistor seconds is received, and this first transistor in two adjacent those shift register cells is opposite with this inversion clock signal with this clock signal that this transistor seconds is received.
2. shift-register circuit as claimed in claim 1, wherein, this shift-register circuit more comprises an electric capacity, and first end of this electric capacity is coupled to the first source/drain electrode end of this transistor seconds, and second end of this electric capacity is coupled to the gate terminal of this transistor seconds.
3. shift-register circuit as claimed in claim 2, wherein this first transistor, this transistor seconds, and the 3rd crystal piping one metal-oxide-semiconductor (MOS) (Metal Oxide Semiconductor, MOS) transistor.
4. shift-register circuit as claimed in claim 3, wherein, this electric capacity is the grid source electrode stray capacitance of this transistor seconds.
5. shift-register circuit as claimed in claim 3, wherein, this first transistor, this transistor seconds and the 3rd transistor are P type MOS transistor.
6. shift-register circuit as claimed in claim 3, wherein, this first transistor, this transistor seconds and the 3rd transistor are N type MOS transistor.
7. shift-register circuit as claimed in claim 1, wherein, this phase inverter comprises:
One the 4th transistor, the 4th transistorized first source/drain electrode end and gate terminal are coupled to a power supply, and the 4th transistorized second source/drain electrode end is coupled to the 3rd transistorized gate terminal; And
One the 5th transistor, the 5th transistorized first source/drain electrode end is coupled to the 4th transistorized second source/draw end, the 5th transistorized gate terminal is coupled to the second source/drain electrode end of this first transistor, and the 5th transistorized second source/drain electrode end is coupled to ground.
8. shift-register circuit as claimed in claim 7, wherein, the 4th transistor and the 5th transistor are MOS transistor.
9. a shift-register circuit is composed in series by a plurality of shift register cells, and this shift-register circuit comprises:
One first shift register cell comprises:
One the first transistor, first source of this first transistor/drain electrode end receives an input signal, and the gate terminal of this first transistor receives one first clock signal;
One transistor seconds, first source of this transistor seconds/drain electrode end receive a second clock signal, and the gate terminal of this transistor seconds is coupled to second source of this first transistor/drain electrode end, second source of this transistor seconds/draw end to export one first output signal;
One the 3rd transistor, the 3rd transistorized first source/drain electrode end is coupled to the second source/drain electrode end of this transistor seconds, and the 3rd transistorized second source/drain electrode end is coupled to a power end; And
One first phase inverter, the input end of this first phase inverter is coupled to second source of this first transistor/drain electrode end, and the output terminal of this phase inverter is coupled to the 3rd transistorized gate terminal.
One second shift register cell comprises:
One the 4th transistor, the 4th transistorized first source/drain electrode end are coupled to second source of this transistor seconds/draw end, and the 4th transistorized gate terminal receives this second clock signal;
One the 5th transistor, the 5th transistorized first source/drain electrode end receives this first clock signal, and the 5th transistorized gate terminal is coupled to the 4th transistorized second source/drain electrode end, the 5th transistorized second source/draw end to export one second output signal;
One the 6th transistor, the 6th transistorized first source/drain electrode end is coupled to the 5th transistorized second source/drain electrode end, and the 6th transistorized second source/drain electrode end is coupled to this power end; And
One second phase inverter, the input end of this second phase inverter are coupled to the 4th transistorized second source/drain electrode end, and the output terminal of this phase inverter is coupled to the 6th transistorized gate terminal.
10. shift-register circuit as claimed in claim 9, wherein, this first clock signal and this second clock signal are anti-phase clock signals.
11. shift-register circuit as claimed in claim 9, wherein, this first shift register cell comprises one first electric capacity, and first end of this first electric capacity is coupled to the first source/drain electrode end of this transistor seconds, and second end of this electric capacity is coupled to the gate terminal of this transistor seconds.
12. shift-register circuit as claimed in claim 11, wherein, this second shift register cell comprises one second electric capacity, and first end of this second electric capacity is coupled to the 5th transistorized first source/drain electrode end, and second end of this electric capacity is coupled to the 5th transistorized gate terminal.
13. shift-register circuit as claimed in claim 12, wherein, this first transistor, this transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor are MOS transistor.
14. shift-register circuit as claimed in claim 13, wherein, the grid source electrode stray capacitance that this first electric capacity is this transistor seconds.
15. shift-register circuit as claimed in claim 13, wherein, this second electric capacity is the 5th transistorized grid source electrode stray capacitance.
16. shift-register circuit as claimed in claim 13, wherein, this first transistor, this transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor are P type MOS transistor.
17. shift-register circuit as claimed in claim 13, wherein, this first transistor, this transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor are N type MOS transistor.
18. shift-register circuit as claimed in claim 9, wherein, this first phase inverter comprises:
One the 7th transistor, the 7th transistorized first source/drain electrode end and gate terminal are coupled to a power supply, and the 7th transistorized second source/drain electrode end is coupled to the 3rd transistorized gate terminal; And
One the 8th transistor, the 8th transistorized first source/drain electrode end is coupled to the 7th transistorized second source/draw end, the 8th transistorized gate terminal is coupled to the second source/drain electrode end of this first transistor, and the 8th transistorized second source/drain electrode end is coupled to ground.
19. shift-register circuit as claimed in claim 18, wherein, the 7th transistor and the 8th transistor are MOS transistor.
20. shift-register circuit as claimed in claim 9, wherein, this second phase inverter comprises:
One the 7th transistor, the 7th transistorized first source/drain electrode end and gate terminal are coupled to a power supply, and the 7th transistorized second source/drain electrode end is coupled to the 3rd transistorized gate terminal; And
One the 8th transistor, the 8th transistorized first source/drain electrode end is coupled to the 7th transistorized second source/draw end, the 8th transistorized gate terminal is coupled to the second source/drain electrode end of this first transistor, and the 8th transistorized second source/drain electrode end is coupled to ground.
21. shift-register circuit as claimed in claim 20, wherein, the 7th transistor and the 8th transistor are MOS transistor.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894583A (en) * | 2010-07-08 | 2010-11-24 | 矽创电子股份有限公司 | Memory unit capable of saving circuit area |
| CN106169280A (en) * | 2016-06-28 | 2016-11-30 | 厦门天马微电子有限公司 | Shifting deposit unit, drive circuit and display device |
| CN107195328A (en) * | 2009-10-09 | 2017-09-22 | 株式会社半导体能源研究所 | Shift register and display device and its driving method |
| CN112737593A (en) * | 2020-12-24 | 2021-04-30 | 重庆邮电大学 | Propagation chain chasing type low-power-consumption time domain comparator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4446567A (en) * | 1980-03-05 | 1984-05-01 | Tokyo Shibaura Denki Kabushiki Kaisha | Dynamic shift register circuit |
| CN1553456A (en) * | 2003-06-04 | 2004-12-08 | 友达光电股份有限公司 | Shift register circuit |
| CN1609939A (en) * | 2003-01-25 | 2005-04-27 | 夏普株式会社 | Shift register |
-
2006
- 2006-05-24 CN CN2006100898246A patent/CN101079325B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4446567A (en) * | 1980-03-05 | 1984-05-01 | Tokyo Shibaura Denki Kabushiki Kaisha | Dynamic shift register circuit |
| CN1609939A (en) * | 2003-01-25 | 2005-04-27 | 夏普株式会社 | Shift register |
| CN1553456A (en) * | 2003-06-04 | 2004-12-08 | 友达光电股份有限公司 | Shift register circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195328A (en) * | 2009-10-09 | 2017-09-22 | 株式会社半导体能源研究所 | Shift register and display device and its driving method |
| CN107195328B (en) * | 2009-10-09 | 2020-11-10 | 株式会社半导体能源研究所 | Shift register, display device and driving method thereof |
| US11296120B2 (en) | 2009-10-09 | 2022-04-05 | Semiconductor Energy Laboratory Co., Ltd. | Shift register and display device and driving method thereof |
| CN101894583A (en) * | 2010-07-08 | 2010-11-24 | 矽创电子股份有限公司 | Memory unit capable of saving circuit area |
| CN101894583B (en) * | 2010-07-08 | 2016-03-02 | 矽创电子股份有限公司 | Save the mnemon of circuit area |
| CN106169280A (en) * | 2016-06-28 | 2016-11-30 | 厦门天马微电子有限公司 | Shifting deposit unit, drive circuit and display device |
| CN112737593A (en) * | 2020-12-24 | 2021-04-30 | 重庆邮电大学 | Propagation chain chasing type low-power-consumption time domain comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101079325B (en) | 2010-12-29 |
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