CN106169280A - Shifting deposit unit, drive circuit and display device - Google Patents
Shifting deposit unit, drive circuit and display device Download PDFInfo
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- CN106169280A CN106169280A CN201610487236.1A CN201610487236A CN106169280A CN 106169280 A CN106169280 A CN 106169280A CN 201610487236 A CN201610487236 A CN 201610487236A CN 106169280 A CN106169280 A CN 106169280A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- General Physics & Mathematics (AREA)
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Abstract
The invention provides shifting deposit unit, drive circuit and display device, wherein shifting deposit unit includes: latch cicuit, the first computing circuit and the second computing circuit；Latch cicuit includes the first transistor, the first phase inverter, the second phase inverter, the 3rd phase inverter and the 4th transistor；The grid of the outfan electrical connection the first transistor of the first phase inverter, first pole of the first transistor electrically connects the input of the second phase inverter, second pole of the first transistor is electrically connected the outfan of the 3rd phase inverter and subordinate's signal output part of shifting deposit unit, the input of outfan electrical connection the 3rd phase inverter of the second phase inverter, first computing circuit includes transistor seconds, first pull-down and the 4th phase inverter, second computing circuit includes third transistor, second pull-down and the 5th phase inverter, the present invention can be greatly reduced TFT device count, to realize narrow frame, and reduce power consumption.
Description
Technical field
The present invention relates to show driving field, particularly relate to a kind of shifting deposit unit, drive circuit and display device.
Background technology
The development of the technology such as the requirement tested along with user opponent's body is more and more higher, large-size screen monitors accounting, narrow frame, low-power consumption is also
Increasingly faster, high screen accounting, low-power consumption also becomes the advantage place of mobile phone faceplate manufacturer.Existing VSR normal circuit operation needs
19 TFT devices, 12 TFT devices therein are wanted to form latch cicuit.The TFT device of circuit is the most will increase frame
Width, it is difficult to realize the effect of narrow frame.
Summary of the invention
For the problems of the prior art, it is an object of the invention to provide shifting deposit unit, drive circuit and show
Showing device, it is possible to TFT device count be greatly reduced to realize narrow frame, and reduce power consumption.
A kind of shifting deposit unit that the embodiment of the present invention provides, including: latch cicuit, the first computing circuit and second
Computing circuit；
The input of described first computing circuit and the input of the second computing circuit are respectively electrically connected to described latch electricity
The outfan on road；The outfan of described first computing circuit electrically connects the first output signal output of described shifting deposit unit
End, the outfan of described second computing circuit electrically connects the second output signal outfan of described shifting deposit unit；
Described latch cicuit includes that the first transistor, the first phase inverter, the second phase inverter, the 3rd phase inverter and the 4th are brilliant
Body pipe；The outfan of described first phase inverter electrically connects the grid of described the first transistor, the first pole of described the first transistor
Electrically connecting the input of described second phase inverter, the second pole of described the first transistor is electrically connected described 3rd phase inverter
Subordinate's signal output part of outfan and described shifting deposit unit, the outfan electrical connection the described 3rd of described second phase inverter
The input of phase inverter, and the outfan of described second phase inverter is configured to the outfan of described latch cicuit, described first
The input of phase inverter and the grid of described 4th transistor are electrically connected the latch signal input of described shifting deposit unit
End, the first pole of described 4th transistor electrically connects the enabling signal input of described shifting deposit unit, described 4th crystal
Second pole of pipe electrically connects the input of described second phase inverter；
Described first computing circuit includes transistor seconds, the first pull-down and the 4th phase inverter, and described second is brilliant
The grid of body pipe electrically connects the first clock signal input terminal of described shifting deposit unit, and the first of described transistor seconds is the most electric
Connecting the input of described first computing circuit, the input of described first pull-down and described 4th phase inverter is electrically connected respectively
Connect the second pole of described transistor seconds；
Described second computing circuit includes third transistor, the second pull-down and the 5th phase inverter, described trimorphism
The grid of body pipe electrically connects the second clock signal input part of described shifting deposit unit, and the first of described third transistor is the most electric
Connecting the input of described second computing circuit, the input of described second pull-down and described 5th phase inverter is electrically connected respectively
Connect the second pole of described third transistor.
The embodiment of the present invention additionally provides a kind of drive circuit, including multistage shifting deposit unit described above, upper level
The enabling signal input of shifting deposit unit described in subordinate's signal output part electrical connection next stage of described shifting deposit unit.
The embodiment of the present invention additionally provides a kind of display device, including viewing area and the limit that surrounds described viewing area
Frame region, described viewing area includes multi-strip scanning line, a plurality of data lines and the battle array surrounded by described scan line, data wire
Row type pixel region, the described frame region of at least side, described viewing area arranges drive circuit described above, to control
State the signal output timing of scan line.
The shifting deposit unit of the present invention, drive circuit and display device can be greatly reduced TFT device count, with
Realize narrow frame, and reduce power consumption.
Accompanying drawing explanation
By the detailed description non-limiting example made with reference to the following drawings of reading, the further feature of the present invention,
Purpose and advantage will become more apparent upon.
Fig. 1 is the circuit diagram of the shifting deposit unit of first embodiment of the invention.
Fig. 2 is the circuit theory diagrams of the shifting deposit unit of first embodiment of the invention.
Fig. 3 is each input of the shifting deposit unit in first embodiment of the invention, the sequential chart of outfan.
Fig. 4 is the connection diagram of the drive circuit of first embodiment of the invention.
Fig. 5 is the circuit diagram of the shifting deposit unit of second embodiment of the invention.
Fig. 6 is the circuit theory diagrams of the shifting deposit unit of second embodiment of the invention.
Fig. 7 is each input of the shifting deposit unit in second embodiment of the invention, the sequential chart of outfan.And
Fig. 8 is the connection diagram of the drive circuit of second embodiment of the invention.
Detailed description of the invention
It is described more fully with example embodiment referring now to accompanying drawing.But, example embodiment can be with multiple shape
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, it is provided that these embodiments make the present invention incite somebody to action
Fully and completely, and by the design of example embodiment those skilled in the art is conveyed to all sidedly.The most identical is attached
Figure labelling represents same or similar structure, thus will omit repetition thereof.
First embodiment
Fig. 1 is the circuit diagram of the shifting deposit unit of first embodiment of the invention.Fig. 2 is first embodiment of the invention
The circuit theory diagrams of shifting deposit unit.As illustrated in fig. 1 and 2, the shifting deposit unit of the present invention, including latch cicuit 100,
First computing circuit the 200, second computing circuit 300, restart circuit the 400, first current potential Vgh and the second current potential Vgl.Wherein,
First current potential Vgh is high level, and the second current potential Vgl is low level.
The input of the first computing circuit 200 and the input of the second computing circuit 300 are respectively electrically connected to latch cicuit
The outfan of 100.First output signal outfan 56 of the outfan electrical connection shifting deposit unit of the first computing circuit 200,
Second output signal outfan 57 of the outfan electrical connection shifting deposit unit of the second computing circuit 300.
Latch cicuit 100 include the first transistor T1, the first phase inverter F1, the second phase inverter F2, the 3rd phase inverter F3 with
And the 4th transistor T4.The grid of the outfan electrical connection the first transistor T1 of the first phase inverter F1, the of the first transistor T1
One pole electrically connects the input of the second phase inverter F2, and second pole of the first transistor T1 is electrically connected the defeated of the 3rd phase inverter F3
Go out subordinate's signal output part 58 of end and shifting deposit unit, outfan electrical connection the 3rd phase inverter F3's of the second phase inverter F2
Input, and the outfan of the second phase inverter F2 is configured to the outfan of latch cicuit 100, the input of the first phase inverter F1
With the latch signal input 52 that the grid of the 4th transistor T4 is electrically connected shifting deposit unit, the of the 4th transistor T4
The enabling signal input 51 of one pole electrical connection shifting deposit unit, second pole of the 4th transistor T4 electrically connects the second phase inverter
The input of F2.The latch cicuit 100 of the present invention is reduced to 8 TFT by 12 original TFT, greatly reduces TFT device.
First computing circuit 200 includes transistor seconds T2, the first pull-down and the 4th phase inverter F4, the second crystal
First clock signal input terminal 53 of the grid electrical connection shifting deposit unit of pipe T2, the first pole electrical connection of transistor seconds T2
The input of the first computing circuit 200, the input of the first pull-down and the 4th phase inverter F4 is electrically connected the second crystal
Second pole of pipe T2.First pull-down includes that the 6th transistor T6, the grid of the 6th transistor T6 electrically connect the second computing electricity
The outfan on road 300, second pole of the first pole electrical connection transistor seconds T2 of the 6th transistor T6, the of the 6th transistor T6
Two poles electrically connect the first current potential Vgh.
Second computing circuit 300 includes third transistor T3, the second pull-down and the 5th phase inverter F5, the 3rd crystal
The second clock signal input part 54 of the grid electrical connection shifting deposit unit of pipe T3, the first pole electrical connection of third transistor T3
The input of the second computing circuit 300, the input of the second pull-down and the 5th phase inverter F5 is electrically connected the 3rd crystal
Second pole of pipe T3.Second pull-down includes that the grid of the 7th transistor T7, the 7th transistor T7 connects shifting deposit unit
Control signal input 59, the 7th transistor T7 first pole electrical connection third transistor T3 the second pole, the 7th transistor
Second pole of T7 electrically connects the first current potential Vgh.
Restart the weight that circuit 400 includes the grid electrical connection shifting deposit unit of the 5th transistor T5, the 5th transistor T5
Put signal input part 55, the outfan of the first pole electrical connection latch cicuit 100 of the 5th transistor T5, the of the 5th transistor T5
Two poles electrically connect the first current potential Vgh.
First phase inverter F1 includes the 8th transistor T8 and the 9th transistor T9, the grid of the 8th transistor T8 and the 9th crystalline substance
The grid of body pipe T9 is connected to primary nodal point, and primary nodal point is configured to the input of the first phase inverter F1, the 8th transistor T8
The first pole electrically connect the first current potential Vgh, first pole of the 9th transistor T9 electrically connects the second current potential Vgl, the 8th transistor T8
The second pole and second pole of the 9th transistor T9 be connected to secondary nodal point, secondary nodal point is configured to the defeated of the first phase inverter F1
Go out end.
Second phase inverter F2 includes the tenth transistor T10 and the 11st transistor T11, the grid of the tenth transistor T10 and
The grid of the 11st transistor T11 is connected to the 3rd node, and the 3rd node is configured to the input of the second phase inverter F2, and the tenth
First pole of transistor T10 electrically connects the first current potential Vgh, and first pole of the 11st transistor T11 electrically connects the second current potential Vgl,
Second pole of the tenth transistor T10 and second pole of the 11st transistor T11 are connected to fourth node, and fourth node is configured to
The outfan of the second phase inverter F2.
3rd phase inverter F3 includes the tenth two-transistor T12 and the 13rd transistor T13, the grid of the tenth two-transistor T12
The grid of pole and the 13rd transistor T13 is connected to the 5th node, and the 5th node is configured to the input of the 3rd phase inverter F3,
First pole of the tenth two-transistor T12 electrically connects first pole electrical connection first electricity of the second current potential Vgl, the 13rd transistor T13
Position Vgh, second pole of the tenth two-transistor T12 and second pole of the 13rd transistor T13 is connected to the 6th node, the 6th node
It is configured to the outfan of the 3rd phase inverter F3.
4th phase inverter F4 includes the 14th transistor T14 and the 15th transistor T15, the grid of the 14th transistor T14
The grid of pole and the 15th transistor T15 is connected to the 7th node, and the 7th node is configured to the input of the 4th phase inverter F4,
First pole of the 14th transistor T14 electrically connects first pole electrical connection second electricity of the first current potential Vgh, the 15th transistor T15
Position Vgl, second pole of the 14th transistor T14 and second pole of the 15th transistor T15 is connected to the 8th node, the 8th node
It is configured to the outfan of the 4th phase inverter F4.
5th phase inverter F5 includes the 16th transistor T16 and the 17th transistor T17, the grid of the 16th transistor T16
The grid of pole and the 17th transistor T17 is connected to Psychotria rubra (Lour.) Poir. point, and Psychotria rubra (Lour.) Poir. point is configured to the input of the 5th phase inverter F5,
First pole of the 16th transistor T16 electrically connects first pole electrical connection second electricity of the first current potential Vgh, the 17th transistor T17
Position Vgl, second pole of the 16th transistor T16 and second pole of the 17th transistor T17 are connected to protelum point, protelum point
It is configured to the outfan of the 5th phase inverter F5.
In the present embodiment, the first transistor T1, transistor seconds T2, the 3rd body crystalline substance pipe T3, the 4th body crystalline substance pipe T4, the 6th crystalline substance
Body pipe T6, the 7th transistor T7, the 9th body crystalline substance pipe T9, the 11st transistor T11, the tenth two-transistor T12, the 15th transistor
T15, the 17th transistor T17 are N-channel transistor npn npn.5th transistor T5, the 8th transistor T8, the tenth body pipe T10,
13 body pipe T13, the 14th transistor T14, the 16th transistor T16 are P-channel transistor npn npn.But it is not limited.
Fig. 3 is each input of the shifting deposit unit in first embodiment of the invention, the sequential chart of outfan.Wherein,
STV represents the enabling signal that enabling signal input 51 inputs；CKV1 represents the latch signal that latch signal input 52 inputs；
NO represents the output signal of latch cicuit 100；CKV2 represents the first clock signal of the first clock signal input terminal 53 input；
CKV3 represents the second clock signal that second clock signal input part 54 inputs；GOUT1 represents the first output signal outfan 56
First output signal of output；GOUT2 represents the second output signal of the second output signal outfan 57 output；Under NEXT represents
Subordinate's signal of level signal output part 58 output.Referring to figs. 1 to shown in 3, when latch signal CKV1 high level is effective, the 4th is brilliant
Body pipe T4 opens, and enabling signal STV enters latch cicuit 100；When latch signal CKV1 Low level effective, the first transistor T1
Opening, latch cicuit 100 works in latch mode, generates output signal and the subordinate signal NEXT of latch cicuit 100.
Transistor seconds T2 is the output signal of output latch circuit 100 under the control of the first clock signal CKV2,
When one clock signal CKV2 signal is effective, the output signal of latch cicuit 100 enters the 4th phase inverter F4 and exports the first output
Signal Gout1.When second clock signal CKV3 signal is effective, third transistor T3 is opened and is made the output of latch cicuit 100 believe
Number enter and open the second output signal Gout2, meanwhile, the 6th transistor T6 can when the second output signal Gout2 is effective incite somebody to action
First output signal Gout1 drags down, it is ensured that in the 4th phase inverter F4 and the 5th phase inverter F5, only one of which phase inverter is unlocked.Its
In the 6th transistor T6 and the 7th transistor T7 function identical, all can have one before the phase inverter that i.e. every one-level grid is corresponding
Pull-down.
Fig. 4 is the connection diagram of the drive circuit of first embodiment of the invention.As shown in Figure 4, the present invention also provides for one
Kind of drive circuit, goes between 61 including the shifting deposit unit of multiple cascades such as Fig. 1 and Fig. 2 and enabling signal, latch signal draws
Line the 62, first clock signal lead-in wire 63, second clock signal lead 64, reset signal lead-in wire 65, output signal lead-in wire 66, subordinate
Signal lead 67.Wherein, subordinate's signal output part 58 of upper level shifting deposit unit electrically connects next stage shifting deposit unit
Enabling signal input 51, enabling signal lead-in wire 61 is configured to transmission start signal STV, and latch signal lead-in wire 62 is configured
For transmission latch signal CKV1, the first clock signal lead-in wire 63 is configured to transmit the first clock signal CKV2, and second clock is believed
Number lead-in wire 64 be configured to transmit second clock signal CKV3, reset signal lead-in wire 65 be configured to transmit reset signal, output
Signal lead 66 is configured to transmit the first output signal Gout1 and the second output signal Gout2, and subordinate's signal lead 67 is joined
It is set to transmit subordinate signal NEXT (seeing Fig. 3).
Adjacent three shifting deposit unit arranged in the first direction is configured to a first shift LD group, each
In first shift LD group, enabling signal input 51 electrical connection of first shifting deposit unit in the first direction starts letter
Number lead-in wire 61, latch signal input 52 electrically connect latch signal lead-in wire 62, the first clock signal input terminal 53 electrically connects first
Clock signal lead-in wire 63, second clock signal input part 54 electrically connects second clock signal lead 64, reset signal input 55
Electrical connection reset signal lead-in wire 65, first output signal outfan the 56, second output signal outfan 57 and control signal are defeated
Entering end 59 electrical connection output signal lead-in wire 66, subordinate's signal output part 58 electrically connects subordinate's signal lead 67.
The enabling signal input 51 of second shifting deposit unit in the first direction in each first shift LD group
Electrical connection subordinate signal lead 67, latch signal input 52 electrically connects second clock signal lead 64, and the first clock signal is defeated
Entering end 53 electrical connection latch signal lead-in wire 62, second clock signal input part 54 electrically connects the first clock signal lead-in wire 63, resets
Signal input part 55 electrically connect reset signal lead-in wire 65, first output signal outfan the 56, second output signal outfan 57 with
And control signal input 59 electrically connects output signal lead-in wire 66, subordinate's signal output part 58 electrically connects subordinate's signal lead 67.
The enabling signal input 51 of the 3rd shifting deposit unit in the first direction in each first shift LD group
Electrical connection subordinate signal lead 67, latch signal input 52 electrically connects the first clock signal lead-in wire 63, and the first clock signal is defeated
Entering end 53 electrical connection second clock signal lead 64, second clock signal input part 54 electrically connects latch signal lead-in wire 62, resets
Signal input part 55 electrically connect reset signal lead-in wire 65, first output signal outfan the 56, second output signal outfan 57 with
And control signal input 59 electrically connects output signal lead-in wire 66, subordinate's signal output part 58 electrically connects subordinate's signal lead 67.
By the drive circuit of the present invention carries out 24 grades of cascade emulation, its output signal is without exception, is greatly reducing carrying of TFT device
Front lower, it is possible to achieve same drives effect.
In a preferred embodiment, first clock signal lead-in wire 63 transmission the first clock signal, second clock signal draws
Line 64 transmit second clock signal, the first clock signal and second clock signal within a cycle before 1/3rd cycle
For low level current potential, the cycle of middle 1/3rd is high level current potential, and the cycle of rear 1/3rd is low level current potential.
The present invention also provides for a kind of display device, including viewing area and the frame region of encirclement viewing area, display
Region includes multi-strip scanning line, a plurality of data lines and the array type pixel region surrounded by scan line, data wire, viewing area
The frame region of at least side, territory arranges drive circuit as shown in Figure 4, to control the signal output timing of scan line, its principle
With effect as it was previously stated, here is omitted.
Second embodiment
Fig. 5 is the circuit diagram of the shifting deposit unit of second embodiment of the invention.Fig. 6 is second embodiment of the invention
The circuit theory diagrams of shifting deposit unit.As it can be seen in figures 5 and 6, the shifting deposit unit of the present invention, including latch cicuit 100,
First computing circuit the 200, second computing circuit 300, restart circuit the 400, first current potential Vgh and the second current potential Vgl.Wherein,
First current potential Vgh is high level, and the second current potential Vgl is low level.
The input of the first computing circuit 200 and the input of the second computing circuit 300 are respectively electrically connected to latch cicuit
The outfan of 100.First output signal outfan 56 of the outfan electrical connection shifting deposit unit of the first computing circuit 200,
Second output signal outfan 57 of the outfan electrical connection shifting deposit unit of the second computing circuit 300.
Latch cicuit 100 include the first transistor T1, the first phase inverter F1, the second phase inverter F2, the 3rd phase inverter F3 with
And the 4th transistor T4.The grid of the outfan electrical connection the first transistor T1 of the first phase inverter F1, the of the first transistor T1
One pole electrically connects the input of the second phase inverter F2, and second pole of the first transistor T1 is electrically connected the defeated of the 3rd phase inverter F3
Go out subordinate's signal output part 58 of end and shifting deposit unit, outfan electrical connection the 3rd phase inverter F3's of the second phase inverter F2
Input, and the outfan of the second phase inverter F2 is configured to the outfan of latch cicuit 100, the input of the first phase inverter F1
With the latch signal input 52 that the grid of the 4th transistor T4 is electrically connected shifting deposit unit, the of the 4th transistor T4
The enabling signal input 51 of one pole electrical connection shifting deposit unit, second pole of the 4th transistor T4 electrically connects the second phase inverter
The input of F2.The latch cicuit 100 of the present invention is reduced to 8 TFT by 12 original TFT, greatly reduces TFT device.
First computing circuit 200 includes transistor seconds T2, the first pull-down and the 4th phase inverter F4, the second crystal
First clock signal input terminal 53 of the grid electrical connection shifting deposit unit of pipe T2, the first pole electrical connection of transistor seconds T2
The input of the first computing circuit 200, the input of the first pull-down and the 4th phase inverter F4 is electrically connected the second crystal
Second pole of pipe T2.First pull-down includes the grid electrical connection displacement of the 18th transistor T18, the 18th transistor T18
Second pole of the first pole electrical connection transistor seconds T2 of control signal input the 59, the 18th transistor T18 of deposit unit,
Second pole of the 18th transistor T18 electrically connects the first current potential Vgh.
Second computing circuit 300 includes third transistor T3, the second pull-down and the 5th phase inverter F5, the 3rd crystal
The second clock signal input part 54 of the grid electrical connection shifting deposit unit of pipe T3, the first pole electrical connection of third transistor T3
The input of the first computing circuit 300, the input of the second pull-down and the 5th phase inverter F5 is electrically connected the 3rd crystal
Second pole of pipe T3.Second pull-down includes the grid electrical connection displacement of the 19th transistor T19, the 19th transistor T19
Second pole of first pole electrical connection third transistor T3 of control signal input the 59, the 19th transistor T19 of deposit unit,
Second pole of the 19th transistor T19 electrically connects the first current potential Vgh.
Unlike first embodiment, the present embodiment connects the 18th respectively by increase control signal input 59
The grid of transistor T18 and the grid of the 19th transistor T19, by the impulse waveform of control signal to the 18th transistor
T18, the 19th transistor T19 are controlled.
Restart the weight that circuit 400 includes the grid electrical connection shifting deposit unit of the 5th transistor T5, the 5th transistor T5
Put signal input part 55, the outfan of the first pole electrical connection latch cicuit 100 of the 5th transistor T5, the of the 5th transistor T5
Two poles electrically connect the first current potential Vgh.
First phase inverter F1 includes the 8th transistor T8 and the 9th transistor T9, the grid of the 8th transistor T8 and the 9th crystalline substance
The grid of body pipe T9 is connected to primary nodal point, and primary nodal point is configured to the input of the first phase inverter F1, the 8th transistor T8
The first pole electrically connect the first current potential Vgh, first pole of the 9th transistor T9 electrically connects the second current potential Vgl, the 8th transistor T8
The second pole and second pole of the 9th transistor T9 be connected to secondary nodal point, secondary nodal point is configured to the defeated of the first phase inverter F1
Go out end.
Second phase inverter F2 includes the tenth transistor T10 and the 11st transistor T11, the grid of the tenth transistor T10 and
The grid of the 11st transistor T11 is connected to the 3rd node, and the 3rd node is configured to the input of the second phase inverter F2, and the tenth
First pole of transistor T10 electrically connects the first current potential Vgh, and first pole of the 11st transistor T11 electrically connects the second current potential Vgl,
Second pole of the tenth transistor T10 and second pole of the 11st transistor T11 are connected to fourth node, and fourth node is configured to
The outfan of the second phase inverter F2.
3rd phase inverter F3 includes the tenth two-transistor T12 and the 13rd transistor T13, the grid of the tenth two-transistor T12
The grid of pole and the 13rd transistor T13 is connected to the 5th node, and the 5th node is configured to the input of the 3rd phase inverter F3,
First pole of the tenth two-transistor T12 electrically connects first pole electrical connection first electricity of the second current potential Vgl, the 13rd transistor T13
Position Vgh, second pole of the tenth two-transistor T12 and second pole of the 13rd transistor T13 is connected to the 6th node, the 6th node
It is configured to the outfan of the 3rd phase inverter F3.
4th phase inverter F4 includes the 14th transistor T14 and the 15th transistor T15, the grid of the 14th transistor T14
The grid of pole and the 15th transistor T15 is connected to the 7th node, and the 7th node is configured to the input of the 4th phase inverter F4,
First pole of the 14th transistor T14 electrically connects first pole electrical connection second electricity of the first current potential Vgh, the 15th transistor T15
Position Vgl, second pole of the 14th transistor T14 and second pole of the 15th transistor T15 is connected to the 8th node, the 8th node
It is configured to the outfan of the 4th phase inverter F4.
5th phase inverter F5 includes the 16th transistor T16 and the 17th transistor T17, the grid of the 16th transistor T16
The grid of pole and the 17th transistor T17 is connected to Psychotria rubra (Lour.) Poir. point, and Psychotria rubra (Lour.) Poir. point is configured to the input of the 5th phase inverter F5,
First pole of the 16th transistor T16 electrically connects first pole electrical connection second electricity of the first current potential Vgh, the 17th transistor T17
Position Vgl, second pole of the 16th transistor T16 and second pole of the 17th transistor T17 are connected to protelum point, protelum point
It is configured to the outfan of the 5th phase inverter F5.
In the present embodiment, the first transistor T1, transistor seconds T2, the 3rd body crystalline substance pipe T3, the 4th body crystalline substance pipe T4, the 18th
Transistor T18, the 19th transistor T19, the 9th body crystalline substance pipe T9, the 11st transistor T11, the tenth two-transistor T12, the 15th
Transistor T15, the 17th transistor T17 are N-channel transistor npn npn.5th transistor T5, the 8th transistor T8, the tenth body pipe
T10, the 13rd body pipe T13, the 14th transistor T14, the 16th transistor T16 are P-channel transistor npn npn.But not as
Limit.
Fig. 7 is each input of the shifting deposit unit in second embodiment of the invention, the sequential chart of outfan.Wherein,
STV represents the enabling signal that enabling signal input 51 inputs；CKV1 represents the latch signal that latch signal input 52 inputs；
NO represents the output signal of latch cicuit 100；CKV2 represents the first clock signal of the first clock signal input terminal 53 input；
CKV3 represents the second clock signal that second clock signal input part 54 inputs；GOUT1 represents the first output signal outfan 56
First output signal of output；GOUT2 represents the second output signal of the second output signal outfan 57 output；Under NEXT represents
Subordinate's signal of level signal output part 58 output；OE represents the control signal that control signal input 59 inputs.Referring to figs. 1 to 3
Shown in, when latch signal CKV1 high level is effective, the 4th transistor T4 opens, and enabling signal STV enters latch cicuit 100；
When latch signal CKV1 Low level effective, the first transistor T1 opens, and latch cicuit 100 works in latch mode, generates lock
Deposit output signal and the subordinate signal NEXT of circuit 100.As it is shown in fig. 7, in a second embodiment, in order to avoid the first output letter
The second output signal that the trailing edge of the first output signal of number outfan 56 output exports with the second output signal outfan 57
Rising edge overlapping situation occurs, add the control signal of control signal input 59 input, and control second clock
The rising edge of signal CKV3 postpones a timing slack e, the pulse of control signal OE than the trailing edge of the first clock signal CKV2
Width is also equal to timing slack e.Unlike first embodiment, in the present embodiment, the control signal input of increase by 59 points
Not Lian Jie the grid of the 18th transistor T18 and the grid of the 19th transistor T19, by the impulse waveform of control signal to
18 transistor T18, the 19th transistor T19 are controlled, when the pulse of control signal OE is effectively to drag down first by force
First output signal of output signal outfan 56 output and the second output signal of the second output signal outfan 57 output；When
After control signal OE end-of-pulsing, the second output signal just begins to ramp up edge so that the first output signal outfan 56 output
Exist between the rising edge of the second output signal of the trailing edge of the first output signal and the output of the second output signal outfan 57
The interval of one timing slack e, thus avoid the trailing edge of the first output signal of the first output signal outfan 56 output
With the rising edge of the second output signal of the second output signal outfan 57 output, overlapping situation occurs.Fig. 8 is the present invention
The connection diagram of the drive circuit of two embodiments.As shown in Figure 8, the present invention also provides for a kind of drive circuit, this drive circuit
Including multiple cascades the shifting deposit unit such as Fig. 5 and Fig. 6, gap signal lead-in wire 60, enabling signal lead-in wire 61, latch signal
Lead-in wire 62, first clock signal lead-in wire 63, second clock signal lead 64, reset signal lead-in wire 65, output signal lead-in wire 66 with
And subordinate's signal lead 67.Wherein, subordinate's signal output part 58 of upper level shifting deposit unit electrically connect next stage displacement post
The enabling signal input 51 of memory cell, gap signal lead-in wire 60 is configured to transmission of control signals OE, enabling signal lead-in wire 61
Being configured to transmission start signal STV, latch signal lead-in wire 62 is configured to transmit latch signal CKV1, and the first clock signal is drawn
Line 63 is configured to transmit the first clock signal CKV2, and second clock signal lead 64 is configured to transmit second clock signal
CKV3, reset signal lead-in wire 65 is configured to transmit reset signal, and output signal lead-in wire 66 is configured to transmit the first output letter
Number Gout1 and the second output signal Gout2, subordinate's signal lead 67 is configured to transmit subordinate signal NEXT (seeing Fig. 7).With
Unlike first embodiment, in the present embodiment, all of control signal input 59 is connected respectively to gap signal lead-in wire 60
Introduce the pulse of control signal.
Adjacent three shifting deposit unit arranged in the first direction is configured to a second shift LD group, each
In second shift LD group, enabling signal input 51 electrical connection of first shifting deposit unit in the first direction starts letter
Number lead-in wire 61, latch signal input 52 electrically connect latch signal lead-in wire 62, the first clock signal input terminal 53 electrically connects first
Clock signal lead-in wire 63, second clock signal input part 54 electrically connects second clock signal lead 64, reset signal input 55
Electrical connection reset signal lead-in wire 65, first output signal outfan the 56, second output signal outfan 57 electrically connects output signal
Lead-in wire 66, control signal input 59 electrically connects gap signal lead-in wire 60, and subordinate's signal output part 58 electrically connects subordinate's signal and draws
Line 67.
The enabling signal input 51 of second shifting deposit unit in the first direction in each second shift LD group
Electrical connection subordinate signal lead 67, latch signal input 52 electrically connects second clock signal lead 64, and the first clock signal is defeated
Entering end 53 electrical connection latch signal lead-in wire 62, second clock signal input part 54 electrically connects the first clock signal lead-in wire 63, resets
Signal input part 55 electrically connects reset signal lead-in wire 65, first output signal outfan the 56, second output signal outfan 57 electricity
Connecting output signal lead-in wire 66, control signal input 59 electrically connects gap signal lead-in wire 60, and subordinate's signal output part 58 is electrically connected
Connect subordinate's signal lead 67.
The enabling signal input 51 of the 3rd shifting deposit unit in the first direction in each second shift LD group
Electrical connection subordinate signal lead 67, latch signal input 52 electrically connects the first clock signal lead-in wire 63, and the first clock signal is defeated
Entering end 53 electrical connection second clock signal lead 64, second clock signal input part 54 electrically connects latch signal lead-in wire 62, resets
Signal input part 55 electrically connects reset signal lead-in wire 65, first output signal outfan the 56, second output signal outfan 57 electricity
Connecting output signal lead-in wire 66, control signal input 59 electrically connects gap signal lead-in wire 60, and subordinate's signal output part 58 is electrically connected
Connect subordinate's signal lead 67.Gap signal goes between 60 transmission pulse signals, and the high level end time of the first clock signal is leading
Pulse width in one pulse signal of high level initial time of second clock signal.By the drive circuit of the present invention is entered
Row 24 grades cascade emulation, its output signal is without exception, greatly reduce TFT device in advance under, it is possible to achieve same circuit
Drive effect.
In a preferred embodiment, first clock signal lead-in wire 63 transmission the first clock signal, second clock signal draws
Line 64 transmit second clock signal, the first clock signal and second clock signal within a cycle before 1/3rd cycle
For low level current potential, the cycle of middle 1/3rd is high level current potential, and the cycle of rear 1/3rd is low level current potential.
The present invention also provides for a kind of display device, including viewing area and the frame region of encirclement viewing area, display
Region includes multi-strip scanning line, a plurality of data lines and the array type pixel region surrounded by scan line, data wire, viewing area
The frame region of at least side, territory arranges drive circuit as shown in Figure 8, to control the signal output timing of scan line, its principle
With effect as it was previously stated, here is omitted.
In sum, the shifting deposit unit of the present invention, drive circuit and display device can be greatly reduced TFT device
Number of packages mesh, to realize narrow frame, and reduces power consumption.
Above content is to combine concrete preferred implementation further description made for the present invention, it is impossible to assert
Being embodied as of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of present inventive concept, it is also possible to make some simple deduction or replace, all should be considered as belonging to the present invention's
Protection domain.
Claims (13)
1. a shifting deposit unit, including: latch cicuit, the first computing circuit and the second computing circuit, it is characterised in that:
The input of described first computing circuit and the input of the second computing circuit are respectively electrically connected to described latch cicuit
Outfan；The outfan of described first computing circuit electrically connects the first output signal outfan of described shifting deposit unit, institute
The outfan stating the second computing circuit electrically connects the second output signal outfan of described shifting deposit unit；
Described latch cicuit includes the first transistor, the first phase inverter, the second phase inverter, the 3rd phase inverter and the 4th crystal
Pipe；The outfan of described first phase inverter electrically connects the grid of described the first transistor, and the first of described the first transistor is the most electric
Connecting the input of described second phase inverter, the second pole of described the first transistor is electrically connected the defeated of described 3rd phase inverter
Going out end and subordinate's signal output part of described shifting deposit unit, the outfan electrical connection of described second phase inverter is described 3rd anti-
The input of phase device, and the outfan of described second phase inverter is configured to the outfan of described latch cicuit, described first anti-
The input of phase device and the grid of described 4th transistor are electrically connected the latch signal input of described shifting deposit unit,
First pole of described 4th transistor electrically connects the enabling signal input of described shifting deposit unit, described 4th transistor
Second pole electrically connects the input of described second phase inverter；
Described first computing circuit includes transistor seconds, the first pull-down and the 4th phase inverter, described transistor seconds
Grid electrically connect described shifting deposit unit the first clock signal input terminal, described transistor seconds first pole electrical connection
The input of described first computing circuit, the input of described first pull-down and described 4th phase inverter is electrically connected institute
State the second pole of transistor seconds；
Described second computing circuit includes third transistor, the second pull-down and the 5th phase inverter, described third transistor
Grid electrically connect described shifting deposit unit second clock signal input part, described third transistor first pole electrical connection
The input of described second computing circuit, the input of described second pull-down and described 5th phase inverter is electrically connected institute
State the second pole of third transistor.
Shifting deposit unit the most according to claim 1, it is characterised in that also include restarting circuit, the first current potential and
Second current potential, described first current potential is high level, and described second current potential is low level；
Described restarting circuit and include the 5th transistor, the grid of described 5th transistor electrically connects the weight of described shifting deposit unit
Putting signal input part, the first pole of described 5th transistor electrically connects the outfan of described latch cicuit, described 5th transistor
Second pole electrically connect described first current potential.
Shifting deposit unit the most according to claim 2, it is characterised in that described first pull-down includes the 6th crystal
Pipe, the grid of described 6th transistor electrically connects the outfan of described second computing circuit, the first pole of described 6th transistor
Electrically connecting the second pole of described transistor seconds, the second pole of described 6th transistor electrically connects described first current potential；
Described second pull-down includes the 7th transistor, and the grid of described 7th transistor connects described shifting deposit unit
Control signal input, the first pole of described 7th transistor electrically connects the second pole of described third transistor, described 7th crystalline substance
Second pole of body pipe electrically connects described first current potential.
Shifting deposit unit the most according to claim 3, it is characterised in that described the first transistor, transistor seconds,
Three body crystalline substance pipes, the 4th body crystalline substance pipe, the 6th transistor, the 7th transistor are N-channel transistor npn npn；Described 5th transistor is P
Channel transistor.
Shifting deposit unit the most according to claim 2, it is characterised in that described first pull-down includes that the 18th is brilliant
Body pipe, the control signal input of the grid described shifting deposit unit of electrical connection of described 18th transistor, the described 18th
First pole of transistor electrically connects the second pole of described transistor seconds, and the second pole electrical connection of described 18th transistor is described
First current potential；
Described second pull-down includes the 19th transistor, and the grid of described 19th transistor electrically connects described shift LD
The control signal input of unit, the first pole of described 19th transistor electrically connects the second pole of described third transistor, institute
The second pole stating the 19th transistor electrically connects described first current potential.
Shifting deposit unit the most according to claim 5, it is characterised in that described the first transistor, transistor seconds,
Three body crystalline substance pipes, the 4th body crystalline substance pipe, the 18th transistor, the 19th transistor are N-channel transistor npn npn；Described 5th transistor
For P-channel transistor npn npn.
7. according to the shifting deposit unit described in claim 3 or 5, it is characterised in that described first phase inverter includes that the 8th is brilliant
Body pipe and the 9th transistor, the grid of described 8th transistor and the grid of described 9th transistor are connected to primary nodal point, institute
State primary nodal point and be configured to the input of described first phase inverter, the first pole electrical connection described first of described 8th transistor
Current potential, the first pole of described 9th transistor electrically connects described second current potential, the second pole of described 8th transistor and described the
Second pole of nine transistors is connected to secondary nodal point, and described secondary nodal point is configured to the outfan of described first phase inverter；
Described second phase inverter includes the tenth transistor and the 11st transistor, the grid and the described tenth of described tenth transistor
The grid of one transistor is connected to the 3rd node, and described 3rd node is configured to the input of described second phase inverter, described
First pole of the tenth transistor electrically connects described first current potential, the first described second electricity of pole electrical connection of described 11st transistor
Position, the second pole of described tenth transistor and the second pole of described 11st transistor is connected to fourth node, described Section four
Point is configured to the outfan of described second phase inverter；
Described 3rd phase inverter includes the tenth two-transistor and the 13rd transistor, the grid of described tenth two-transistor and described
The grid of the 13rd transistor is connected to the 5th node, and described 5th node is configured to the input of described 3rd phase inverter,
First pole of described tenth two-transistor electrically connects described second current potential, and the first pole electrical connection of described 13rd transistor is described
First current potential, the second pole of described tenth two-transistor and the second pole of described 13rd transistor are connected to the 6th node, institute
State the 6th node and be configured to the outfan of described 3rd phase inverter；
Described 4th phase inverter includes the 14th transistor and the 15th transistor, the grid of described 14th transistor and described
The grid of the 15th transistor is connected to the 7th node, and described 7th node is configured to the input of described 4th phase inverter,
First pole of described 14th transistor electrically connects described first current potential, and the first pole electrical connection of described 15th transistor is described
Second current potential, the second pole of described 14th transistor and the second pole of described 15th transistor are connected to the 8th node, institute
State the 8th node and be configured to the outfan of described 4th phase inverter；
Described 5th phase inverter includes the 16th transistor and the 17th transistor, the grid of described 16th transistor and described
The grid of the 17th transistor is connected to Psychotria rubra (Lour.) Poir. point, and described Psychotria rubra (Lour.) Poir. point is configured to the input of described 5th phase inverter,
First pole of described 16th transistor electrically connects described first current potential, and the first pole electrical connection of described 17th transistor is described
Second current potential, the second pole of described 16th transistor and the second pole of described 17th transistor are connected to protelum point, institute
State protelum point and be configured to the outfan of described 5th phase inverter；
Described 9th body crystalline substance pipe, the 11st transistor, the tenth two-transistor, the 15th transistor, the 17th transistor are N ditch
Road transistor npn npn；Described 8th transistor, the tenth body pipe, the 13rd body pipe, the 14th transistor, the 16th transistor are P
Channel transistor.
8. a drive circuit, it is characterised in that: include multistage shifting deposit unit as described in claim 3 or 5, upper level
The enabling signal input of shifting deposit unit described in subordinate's signal output part electrical connection next stage of described shifting deposit unit.
Drive circuit the most according to claim 8, it is characterised in that described drive circuit includes enabling signal lead-in wire, lock
Deposit signal lead, the first clock signal lead-in wire, second clock signal lead, reset signal lead-in wire, output signal lead-in wire and under
Level signal lead.
Drive circuit the most according to claim 9, it is characterised in that described drive circuit include multiple cascade as power
Profit requires the shifting deposit unit described in 3；
Adjacent three shifting deposit unit arranged in the first direction is configured to a first shift LD group, and each first
In shift LD group, the described enabling signal input electrical connection of first described shifting deposit unit in the first direction is described
Enabling signal goes between, and described latch signal input electrically connects described latch signal lead-in wire, described first clock signal input terminal
Electrically connecting described first clock signal lead-in wire, described second clock signal input part electrically connects described second clock signal lead,
Described reset signal input electrically connects described reset signal lead-in wire, described first output signal outfan, described second output
Signal output part and described control signal input electrically connect described output signal lead-in wire, and described subordinate signal output part is electrically connected
Connect described subordinate signal lead；
The described enabling signal input of second described shifting deposit unit in the first direction in each first shift LD group
End electrically connects described subordinate signal lead, and described latch signal input electrically connects described second clock signal lead, and described the
One clock signal input terminal electrically connects described latch signal lead-in wire, during described second clock signal input part electrical connection described first
Clock signal lead, described reset signal input electrically connects described reset signal lead-in wire, described first output signal outfan, institute
State the second output signal outfan and described control signal input electrically connects described output signal lead-in wire, described subordinate signal
Outfan electrically connects described subordinate signal lead；
The described enabling signal input of the 3rd described shifting deposit unit in the first direction in each first shift LD group
End electrically connects described subordinate signal lead, the described first clock signal lead-in wire of described latch signal input electrical connection, and described the
One clock signal input terminal electrically connects described second clock signal lead, and described second clock signal input part electrically connects described lock
Depositing signal lead, described reset signal input electrically connects described reset signal lead-in wire, described first output signal outfan, institute
State the second output signal outfan and described control signal input electrically connects described output signal lead-in wire, described subordinate signal
Outfan electrically connects described subordinate signal lead.
11. drive circuits according to claim 9, it is characterised in that described drive circuit include multiple cascade as power
Profit requires the shifting deposit unit described in 5 and gap signal lead-in wire；
Adjacent three shifting deposit unit arranged in the first direction is configured to a second shift LD group, and each second
In shift LD group, the described enabling signal input electrical connection of first described shifting deposit unit in the first direction is described
Enabling signal goes between, and described latch signal input electrically connects described latch signal lead-in wire, described first clock signal input terminal
Electrically connecting described first clock signal lead-in wire, described second clock signal input part electrically connects described second clock signal lead,
Described reset signal input electrically connects described reset signal lead-in wire, described first output signal outfan, described second output
Signal output part electrically connects described output signal lead-in wire, and described control signal input electrically connects described gap signal lead-in wire, institute
State subordinate's signal output part and electrically connect described subordinate signal lead；
The described enabling signal input of second described shifting deposit unit in the first direction in each second shift LD group
End electrically connects described subordinate signal lead, and described latch signal input electrically connects described second clock signal lead, and described the
One clock signal input terminal electrically connects described latch signal lead-in wire, during described second clock signal input part electrical connection described first
Clock signal lead, described reset signal input electrically connects described reset signal lead-in wire, described first output signal outfan, institute
Stating the second output signal outfan and electrically connect described output signal lead-in wire, described control signal input electrically connects described gap letter
Number lead-in wire, described subordinate signal output part electrically connects described subordinate signal lead；
The described enabling signal input of the 3rd described shifting deposit unit in the first direction in each second shift LD group
End electrically connects described subordinate signal lead, the described first clock signal lead-in wire of described latch signal input electrical connection, and described the
One clock signal input terminal electrically connects described second clock signal lead, and described second clock signal input part electrically connects described lock
Depositing signal lead, described reset signal input electrically connects described reset signal lead-in wire, described first output signal outfan, institute
Stating the second output signal outfan and electrically connect described output signal lead-in wire, described control signal input electrically connects described gap letter
Number lead-in wire, described subordinate signal output part electrically connects described subordinate signal lead；
Described gap signal lead-in wire transmission pulse signal, the high level end time of described first clock signal leads over described the
The pulse width of one described pulse signal of high level initial time of two clock signals.
12. according to the drive circuit described in claim 10 or 11, it is characterised in that described first clock signal lead-in wire transmission the
One clock signal, described second clock signal lead transmission second clock signal, described first clock signal and second clock letter
Before number within a cycle, the cycle of 1/3rd is low level current potential, and the cycle of middle 1/3rd is high level current potential,
The cycle of rear 1/3rd is low level current potential.
13. 1 kinds of display devices, including viewing area and the frame region of surrounding described viewing area, described viewing area is wrapped
Including multi-strip scanning line, a plurality of data lines and the array type pixel region surrounded by described scan line, data wire, its feature exists
In: the described frame region of at least side, described viewing area arranges the driving as described in any one in claim 8 to 12
Circuit, to control the signal output timing of described scan line.
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| CN201610487236.1A CN106169280B (en) | 2016-06-28 | 2016-06-28 | Shifting deposit unit, driving circuit and display device |
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| CN201610487236.1A CN106169280B (en) | 2016-06-28 | 2016-06-28 | Shifting deposit unit, driving circuit and display device |
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