TWI475806B - Off-chip driver - Google Patents

Description

Chip output drive circuit

The present invention relates to signal output from a chip, and more particularly to a wafer off-chip driver.

The chip output drive circuit is a buffer for the output signal of the chip, and is usually directly connected to the external pad of the chip to remove the unstable fluctuation of the output signal, so that it is smooth and stable.

1 is a circuit diagram of a conventional wafer output driving circuit. Among them, the driving signals PUD and PDD pass through inverters G3 and G4, respectively. P-channel metal oxide semiconductor field effect transistor (PM-type) and n-channel metal oxide semiconductor field effect transistor (n-channel metal oxide semiconductor field effect transistor) NM1 constitutes a driving circuit, which can control the output of inverter G3, pull the voltage DQS of the pad pad PAD to the power supply voltage VDDQ, or accept the output control of the inverter G4, and pull the voltage DQS of the wafer pad PAD. Down to ground voltage.

A problem with the wafer output drive circuit of Figure 1 is that its output is still not sufficiently stable. Please refer to FIG. 3A and FIG. 3B. FIG. 3A is an eye diagram of the output voltage of the pad voltage DQS of FIG. 1. FIG. 3B is an eye diagram of the pad voltage DQS after a load, which is not shown in the figure. As can be seen from FIG. 3B, the output voltage of the wafer output driving circuit of FIG. 1 still has significant fluctuations at the load end, which is not stable enough.

2 is a circuit diagram of another conventional wafer output drive circuit, taken from U.S. Patent No. 7,440,340. The wafer output drive circuit of FIG. 2 is comprised of drive circuits 294 and 298, wherein drive circuit 294 is identical to the wafer output drive circuit of FIG. The drive circuit 298 receives the drive signals PUD, PDD and the control signal PRMPS. Before the driving signals PUD and PDD start to operate, the control signal PRMPS is enabled in advance, causing the driving circuit 298 to pull up the voltage DQS of the wafer pad PAD in advance. This action can make the timing of the pad voltage DQS rise for the first time and the subsequent pull-up timing more consistent, so that the output voltage is more stable. Even so, the wafer output drive circuit of Figure 2 still has room for improvement.

The present invention provides a wafer output drive circuit in which the output voltage is more stable.

The present invention provides a wafer output drive circuit including a first brake inverter, a second brake inverter, and a first drive circuit. The first brake inverter includes a plurality of MOS transistors, receives the first drive signal, and inverts the first drive signal. One of the MOS transistors of the first brake inverter is always in an on state. The second brake inverter includes a plurality of MOS transistors, receives the second drive signal, and inverts the second drive signal. One of the MOS transistors of the second brake inverter is always in an on state. The first driving circuit is coupled to the first brake inverter and the second brake inverter, and pulls the voltage of the wafer pad to the first voltage or according to the output of the first brake inverter and the second brake inverter Pull down to the second voltage.

In an embodiment of the invention, the first brake inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first PMOS transistor is coupled to the first voltage and the second voltage because the first voltage and the second voltage are always in an on state. The second PMOS transistor is coupled between the first voltage and the output of the first brake inverter to receive the first driving signal. The first NMOS transistor is coupled to the output of the first brake inverter and the first PMOS transistor. The second NMOS transistor is coupled between the first NMOS transistor and the second voltage to receive the first driving signal.

In an embodiment of the invention, the second brake inverter includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The third NMOS transistor is coupled to the first voltage and the second voltage because the first voltage and the second voltage are always in an on state. The third PMOS transistor is coupled to the first voltage and receives the second driving signal. The fourth PMOS transistor is coupled between the third PMOS transistor, the third NMOS transistor, and the output of the second brake inverter. The fourth NMOS transistor is coupled between the output of the second brake inverter and the second voltage to receive the second driving signal.

The present invention further provides a wafer output driving circuit including a logic circuit and a second driving circuit in addition to the first brake inverter, the second brake inverter, and the first driving circuit. The logic circuit receives the first drive signal, the second drive signal, the first control signal, and the second control signal. The second driving circuit is coupled to the logic circuit to assist the first driving circuit to change the voltage of the wafer pad according to the output of the logic circuit.

In an embodiment of the invention, the logic circuit includes a first inverter, a second inverter, a NAND gate, and a NOR gate. The first inverter receives the first control signal. The NAND gate receives the first drive signal and the output of the first inverter and provides its output to the second drive circuit. The second inverter receives the second control signal. The inverse OR gate receives the second drive signal and the output of the second inverter and provides its output to the second drive circuit.

The first brake inverter and the second brake inverter of the present invention can make the output signal exhibit a significant brake buffering phenomenon, thereby making the output voltage of the wafer more stable.

The above described features and advantages of the present invention will be more apparent from the following description.

5 is a circuit diagram of a wafer output driving circuit in which symbols such as U, D, U1, D1, XDQ, etc., may represent circuit terminals, or voltage signals at circuit terminals, in accordance with an embodiment of the present invention. The wafer output drive circuit of FIG. 5 includes brake inverters 510, 520, drive circuits 530, 540, and logic circuit 550. The brake inverter 510 receives the drive signal UP and inverts the drive signal UP. The brake inverter 520 receives the drive signal DN and inverts the drive signal DN. The phases of the drive signals UP and DN are the same. The driving circuit 530 is coupled to the braking inverters 510 and 520, and pulls the voltage of the wafer pad XDQ to the power supply voltage VDD according to the output of the braking inverters 510 and 520, or pulls the voltage of the wafer pad XDQ to ground. Voltage. The logic circuit 550 receives the drive signals UP, DN and the control signals CTL, CTLN. The driving circuit 540 is coupled to the logic circuit 550 to assist the driving circuit 530 to change the voltage of the pad XDQ according to the output of the logic circuit 550.

The brake inverter 510 includes PMOS transistors P1, P2 and NMOS transistors N1, N2. The PMOS transistor P1 is coupled to the power supply voltage VDD and the ground voltage, and is always in an on state because the power supply voltage VDD and the ground voltage. The PMOS transistor P2 is coupled between the power supply voltage VDD and the output terminal U of the brake inverter 510 to receive the drive signal UP. The NMOS transistor N1 is coupled to the output terminal U of the brake inverter 510 and the PMOS transistor P1. The NMOS transistor N2 is coupled between the NMOS transistor N1 and the ground voltage to receive the driving signal UP.

Since the PMOS transistor P1 is always turned on, the voltage KU is equal to VDD. When the driving signal UP is logic 1, the NMOS transistors N1 and N2 are turned on, and the output voltage U of the brake inverter 510 is lowered to the ground voltage, which is equivalent to logic 0. When the drive signal UP is logic 0, the PMOS transistor P2 is turned on, causing the output voltage U of the brake inverter 510 to rise to the power supply voltage VDD, which is equivalent to logic 1.

Brake inverter 520 includes PMOS transistors P3, P4 and NMOS transistors N3, N4. The NMOS transistor N3 is coupled to the power supply voltage VDD and the ground voltage, and is always in an on state because the power supply voltage VDD and the ground voltage. The PMOS transistor P3 is coupled to the power supply voltage VDD and receives the drive signal DN. The PMOS transistor P4 is coupled between the PMOS transistor P3, the NMOS transistor N3, and the output terminal D of the brake inverter 520. The NMOS transistor N4 is coupled between the output terminal D of the brake inverter 520 and the ground voltage, and receives the driving signal DN.

Since the NMOS transistor N3 is always turned on, the voltage KD is equal to the ground voltage. When the drive signal DN is logic 1, the NMOS transistor N4 is turned on, causing the output voltage D of the brake inverter 520 to drop to the ground voltage, which is equivalent to a logic zero. When the drive signal DN is logic 0, the PMOS transistors P3 and P4 are turned on, and the output voltage D of the brake inverter 520 is raised to the power supply voltage VDD, which is equivalent to logic 1.

The driving circuit 530 includes a PMOS transistor P5 and an NMOS transistor N5. The PMOS transistor P5 is coupled between the power supply voltage VDD, the output terminal U of the brake inverter 510, and the die pad XDQ. If the output voltage U of the brake inverter 510 is logic 0, P5 is turned on, and the voltage of the pad XDQ is pulled up to the power supply voltage VDD. The NMOS transistor N5 is coupled between the ground voltage, the output terminal D of the brake inverter 520, and the pad XDQ. If the output voltage D of the brake inverter 520 is logic 1, N5 is turned on, and the voltage of the pad XDQ is pulled down to the ground voltage.

Logic circuit 550 includes inverters I1, I2, inverse gate G1, and inverse gate G2. The inverter I1 receives the control signal CTLN. The gate G1 receives the drive signal UP and the output of the inverter I1, and supplies its output to the PMOS transistor P6 of the drive circuit 540. The inverter I2 receives the control signal CTL. The inverse OR gate G2 receives the output of the drive signal DN and the inverter I2 and supplies its output to the NMOS transistor N6 of the drive circuit 540. The control signal CTL is opposite in phase to the CTLN.

The driving circuit 540 includes a PMOS transistor P6 and an NMOS transistor N6. The PMOS transistor P6 is coupled between the power supply voltage VDD, the output terminal U1 of the logic circuit 550, and the pad XDQ, and assists the driving circuit 530 to pull up the voltage of the pad XDQ according to the output voltage U1 of the gate G1. The NMOS transistor N6 is coupled between the ground voltage, the other output terminal D1 of the logic circuit 550 and the pad XDQ, and assists the driving circuit 530 to lower the voltage of the pad XDQ according to the output voltage D1 of the inverse gate G2.

The operational principles of logic circuit 550 and driver circuit 540 are the same as those of driver circuit 298 of Figure 2 (U.S. Patent No. 7,440,340). The roles of the control signals CTL and CTLN are the same as the control signal PRMPS of FIG. Therefore, the details of the logic circuit 550 and the drive circuit 540 will not be described.

4A is an eye diagram of the pad output driving circuit of FIG. 5 in which the pad voltage XDQ. 4B is an eye diagram of the wafer output driving circuit of FIG. 5 in which the pad voltage XDQ is loaded. Due to the MOS transistors P1, N1 of the brake inverter 510 and the MOS transistors N3, P4 of the brake inverter 520, the voltage of the drive circuit 530 outputted to the pad XDQ will appear as shown in part 401 of FIG. 4A. Brake buffering, which is a significant change in the 401 part. This brake buffer allows the pad XDQ to be more stable after loading. Comparing the conventional signal waveform of FIG. 3B with the signal waveform of FIG. 4B, it is apparent that the load terminal output voltage of the present embodiment is more stable than the conventional load terminal output voltage, which is the efficiency of the brake inverters 510 and 520.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

294,298. . . Drive circuit

401. . . Voltage signal waveform

510, 520. . . Brake inverter

530, 540. . . Drive circuit

550. . . Logic circuit

CTL, CTLN, PRMPS. . . control signal

DQS. . . Voltage signal

G1-G9. . . Logic gate

I1, I2. . . inverter

KU, KD, U, D, U1, D1. . . Circuit end point / voltage signal

N1-N6, NM1, NM2. . . NMOS transistor

P1-P6, PM1, PM2. . . PMOS transistor

PE9. . . Circuit end point

PAD, XDQ. . . Wafer pad

PUD, PDD. . . Drive signal

VDD, VDDQ. . . voltage

UP, DN. . . Drive signal

1 and 2 are circuit diagrams of a conventional wafer output driving circuit.

3A and 3B are signal eye diagrams of the wafer output driving circuit of Fig. 1.

4A and 4B are signal eye diagrams of a wafer output driving circuit in accordance with an embodiment of the present invention.

FIG. 5 is a circuit diagram of a wafer output driving circuit in accordance with an embodiment of the present invention.

510, 520. . . Brake inverter

530, 540. . . Drive circuit

550. . . Logic circuit

CTL, CTLN. . . control signal

G1, G2. . . Logic gate

I1, I2. . . inverter

KU, KD, U, D, U1, D1. . . Circuit end point / voltage signal

N1-N6. . . NMOS transistor

P1-P6. . . PMOS transistor

VDD. . . voltage

UP, DN. . . Drive signal

XDQ. . . Wafer pad

Claims (12)

A chip output driving circuit comprising: a first brake inverter, receiving a first driving signal, and inverting the first driving signal; and a second braking inverter comprising a plurality of MOS transistors, receiving one a second driving signal, the second driving signal is inverted and outputted, one of the MOS transistors of the second braking inverter is always in an on state; and a driving circuit coupled to the first braking inverter and the a second brake inverter, according to the output of the first brake inverter and the second brake inverter, pulling a voltage of a pad of a wafer to a first voltage or pulling down to a second voltage The first brake inverter includes: a first PMOS transistor, the gate of which is coupled to the second voltage, and one of the remaining two poles is coupled to the first voltage, because the first voltage is higher than the second The voltage is always in a conducting state; a second PMOS transistor coupled between the first voltage and the output of the first brake inverter receives the first driving signal; a first NMOS transistor coupled Connecting the output of the first brake inverter to the first PMOS And a second NMOS transistor coupled between the first NMOS transistor and the second voltage to receive the first driving signal. The chip output driving circuit of claim 1, wherein the second brake inverter comprises: a third NMOS transistor, the gate is coupled to the first voltage, and one of the remaining two poles is coupled to the Second voltage because the first voltage is higher than the first The second PMOS transistor is coupled to the first voltage to receive the second driving signal, and the fourth PMOS transistor is coupled to the third PMOS transistor and the third NMOS. a transistor, and an output of the second brake inverter; and a fourth NMOS transistor coupled between the output of the second brake inverter and the second voltage, receiving the second Drive signal. The chip output driving circuit of claim 1, wherein the driving circuit comprises: a fifth PMOS transistor coupled to the first voltage, an output end of the first braking inverter, and the soldering Between the pads, the voltage of the pad is pulled up to the first voltage according to the output of the first brake inverter; and a fifth NMOS transistor coupled to the second voltage and the second brake The output of the phase comparator and the pad are pulled down to the second voltage according to the output of the second brake inverter. The wafer output driving circuit of claim 1, wherein the first driving signal and the second driving signal have the same phase. A chip output driving circuit comprising: a first brake inverter comprising a plurality of MOS transistors, receiving a first driving signal, inverting and outputting the first driving signal, and MOS of the first braking inverter One of the crystals is always in an on state; a second brake inverter includes a plurality of MOS transistors, receives a second drive signal, and inverts the second drive signal, the second brake One of the MOS transistors of the inverter is always in an on state; a first driving circuit is coupled to the first brake inverter and the second brake inverter, according to the first brake inverter and the first The output of the two brake inverters pulls the voltage of a pad of a wafer to a first voltage or to a second voltage; a logic circuit receives the first driving signal, the second driving signal, a first control signal and a second control signal; and a second driving circuit coupled to the logic circuit to assist the first driving circuit to change a voltage of the pad according to an output of the logic circuit. The chip output driving circuit of claim 5, wherein the first brake inverter comprises: a first PMOS transistor, the gate of which is coupled to the second voltage, and one of the remaining two poles is coupled to the The first voltage is always in an on state because the first voltage is higher than the second voltage; a second PMOS transistor is coupled between the first voltage and the output of the first brake inverter, and receives a first NMOS transistor coupled to the output of the first brake inverter and the first PMOS transistor; and a second NMOS transistor coupled to the first NMOS transistor The first drive signal is received between the second voltage. The chip output driving circuit of claim 5, wherein the second brake inverter comprises: a third NMOS transistor, the gate of which is coupled to the first voltage, and one of the remaining two poles is coupled to the Second voltage because the first voltage is higher than the first The second PMOS transistor is coupled to the first voltage to receive the second driving signal, and the fourth PMOS transistor is coupled to the third PMOS transistor and the third NMOS. a transistor, and an output of the second brake inverter; and a fourth NMOS transistor coupled between the output of the second brake inverter and the second voltage, receiving the second Drive signal. The chip output driving circuit of claim 5, wherein the first driving circuit comprises: a fifth PMOS transistor coupled to the first voltage, an output end of the first braking inverter, and Between the pads, the voltage of the pad is raised to the first voltage according to the output of the first brake inverter; and a fifth NMOS transistor coupled to the second voltage, the second The output of the brake inverter and the pad are pulled down to the second voltage according to the output of the second brake inverter. The chip output driving circuit of claim 5, wherein the second driving circuit comprises: a sixth PMOS transistor coupled between the first voltage, the logic circuit, and the pad, according to The output of the logic circuit assists the first driving circuit to raise the voltage of the pad; and a sixth NMOS transistor coupled between the second voltage, the logic circuit, and the pad, according to the logic The output of the circuit assists the first drive circuit in pulling down the voltage of the pad. The chip output drive circuit of claim 5, wherein the logic circuit comprises: a first inverter receiving the first control signal; a reverse gate, receiving the first drive signal and the first An output of the inverter and providing an output thereof to the second driving circuit; a second inverter receiving the second control signal; and an inverse OR gate receiving the second driving signal and the second inverter The output and provide its output to the second drive circuit. The wafer output driving circuit of claim 5, wherein the first driving signal and the second driving signal have the same phase. The wafer output driving circuit of claim 5, wherein the first control signal is opposite in phase to the second control signal.