1317021 九、發明說明： 【發明所屬之技術領域】 本發明係有_掃_試裝置，尤指—種包括一婦描 測解元及-標準連接介面，標準連接介面分麟該掃描 測4單70及-電子裝置之另—標準連接介面相連接，藉以 對該電子裝置之内部树進行除錯或更新者。 【先前技術】 習知-般基板測試之方式，大都由基板之表面，利用 探針法來進行所謂「插人式電路測試化⑽也㈣， ft稱㈣」，以得知元件之功能正常與否，然而，隨著電 腦及各種資訊產品之生產技術不斷的推陳㈣，加上現今 電子資訊產品之設計導向均细_短小為趨勢，使得各 種電子產品之内部以及電路板上所裝設之晶片及元件的 數量與密度均快速提高，導致安裝各組件之腳端的節距， 已逐漸小於測期探針之節距，因此’習知之插入式電路 測試之方法即無法滿足現今之需求。 因此，另-麵之為rJTAG (即所謂邊界掃描測試： Boundary Scan Test)」的測試方式即因應而生，而所謂 JTAG之職方法，係依序掃描積體電路元件之全部外界輸 入輸出腳端’擷取輸人輸出端之測試數據，細元: 内部之功能’而-般使用之測試方式，係可針對元 件之誤插接、外界電路與元件間之輸人/輸出信號監視、 元件間之互翻試，以及_邏輯電路之魏測試，不僅 測試方便’且由於制狱度快’故深受各製造廠商所歡 1317021 迎’此外’經由外界電腦主機即可進行JTAG、測試，在使 用上極具彈性。 而目别開發中的晶片或微處理器均具有JTAG介面， 以供用以進行_或除錯，然而，當該等晶片或微處理器 在研發完成後，通常該皿介面即再無機會進行使用， 制是體雜薄則、的電子產品，要進行愿測試即需 拆除外破，並在JTAG之訊號線上加焊連接介面後，方能 進行細、除錯或更_觀式，不僅相當不便，且往往 • 觸電子產品造成破壞’因此’便有業相發出-種「具 _之JTAG除錯介面（Debugging⑽咐咖）」，該除錯 介面係具有USB (Universal Serial Bus，萬用串列匯流 埠）連接埠及一控制晶片，藉由該USB連接埠連接在一電 +產αα上，即可以該控制晶片快速地對該電子產品進行除 錯和程式燒錄，由於方便且即具彈性，深受電子產品相關 之使用者及工作者所歡迎。 φ 此外，對於另一種對於「晶片系統」 (System-On-Chip，簡稱S0C)之測試，亦遭遇與上述JTAG 測4相同之問題，即一般的晶片系統上雖均設有一通用非 同步收發傳輸（Universal Asynchronous Receiver /1317021 IX. Description of the invention: [Technical field to which the invention pertains] The present invention has a _scan_test device, especially a type including a female descriptive solution and a standard connection interface, and a standard connection interface. 70 and - the electronic device is connected to the standard connection interface, whereby the internal tree of the electronic device is debugged or updated. [Prior Art] Conventionally, the method of substrate testing is mostly performed on the surface of the substrate by the probe method. The so-called "plug-in circuit test (10) is also (4), ft (4)" to know that the function of the device is normal. No, however, with the continuous development of the production technology of computers and various information products (4), and the design orientation of today's electronic information products are thin and short, the interior of various electronic products and the boards are installed. The number and density of wafers and components are rapidly increasing, resulting in the pitch of the foot ends of the mounted components, which has gradually become smaller than the pitch of the probes. Therefore, the conventional plug-in circuit test method cannot meet the needs of today. Therefore, the test method of the other side is rJTAG (so-called Boundary Scan Test), and the so-called JTAG job method is to sequentially scan all external input and output terminals of the integrated circuit components. 'Retrieve the test data of the output of the input, the element: the internal function' and the general test method, which can be used for the error insertion of the component, the input/output signal monitoring between the external circuit and the component, and the component The mutual test, and the _ logic circuit Wei test, not only the test is convenient 'and because of the fast prisoner', so it is well received by various manufacturers, 13170021 welcoming 'in addition' through the external computer host can JTAG, test, in use Extremely flexible. The chip or microprocessor under development has a JTAG interface for _ or debugging. However, when the chip or microprocessor is developed, the device interface usually has no chance to be used. The system is a thin electronic product. If you want to test it, you need to dismantle it and add a soldering interface on the JTAG signal line before you can fine-tune, debug or _view. It is not only inconvenient. And often • Touching electronic products causing damage 'so that's there is a kind of industry--"JTAG debugging interface (Debugging (10) 咐 ))", the debugging interface has USB (Universal Serial Bus) The connection port and the control chip are connected to an electric device by means of the USB port, so that the control chip can quickly debug and program the electronic product, which is convenient and flexible. It is very popular among users and workers related to electronic products. φ In addition, for another test of "System-On-Chip" (S0C), the same problem as the above JTAG test 4 is encountered, that is, a general non-synchronous transmission and transmission is provided on a general wafer system. (Universal Asynchronous Receiver /
Transmitter)介面，以輔助軟體開發人員在進行程式除 錯時輸出除錯訊息，但當該晶片系統進入量產階段後，為 避免佔用空間，該通用非同步收發傳輸介面即不再保留， 右要再進行除錯或韌體更新，即需拆除產品外殼，惟，前 述具USB之JTAG除錯介面雖可解決JTAG之測試問題，但 1317021 卻無法對於晶片系統進行除錯，且由於前述具哪之 ’ 除錯介面的價格過於昂貴，亦令消費者望之卻步，因為當 -產品需花費昂貴之代_得時’該產品即需具有極優異 之功能’方能提高消費者之蹲買意願，因此，如何使用最 低成本以解決上述問題，即成為相關製造商之一大挑戰。 【發明内容】 有鑑於前述使用JTAG之測試方法，成本過於昂貴及 無法對晶片系統進行測試等諸多缺失，發明人經過長久努 _ 力研究與實驗，終於開發設計出本發明之一種掃描測試裝 置，以期降低所需之成本，並藉以提供更多測試功能。 本發明之一目的，係提供一種掃描測試裝置，該掃描 測試裝置係設有一掃描測試單元，該掃描測試單元係設有 一訊號傳輸部，該訊號傳輸部係與該掃描測試裝置内所設 之一標準連接介面相連接，而該標準連接介面係另與一電 子裝置相連接，藉該標準連接介面，該掃描測試單元與該 _ 電子裝置之内部元件間，係可傳送邊界掃描測試數據或晶 片系統測試數據，以對該電子裝置之内部元件進行偵測、 除錯或更新等動作。 為便貴審查委員能對本發明之目的、技術特徵及其 功效，做更進一步之認識與瞭解，茲舉實施例配合圖式， 詳細說明如下： 【實施方式】 本發明係一種掃描測試裝置，請參閱第丨圖所示，係 由一掃描測試單元2及一標準連接介面4所組成，其中該 掃插測試單元？在Μ 面4之，mf抑铺鮮連接介 介面50連接，該標準，置5上所設之另一標準連接 輪部21相接，如此%由二面4之另一侧則與該訊號傳 單元2與該電子裝置5曰之内^票準連接介面4 ’該掃描測試 挪試數據^“^_^_’係可進行邊界掃描 進杆仙 叙傳輸，㈣該電子裝置5 進仃偵洌、除錯或更新等動作。 在本發明之-實施例中，復請參 係包括一第一測試模組23及一第二測試： ’、中該第-測試模組23係供產生該邊界掃描測試 +用以對該電子裝置5進行邊界掃描測試，該邊界掃 為測4數據至少包括一輸入訊號、一時脈訊號、一操作訊 號及一重置訊號，而該第二測試模組25係供產生該晶片 系統測試數據，用以對該電子裝置5進行晶片系統測試， 該晶片系統測試數據至少包括另一輪入訊號。 在該實施例中’請參閱第2圖所示’該訊號傳輸部21 係包括一測試訊號輸入腳211、一測試訊號輸出腳212、 一時脈訊號傳輸腳213、一測試模式控制聊214及一重置 訊號傳輸腳215，其中該測試訊號輸入腳211係可傳送該 輸入訊號或該另一輸入訊號到該標準連接介面4，該測試 訊號輪出腳212係可接收自該標準連接介面4所傳輸之一 輸出訊號或另一輸出訊號，該時脈訊號傳輸腳213係可傳 送該時脈訊號到該標準連接介面4’該測試模式控制腳214 係可傳送該操作訊號到該標準連接介面4 ’而該重置訊號 1317021 傳輸腳215可傳送該重置訊號到該標準連接介面4，如此， 經由該訊號傳輪部21及標準連接介面4傳賴等訊號， 即可對該電子褒置5進行酬、除錯或更新等動作。 在該實施例巾’復請參料2 _示，該標準連接介 面4之「側係設有一命令訊號傳輸端4()，該命令訊號傳輸 端40係可接收該測試訊號輪入腳211傳送的該輸入訊號 或该另-輸人訊號’並傳送觸另-鮮連接介面5〇上 所設之方Transmitter) interface to help the software developer to output debug information when debugging the program. However, when the wafer system enters the mass production stage, in order to avoid taking up space, the universal asynchronous transmission and transmission interface is no longer reserved. To debug or firmware update, the product housing needs to be removed. However, the aforementioned JTAG debug interface with USB can solve the JTAG test problem, but 1317021 can't debug the chip system, and because of the above. The price of the debug interface is too expensive, and it is also prohibitive for consumers, because when the product needs to be expensive, the product needs to have excellent functions to enhance the consumer’s willingness to buy. How to use the lowest cost to solve the above problems, that is, become a big challenge for related manufacturers. SUMMARY OF THE INVENTION In view of the foregoing test methods using JTAG, the cost is too expensive and the wafer system cannot be tested, and the inventors have finally developed and designed a scanning test device according to the long-term research and experiment. In order to reduce the cost required, and to provide more testing capabilities. An object of the present invention is to provide a scan test device, which is provided with a scan test unit, the scan test unit is provided with a signal transmission unit, and the signal transmission unit is provided with one of the scan test devices. The standard connection interface is connected, and the standard connection interface is further connected to an electronic device. The standard connection interface, the scan test unit and the internal components of the electronic device can transmit boundary scan test data or a wafer system. Test data to detect, debug, or update internal components of the electronic device. For the purpose of the present invention, the present invention is a scanning test device, please provide a further understanding and understanding of the object, technical features and effects of the present invention. Referring to the figure, it consists of a scan test unit 2 and a standard connection interface 4, wherein the scan test unit? In the face 4, the mf suppresses the fresh connection interface 50, and the standard, another standard connection wheel portion 21 provided on the 5 is connected, so that the other side of the two sides 4 is connected to the signal leaflet. The element 2 is connected to the electronic device 5 ^ 准 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 In the embodiment of the present invention, the reference parameter includes a first test module 23 and a second test: ', the first test module 23 is for generating the boundary The scan test is used to perform a boundary scan test on the electronic device 5, and the boundary scan data includes at least one input signal, one clock signal, one operation signal and one reset signal, and the second test module 25 is Providing the wafer system test data for performing a wafer system test on the electronic device 5, the wafer system test data including at least another round-in signal. In this embodiment, 'Please refer to FIG. 2' for the signal transmission portion 21 series includes a test signal input pin 211, a test message The output pin 212, a clock signal transmission pin 213, a test mode control chat 214, and a reset signal transmission pin 215, wherein the test signal input pin 211 can transmit the input signal or the other input signal to the standard connection interface. 4. The test signal wheel 212 can receive one of the output signals or another output signal transmitted from the standard connection interface 4, and the clock signal transmission pin 213 can transmit the clock signal to the standard connection interface 4. 'The test mode control pin 214 can transmit the operation signal to the standard connection interface 4' and the reset signal 1317021 transmission pin 215 can transmit the reset signal to the standard connection interface 4, and thus, via the signal transmission part 21 and the standard connection interface 4 pass the signal, etc., and the electronic device 5 can be compensated, debugged or updated. In the embodiment, the towel 'receives the reference 2 _, the standard connection interface 4 The side signal is provided with a command signal transmitting end 4 (), and the command signal transmitting end 40 can receive the input signal or the other input signal transmitted by the test signal wheel 211 and transmit the touch-and-fresh connection interface 5 Provided on the side of
〒7汛現得輸端，使該輸入訊號或該另一輸入 訊號被傳蝴該t子裝置5 _職4树，以對該電 子裝置5進行除錯或偵測等動作。 在該實施例巾’復請㈣第2 _示，該鮮連接介 面4之一侧係設有一第一資料傳輸端42，該第-資料傳輸 端42係與該另―標準連接介面50上所設之另—第一資料 =輸端連接，供魏魏子裝置5内之各元件所傳送之該 ^出訊號或4另-輸出訊號，並經該測試訊號輸出腳犯 該掃描測試單元2，即可得知對該電子裳置5進行 偵測或除錯之結果。 在对關巾’輯參_ 2圖獅，鋪準連接介 端44 ^健有巧脈訊號傳輪端44，該時脈訊號傳輸 傳幹端準連接介面5G上所設之另—時脈訊號 可=，該時脈訊號傳輸聊213傳送的該時脈訊號即 、、：觀號傳輸端44,被傳送到該電子裝置5内所設 錄之^早元，錢正職子裝置5内之―計時單元所記 9 1317021 在該實施例中’復請參閱第2圖所示，該標準連接介 面4之-侧係没有―第二資料傳輸端46，該第二資料傳輸 端46係與該另-標準連接介㈣上所設之另—第二資料 傳輸端相連接，該測試模式控_ 214傳送的該操作訊號 即可經該第—資料傳輸端46，被傳送到該電子裝置 ==各元件，該電子裝置5内之各元件即產生不同的動 作織’減’即可在各個«下藉由傳賴等輸入訊號 以進行偵測。 在該實施例中，復請參閱第2圖所示，該標準連接介 =4之-側係設有一第三資料傳輸端仙，該第三資料傳輸 係與該另—標準連接介面5G上所設之另-第三資料 =輸端j接’該重置訊號傳輸腳215傳送的該重置訊 二==:::=所設之各元件，《解除 r py之各兀件不同的動作狀態。 在該實施例中，復請參閱第2圖所ς，該標準連接介 =尚設有-接地端49，該接地端49係與該另一標準連 所設之另―接地端相連接。藉上揭結構，即可 職模組23與該標準連接介面4，對該電子裝 =邊界掃描職，而該第二戦模組沾係可產生 -另-輸人訊號並傳送到該標準連接介面4，又可接收該 輪^=號’觸^馳25 _該測試訊號 傳腳2U及測試訊繼腳212，作為通細步收發 frrrSal ASynChr〇n〇US Recei- / fitter) 車，對該電子裝置5内之晶片系統汛7汛 The input end is such that the input signal or the other input signal is transmitted to the t-device 5 _ job 4 tree to perform debugging or detection of the electronic device 5. In the embodiment, the second embodiment of the fresh connection interface 4 is provided with a first data transmission end 42, and the first data transmission end 42 is connected to the other standard connection interface 50. In addition, the first data = the connection of the terminal, the signal to be transmitted by the components in the Weiweizi device 5 or the signal of the other signal, and the scan test unit 2 is executed by the test signal output pin. The result of detecting or debugging the electronic skirt 5 can be known. In the pair of 巾 ' 辑 _ 2 图 , , , , , , , ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Yes, the clock signal transmitted by the clock signal transmission chat 213, that is, the observation number transmission end 44, is transmitted to the early date of the electronic device 5, and the money is in the sub-device 5 9 1317021 in the timing unit. In the embodiment, as shown in FIG. 2, the side of the standard connection interface 4 has no "second data transmission end 46", and the second data transmission end 46 is associated with the other. - the second data transmission end connected to the standard connection medium (4) is connected, and the operation signal transmitted by the test mode control 214 can be transmitted to the electronic device via the first data transmission terminal 46. The components, the components in the electronic device 5, which generate different motions, can be detected by inputting signals under the respective signals. In this embodiment, as shown in FIG. 2, the standard connection interface 4 is provided with a third data transmission terminal, and the third data transmission system is connected to the other standard connection interface 5G. The other-third data = the input terminal j is connected to the reset signal transmission pin 215, the reset signal 2 ==:::= each component is set, "the action of releasing the different components of r py" status. In this embodiment, referring to Fig. 2, the standard connection is still provided with a ground terminal 49 which is connected to another ground terminal of the other standard connection. By means of the uncovering structure, the service module 23 and the standard connection interface 4, the electronic device = boundary scan job, and the second UI module can generate - another - input signal and transmit to the standard connection The interface 4 can also receive the round ^= number 'touch 25 25 _ the test signal transmitter 2U and the test relay foot 212, as a fine-step transceiving frrrSal ASynChr〇n〇US Recei- / fitter) car, Wafer system in electronic device 5
1317021 此’即1棚對該電子裝置5進行其内各元件之誤插接測 武’外1電路與70件H/輪出信號監視，s件間之 互接測試，以及_電路之魏職等目的。 在該實施例中，復請參閱第1圖所示，該等桿準連接 介面4、50係可為—SD(SerialData)介面，亦可為一 安全數位輸出人（Serial Data Input/Gutput)介面而 該電子裝置5係可為具有該SD介面或該安全數位輸出入 介面之—行動電話’或—個人數位助理器（⑽⑽1317021 This is the '1 shed' for the electronic device 5 to carry out the mis-plugging of the various components in the internal control of the 'outside 1 circuit and 70 pieces of H / wheel out signal monitoring, s inter-connected test, and _ circuit of the Wei Wait for the purpose. In this embodiment, as shown in FIG. 1 , the quasi-connecting interfaces 4 and 50 can be an SD (SerialData) interface or a Serial Data Input/Gutput interface. The electronic device 5 can be a mobile phone having the SD interface or the secure digital input/output interface or a personal digital assistant ((10)(10)
Digital ASSistant ’簡稱舰），如此，藉該標準連接介 面4及另-鮮連接介面5()，即謂該電子裝置 JTAG及S0C之測試方法，不僅成本低廉，並擴大 試裝置之測試觀。 _ 按，以上所述，僅為本發明最佳之一具體實施例，惟 本發明之構造概料舰於此，任何熟悉該項技藐者在 本發明領域内，可輕易思及之變化或修飾，皆可涵i在以 下本案之專利範圍。 【圖式簡單說明】 第1圖係本發明之掃描測試裝置示意圖；及 第2圖係本發明之掃描測試裝置電路 【主要元件符號說明】 掃描測試單元.........2 測試訊號輸入腳......211 時脈訊號傳輸腳......213 重置訊號傳輸腳......215 訊號傳輸部............21 测試訊號輸出腳......212 测試模式控制腳......214 π ................23 1317021 第二測試模組.........25 標準連接介面 4 命令訊號傳輸端……40 第一資料傳輸端……42 時脈訊號傳輸端......44 第二資料傳輸端 46 第三資料傳輸端……48 接地端..................49 電子裝置...............5 另一標準連接介面…50Digital ASSistant is referred to as the ship. Thus, by using the standard connection interface 4 and the other-fresh connection interface 5 (), the test methods of the electronic devices JTAG and S0C are not only low in cost, but also expand the test concept of the test device. _, as described above, is only one of the best embodiments of the present invention, but the structure of the present invention is hereby known, and anyone skilled in the art can easily think of changes or Modifications can be made in the following patent scope of this case. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a scanning test apparatus of the present invention; and FIG. 2 is a circuit of a scanning test apparatus of the present invention. [Main component symbol description] Scanning test unit... 2 Test Signal input pin...211 Clock signal transmission pin...213 Reset signal transmission pin...215 Signal transmission unit............21 Test signal output pin...212 Test mode control pin...214 π ................23 1317021 Second test module.. .......25 standard connection interface 4 command signal transmission end ... 40 first data transmission end ... 42 clock signal transmission end ... 44 second data transmission end 46 third data transmission end ...48 Ground terminal..................49 Electronic device...............5 Another standard connection interface...50
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