CN101339228A - Scanning tester - Google Patents
Scanning tester Download PDFInfo
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- CN101339228A CN101339228A CNA2007100289685A CN200710028968A CN101339228A CN 101339228 A CN101339228 A CN 101339228A CN A2007100289685 A CNA2007100289685 A CN A2007100289685A CN 200710028968 A CN200710028968 A CN 200710028968A CN 101339228 A CN101339228 A CN 101339228A
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Abstract
The invention discloses a scan test device which comprises a scan test unit and a standard connecting interface. One side of the standard connecting interface comprises at least a command signal transmission terminal, a first data transmission terminal and a second data transmission terminal. The scan test unit is connected with the other side of the standard connecting interface via a signal transmission part arranged on the scan test unit. In addition, the scan test unit transmits boundary scan test data via the command signal transmission terminal, the first data transmission terminal and the second data transmission terminal or transmits chip system test data via the command signal transmission terminal and the first data transmission terminal so that the scan test unit can perform actions of detecting, debugging or updating, and the like for an electric device.
Description
Technical field
The invention relates to a kind of proving installation, refer to a kind of scanning tester that the inside components and parts of electronic installation is carried out debug or renewal especially.
Background technology
The mode of previous general tester substrate, mostly by the surface of substrate, utilize sonde method to carry out what is called " plug-in circuit test (in-Circuit Test; be called for short ICE) ", with the function of learning components and parts normally whether, yet, along with the production technology of computing machine and various information products is constantly weeded out the old and bring forth the new, add that the shaping-orientation of electronics and IT products all is to be trend with compact now, make the chip installed on the inside of various electronic products and the circuit board and the quantity and the density of components and parts all improve fast, cause installing the pitch of the foot of each components and parts, gradually less than the pitch of detecting probe, therefore, the method for previous plug-in circuit test promptly can't satisfy demand now.
Therefore, another kind be referred to as " JTAG (and be so-called boundary scan testing: Boundary Scan Test) " test mode promptly in response to and give birth to, and the method for testing of so-called JTAG, it is the whole extraneous input and output foot of scan IC components and parts in regular turn, the test data of acquisition input/output terminal, and then the function of test components and parts inside, and generally use the test mode of JTAG, be to connect at mispluging of components and parts, input/output signal between external circuitry and components and parts monitors, mutual connection test between components and parts, and the functional test of internal logic circuit, convenient test not only, and because its test speed is fast, thus welcome by each manufacturer deeply, in addition, can carry out jtag test via extraneous main frame, have elasticity in the use.
And chip or microprocessor in the exploitation at present all have jtag interface, for in order to detect or debug, yet, when this described chip or microprocessor after research and development are finished, common this jtag interface does not promptly have chance again to be used, the compact electronic product of volume particularly, carry out jtag test and promptly need remove shell, and the signal of JTAG online add the weldering connecting interface after, can detect, debug or renewal firmware program, not only quite inconvenience, and often this electronic product is damaged, therefore, just have the dealer to develop a kind of " the JTAG debug interface (Debugging Interface) of tool USB ", this debug interface is to have USB (Universal Serial Bus, universal serial) connectivity port and a control chip are connected on the electronic product by this usb connecting port, promptly can carry out debug and burning program to this electronic product apace by this control chip, owing to making things convenient for and being tool elasticity, welcome by electronic product relevant user and worker.
In addition, for another kind for " chip system " (System-On-Chip, abbreviation SOC) test, also meet with the problem identical with above-mentioned jtag test, though be to be equipped with universal asynchronous receiving-transmitting transmission (Universal Asynchronous Receiver/Transmitter) interface on the general chip system, when carrying out program debugging, export debugging information with the assisting software development personnel, but when this chip system enters volume production after the stage, for avoiding taking up room, this universal asynchronous receiving-transmitting transmission interface promptly no longer keeps, if debug or firmware update will be carried out again, promptly need remove product casing.Though the JTAG debug interface of aforementioned tool USB can solve the test problem of JTAG, but can't carry out debug for chip system, and because the price of the JTAG debug interface of aforementioned tool USB is too expensive, the stepping back that also makes the consumer hope is because when a product needed the cost of both expensive to buy, this product promptly need have extremely excellent function, can improve consumer's purchase intention, therefore, how to use least cost, promptly become a major challenge of relevant manufacturer to address the above problem.
Summary of the invention
Because the method for testing of aforementioned use JTAG, cost is too expensive and can't many disappearances such as test to chip system, the inventor is through the permanent research and experiment of making great efforts, finally development and Design goes out a kind of scanning tester of the present invention, in the hope of reducing required cost, and provide more test functions whereby.
A purpose of the present invention, be to provide a kind of scanning tester, and this scanning tester is provided with the one scan test cell, on this scan test cell, be provided with a signal transport part, this signal transport part is connected with the interior set standard connecting interface of this scanning tester, and this standard connecting interface is to be connected with an electronic installation in addition, by this standard connecting interface, between the inside components and parts of this scan test cell and this electronic installation, be to transmit boundary scan testing data or chip system test data, detect with inside components and parts to this electronic installation, action such as debug or renewal.
By of the present invention, can test chip system very easily, and should test simply, test speed is fast, and cost is lower, in addition, also can provide multiple test function.
Description of drawings
Fig. 1 is a scanning tester synoptic diagram of the present invention;
Fig. 2 is a scanning tester circuit diagram of the present invention.
Embodiment
The present invention is a kind of scanning tester, see also shown in Figure 1, it is formed by an one scan test cell 2 and a standard connecting interface 4, wherein this scan test cell 2 is provided with a signal transport part 21, and a side of this standard connecting interface 4 for an electronic installation 5 on being connected of set another standard connecting interface 50, the opposite side of this standard connecting interface 4 then joins with this signal transport part 21, so, by this standard connecting interface 4, between the inside components and parts of described scan test cell 2 and electronic installation 5, be the transmission that to carry out boundary scan testing data or chip system test data, so that described electronic installation 5 is detected, action such as debug or renewal.
In one embodiment of this invention, see also shown in Figure 1, described scan test cell 2 is to comprise one first test module 23 and one second test module 25, wherein said first test module 23 provides and produces the boundary scan testing data, in order to described electronic installation 5 is carried out boundary scan testing, described boundary scan testing data comprise an input signal at least, one frequency signal, one operation signal and a reset signal, and described second test module 25 is for producing described chip system test data, in order to described electronic installation 5 is carried out the chip system test, described chip system test data comprises another input signal at least.
In this embodiment, see also shown in Figure 2, described signal transport part 21 comprises a test signal input pin 211, one test signal output pin 212, one frequency signal transmission pin 213, one test pattern control pin 214 and reset signal transmission pin 215, wherein said test signal input pin 211 is can transmit this input signal or another input signal to described standard connecting interface 4, described test signal output pin 212 is to be received from an output signal or another output signal that this standard connecting interface 4 is transmitted, described frequency signal transmission pin 213 is can transmit described frequency signal to described standard connecting interface 4, described test pattern control pin 214 is can transmit this operation signal to this described standard connecting interface 4, and this described reset signal transmission pin 215 can transmit this reset signal to described standard connecting interface 4, so, transmit these signals via described signal transport part 21 and standard connecting interface 4, can detect this described electronic installation 5, action such as debug or renewal.
In this embodiment, please consult shown in Fig. 2 again, one side of described standard connecting interface 4 is to be provided with a command signal transmission ends 40, this command signal transmission ends 40 is to receive input signal or another input signal that this test signal input pin 211 transmits, and be sent to another set on described another standard connecting interface 50 command signal transmission ends, make this described input signal or another input signal be sent to each set components and parts of described electronic installation 5 inside, so that this described electronic installation 5 is carried out actions such as debug or detecting.
In this embodiment, see also shown in Fig. 2, one side of this described standard connecting interface 4 is provided with one first data transmission terminal 42, another set on this described first data transmission terminal 42 and described another standard connecting interface 50 first data transmission terminal is connected, for the output signal that each components and parts transmitted or another output signal that receive in the described electronic installation 5, and be sent to described scan test cell 2 through described test signal output pin 212, can learn this described electronic installation 5 is detected or the result of debug.
In this embodiment, see also shown in Fig. 2, one side of this described standard connecting interface 4 is provided with a frequency signal transmission ends 44, another set on this described frequency signal transmission ends 44 and another standard connecting interface 50 frequency signal transmission ends is connected, this frequency signal that described frequency signal transmission pin 213 transmits can be through this frequency signal transmission ends 44, be sent to a set timing unit in the described electronic installation 5, to proofread and correct the time that these electronic installation 5 interior timing units are write down.
In this embodiment, see also shown in Fig. 2, one side of this described standard connecting interface 4 is provided with one second data transmission terminal 46, this described second data transmission terminal 46 is to be connected with set another second data transmission terminal on described another standard connecting interface 50, this operation signal that described test pattern control pin 214 transmits can be through this described second data transmission terminal 46, be sent to this each set components and parts of described electronic installation 5 inside, each components and parts in this described electronic installation 5 promptly produce different operating states, so, can be by transmitting these input signals under each state to detect.
In this embodiment, see also shown in Figure 2, one side of this figure standard connecting interface 4 is provided with one the 3rd data transmission terminal 48, this figure the 3rd data transmission terminal 48 is to be connected with set another the 3rd data transmission terminal on another standard connecting interface 50, this reset signal that this reset signal transmission pin 215 transmits, be to be sent to each set components and parts of figure electronic installation 5 inside, to remove the different operating state of each components and parts in this electronic installation 5.
In this embodiment, see also shown in Fig. 2, described standard connecting interface 4 still is provided with an earth terminal 49, and this earth terminal 49 is to be connected with set another earth terminal of another standard connecting interface 50.In conjunction with said structure, can be by this described first test module 23 and standard connecting interface 4, described electronic installation 5 is carried out boundary scan testing, and this described second test module 25 is can produce another input signal and be sent to this described standard connecting interface 4, can receive another output signal again, make described second test module 25 can pass through this described test signal input pin 211 and test signal output pin 212, as universal asynchronous receiving-transmitting transmission (Universal Asynchronous Receiver/Transmitter) port, the chip system (SOC) in the described electronic installation 5 is tested.So, can reach and this described electronic installation 5 be carried out mispluging of each components and parts connects test in it, the input/output signal between external circuitry and components and parts monitors, the mutual connection test between components and parts, and the purposes such as functional test of internal logic circuit.
In this embodiment, see also shown in Figure 1, described standard connecting interface 4,50 can be a SD (SerialData) interface, also can be a secure digital and export interface into (Serial Data Input/Output), and described electronic installation 5 is to can be the mobile phone with this SD interface or this secure digital output/input interface, an or personal digital aid (PDA) (Personal Digital Assistant, be called for short PDA), so, by this standard connecting interface 4 and another standard connecting interface 50, can carry out the method for testing of JTAG and SOC to this electronic installation 5, not only with low cost, and enlarge the test function of this scanning tester.
Press, the above only is a specific embodiment of the best of the present invention, and only structural attitude of the present invention is not limited thereto, and anyly is familiar with this skill person in field of the present invention, can think easily and variation or modification, all can be encompassed in the claim of following this case.
Claims (11)
1, a kind of scanning tester is characterized in that, comprising:
One standard connecting interface, a side of this standard connecting interface comprise a command signal transmission ends, one first data transmission terminal and one second data transmission terminal at least; And
The one scan test cell, it is provided with a signal transport part, and this signal transport part is to be connected with the opposite side of above-mentioned standard connecting interface, this scan test cell is to transmit the boundary scan testing data by described command signal transmission ends, first data transmission terminal and second data transmission terminal, or transmits the chip system test data by the described command signal transmission ends and first data transmission terminal.
2, scanning tester as claimed in claim 1, it is characterized in that, be respectively equipped with a frequency signal transmission ends and one the 3rd data transmission terminal on one side of described standard connecting interface, and this frequency signal transmission ends and the 3rd data transmission terminal are for respectively in order to transmit this boundary scan testing data.
3, scanning tester as claimed in claim 1 is characterized in that, described scan test cell comprises:
One first test module be for generation boundary scan testing data, and these boundary scan testing data comprises an input signal, a frequency signal, an operation signal and a reset signal at least; And
One second test module be for generation chip system test data, and this chip system test data comprises another input signal at least.
4, scanning tester as claimed in claim 1 is characterized in that, described signal transport part is provided with one in order to transmit input signal or another input signal test signal input pin to the command signal transmission ends.
5, scanning tester as claimed in claim 1 is characterized in that, described signal transport part is provided with one in order to the output signal that receives first data transmission terminal transmission or the test signal output pin of another output signal.
6, scanning tester as claimed in claim 1, it is characterized in that, described signal transport part is provided with frequency signal transmission pin, this frequency signal transmission pin is that the frequency signal transmission ends that a side is provided with is connected with described standard connecting interface, and this frequency signal is sent to described frequency signal transmission ends through this frequency signal transmission pin.
7, scanning tester as claimed in claim 1 is characterized in that, described signal transport part is provided with one in order to the test pattern control pin of transfer operation signal to described second data transmission terminal.
8, scanning tester as claimed in claim 1, it is characterized in that, described signal transport part is provided with reset signal transmission pin, this reset signal transmission pin is connected with one the 3rd data transmission terminal that side was provided with of described standard connecting interface, and reset signal is to be sent to described the 3rd data transmission terminal through this reset signal transmission pin.
9, scanning tester as claimed in claim 1 is characterized in that, a side of described standard connecting interface is provided with an earth terminal.
10, scanning tester as claimed in claim 1 is characterized in that, described standard connecting interface is a SD interface.
11, scanning tester as claimed in claim 1 is characterized in that, described standard connecting interface is a secure digital output/input interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100289685A CN101339228A (en) | 2007-07-02 | 2007-07-02 | Scanning tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100289685A CN101339228A (en) | 2007-07-02 | 2007-07-02 | Scanning tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101339228A true CN101339228A (en) | 2009-01-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100289685A Pending CN101339228A (en) | 2007-07-02 | 2007-07-02 | Scanning tester |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104181451A (en) * | 2013-05-22 | 2014-12-03 | 英业达科技有限公司 | Testing device and testing method |
| CN108226764A (en) * | 2017-12-20 | 2018-06-29 | 北京松果电子有限公司 | Debugging apparatus and adjustment method |
-
2007
- 2007-07-02 CN CNA2007100289685A patent/CN101339228A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104181451A (en) * | 2013-05-22 | 2014-12-03 | 英业达科技有限公司 | Testing device and testing method |
| CN108226764A (en) * | 2017-12-20 | 2018-06-29 | 北京松果电子有限公司 | Debugging apparatus and adjustment method |
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Open date: 20090107 |