TWI315089B - Wire-bonding method for wire-bonding apparatus - Google Patents
Wire-bonding method for wire-bonding apparatus Download PDFInfo
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- TWI315089B TWI315089B TW095140096A TW95140096A TWI315089B TW I315089 B TWI315089 B TW I315089B TW 095140096 A TW095140096 A TW 095140096A TW 95140096 A TW95140096 A TW 95140096A TW I315089 B TWI315089 B TW I315089B
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- wire
- wafer
- head
- wire bonding
- region
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- 238000000034 method Methods 0.000 title claims description 18
- 235000012431 wafers Nutrition 0.000 claims description 70
- 239000000758 substrate Substances 0.000 claims description 20
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 229910052786 argon Inorganic materials 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 238000004080 punching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005491 wire drawing Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
- B23K20/004—Wire welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/789—Means for monitoring the connection process
- H01L2224/78901—Means for monitoring the connection process using a computer, e.g. fully- or semi-automatic bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S228/00—Metal fusion bonding
- Y10S228/904—Wire bonding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Wire Bonding (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Description
•1315089•1315089
' CONFIDENTIAL 九、發明說明: 【發明所屬之技術領域】 本發明是有關於-種打線機台 有關於—伽至少_㈣頭,且特別是 内之晶片同時打線之方法。 土板上不同區域 【先前技術】 目前在半導體產業中,對 _、小型化、元件密集度的要求逐漸 於封裝結構及技_改良,以域 = = = ^對 也不斷被推動著。 θ展软·備效率的潮流 以目前封裝製程中經常被使 生產線上叫、嶋進行連、為例,係在 業。也因此目前在單一生產線上 =度的打線作 具打線機台進行打線。 基板上,僅能以一 時,打線作業佔整體料限制下無法擴充生產線 善。 、.輕的比例無法獲得顯著改 【發明内容】 有鑑於此,本發明的 _ 打線方法,可以至少兩、就疋在提供一種打線機台之 域同時進行打線作業,可r頭+同時在單一基板上的不同區 相同的單位時間内增 ^顯著提升打線作業的效率,在 根據本發明的目的,二°:單位產量。 種打線機台之打線方法。 6 ,1315089<CONFIDENTIAL IX. OBJECTS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of wire-bonding machine-related at least _(four) heads, and in particular, the inner wafers are simultaneously wired. Different areas on the earth plate [Prior Art] At present, in the semiconductor industry, the requirements for _, miniaturization, and component density are gradually being improved by the package structure and technology, and the domain = = = ^ is also constantly being promoted. The trend of θ exhibition softness and preparation efficiency is often used in the current packaging process, which is often called the production line. Therefore, it is currently working on a single production line with a degree of wire drawing machine. On the substrate, it is only possible to expand the production line for a while. The light proportion cannot be significantly changed. [Invention] In view of the above, the _ wire-laying method of the present invention can perform wire-drawing operations at the same time in at least two fields of providing a wire-bonding machine, and can be r-head + simultaneously in a single Increasing the efficiency of the wire bonding operation in the same unit time on different areas on the substrate, in accordance with the purpose of the present invention, two degrees: unit throughput. A method of threading a wire machine. 6, 1315089
' CONFIDENTIAL '打線機台包括至少一第一打線頭及一第二打線頭,第一打 線頭及第二打線頭用以對一基板上至少一第一區域内之 多個第一晶片及一第二區域内之多個第二晶片同時進行 打線。打線方法包括:首先,取得第一區域及第二區域之 起始定位座標;接著,判斷第一區域及第二區域之間距是 否大於一設定間距;當第一區域及該第二區域之間距大於 設定間距時,第一打線頭及第二打線頭分別同時對第一晶 片及第二晶片進行打線;當第一區域及第二區域之間距小 > 於設定間距時,第二打線頭遠離第一打線頭並移動至基板 之一具有多個第三晶片之第三區域上方,第一打線頭及第 二打線頭分別同時對第一晶片及第三晶片進行打線。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 【實施方式】 > 請參照第1圖,其繪示第一種打線頭及基板上之晶片 的示意圖。本發明所使用之打線機台,包括至少第一打線 頭210及第二打線頭220,第一打線頭210及第二打線頭 220用以對基板100上至少第一區域110内之多個第一晶 片112,及第二區域120内之多個第二晶片122同時進行 打線。第1圖中第一區域110、第二區域120及第三區域 130係為基板100上之不同列。第一晶片112、第二晶片 122及第三晶片132分別成一直線排列於第一區域110、 7 ’1315089The 'CONFIDENTIAL' wire splicing machine includes at least a first wire splicing head and a second wire splicing head, wherein the first wire splicing head and the second wire splicing head are used for a plurality of first chips and at least one of the first regions on a substrate A plurality of second wafers in the two regions are simultaneously wired. The method of wire bonding includes: firstly, obtaining a starting positioning coordinate of the first area and the second area; and then determining whether a distance between the first area and the second area is greater than a set spacing; when the distance between the first area and the second area is greater than When the pitch is set, the first wire bonding head and the second wire bonding head respectively wire the first wafer and the second wafer; when the distance between the first region and the second region is small, the second wire bonding head is away from the first The first wafer and the third wafer are simultaneously wired to the first wafer and the third wafer, respectively. The above described objects, features, and advantages of the present invention will become more apparent and understood. , which shows a schematic diagram of the first type of wire head and the wafer on the substrate. The wire bonding machine used in the present invention includes at least a first wire bonding head 210 and a second wire bonding head 220. The first wire bonding head 210 and the second wire bonding head 220 are used to face at least a plurality of first regions 110 on the substrate 100. A wafer 112, and a plurality of second wafers 122 in the second region 120 are simultaneously wired. The first region 110, the second region 120, and the third region 130 in Fig. 1 are different columns on the substrate 100. The first wafer 112, the second wafer 122, and the third wafer 132 are arranged in a line in the first region 110, 7'1315089, respectively.
' CONFIDENTIAL 桊 •第二區域120及第三區域130内。其中每一第一晶片112、 第二晶片122及第三晶片132之間係維持間距D1。 請參照第2圖,其繪示本發明之打線方法的流程圖。 並請同時參照第1圖。首先,如步驟201所示,取得第一 區域110及第二區域120之起始定位座標。 接著,如步驟202所示,打線機台更包括一處理單 元,由處理單元判斷第一區域110及第二區域120之間 距,也就是第一晶片112及第二晶片122之間距D1是否 > 大於一設定間距。此一步驟是確保第一打線頭210及第二 打線頭220之間保持一安全距離,避免在打線過程中發生 碰撞。 當第一區域110及第二區域120之間距小於設定間 距,也就是第一晶片112及第二晶片122之間距D1小於 設定間距時,如步驟203所示,第二打線頭220遠離第一 打線頭210並移動至基板100之一第三區域130上方,第 三區域130内具有多個第三晶片132。 I 然後,如步驟204所示,處理單元係分別發出一定位 訊號至第一打線頭210及第二打線頭220,使第一打線頭 210及第二打線頭220分別對位第一區域110及第三區域 130之起始位置。 接著,如步驟205所示,第一打線頭210及第二打線 頭220分別同時對第一晶片112及第三晶片132進行打線。 若步驟202中,當第一區域110及第二區域120之間 距D1大於設定間距時,也就是第一晶片112及第二晶片 8 4315089'CONFIDENTIAL 桊 • In the second area 120 and the third area 130. A spacing D1 is maintained between each of the first wafer 112, the second wafer 122, and the third wafer 132. Please refer to FIG. 2, which shows a flow chart of the wire bonding method of the present invention. Please also refer to Figure 1 at the same time. First, as shown in step 201, the initial positioning coordinates of the first region 110 and the second region 120 are obtained. Next, as shown in step 202, the wire bonding machine further includes a processing unit, and the processing unit determines the distance between the first region 110 and the second region 120, that is, whether the distance D1 between the first wafer 112 and the second wafer 122 is > Greater than a set spacing. This step is to ensure a safe distance between the first wire head 210 and the second wire head 220 to avoid collision during the wire bonding process. When the distance between the first region 110 and the second region 120 is less than the set pitch, that is, when the distance D1 between the first wafer 112 and the second wafer 122 is less than the set interval, as shown in step 203, the second wire head 220 is away from the first wire. The head 210 is moved over a third region 130 of the substrate 100 having a plurality of third wafers 132 therein. Then, as shown in step 204, the processing unit sends a positioning signal to the first wire bonding head 210 and the second wire bonding head 220 respectively, so that the first wire bonding head 210 and the second wire bonding head 220 respectively align the first region 110 and The starting position of the third region 130. Next, as shown in step 205, the first wire bonding head 210 and the second wire bonding head 220 respectively wire the first wafer 112 and the third wafer 132. In step 202, when the distance D1 between the first region 110 and the second region 120 is greater than the set pitch, that is, the first wafer 112 and the second wafer 8 4315089
' CONFIDENTIAL 122之間距D1大於設定間距時’則直接跳至步驟204。處 理單元係分別發出一定位訊號至第一打線頭210及第二打 線頭220,使第一打線頭21〇及第二打線頭220分別對位 第一區域110及第二區域120之起始位置。然後,如步驟 205所示,第一打線頭210及第二打線頭220分別同時對 第一晶片112及第二晶片122進行打線。If the distance between the CONFIDENTIAL 122 and the D1 is greater than the set interval, then jump directly to step 204. The processing unit sends a positioning signal to the first wire bonding head 210 and the second wire bonding head 220 respectively, so that the first wire bonding head 21〇 and the second wire bonding head 220 respectively align the starting positions of the first region 110 and the second region 120. . Then, as shown in step 205, the first wire bonding head 210 and the second wire bonding head 220 simultaneously wire the first wafer 112 and the second wafer 122, respectively.
然而,本發明所屬之技術領域中具有通常知識者,可 知本發明之技術不限於此《如第3圖所示,其缘示第二種 打線頭及基板上之晶片的示意圖。第一區域ll〇a、第二區 域120a及第三區域130a係為排列於基板l〇〇a上之不同 行,第一晶片112a、第二晶片122a及第三晶片132a係分 別成一直線排列於第一區域110a、第二區域120a及第三 區域130a内。每一第一晶片U2a、第二晶片122a及第三 晶片132a係維持間距D2。因此上述之打線方法亦可適用 於此種晶片排列方式,藉由打線機台之處理單元判斷間距 D2是否大於一設定間距,決定第二打線頭21〇是否要移動 到下-個區域,例如第三區$施。當確定第一打線頭 210及第二打線頭220倮持安全距離後,則分別於不同區 域同時進行打線作業。 如第4圖所示,其繪示第三種打線頭及基板上之晶片 的示意圖。基板議上具有第-區域、第二區域120 b第一區域130b及第四區域14〇b。各區域内分別具有排 列成4X4陣列的第-晶片lm、第二晶片12%、第三晶 片132b及第四晶片142b。此外,各工作區内的晶片分別 9 •1315089However, those skilled in the art to which the present invention pertains, it is to be understood that the technique of the present invention is not limited to this, as shown in Fig. 3, which is a schematic view of a second type of wire bonding head and a wafer on a substrate. The first region 11a, the second region 120a, and the third region 130a are different rows arranged on the substrate 10a, and the first wafer 112a, the second wafer 122a, and the third wafer 132a are respectively arranged in a line. The first region 110a, the second region 120a, and the third region 130a. Each of the first wafer U2a, the second wafer 122a, and the third wafer 132a maintains a pitch D2. Therefore, the above-mentioned wire bonding method can also be applied to the wafer arrangement mode. The processing unit of the wire bonding machine determines whether the spacing D2 is greater than a set spacing, and determines whether the second wire bonding head 21 is to move to the next region, for example, Three districts. When it is determined that the first wire head 210 and the second wire head 220 are held at a safe distance, the wire bonding operation is simultaneously performed in different regions. As shown in Fig. 4, a schematic view of the third type of wire head and the wafer on the substrate is shown. The substrate has a first region, a second region 120b, a first region 130b, and a fourth region 14b. Each of the regions has a first wafer lm, a second wafer 12%, a third wafer 132b, and a fourth wafer 142b arranged in a 4X4 array. In addition, the wafers in each work area are respectively 9 • 1315089
CONFIDENTIAL 與其他工作區内的晶片維持間距D 3。因此上述之打線方法 也可用於晶片排列成陣列之形式,且各陣列内之晶片數量 不一定相同。當處理單元判斷晶片間之間距D3小於設定 間距,使得第一打線頭210及第二打線頭220有碰撞之虞 時,則將第二打線頭220遠離第一打線頭210移往其他區 域。當判定安全無虞後,則令第一打線頭210及第二打線 頭220同時進行打線。 此外,打線機台更可包括一資料庫,用以儲存操作參 數資料。操作參數資料包括各區域之晶片排列、晶片數 量、晶片尺寸及起始定位座標。另外設定間距亦可儲存於 資料庫内,供處理單元判斷第一打線頭210及第二打線頭 220之間距是否安全。 另外,本實施例不限於僅以兩個打線頭同時操作打 線,工作區域之形狀及内部之晶片數目也不做限制。只要 有兩個以上之打線頭,於一基板上之不同區域内同時進行 打線,皆屬於本發明之範圍。 本發明上述實施例所揭露之打線機台之打線方法,係 以至少兩打線頭同時對一基板上不同區域内之晶片同時 進行打線,可在單一生產線上大幅增進打線作業之效率, 使相同的單位時間内產品的單位產量增加。而打線機台可 對不同工作區域内同時進行打線作業之打線頭做適當距 離的分隔,以避免碰撞發生。 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明。本發明所屬技術領域中具有通 -1315089CONFIDENTIAL maintains a distance D 3 from the wafers in other work areas. Therefore, the above-described wire bonding method can also be used in the form of arrays of wafers, and the number of wafers in each array is not necessarily the same. When the processing unit determines that the inter-wafer distance D3 is less than the set spacing, so that the first wire-punching head 210 and the second wire-punching head 220 have a collision, the second wire-punching head 220 is moved away from the first wire-punching head 210 to other regions. When it is determined that the safety is intact, the first wire head 210 and the second wire head 220 are simultaneously wired. In addition, the wire bonding machine may further include a database for storing operating parameter data. The operational parameter data includes the wafer arrangement, wafer count, wafer size, and initial positioning coordinates for each region. In addition, the set spacing can also be stored in the data base for the processing unit to determine whether the distance between the first wire head 210 and the second wire head 220 is safe. Further, the present embodiment is not limited to the simultaneous operation of the wire by only two wire heads, and the shape of the work area and the number of wafers inside are not limited. As long as there are more than two wire ends, simultaneous wire bonding in different regions on a substrate is within the scope of the present invention. The wire bonding method of the wire bonding machine disclosed in the above embodiments of the present invention is to simultaneously wire the wafers in different areas on a substrate at the same time by at least two wire heads, thereby greatly improving the efficiency of the wire bonding operation on a single production line, so that the same The unit output of the product increased per unit time. The wire-bonding machine can separate the wire-punching heads of different working areas at the same time to avoid collisions. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. The invention belongs to the technical field of the invention -1315089
CONFIDENTIAL • 常知識者,在不脫離本發明之精神和範圍内,當可作各種 之更動與潤飾。因此,本發明之保護範圍當視後附之申請 專利範圍所界定者為準。CONFIDENTIAL • A person skilled in the art can make various changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
11 •131508911 • 1315089
' CONFIDENTIAL 【圖式簡單說明】 第1圖繪示第一種打線頭及基板上之晶片的示意圖; 第2圖繪示本發明之打線方法的流程圖; 第3圖繪示第二種打線頭及基板上之晶片的示意 圖;以及 第4圖繪示第三種打線頭及基板上之晶片的示意圖。 【主要元件符號說明】'CONFIDENTIAL' is a schematic diagram of the first type of wire bonding head and the wafer on the substrate; FIG. 2 is a flow chart of the wire bonding method of the present invention; And a schematic view of the wafer on the substrate; and FIG. 4 is a schematic view of the third wire bonding head and the wafer on the substrate. [Main component symbol description]
100、 100a 、100b 基板 110、 110a 、110b 第 區域 112、 112a 、112b 第 mm 1— 晶片 120、 120a > 120b 第 二 區域 122、 122a 、122b 第 — 晶片 130、 130a 、130b 第 三 區域 132、 132a 、132b 第 三 晶片 140b :第四區域 142b •第四晶片 210 : 第一 打線頭 220 : 第二 打線頭 12100, 100a, 100b substrate 110, 110a, 110b first region 112, 112a, 112b mm 1 - wafer 120, 120a > 120b second region 122, 122a, 122b first wafer 130, 130a, 130b third region 132, 132a, 132b third wafer 140b: fourth region 142b • fourth wafer 210: first wire bonding head 220: second wire bonding head 12
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TW095140096A TWI315089B (en) | 2006-10-30 | 2006-10-30 | Wire-bonding method for wire-bonding apparatus |
US11/905,868 US7581666B2 (en) | 2006-10-30 | 2007-10-05 | Wire-bonding method for wire-bonding apparatus |
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TW095140096A TWI315089B (en) | 2006-10-30 | 2006-10-30 | Wire-bonding method for wire-bonding apparatus |
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TW200820353A TW200820353A (en) | 2008-05-01 |
TWI315089B true TWI315089B (en) | 2009-09-21 |
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TW095140096A TWI315089B (en) | 2006-10-30 | 2006-10-30 | Wire-bonding method for wire-bonding apparatus |
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US9153554B2 (en) * | 2012-04-22 | 2015-10-06 | Kulicke And Soffa Industries, Inc. | Methods of adjusting ultrasonic bonding energy on wire bonding machines |
US10600756B1 (en) | 2017-02-15 | 2020-03-24 | United States Of America, As Represented By The Secretary Of The Navy | Wire bonding technique for integrated circuit board connections |
US10923456B2 (en) * | 2018-12-20 | 2021-02-16 | Cerebras Systems Inc. | Systems and methods for hierarchical exposure of an integrated circuit having multiple interconnected die |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
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US3840169A (en) * | 1971-01-27 | 1974-10-08 | Inforex | Automatic bonding apparatus with multiple bonding heads |
JP2558976B2 (en) * | 1991-11-08 | 1996-11-27 | 松下電器産業株式会社 | Method of joining electrodes and leads of electronic parts |
JP2541489B2 (en) * | 1993-12-06 | 1996-10-09 | 日本電気株式会社 | Wire bonding equipment |
JPH08153759A (en) * | 1994-11-29 | 1996-06-11 | Nec Yamagata Ltd | Single-point bonder and manufacture of semiconductor device |
US5839640A (en) * | 1996-10-23 | 1998-11-24 | Texas Instruments Incorporated | Multiple-tool wire bonder |
US5944249A (en) * | 1996-12-12 | 1999-08-31 | Texas Instruments Incorporated | Wire bonding capillary with bracing component |
US6112973A (en) * | 1997-10-31 | 2000-09-05 | Texas Instruments Incorporated | Angled transducer-dual head bonder for optimum ultrasonic power application and flexibility for tight pitch leadframe |
CN1211178C (en) * | 2000-05-04 | 2005-07-20 | 德克萨斯仪器股份有限公司 | System and method for reducing welding program error for IC welding machine |
US6572001B2 (en) * | 2001-07-05 | 2003-06-03 | Asm Technology Singapore Pte Ltd. | Bonding system |
US6789235B1 (en) * | 2001-09-05 | 2004-09-07 | National Semiconductor Corporation | Bond program verification system |
US6749100B2 (en) * | 2001-11-28 | 2004-06-15 | Asm Technology Singapore Pte Ltd. | Multiple-head wire-bonding system |
US7320423B2 (en) * | 2002-11-19 | 2008-01-22 | Kulicke And Soffa Industries, Inc. | High speed linear and rotary split-axis wire bonder |
TW200810051A (en) * | 2006-08-14 | 2008-02-16 | Advanced Semiconductor Eng | Wire-bonding apparatus and wire-bonding method thereof |
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2006
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TW200820353A (en) | 2008-05-01 |
US20080102539A1 (en) | 2008-05-01 |
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