1352386 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種晶圓切割之方法，尤 片晶圓堆疊且具有雜之晶_财法。 媽用在又 【先前技術】 斬會：著系:級卿鸡⑽h恤够’ SIP)的技術發展趨勢曰 二要’二維即)堆疊構裝❾技術’日益受電子產品市場的囑目。 D堆且構裝的發展，除了能將記憶體在電路板 ==電If品縮小化的效率外，更能將顺^ j統級封裝是指結合單/多片晶片（IC)以及離散被動元 ^且件在早—封針，提供完整的纽或是次纽，是以封裝技 成本、小體積與高效能的解決方案。系統產品朝整 成了新型態的系統級封裝成為早—山未外’也促 (Dartit系統裝生產中使用了先進的系統設計方法，分割 技術、l(>m整合專有麟、覆晶猶、線接合_ 一㈣ 和其技術、高密絲著麟，以及最佳化的測試方法 和其匕技術；利用以下敘述加以解釋。 割方圖f 之雙片晶圓堆叠切 面及-上表®。甘先 乂供一第一晶圓具有一下表 、中，第一晶圓可以為單純之晶圓或是具有晶粒 5 (S ) 1352386 結構之晶圓。 々接著，步帮S12 ’提供一第二晶圓具有一主動面及一背面， ，第二晶圓主動面上具有複數條切割線，其複數條切割線係互相 =錯以形成複數個空格，該些複數個空格中定義出複數個晶粒， 每-個晶粒具有-雜墊塊、複數個接墊及_微型機構。1352386 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of wafer dicing, in particular, wafer stacking and having a hybrid crystal. Mom used it again [Previous technology] 斩会: The system: the level of the chicken (10) h-shirt enough 'SIP' technology development trend 曰 two to 'two-dimensional, that is, stacking technology ’ technology is increasingly attracting attention in the electronic product market. The development of D-stack and configuration, in addition to the efficiency of reducing the memory on the board == electric If, can more effectively combine the single/multi-chip (IC) and discrete passive Yuan ^ and the piece in the early - sealing needle, providing a complete New Zealand or secondary New Zealand, is a solution cost, small size and high efficiency solution. The system products have become a new type of system-level packaging, which has become an early-out-of-the-season. (Dartit system production uses advanced system design methods, segmentation technology, l(>m integration of proprietary lining, overlay) Crystal, wire bonding _ one (four) and its technology, high-density silk, and optimized test methods and its know-how; explained by the following description. Two-piece wafer stacking cut-off of the cut-off map f - Top Table® The first wafer can be a simple wafer or a wafer with a die 5 (S) 1352386 structure. 々 Next, the step S12 'provides a The second wafer has an active surface and a back surface, and the second wafer active surface has a plurality of cutting lines, and the plurality of cutting lines are mutually wrong=to form a plurality of spaces, and the plurality of spaces define a plurality of spaces Each of the grains has a hetero-block, a plurality of pads and a micro-mechanism.
、展狀塾塊之材質通巾為環氧細旨；微型機構係位於環 狀塾塊所定義之空_ ’微型機構可以是微主動元件如：積體 電路、微機械元件或移動元件等，或是微被動元件，如 電容器或電阻料，·複數個齡係錄雜墊麟定|之2間 外，該些接墊係於_製程後電行連接至外部電路。 之後’步驟S14，第-晶圓覆蓋且接合於第二晶圓之上，以 形成複數個空腔，使該微型機構位於空腔内；其中 下表面(主動面)係面對第二晶圓之主動面。、 曰曰 二==分別切割第一晶圓及第二晶圓，The material of the paving block is made of epoxy; the micro-mechanism is located in the space defined by the ring-shaped block. The micro-mechanism can be a micro-active component such as an integrated circuit, a micro-mechanical component or a moving component. Or micro-passive components, such as capacitors or resistors, and a plurality of age-old recording pads, which are connected to an external circuit after the process. Then, in step S14, the first wafer is covered and bonded on the second wafer to form a plurality of cavities, so that the micro-mechanism is located in the cavity; wherein the lower surface (active surface) faces the second wafer The active side. , 曰曰 2 == cutting the first wafer and the second wafer, respectively
在習知技射，因為第一晶圓之下表面係面對第二晶圓之主 然而m切割線係位於下表面上，第二晶圓之切 ⑽係位於主動面上，因此，當要切割第_晶圓時需向上表面進 製=’要切鄕二·時需向其背面進行姆说程，而第 =圓及第二晶_為不咖之材f，使得切割製程的實施 1352386 l發明内容】 本發明之目的在於提供一種 圓堆疊且具有空腔之晶__程t，顧在雙片晶 準確性以及對位方便的需求。 貫現曰曰圓切割製程中之 本發明提供-種晶m蝴方法 裝結構，該方法包括··提供—第—晶圓應=雙=圓接合之封 面；擇定—第—預設距離，並利用刀|以2—上表面及一下表 晶圓一部份以去除—第-斜面；提供::第設^離，第一 -主動面及-背面，其巾， 日日第-晶圓具有 =:方=割線交錯排列而成;覆蓋且接合第一晶_第 曰圓上晶圓上之複數個對位點係顯露於外；以及藉 由第一曰曰圓上外露的對位點，做 晶圓及第二晶圓，以形成-系統級封裝構造U別切割第一 【實施方式】 ，了解決績所遇到雙U卿㈣，其_上所遇到對位 f切割時準麵之問題；本發明提供-種晶圓切割之方法， 丨帛晶圓製作出兩切面’使第—晶圓覆蓋於一第二晶 圓上實可方便對域_，輯加其雜之讀及切觸準確性。 曰月參閱圖―’係為本發明_實施例之__第—晶圓示意圖。第 阳圓20具有一下表面及一上表面。需制說明的是，此圖中所 、’會不，為第-晶15 2G之上表面，且為—透棚，以便清楚觀察到 第BB圓之下表面，明瞭該下表面上各個元件的配置情形。其中， 如圖所7F ’下表面上具有複數條蝴線，係由複數條第一方向切 =線26(在圖中第一方向係定義為平行X轴之方向)與複數條第二 方向切割線28(在@中第二方向係定義為平行γ軸之方向)交錯排 列而成。 -第-方向與第二方向係互相垂直，而第一方向切割線％與第 二方向切割線28互相交錯定義出複數個晶粒空間2〇〇，每一個晶 粒空間200中可以形成一個晶粒(die)。 此實施例中之第-晶圓2G ’係利用—完整的晶圓2先行切除 兩斜面’以提供後續的製程。其中，第一晶圓2〇自上述晶圓2圓 周同-點起算-第-預定距離m ’细刀具切割掉晶圓2下方之 一部分(即一第一斜面22),而產生一第一斜邊222。另外，第一 晶圓20再自上述晶圓2圓周同一點起算一第二預定距離n，利用 刀具切割掉晶圓2左方圓周之一部分(即一第二斜面24)，而產生 一第二斜邊242。 在本實施例中，第一晶圓20係為一單純晶圓，其上先行切割 捨去兩部分斜面(即第一斜面22與第二斜面24)，且第一晶圓2〇 表面上並無任何晶粒結構’僅做為覆蓋晶圓(Cap wafer)之用途；然 而，第一晶圓20亦可僅割除一邊斜面，且可選擇使用具有晶粒結 構之元件晶圓(device wafer)，視其所欲生產之晶片功能以決定第 一晶圓20之使用。 接著，請配合參閱圖三，係為本發明一實施例一第二晶圓之 示意圖。如圖所示’第二晶圓3具有一主動面(圖中所示係為第二 晶圓3主動面)及一背面，主動面上具有複數條切割線，係由複數 條第一方向切割線36(在圖中第一方向係定義為平行又軸之方向） 與複數條第二方向切割線38(在圖中第二方向係定義為平行γ轴 之方向）交錯排列而成。 1352386 第一方向與第二方向係互相垂直’而第一方向切割線36與第 二方向切割線38互相交錯定義出複數個晶粒空間3〇〇，每—個曰 粒空間300中可以形成一個晶粒(die)。其中，每一個晶粒具有一 環狀墊塊302、複數個接墊306及一微型機構304。 、 環狀墊塊302之材質可以用環氧樹脂或其它相類似之材料； 微型機構304係位於環狀墊塊302所定義之空間内，微型機構3〇4 可以是微主動元件，如：積體電路、微機械元件、移動元件、投 影晶片或光學晶片等，或是微被動元件，如：麥克風、感測器、 電f器、電阻器、壓力感應器或致動器等；複數個接墊3〇6係位 於裱狀墊塊302所定義之空間外，該些接墊3〇6係於切割製程 電性連接至外部電路。 需特別說_是，為進-步說額2G去除兩部 分斜面之用意，請對照圖二以及圖三。其中，第二晶圓3具有一 第一對位點a，且該第-對位點a至晶圓2邊緣切線之直線距離A 糸’、第S向垂直’上述之第一預定距離瓜大於直線距離a，即 m>A’且第一預定距離111與直線距離a皆以晶圓2圓周上同一點 =起算輯；刀具·著X軸之方_平行第-方向)切割晶 ®以去除第一斜面22，產生第一斜邊222。 =，第二晶圓3亦具有一第二對位點匕，當第一晶圓2〇以 ^預疋距離n，利用刀具切割掉晶圓2左方之第二斜面24時， 倾距離係以第二對健b與晶圓2圓周之間的直線距離 。其中’第二對位點b至晶圓2圓周之直線距離 且坌1、 一 σ垂直，第二預定距離n大於直線距離C，即n>c， 算】i預ίί離n與直線距離以晶圓2圓周上同-點開始起 算距離，刀具係沿著Υ軸之方向(即平行第二方向)切割晶圓2以 3 去除第一斜面24 ’產生第二斜邊242。 請參閱圖四’係為本發明-實施例第—晶圓與第二晶圓堆疊 以具有空腔結構之剖面圖。圖四中所示之剖面，係為圖二中第一 晶圓20與圖三中第二晶圓3堆疊後之££，切面，其中，乃是將上 述實施例之第m 2G與第二晶圓3，經過邊緣對位、鮮後， 可利用-介質4加以黏著第—晶圓2G與第二晶圓3 ;或是不使用 介質’而是_高溫、高壓或電壓等方式，將第—晶圓2與第二 晶圓3加以堆疊岐。其中’介質可以是玻璃f、黏著膠、 及銲錫等材料。 當第 。—Bsil 2ϋ覆纽接合於第二晶圓3之上時，由於第二晶 f 1*^每阳粒中之城塾塊302具有一高度，會使第一晶圓20 二日日圓3之間形成一空腔結構之系統級封裳。又第一晶圓 程時’預先嫌兩斜面22、24，旨在前述兩晶圓堆疊後，使 ^晶圓3上的對位點a、b可以顯露出來。其中，第—對位點a 笛-f第斜面22後所產生之第一斜邊222的直線距離為B，而 ㈣^立點b與去除第二斜面24後所產生之第二斜邊242的直線 6 f丨距離B係大於第—敢距離m，距離D係大於第二 被以麵第二晶紅之触點a、b㈣在堆叠後完全 片曰哺助切割時之定位需求，並改善習知技術中當兩 日日立後’欲切割晶粒時無法切割或準確度不佳的情形發生。 的、C ’係為本發明—實施例雙片晶圓堆疊之切割方法 =第日先’步驟提供—第一晶圓具有一上表面及下 粒社槿之曰日曰门圓20可以.選擇是單純無任何結構之晶圓或是具有晶 粒4之晶圓。其中，配合參考第二圖崎示之實施例，可瞭解 上述之第一晶圓20之上表面且女. 複數條第-方向切割線複數健有複數條切割線，該些切割線係由 義出複數個空格。 ’、一方向切割線交錯排列而成並定 接著，步驟S502,擇定一笛一π 離m，利用刀具沿著第一，二預設距離m ’並以第一預設距 -部份，以去除-第即平行第—方向)切掉第—晶圓 步驟S504，擇定一笛- 向垂直第一晶圓20上第離n，且第二預設距離n之方 η，利用刀鮮著第-^ 切割線。接著，以第二預設距離 欄刀具々者第一方向(即平行 部份，以去除一第二斜面。 力⑺刀桿第日曰圓20 - 步驟S506,提供一第二晶圓 主動面上具有至少-對位點有一主動面及一背面；其甲， .r ” 複數個晶粒(dies)以及複數條切宏，丨 線六:ί二割線:由複數條第一方向切割線複數條第二方向切钙 H曰空格，每—個空格中定義出—個晶粒: 每個曰曰粒具有一械墊塊、複數個接墊及一微型機構。 之^後’步驟纖，將第-晶圓20之下表面正對於第二晶圓3 ^動、崎，使w覆蓋與接合 於第二晶圓3上每一晶粒中之環狀 數I 純，會使f —_2G與第二晶®3之間形成複 數個空腔’且該微型機構304位於上述之複數個空腔内。又，^ =第-晶圓20已於前置步驟S5〇4中被移除，可進一步透過被 ，除之部分第-晶圓20所形成的缺口使第二晶圓3上之複數個對 ^點顯露称其中，第-晶圓2〇與第二晶圓3之接合方式可^ :利用介質加以黏著接合，或是高壓、高溫或電壓之方式 且固疋等’並不以上述任一方式為限。 1352386 步驟S510 ’藉由第二晶圓3上外露的對位點做為對位並進 而推算魏條切割線之位置所在’再利用刀具同時切割第一晶圓 2〇及第二晶圓3 ’以形成具空腔之系統級封裝構造。 此外，亦可麟㈣完成之輕續縣製程視盆需 要將第-晶圓20與第二晶圓3相接合之晶粒直接進行封裝程序， 或是施以-外力或振_方式將第—晶圓2G與第二晶圓3相接合 之晶粒分開，各自進行後續封裝程序，以製成最終產品。 藉由上述實施例，可以知道本發明所提供之晶_割方法， 可以有效秋定位_之缺點，使其在切程中能有更高 的效率。又_L述實施例伽每具有兩鑛健做為說明， 但並不代表限雜兩麵健，若财—鑛健或是複數個對 位點亦為本發明實施精神之推衍。 本發明所提供的晶_财法，將第先行切割去除至 少-斜面，使第-晶圓與第二晶圓相堆疊接合時，可以將第二晶 圓上之對位點外露出來，以便在切割製程中_精準對位，^ 確的切割第-晶_第二上之晶粒，使其在婦说程中能有 更高的良率；如此，可以有效避免習知技術雙晶欧位困難之缺 點，以及因對位錯誤而造成切割製程中良率的降低。 本發明雖以較佳f施·明如上’然其麟用嫌定本發明 精神及發明實體。對所屬技術領域中具有通常知識者，當可拳= 瞭解並利用其它元件或方式來產生相同的功效。是以，在不脫離 本發明之精神及範圍内所作之修改，均應包含在下述之申請專利 12 範圍内。 【圖式簡單說明】 腔結構之雙片晶圓堆疊切割方法％ 圖一係為習知技術具有空 流程圖； 圖一係為本發明一實施七 Μ一第一晶圓之示意圖；In conventional techniques, since the lower surface of the first wafer faces the second wafer but the m-cut line is on the lower surface, the second wafer is cut (10) on the active surface, so When cutting the _th wafer, the upper surface hexadecimal = 'to be cut 鄕 two · need to go to the back of the m said process, and the = circle and the second crystal _ is not the material f, so that the implementation of the cutting process 1352386 SUMMARY OF THE INVENTION The object of the present invention is to provide a circular stack and a cavity __process t, which is in need of double chip crystal accuracy and convenient alignment. The present invention provides a method for fabricating a seed crystal, and the method includes: providing a first wafer to be double = a cover of a circular joint; a selection - a preset distance, And use the knife|to remove the ---bevel on the upper surface and a part of the wafer; provide:: the first set, the first-active surface and the back, the towel, the day-day wafer Having a =: square = secant line staggered; covering and joining a plurality of pairs of dots on the first crystal on the wafer on the first circle is exposed; and by the exposed point on the first circle , do the wafer and the second wafer to form - system-level package structure U do not cut the first [implementation], the solution met the double U Qing (four), the _ on the encounter of the alignment f cutting time The invention provides a method for wafer dicing, and the enamel wafer is fabricated with two cut surfaces, so that the first wafer is covered on a second wafer, which is convenient for the domain _, and the miscellaneous reading is added. And the accuracy of the touch. The following is a schematic diagram of the __first-wafer of the present invention. The first circle 20 has a lower surface and an upper surface. It should be noted that, in this figure, 'will not, is the surface of the first crystal 15 2G, and is - shed, so as to clearly observe the lower surface of the BB circle, to understand the various components on the lower surface Configuration situation. Wherein, as shown in FIG. 7F, the lower surface has a plurality of butterfly lines, which are cut by a plurality of first direction=line 26 (the first direction is defined as a direction parallel to the X axis) and a plurality of second directions are cut. Line 28 (defined in the direction of the parallel gamma axis in the second direction of @) is staggered. The first direction and the second direction are perpendicular to each other, and the first direction cutting line % and the second direction cutting line 28 are mutually staggered to define a plurality of grain spaces 2〇〇, and a crystal can be formed in each of the grain spaces 200 Die. The first wafer 2G' in this embodiment utilizes the complete wafer 2 to cut the two slopes first to provide a subsequent process. Wherein, the first wafer 2 is cut from the circumference of the wafer 2 from the same point to the first predetermined distance m', and the cutter cuts a portion below the wafer 2 (ie, a first slope 22) to generate a first slope. Side 222. In addition, the first wafer 20 is further calculated from the same point on the circumference of the wafer 2 by a second predetermined distance n, and a part of the left circumference of the wafer 2 (ie, a second slope 24) is cut by the cutter to generate a second Beveled edge 242. In this embodiment, the first wafer 20 is a simple wafer on which the two portions of the slopes (ie, the first slope 22 and the second slope 24) are cut first, and the first wafer 2 is on the surface of the wafer. No grain structure is used only for the purpose of a cap wafer; however, the first wafer 20 may also only cut one side of the bevel, and may optionally use a device wafer having a grain structure. The use of the first wafer 20 is determined by the function of the wafer to be produced. Next, please refer to FIG. 3, which is a schematic diagram of a second wafer according to an embodiment of the present invention. As shown in the figure, 'the second wafer 3 has an active surface (shown as a second wafer 3 active surface) and a back surface, and the active surface has a plurality of cutting lines, which are cut by a plurality of first directions A line 36 (defined in the first direction in the drawing as a direction parallel to the axis) is interleaved with a plurality of second direction cutting lines 38 (defined in the direction in which the second direction is parallel to the gamma axis). 1352386 The first direction and the second direction are perpendicular to each other' and the first direction cutting line 36 and the second direction cutting line 38 are mutually staggered to define a plurality of grain spaces 3〇〇, and each of the grain spaces 300 may form one Die. Each of the dies has an annular spacer 302, a plurality of pads 306, and a micro-mechanism 304. The material of the annular block 302 may be epoxy or other similar materials; the micro-mechanism 304 is located in the space defined by the annular block 302, and the micro-mechanism 3〇4 may be a micro-active component, such as: Body circuit, micromechanical component, moving component, projection wafer or optical wafer, etc., or micro passive component, such as: microphone, sensor, electric device, resistor, pressure sensor or actuator; The pads 3〇6 are located outside the space defined by the beryllium pads 302, and the pads 3〇6 are electrically connected to the external circuit in the cutting process. Need to say in particular _ Yes, for the purpose of step-by-step 2G to remove the two parts of the slope, please refer to Figure 2 and Figure 3. The second wafer 3 has a first pair of sites a, and the straight line distance A 糸 ' of the first pair of sites a to the edge of the wafer 2 is perpendicular to the first predetermined distance of the first predetermined distance. The straight line distance a, that is, m>A', and the first predetermined distance 111 and the straight line distance a are the same point on the circumference of the wafer 2 = the calculation piece; the tool is on the X-axis side _ parallel first direction) to cut the crystal ® to remove The first bevel 22 creates a first bevel 222. =, the second wafer 3 also has a second pair of sites 匕, when the first wafer 2 is pre-twisted by a distance n, and the second bevel 24 on the left side of the wafer 2 is cut by the cutter, the tilting distance is The linear distance between the second pair of health b and the circumference of the wafer 2. Wherein the linear distance between the second pair of sites b to the circumference of the wafer 2 is 坌1, a σ is perpendicular, and the second predetermined distance n is greater than the linear distance C, ie, n>c, which is calculated as the distance between n and the straight line. The distance between the same point on the circumference of the wafer 2 starts, and the tool cuts the wafer 2 along the direction of the x-axis (ie, parallel to the second direction) to remove the first slope 24' to produce the second bevel 242. Please refer to FIG. 4 for the present invention - the first embodiment - the wafer and the second wafer are stacked to have a cross-sectional view of the cavity structure. The cross section shown in FIG. 4 is the top surface of the first wafer 20 in FIG. 2 and the second wafer 3 in FIG. 3, and the cut surface is the m 2G and the second of the above embodiment. After the wafer 3 is edge-aligned and fresh, the medium 4 can be adhered to the first wafer 2G and the second wafer 3; or the medium is not used, but the high temperature, high voltage or voltage is used. — The wafer 2 and the second wafer 3 are stacked. The medium may be glass f, adhesive, and solder. When the first. - When the Bsil 2 接合 bond is bonded over the second wafer 3, since the second crystal f 1*^ has a height in each of the positive granules 302, the first wafer 20 is between two yen 3 A system-level seal that forms a cavity structure. In the first wafer process, the two slopes 22 and 24 are preliminarily suspected, so that the alignment of the two wafers is such that the alignment points a and b on the wafer 3 can be exposed. Wherein, the linear distance of the first oblique side 222 generated after the first-parallel position a flute-f first inclined surface 22 is B, and the (four) ^ vertical point b and the second oblique side 242 generated after the second inclined surface 24 is removed. The straight line 6 f丨 distance B is greater than the first-dare distance m, and the distance D is larger than the second quilted second crystal red contact a, b (four) after the stack is completely loaded and assisted in cutting, and improved In the prior art, when the crystal is to be cut after two days of Hitachi, it is impossible to cut or the accuracy is not good. , C ' is the invention - the embodiment of the two-chip stack cutting method = the first day of the 'step supply - the first wafer has an upper surface and the next granules of the 曰 曰 曰 20 20 20 20 20 20 20 20 20 20 20 It is a wafer with no structure or a wafer with die 4. Wherein, with reference to the embodiment of the second figure, it can be understood that the upper surface of the first wafer 20 and the plurality of first-direction cutting lines have a plurality of cutting lines, and the cutting lines are composed of a plurality of cutting lines. A few spaces are repeated. ', a direction of the cutting line is staggered and then set, then step S502, select a flute a π from m, using the tool along the first, two preset distance m ' and the first preset distance - part, Cutting off the first wafer step S504, removing a flute-to the vertical first wafer 20 from the first n, and the second predetermined distance n is the square η, using the knife fresh The -^ cutting line. Then, in the second preset distance column, the cutter is in the first direction (ie, the parallel portion to remove a second slope. The force (7) the cutter pole is rounded 20 - step S506, providing a second wafer active surface Having at least a pair of sites having an active surface and a back surface; its armor, .r ” plural dies and a plurality of cut macros, 丨 line six: ί two secant lines: a plurality of lines cut by a plurality of first directions The second direction is to cut the calcium H曰 space, and each grain defines a grain: each grain has a mechanical pad, a plurality of pads and a micro-mechanism. - the lower surface of the wafer 20 is moving, and the w is covered and bonded to the ring number I in each of the second wafers 3, so that f - 2G and A plurality of cavities are formed between the two crystals 3 and the micro-mechanisms 304 are located in the plurality of cavities described above. Further, the second wafer 20 has been removed in the pre-step S5〇4, which may be further The plurality of pairs of dots on the second wafer 3 are exposed by the gap formed by the portion of the first wafer 20, and the first wafer 2 and the second wafer 3 are The bonding method can be: using a medium for bonding, or a high voltage, a high temperature or a voltage, and the like is not limited to any of the above methods. 1352386 Step S510 'With the exposed pair on the second wafer 3 The position is used as the alignment and then the position of the strip cutting line is calculated. 'Reusing the tool simultaneously cuts the first wafer 2 〇 and the second wafer 3 ′ to form a system-level package structure having a cavity. Lin (4) completed the light-changing process of the process, the wafer needs to be directly bonded to the die-bonded wafer 20 and the second wafer 3, or the first wafer 2G is applied by external force or vibration. The second wafer 3 is bonded to the die, and each of them is subjected to a subsequent packaging process to form a final product. With the above embodiments, it can be known that the crystal cutting method provided by the present invention can effectively locate the shortcomings of the autumn. It can make it more efficient in the cutting process. _L describes the example of the gamma with two mines as a description, but it does not mean that the two sides are healthy, if the wealth - mine or multiple pairs of points It is a derivation of the spirit of the implementation of the present invention. In the crystal method, the first line is cut to remove at least the bevel, so that when the first wafer and the second wafer are stacked and joined, the opposite position on the second wafer can be exposed to be in the cutting process. The alignment, ^ Exactly cut the first crystal - the second upper grain, so that it can have higher yield in the woman's process; thus, it can effectively avoid the shortcomings of the conventional technology double crystal euro position, and the right The bit error causes a decrease in the yield in the cutting process. The present invention is not limited to the above, but the spirit of the present invention and the inventive entity are suspected to be the same as those of ordinary skill in the art. The use of other elements or means to achieve the same effect is intended to be included within the scope of the following patent application 12 without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart of a conventional technique having an empty structure; FIG. 1 is a schematic view showing a first wafer of an embodiment of the present invention;
腔結構之示意圖；以及 S以具有空 圖五係為本發明一實施例雙片晶圓堆疊之切割方法的流程 圖。 【主要元件符號說明】 2晶圓 3第二晶圓 4介質 20第一晶圓 22第一斜面 222第一斜邊 24第二斜面 242第二斜邊 302環狀墊塊 1352386 304微結構物 306接墊 a、b對位點 200、300晶粒空間 26、28、36、38、260、280 切割線A schematic diagram of a cavity structure; and S is a flow diagram of a method of cutting a two-piece wafer stack according to an embodiment of the present invention. [Main component symbol description] 2 wafer 3 second wafer 4 medium 20 first wafer 22 first inclined surface 222 first oblique side 24 second inclined surface 242 second oblique side 302 annular spacer 1352386 304 microstructure 306 Pad a, b to the site 200, 300 die space 26, 28, 36, 38, 260, 280 cutting line