200915406 九、發明說明： 【發明所屬之技術領域】 本發明侧於-種晶圓蝴之方法，尤其是指—種應用在雙 片晶圓堆疊且具有空腔之晶圓切割方法。 【先前技術】 隨著系統級封裝(System in Package，SIP)的技術發展趨勢曰 漸重要’二維(3D)堆疊構裝的技術，日益受電子產品市場的矚目。 3D堆疊構裝的發展，除了能將記憶體在電路板上所佔的面積大幅 縮小，以提升電子產品縮小化的效率外，更能將原本功能不同的 晶片整合在同一構裝模組中，而以最有效益的方式，達到系統級 封裝的效益。 系統級封裝是指結合單/多片晶片（IC)以及離散、被動元件等 零組件在單一封裝中，提供完整的系統或是次系統，是以封裝技 術來創造較低成本、小體積與高效能的解決方案。系統產品朝整 合及縮裝的方向發展時，除了帶動系統單晶片設計需求外，也促 成了新型態的系統級封裝成為發展焦點。 系統級封裝生產中使用了先進的系統設計方法，分割 (partitioning)與整合專有技術、覆晶技術、線接合(wire b〇nding) 技術、多層堆疊技術、高密度黏著技術，以及最佳化的測試方法 和其它技術；利用以下敘述加以解釋。 請參考圖一，係為習知技術具有空腔結構之雙片晶圓堆疊切 割方法的流程圖。首先，步驟S10，提供一第一晶圓具有一下表 面及一上表面。其中，第一晶圓可以為單純之晶圓或是具有晶粒 200915406 結構之晶圓。 接著，步驟S12，提供-第二晶圓具有一主動面及一背面， 其第二晶圓主動面上具有複數條切割線，其複數條切割線係互相 交錯以形成複數個空格，該些複數個空格中定義出複數個晶粒， 每-個晶粒具有-環狀鏡、複數個接墊及—微型機構。 其中，核狀墊塊之材質通常為環氧樹脂；微型機構係位於環 狀塾塊所定義之空間内，微型機構可以是微主動元件，如：積體 電路、微賊元件或軸元件等，歧織航件，如··感測器、 電容器或電阻器等；複數個接墊係位於環狀墊塊所定義之空間 外，該些接墊係於切割製程後電行連接至外部電路。 …之後’步驟S14，第-晶圓覆蓋且接合於第二晶圓之上，以 形成複數個空腔，使該微型機構位於空腔内；其中，第一晶圓之 下表面(主動面)係面對第二晶圓之主動面。 最後’步驟S16，顧刀具分別切割第—晶圓及第二晶圓， 以形成具空腔之系統級封裝構造。 在習知技術中，因為第-晶圓之下表面係面對第二晶圓之主 動面’然:而，第-晶圓之侧線係位於τ表面上，第二晶圓之切 割線係位於主動面上’因此，t要切鄕_晶圓時需向上表面進 行切割製程’要蝴第二晶圓龍向其背面進行_製程，而第 -晶圓及第二晶圓係為不透明之材質，使得切割製程的實施會有 困難。 因此，發日聽提供-種晶_割之方法，以滿足晶圓切割製 程中切割之準確性，以及對位之方便的需求。 200915406 【發明内容】 本發明之目的在於提供—種晶圓切割之方法，應用在曰 圓堆疊且具有空腔之晶圓切割製財，可實現晶圓切# 準確性以及對位方便的需求。 < 本發明提供-種晶_财法，係應祕雙片晶_ 裝結構，該方法包括：提供一第一晶圓，具有一上表面及: 面；擇定-第-預設距離，並利用刀具以第—預設距離切掉第一 部份以去除-第-斜面；提供—第二晶圓，第二晶圓具有 主動面及-背面，其中，主動面上具有至少_對位點、複數個 晶粒以及複數條切割線，該些切割線係域數條第—方向 複，條第二方向切割線交錯排列而成；覆蓋且接合第—晶圓ς第 二晶圓之上’使第UU上之複數個對健_露於外；以及 由第二晶圓上外露的對位點，做為對位以卿刀具分別切巧第二 晶圓及第二晶圓’鄉成—系統級封裝構造。 ° 【實施方式】 為了解決输所遇到雙片晶圓堆叠時，其切割上所遇 f難及切_準確度之_ ;本發贿供—種晶_割之方法， 圓晶圓製作出兩切面，使第-晶圓覆蓋於-第二晶 圓上=了方便對位及_，能增加其對位之方便及_的準賴。 -曰ft閱圖二’係為本發明一實施例之—第—晶圓示意圖。第 日日 具有一下表面及一上表面。需特別說明的是，此圖中所 ί圖: 3膽該下表面上各氣件_置_。其中， 圖所不’下表面上具有複數條切割線，係由複數條第一方向切 200915406 =線26(在圖中第-方向錢義為平行χ軸之方向)吨數條第二 列t割線28(在圖中第二方向係定義為平行γ車由之方向)交錯排 -太ΪΓΓ!與第二方向係、互相垂直，而第—方向切割線26與第 i = = =互相交狀義出複數個晶粒空間，每-個晶 粒工間200中可以形成一個晶粒(die)。 此實施射之第-日日日BJ 2G，係细—完整的晶圓2先行切除 兩斜面，以提供後續的製程。其中，第一 周同-點起算-第一預定距離m，利用刀具切割== -卿p一第一斜面22)，而產生一第一斜邊從。另一 =如再自上述晶圓2圓周同—點起算—第二職距離n，利用 二切割掉晶圓2左方圓周之一部分(即一第二斜面24)，而產生 一第二斜邊242。 在本實施例中，第-晶圓2G係、為—單純晶圓，其上先行切割 =去兩部分斜面(即第一斜面22與第二斜面24)，且第一晶圓如 表面上並無任何晶粒結構，僅做為覆蓋晶圓㈣wa㈣之 缺 =，第-晶圓2G亦可僅割除—邊斜面，且可選擇使用具有晶^ 構之轉a%®_ee wafef),視其所欲生產之“ 一晶圓20之使用。 六疋弟 一立接者’請配合參職三，係為本發明—實施例—第二晶圓之 不意圖。如圖所示’第二晶圓3具有-主動面(圖情示係為第二 晶圓3主動面)及—麵’絲面上具有複數條切·，係由複數 條第一方向切割線36(在财第一方向係定義為平行X轴之方向） 與複數條第二方向切騎S8(在财第二方⑽定義為平行 之方向)交錯排列而成。 200915406 第一方向與第二方向係'互相垂直，而第-方向切割線36與第 =方向切割線38互相交錯定義出複數個晶粒空間3〇〇，每一個晶 粒空間300巾可以形成一個晶粒_。其中，每一個晶粒具有一 環狀墊塊302、複數個接墊306及一微型機構304。 環狀墊塊3〇2之材質可以用環氧樹脂或其它相類似之材料； 微型，構304係、位於環狀墊塊3〇2所定義之郎内，微型機構3〇4 可以是微主動元件，如··積體電路、微機械元件、移動元件、投 影晶片或光學⑼等，或是微鋪元件，如：麥克風、感測器、 電容器、電阻器、壓力感應器或致動器等；複數倾墊3()6係位 於環狀墊塊302所定義之帥外，該些接塾3〇6係於 電性連接至外部電路。 ^ 需特別說明的是，為進—步說明圖二中第— 分斜面之用意，請對照圖二以及圖三。其中，第二晶圓3200915406 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention is directed to a method of wafer wafering, and more particularly to a wafer cutting method for a dual wafer stack having a cavity. [Prior Art] With the development trend of system-in-package (SIP) technology, the technology of two-dimensional (3D) stacking is increasingly attracting attention in the electronic product market. The development of 3D stacking structure, in addition to greatly reducing the area occupied by memory on the circuit board, in order to improve the efficiency of electronic product reduction, it is also possible to integrate chips with different functions into the same package module. And in the most efficient way, to achieve the benefits of system-level packaging. System-in-package refers to the combination of single/multi-chip (IC) and discrete, passive components and other components in a single package, providing a complete system or subsystem, with packaging technology to create lower cost, small size and high efficiency Able solution. When the system products are developed in the direction of integration and shrinking, in addition to driving the system single-chip design requirements, it also promotes the new state of the system-level packaging to become the focus of development. Advanced system design methods, partitioning and integration know-how, flip chip technology, wire b〇nding technology, multi-layer stacking technology, high-density bonding technology, and optimization are used in system-in-package production. Test methods and other techniques; explained using the following description. Please refer to FIG. 1 , which is a flow chart of a two-piece wafer stack cutting method having a cavity structure in the prior art. First, in step S10, a first wafer is provided with a lower surface and an upper surface. The first wafer may be a simple wafer or a wafer having a die structure of 200915406. Next, in step S12, the second wafer has an active surface and a back surface, and the second wafer active surface has a plurality of cutting lines, and the plurality of cutting lines are interlaced to form a plurality of spaces, and the plurality of spaces A plurality of dies are defined in the spaces, and each of the dies has a ring mirror, a plurality of pads, and a micro-mechanism. Wherein, the material of the nuclear spacer is usually epoxy; the micro mechanism is located in the space defined by the annular block, and the micro mechanism may be a micro active component, such as an integrated circuit, a micro thief element or a shaft component, A woven article, such as a sensor, a capacitor or a resistor, etc.; a plurality of pads are located outside the space defined by the annular block, and the pads are electrically connected to the external circuit after the cutting process. After [Step S14, the first wafer is covered and bonded over the second wafer to form a plurality of cavities such that the micro-mechanism is located in the cavity; wherein the first wafer lower surface (active surface) It faces the active surface of the second wafer. Finally, in step S16, the cutters respectively cut the first wafer and the second wafer to form a system-in-package structure having a cavity. In the prior art, because the lower surface of the first wafer faces the active surface of the second wafer, the side line of the first wafer is located on the surface of the τ, and the cutting line of the second wafer Located on the active surface 'Therefore, t has to cut _the wafer needs to be cut to the upper surface'. The second wafer dragon is to be processed on the back side, and the first wafer and the second wafer are opaque. The material makes it difficult to implement the cutting process. Therefore, the method of providing a seed-cutting method to meet the accuracy of cutting in the wafer cutting process and the convenience of alignment is required. [Invention] The object of the present invention is to provide a method for wafer dicing, which is applied to a wafer-cutting process with a circular stack and a cavity, which can realize the accuracy of wafer cutting and the convenience of alignment. < The present invention provides a seed crystal-finishing method, which is a dual-chip structure, comprising: providing a first wafer having an upper surface and: a surface; a selected-first-predetermined distance, And using the cutter to cut the first portion at a first preset distance to remove the -th-bevel; providing - the second wafer, the second wafer having an active surface and a back surface, wherein the active surface has at least _ alignment a plurality of dies and a plurality of dicing lines, wherein the plurality of dicing lines are multi-directionally aligned, and the second directional cutting lines are staggered; covering and bonding the first wafer to the second wafer 'Make the plurality of pairs on the UU _ outside; and the opposite point on the second wafer, as the alignment, the second and second wafers respectively - System level package construction. ° [Embodiment] In order to solve the problem of double-wafer stacking when the transmission encounters, it is difficult to cut and the accuracy of the cutting. The method of making a bribe - seeding_cutting method, making a wafer The two cut surfaces allow the first wafer to be overlaid on the second wafer = convenient alignment and _, which can increase the convenience of the alignment and the _. - Figure 2 is a schematic diagram of a wafer as an embodiment of the present invention. The first day has a surface and an upper surface. It should be specially noted that the figure in this figure: 3 biliary on the lower surface of each gas _ _. Wherein, the figure does not have a plurality of cutting lines on the lower surface, which is cut by the first direction of the plurality of lines 200915406 = line 26 (in the direction of the first direction of the figure is the direction of the parallel axis) tons of the second column t The secant line 28 (defined as the direction of the parallel gamma in the second direction in the figure) is staggered - too ΪΓΓ! and the second direction is perpendicular to each other, and the first direction cutting line 26 intersects with the i = = = A plurality of grain spaces are defined, and one die can be formed in each of the grain chambers 200. This implementation of the first day-to-day BJ 2G, the fine-complete wafer 2 is first cut off the two slopes to provide a subsequent process. Wherein, the first week starts from the same point - the first predetermined distance m, and the cutter cuts == - qing p a first slope 22), and a first oblique edge is generated. Another = if the distance from the circumference of the wafer 2 is the same as the point - the second duty distance n, one part of the left circumference of the wafer 2 is cut by two (ie, a second slope 24), and a second oblique side is generated. 242. In this embodiment, the first wafer 2G is a simple wafer, and the first wafer is cut first=two portions of the slope (ie, the first slope 22 and the second slope 24), and the first wafer is on the surface. Without any grain structure, it is only used to cover the wafer (4) wa (4). The first wafer 2G can also be cut off only - the bevel, and the crystal can be selected a%®_ee wafef). To produce "the use of a wafer 20. Six 疋 一 立 立 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接3 has an active surface (the picture shows the second wafer 3 active surface) and the surface has a plurality of strips on the surface, which is defined by a plurality of first direction cutting lines 36 (defined in the first direction of the financial direction) The direction of the parallel X-axis is staggered with the second direction of the second direction S8 (defined in the direction parallel to the second party (10). 200915406 The first direction and the second direction are perpendicular to each other, and - The directional cutting line 36 and the directional cutting line 38 are interdigitated to define a plurality of dies spaces 3 〇〇, and each of the dies 300 spaces can be formed. Each of the crystal grains has an annular spacer 302, a plurality of pads 306 and a micro-mechanism 304. The material of the annular spacer 3〇2 can be epoxy or other similar materials. Micro, 304 series, located within the ring defined by the ring block 3〇2, the micro-mechanism 3〇4 can be micro-active components, such as integrated circuits, micro-mechanical components, moving components, projection wafers or optics (9) etc., or micro-ply components, such as: microphones, sensors, capacitors, resistors, pressure sensors or actuators; the complex pad 3 () 6 is located outside the ring pad 302 definition The contacts 3〇6 are electrically connected to the external circuit. ^ It should be specially stated that, for the purpose of the step-by-step oblique surface in Figure 2, please refer to Figure 2 and Figure 3. Two wafers 3
ί ^位點&，且該第—對健a至晶® 2邊緣树之直線距離A 糸“方向垂直’上述之第一預定距離m大於直線距離A，即 m A且第預疋距離m與直線距離a皆以晶圓2 ϋ周上同一點 ===;刀具係沿著Χ軸之方向(即平行第—方向)切割晶 0 2以去除第一斜面22，產生第一斜邊222。 再者’第二晶圓3亦具有 對位點b，當第一晶圓20以ί ^site &, and the linear distance A of the first-to-the-a-crystal® 2 edge tree A 糸 "direction perpendicular" the first predetermined distance m above is greater than the linear distance A, ie m A and the pre-twist distance m The distance from the straight line a is the same point on the wafer 2 ϋ ===; the cutter cuts the crystal 0 2 along the direction of the Χ axis (ie, the parallel first direction) to remove the first slant 22, and the first slant 222 is generated. Furthermore, the second wafer 3 also has a counter point b when the first wafer 20
赞一 as— ^ aa 1SJ ZU J 第-預疋距離η，利用刀具切割掉晶圓2左方之第二斜面Μ時， 倾距離係以第二對健b與晶圓2圓周之_直線距離 仏為-下限值。其巾，第二對位點b至晶圓 C係與第二方向垂直H定距離n大於直線距離c，離 it預歧離n與直線距離c皆以晶圓2圓周上同—點開始起 算距離，刀具係沿著γ軸之方向(即平行第二方向)_晶圓2以 200915406 去除第一斜面24，產生第二斜邊242。 ，參閱圖四’係為本發明—實施例第—晶圓與第二晶圓堆疊 以、有空腔結構之剖面圖。圖四中所示之剖面，係為圖二令第一 晶圓20與圖三令第二晶圓3堆叠後之肥切面， 乃 述實施例之第-晶圓20與第二晶圓3，經過邊緣對位、^後， =用-，質4加以黏著第—晶圓2G與第二晶圓3，·或是不使用 »質，而疋利用南溫、高魔或電壓等方式，將第一晶圓2二 晶圓3加以堆疊固定。其中，介質 ^ 一 及銲錫等_。 f 了 7"撕、_、金屬 虽第-晶圓20覆蓋且接合於第二晶圓3之上時，由二曰 粒中之環狀墊_具有一高度，會使第一晶圓一二 ^一I 成一空腔結構之系統級封裝。又第一晶圓20 當製== 除兩斜面22，，旨在前述兩晶圓堆疊後，使 ^曰曰圓3上的對位點a、b可以顯露出來。其中，第—對位點& 後所產生之第一斜邊222的直線距離為B，而 第-對健b與去除第二斜面24後職生 =，，係大於第-預定距離m，距離D係 1= 娜a、b㈣在料後完全 辅助_時之定位需求’並改善習知技術中當兩 片阳圓堆豐後’欲切割晶粒時無法切割或準破度不佳的情形發生。 的:=閱，發明一實施例雙片晶圓堆疊之切割方法 =圖。曰百先’步驟S500 ’提供一第一晶圓具有一上表面及下 τ概輸繼叙纖是具有晶 、4之日日圓。其中，配合參考第二圖所繪示之實施例，可瞭解 200915406 上述之第一晶圓20之上表面具有 複數條第-方向切割線複數條第線’該些切割線係由 義出複數個空格。 線交錯排列而成並定 接著，步驟S502，擇定一第 離m，利用刀具沿著第一方向111 ’並以第一預設距 -部份’以去除-第-斜面。 方向)切掉第-晶圓20 步驟S504，擇定一第二預設距離11 * ^，利用刀具沿著第二方^(即平〜 °!線 接著，以第二預設距離 -- 步驟S506,提供一第二晶圓3星右 主動面上具有至少—騎點=個有:^動面及—背面；其中， 線，祕切割㈣由複數純日粒㈣以及複數條切割 線交錯排列以形成複數個空格，每一個空格中定 :：丨 母-個晶粒具有-環·塊、複數個接墊及—微型機構，“ ’ ^後，步驟纖’將第—晶圓2〇之下表面正對 $動=並經過邊緣對位、校準後，使第—晶圓2Q覆蓋與曰接^赞一阿— ^ aa 1SJ ZU J The first pre-twist distance η, when the second bevel 左 on the left side of the wafer 2 is cut by the cutter, the tilt distance is the linear distance between the second pair of health b and the circumference of the wafer 2仏 is the lower limit. The towel, the second pair of sites b to the wafer C is perpendicular to the second direction, and the fixed distance n is greater than the linear distance c, and the distance between the pre-discrimination n and the linear distance c is calculated from the same point on the circumference of the wafer 2. The distance, the tool is along the gamma axis (ie parallel to the second direction) _ wafer 2 removes the first slope 24 with 200915406, resulting in a second bevel 242. Referring to Figure 4, the present invention is a cross-sectional view of a wafer structure and a second wafer stack having a cavity structure. The cross-section shown in FIG. 4 is the fat cut surface of the first wafer 20 and the third wafer 3 stacked in FIG. 2, which are the first wafer 12 and the second wafer 3 of the embodiment. After edge alignment, ^, = with -, quality 4 to adhere to the first wafer 2G and the second wafer 3, or not use the quality, and use the South temperature, high magic or voltage, etc. The first wafer 2 and the second wafer 3 are stacked and fixed. Among them, the medium ^ and solder _. f 7"Tear, _, metal, although the first wafer 12 is covered and bonded on the second wafer 3, the annular pad in the two granules has a height, which makes the first wafer one or two ^I I is a system-in-package of a cavity structure. Further, the first wafer 20 is formed as == except for the two inclined surfaces 22, and after the stacking of the two wafers, the alignment points a and b on the circle 3 can be exposed. Wherein, the linear distance of the first oblique side 222 generated after the first-parallel position & is B, and the first-to-be-birth b and the second oblique surface 24 are removed after the second grade, the system is greater than the first-predetermined distance m, Distance D system 1 = Na a, b (four) after the material is fully assisted _ positioning requirements 'and improved in the conventional technology when two pieces of yang round piled up 'when cutting crystals can not cut or poorly broken conditions occur. The method of cutting a double wafer stack is shown in the following figure. The first step S500' provides a first wafer having an upper surface and a lower surface. The first wafer has a crystal, and a day of the day. With reference to the embodiment illustrated in the second figure, it can be understood that the upper surface of the first wafer 20 described above has a plurality of first-direction cutting lines and a plurality of first lines on the surface of the first wafer 20, and the cutting lines are determined by a plurality of Space. The lines are staggered and then determined. Next, in step S502, a first deviation from m is selected, and the tool is used in the first direction 111' and the first predetermined distance - portion 'to remove the -th-bevel. Direction) cut off the first wafer 12 step S504, select a second preset distance 11 * ^, and use the tool along the second square ^ (ie, the flat ~ °! line, followed by the second preset distance - step S506, providing a second wafer 3 star right active surface having at least - riding point = one: ^ moving surface and - back; wherein, the line, the secret cutting (four) is interlaced by a plurality of pure Japanese particles (four) and a plurality of cutting lines To form a plurality of spaces, each space is determined:: 丨 mother - a die has a - ring · block, a plurality of pads and - a micro-mechanism, " ' ^ after the step fiber ' will be the first wafer 2 The lower surface is facing the movement = and after the edge alignment, after calibration, the first wafer 2Q is covered and spliced ^
日圓3之上。此時’由於第二晶圓3上每—晶粒中之I 龄ΓΓ2具有一高度’會使第一晶圓20與第二晶圓3之間形成複 、固工腔’且該微型機構304位於上述之複數個空腔内。又 分之第-晶圓20已於前置步驟S5〇4中被移除，可進—步透過被 移除之部分第-晶圓20所形成的缺口使第二晶圓3上之複數個 位點顯露於外；其中’第―晶圓2G與第二晶圓3之接合方式 ，利用介質加_著接合，或是利用絲、高溫或賴之方式堆 疊固定等，並不以上述任一方式為限。 11 200915406 4!驟S51G ’藉由第二晶圓3上外露的對健，做為對位並進 而隹算複數條切割線之位置所在，再利用刀具同時切割第一 20及第二晶圓3 ’以形成具空腔之系統級封裝構造。 曰日 此外，亦可將卿縣叙晶粒__縣餘 要將第-晶11 20與第二晶圓3相接合之晶粒直接進行封餘序^ 或是施以-外力或振動的方式將第一晶圓2〇與第二晶圓3 之晶粒分開，各自進行後續封裝程序，以製成最終產品。σ 藉由上述實_ ’可以知道本發騎提供之晶_割方法， 可以有效避免晶®定位_之缺點，使其在_製程巾 的效率。又上述實施例係以每—晶片具有兩個對位點做為說明同 但並不代表限定於兩轉健，若僅有—鑛位點或是複數 位點亦為本發明實施精神之推衍。 本發明酸供的晶綠，將第—晶·行切割去除至 少-斜面，使第-晶圓與第二晶圓相堆叠接合時，可以將第二晶 圓上之對健外糾來’以便在切割製程巾㈣精準對位，並準 確的切割第-晶®與第二晶圓上之晶粒，使其在蝴製程中能有 更高的良率；如此，可以有效避Μ知技術雙晶圓定位困難之缺 點，以及因對位錯誤而造成切割製程中良率的降低。 、本發明雖雜佳實__如上，祕並_珊定本發明 精神及發明實體。騎屬技術領域巾具有通常知識者，當可輕易 瞭解並利用其它元件或方式來產生相_功效。是以，在不脫離 本發明之精神及範圍内所作之修改，均應包含在下述之申請專利 12 200915406 範圍内。 【圖式簡單說明】 圖一係為習知技術具有空腔結構之雙片晶圓堆疊切割方法的 流程圖； 圖一係為本發明一實施例一第一晶圓之示意圖； 圖三係為本發明一實施例一第二晶圓之示意圖； 圖四係為本發明一實施例第一晶圓與第二晶圓堆疊以具有空 腔結構之不意圖；以及 圖五係為本發明一實施例雙片晶圓堆疊之切割方法的流程 圖。 、 【主要元件符號說明】 2晶圓 3第二晶圓 4介質 20第一晶圓 22第一斜面 222第一斜邊 24第二斜面 242第二斜邊 302環狀墊塊 13 200915406 304微結構物 306接墊 a、b對位點 200、300晶粒空間 26、28、36、38、260、280 切割線 14Above the yen 3. At this time, 'there is a height ' between each of the first wafer 20 and the second wafer 3 due to the height I of each of the dies 2 in the second wafer 3, and the micro-mechanism 304 is formed. Located in the plurality of cavities described above. Further, the first-wafer 20 has been removed in the pre-step S5〇4, and the plurality of second wafers 3 can be further advanced through the gap formed by the removed portion of the first wafer 20. The site is exposed; wherein the bonding method of the first wafer 2G and the second wafer 3 is performed by using a medium plus a bonding method, or by using a wire, a high temperature or a stacked method, and the like. The method is limited. 11 200915406 4! Step S51G 'Through the exposed pair on the second wafer 3, as the alignment and then calculate the position of the plurality of cutting lines, and then use the cutter to simultaneously cut the first 20 and the second wafer 3 'To form a system-in-package configuration with a cavity. In addition, the grain of the county may be directly sealed or the external force or vibration may be applied to the grain in which the first crystal grain is joined to the second wafer 3. The first wafer 2 is separated from the die of the second wafer 3, and each is subjected to a subsequent packaging process to form a final product. σ By the above-mentioned real _ ', it can be known that the crystal cutting method provided by the present riding can effectively avoid the disadvantage of the crystal positioning, making it efficient in the process towel. In addition, the above embodiments have two pairs of sites per wafer as the same description but do not mean that they are limited to two rotations. If only the ore sites or complex sites are also the derivation of the spirit of the invention. . The crystal green provided by the acid of the invention removes at least the bevel from the first crystal and the row, so that when the first wafer and the second wafer are stacked and joined, the pair of mats on the second wafer can be corrected. In the cutting process (4) precision alignment, and accurately cut the crystal on the first crystal and the second wafer, so that it can have higher yield in the butterfly process; thus, it can effectively avoid the technical double The shortcomings of wafer positioning difficulties and the reduction in yield during the cutting process due to misalignment. Although the present invention is very good, the above is the secret and the invention entity. The technical field of the rider has a general knowledge when it is easy to understand and utilize other components or means to produce phase-effects. Therefore, modifications made without departing from the spirit and scope of the present invention are intended to be included in the scope of the following patent application 12 200915406. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart of a two-piece wafer stack cutting method having a cavity structure according to the prior art; FIG. 1 is a schematic view of a first wafer according to an embodiment of the present invention; 1 is a schematic view of a second wafer according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a first wafer and a second wafer stack having a cavity structure according to an embodiment of the present invention; and FIG. 5 is an embodiment of the present invention. A flow chart of a method of cutting a two-piece wafer stack. [Major component symbol description] 2 wafer 3 second wafer 4 medium 20 first wafer 22 first inclined surface 222 first oblique side 24 second inclined surface 242 second oblique side 302 annular spacer 13 200915406 304 microstructure 306 pads a, b pairs of sites 200, 300 die spaces 26, 28, 36, 38, 260, 280 cutting line 14