TWI313509B - Manufacturing method for phase change ram with electrode layer process - Google Patents

Description

084 is called 35呦17261twf.doc/〇〇6 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to materials and other material materials based on dryness of the shoe (including methods based on the same.) Read (10) skirting 'and related to manufacturing this [previous technique] phase change based memory material wide. Laser pulse is used to read 00-like crystalline solid phase change after reading material == conversion between phases, and in The memory of the change is also possible by applying a level suitable for implementation in the integrated circuit. The amorphous state is characterized by a specific electrical resistivity, which can be easily Ground sensing to display data. This; special = high-intensity memory circuit, random access can be used to form non-volatile amorphous state until the change of crystalline state is usually lower current operation. From 曰 energy = state two change two Called reset, usually compared to:: It includes -1 gold μ noise _ recorded

After this, the phase change material rapidly cools, suppressing J: part of the phase change junction and stabilizing in the amorphous state. Minimizing the magnitude of the current used to cause the phase change k is the reduction of the size of the t-cup and the contact area of the material of the tissue material to reduce the amount of reset current required for resetting. : I31350S〇84 17261twf.doc/006 Higher current densities can be achieved with smaller absolute current values through phase change material components. A development trend has tended to form small holes in the integrated circuit structure and to fill the small holes with less i-redformable resistive material. The patents for the development of the small hole include: US Patent No. 5,687,112 issued on November 11, 1997. 'Ovshinsky' Multibit Single Cell Memory

Element Having Tapered Contact"; U.S. Patent No. 5,789,277, issued to A.S. Patent No. 5, 789, 277, issued to A.S. Pat. Controllable Ovonic Phase-Change Semiconductor by Doan et al.

Memory Device and Methods of Fabricating the Same"; US Patent No. 6,815,704 B1, issued on November 9, 2004, "Phase Change Memory Device Employing Thermally" by Chen

Insulating Voids". Other techniques include the formation of small electrodes for contact with larger bodies of phase change materials, such as U.S. Patent No. 6,797,979 B2, issued September 28, 2004, and "Metal Structure for a Phase-" by Chiang et al. "Change Memory Device" is described. There are several problems in the manufacture of these devices with very small dimensions and process variations that meet the strict specifications required for large-scale devices. Therefore, it is necessary to provide a small size and A memory cell structure with a low reset current, and a method of fabricating such a structure that meets the stringent process variation specifications required for large-scale memory devices. It is further desirable to provide a fabrication process and structure that is identical to the process and structure Compatible with the 丨4 17261 twf.doc/006 circuit on the integrated circuit. Hsiang-Lan Lung and Shih-Hung Chen, co-pending U.S. Patent Application Serial No. 11/155,067, filed June 17, 2005 A title is described in "THIN FILM FUSE PHASE CHANGE RAM AND MANUFACTURING METHOD" (Lung et al.) Minimum configuration for implementing the phase change memory device, the application now and at the same assignee of the invention 'and in a fully herein by reference as if set forth herein incorporated by this invention.

^ The structure described in the Lung et al. application comprises a thin film bridge having a small size of phase material, which spans from the first electrode to the second insulating layer by two walls, wherein the first electrode and the second electrode are formed. In the integrated electrical layer towel. It is desirable to provide a fabrication layer that is effective for a small size phase change bridge unit. [Summary of the Invention]

The large memory cell PC cleavage is described as being suitable for fabricating a quaternary memory device in which an insulating m electrode between the package electrode and the second electrode is defined across the insulating member = two-path length. The structure of the road defined by the width of the edge member for illustrative purposes (4) in the phase change device is imagined to have a class-like silk bridge comprising at least two types of reversible: the corpse in the genus, the material, for example based on the sparse I3135〇a 丨084 17261t\vf.d〇c/006 Γ: The reversible is achieved by applying a current through the material or applying a voltage across the electrode.体积 The volume of the phase change memory material body can be very thick (path length in the X direction), determined by the edge of the device. In the direction of the ) ) 元 微 微 限制 限制 限制 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the present invention, the width may be smaller than the minimum feature size F, and the last used for the material layer patterning is to use the photoresist trimming technique to define the width of the bridge, and the isotropic The narrowly trimmed photoresist structure that trims the photoresist is then used to lithography the other integrated circuits on the integrated circuit (4). Therefore, 'has a simple junction and is easy to achieve a small reset current and a lower power consumption. In the technique of bribery, it is provided that the 'multiple electrode members in the array and the upper electrode layer therebetween' . The electrode layer has a top surface. Corresponding plurality of film bridges spanning the insulating members between the yak comprise: establishing a film bridge on the surface of the first electrode from the electrode layer of the electrode layer to reach the electrode layer 13135flfl)84 17261twf.doc/006 13135flfl)84 17261twf.doc/006 Electrode's audible, "Every second memory list for __ can be used for logic circuits and: CM〇S technology" to achieve this article The circuit of the example. In one embodiment, the electrode pair below the electrode layer on the circuit (4) J case under a second electrode::,) has a connection between == the second electrode for use The electric parts on the electrode layer of the = road are shaken & ^ 疋 /, so that the electrode parts of the soap are _ secret material _ - two memory cells of the towel. In the spoon, the method of making money is set. The method includes: forming an electrode layer on a substrate of a circuit fabricated by a front-end process. The charging technique is used to form electrodes in the electrode layer, and the technique also uses a layer-to-metallization layer to improve the process of scaling the shortened critical dimension of the metallization layer. In the embodiment of the manufacturing method, the bakelite layer is fabricated by the following process. The process is based on forming a multilayer dielectric layer on the substrate, and engraving the multilayer dielectric layer to form a circuit for the electrode thief. Through hole. Subsequently, an insulating spacer is formed on the sidewall of the through hole. Then, the top layer of the plurality of dielectric layers is removed between the insulating spacers to form a trench between the via holes, and the through holes pass through the insulating gap I31350fi〇84 17261twf.doc/006 In forming an electrode portion contacting the upper circuit

LrL:: fills the through holes and trenches. Grinding the formed structure by a chemical machine, removing the top of the conductive material, defining the first and the first side of the insulating spacer: the first and the second electrode and the insulating spacer It is exposed on the top surface' and acts as an insulating member, a first electrode and a second electrode.

The conductive material comprises a block conductor (for example, a copper or copper alloy suitable for filling through holes and trenches), a first layer, and a second body made of a junction body (for example, TM suitable for contacting the phase change bridge). Floor. The process disk is conventionally CMOS fabrication technology compatible, and since it is filled with Cu, it can be easily and easily scaled with a shortened critical dimension.

A method of fabricating a memory device comprising a programmable resistive material as described herein includes forming a circuit in a substrate having a top surface, the circuit comprising an array of contact windows on a top surface of the substrate. A multilayer structure is formed on the substrate by the array of contact windows. The multilayer structure includes at least a first dielectric fill layer, an etch stop layer on the first dielectric fill layer, and a second dielectric fill layer on the etch stop layer. Subsequently, the multilayer structure is etched in a pattern comprising contact vias that expose selected contact windows in the array of contact windows on the top surface of the substrate. A sidewall dielectric spacer is formed on the sidewall of the contact via, and the multilayer structure is covered with a sacrificial material to fill the contact via. Selectively etching the sacrificial material in a pattern including an opening exposing an electrode region and a sidewall dielectric spacer on the multilayer structure, stopping near a top surface level of the second dielectric filling layer = 10 13135(10) 084 丨7261 twf.doc/006 ^Removing the second dielectric fill layer in the electrode region, stopping ϋ' to form electrode trenches in the multilayer structure, and then channeling the sidewalls, then moving from the contact vias to the opening pairs: , open the wall, fill the contact window through hole and electrode ditch =. Lower level (10) into electricity = except: = = wall of the "material compatible electrode material filling pole = ancient, private resistance: = _ two = storm groove dew = second electrode: filling the individual filling The contact window via and the top of the electrode layer serving as an array are provided and include electrodes on the face of the array of electrodes, the bridge array comprising contacts and dielectrics between the sidewalls and the individual first And the second electrode bridge extends over the first and the first individual top surfaces. The path, the right side of the roadway fixture defines the electrical pathway between the insulating members. The patterned conductive layer is formed to be wide; the second electrode of the defined path length is in electrical communication. On this bridge, the sub-array and the array of electrodes are easy to understand, and the features, advantages and advantages can be more obvious. ^Example 'Sub-combination of the drawing' is described in detail as 11 > 84 17261 twf.d 〇 c / 006 [Embodiment] Mai see Figure 1 to Figure 18, providing an array of thin film phase change memory, and manufacturing The method of these memory cells =, therefore, the memory Figure 1 illustrates a memory field description including on an electrode layer. The basic structure of the cell, which includes the first bridge electrode 13, and the younger one of the first electrode 12 and the second electrode 13. As shown, the first and second electrodes 12, 13 = insulating members and B. Similarly, the insulating member 14 has a top surface 14 of the surface 4 of the surface of the surface 12a, and (5) defines a wide, substantially flat top surface of the electrode layer. In the poor memory case, the electrode is on the flat top surface of the electrode layer, so that the bridge U is located at the bridge

Shape = contact between the 1st pole and the bridge 11 and the contact between the second electric = bottom side. In JL, he is the same as the bridge U. The electrode 13 and the bridge U are four sides: the surface is more detached from the electrode material. Active area in the bridge, wide I)

The first electrode 12 is formed by the cell structure, and the first electrode 12 is not formed by the structure of the brother, and the banding and the 1C electrode 12 between the electrode and the electrode 13 are connected to each other.亓6Α ° and the first electrode 丨3, for # two cr: can be programmed to make a solid phase. For example, a memory material can be used to reversibly implement the use of a chalcogenide-based phase change memory material for the two memory I teeth, which can be at a relatively high resistivity state, at least partially dry of the T-bridge in the bean. ^T is in the current path rate state, 1 is sad, and can also be set in a relatively low resistance /, in the electric '4 diameter, most of the bridge is in a crystalline state. 131350) S〇84 17261twf.doc/006 Figure 3 shows the active channel 16 in the bridge U, where the primary material = the area that is sensed to change between at least two solid phases. It can be appreciated that the active channel 16 can be made to account for the magnitude of the current required to cause a phase change in the illustrated construction. ..., 攸 and reduce the first - ^ ^ ^ yuan (four) important wealth. The insulating member 14 (referred to as a channel dielectric in the figure) of the first electrode 12 and the second electrode is shown in the length L (x direction) of the active channel. The width of the insulating member 14 can be established by using the width of the solid-in-insulating member 14 of the single-turn, which can be used at 1 pole = = upper 14 sidewall dielectric using a thin film deposition technique. Thus, embodiments of the memory cell have a pass length less than the coffee nm and have a channel length L of about 40 mm or less. In another case, the actual = two channel length is less than 2. Nm. It will be appreciated that, depending on the particular application;; the use of Lai deposition techniques (such as atomic layer deposition and similar techniques) can result in channel lengths [even less than 20 nm. Also, in the embodiment of the memory unit, the bridge thickness T (y direction) can be small. This bridge thickness τ can be established using a thin film deposition technique on the top surfaces of the first electrode 12, the insulating member 14, and the second electrode 13. Thus, the embodiment of the memory unit has a bridge thickness of about 5 〇 nm or less. Memory Sheet = Other embodiments have a bridge thickness of about 20 nm or less. In the other two, the thickness τ is about i 〇 nm or less. It will be appreciated that the use of thin film deposition techniques (eg atomic layer deposition: a similar technique) may result in a bridge thickness T of even less than (1) (10), with at least two solids 13 13 1 3 5 θ9 > 〇Β 4 17261 twf.d, depending on the purpose of the component. 〇c/〇〇6 = inverse two through the material - and the second electrode is applied ^ (four) pressure to make it a bridge width w as shown in Figure 4 (the z-direction is chosen to achieve this bridge width w, so that It is small in size. In some embodiments, embodiments of the memory cell having a bridge width wV of J at 1 〇 0 include phase change based = or less.

1 including among the chalcogenide-based materials and the other materials for the bridge including the oxygen (the tree, the chalcogen (Se) and the cerium (Te)) forming part of the group VI of the periodic table. Any one of ^(8), shixi = positively charged element or free radical chalcogenide compound each containing sulfur of other substances (such as transition metals), chalcogenide alloy usually contains - or - (d) from the week ^ Elements of the six rows, such as the domain (Ge) and tin (Sn). The chalcogenide compound includes one or more combinations containing (sb), gallium (Ga), copper (ϊη), and silver (Ag). Many phase change based memory materials have been described in the technical literature 'including Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te,

Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/ 5 Meng of Se/Te and Te/Ge/Sb/S. Various alloy compositions are available in the Ge/Sb/Te alloy family. The composition is characterized by TeaGebSblO〇-(a+b). A researcher has described the most useful alloys with an average concentration of Te in the deposited material suitably below 70%, typically below about 60%, and generally ranging from as low as about 23% to 58% Te, and more Preferably, the concentration of Te°Ge is about 5% or more, and the average value in the material ranges from the lower 14 Ι 3135 Θ » 84 17261 twf. doc / 006 to about 8% to about 30%, generally Keep below 50%. More preferably, the concentration of Ge varies from about 8% to about 40%. In this composition, the remainder of the main constituent elements is Sb. These percentages are atomic percentages based on the total 100% of the atoms constituting the element. (Ovshinsky ‘112 patent, l〇-l 1 line.) Another researcher estimated that the special alloys include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7. (Noboru

Yamada Potential of Ge-Sb-Te Phase-Change Optical

Disks for High-Data-Rate Recording" ,SPIE ν·3109,28-37

Page (1997). More generally, transition metals such as chromium (Cr), iron (Fe), nickel (Νι), ruthenium (), palladium (pd), platinum (Pt), and mixtures or alloys thereof can be combined with Ge/Sb/Te A phase change alloy having a programmable resistance characteristic is formed. Specific examples of usable memory materials are given in 〇vshinsky '11211_13, which are incorporated herein by reference.

In other words, the phase change ί金 can be transferred between the first structural state and the second structural state, and the material in the structural state is generally in an amorphous solid phase, and the first upper velvet towel is in the wire passage of the unit. The regional towel material has a crystalline solid phase in its local order. These alloys are at least bistable. The term ''non-ordered': a relatively unordered structure, has no more term than a single crystal. "Crystals: for example, higher resistivity than crystal phases. Structure is more orderly, recking for more ordered structures' Ratio-amorphous resistivity. Generally, there are measurable characteristics, such as lower than the amorphous phase - the inter-spectral core ==: the more completely amorphous and the completely crystalline, between the detectable states Electrical conversion is carried out. Ι3135θ9〇84 17261twf.doc/0〇6 Other material characteristics affected by the amorphous phase and the crystal phase, including atomic subconversion to two or more solid phases, two t:; side phase Or provide a complete gray state - gray level = in (all amorphous state changes. The electrical properties in the material can be made by applying electrical pulses, the phase can be combined into one. It has been observed that - shorter, _古二', the change of the state of the language to another material changed to a general non-曰^::: The amplitude pulse tends to change the phase change phase change material to 'two lower amplitude pulses tend to make the amount high enough to allow breaking :Two structures:::The energy of the punch is rearranged to a crystalline state and ^ is short enough to prevent the original, and In the case of a suitable experiment, the appropriate rim of the pulse can be determined, especially suitable for the following part of the specific phase change f, the phase change material refers to 1, the other can be used for the present invention. Other implementations of t = tN2 doped GST, GexSby, or other materials that use different crystal phases to retard the electrical resistance; PrxCayMn〇3, p&Mn〇3,

Zr〇x' or use electric pulse to change Wei 阻 四 氛 氛 WT WT WT WT WTCNQ), methylene fuller 6,6 phenyl (10) butyric acid methyl vinegar (PCBM), TCNQ-PCBM, Cu-TCNQ , Ag-TCNQ, C60TCNQ are doped with TCNq of other metals, or any other polymeric material having a bistable steady state resistive state controlled by electrical pulses. The following is a brief overview depicting four types of resistive memory materials. No. 16 13135 〇9°084 17261tvvf.doc/006 - Type is chalcogenide material 'for example 2:2:5, or X is 0~5, y is 〇~ς : ^ where x:y:z = can be substituted Other compositions doped with, for example, NI, Q~1Q are used. An exemplary controlled splashing method for the formation of chalcogenide materials by GeSbTe NN, Sl_, ^- or other elements, the towel (4) Μ A or magnetic butyl water, your milk is Ar, N2 and / or He shrug, the late force is 1 m to 1 〇〇亳 m 2 to find, press ^ ] 5 < 6 ^ 7 m * hang in, to complete the deposition under the dish. A collimator with a field ratio of 1 to 5 can be used to improve the filling performance. In order to improve the filling property, the monthly bias b ′ can also use a DC bias of several tens of volts to the total stone, and the singer of 1 π is 100 volts. Alternatively, a combination of a DC bias and a collimator can be used. It is optional to perform a post-deposition annealino t + , ahng treatment in a vacuum in the form u, 甲 m, 44, ί:^, to improve the crystallization state of the chalcogenide material. The annealing temperature generally fluctuates within the range of i 〇〇 〇 c to _ % where the annealing time is less than 3 〇 minutes. ~ The thickness of the T-based material depends on the design of the cell structure. In general, a sulfur-wet material having a thickness greater than 8 nm may have a phase change characteristic, thereby causing the material to exhibit at least two stable resistance states. "Applicable, the second type of memory material of the embodiment is a giant magnetoresistance ("CMR") material, such as PrxCayMn〇3, wherein χχ5: 〇5, or X is G~Bu y is 〇~1 other composition An alternative is to use a CMR material including manganese oxide. Forming a CMR material (4) showing a pvD impurity or a magnetron tube: a plating method in which the source gas is Ar, n2, 〇2, and/or He, etc., the pressure is 1 mTorr to 100 mTorr. The deposition temperature can be increased from 17 13135 ΘΘ〇 84 17261 twf.doc/006 at room temperature to 6 ° C depending on the post-deposition treatment conditions. The aspect ratio can be used as 1 Improve the filling performance. In order to improve the filling performance, it can also make the DC bias to several hundred volts. On the other hand, it can make the combination of the cake and the straightener at the same time. It can apply dozens of Gauss to as many as one a ^OOGthj The magnetic field of the magnetic field to improve the magnetic crystalline phase., + pull 1 remote control annealing in vacuum or N2 environment or ambiguous mixed environment to improve the crystal state of CMR material. Annealing

The dish was changed within the range of 400 C 600 0C, and the annealing time was less than 2 hours. The thickness of the CMR material depends on the design of the unit structure. CMR with a thickness of 10 nm to 200 nm can be used as the core material. A ybc〇 (YBaCu03's type of superconducting superconductor material) buffer layer is often used to improve the crystalline state of CMR materials. YBC〇 is deposited before the CMR material is deposited. The thickness of YBCO varies from 3 〇 nm to 2 〇〇 nm. The second type of 5 memory material is a two-element compound, such as Nix〇y, TixOy, AlxOy, WxOy, Znx〇y, Zrx〇y, CUx〇y, etc., and its towel x:y = 〇 5:〇],

Or x is another composition of 〇~i and y of 0~1. An exemplary formation method uses a PVD scale or a magnetron hybrid method in which the reaction gas of the towel is Ar, N2, 〇2, and/or He, etc., at a pressure of 1 mTorr to 丨 mTorr, and a target of a metal oxide is used. For example, NixOy, TixOy, Alx〇y, Wx〇y, Znx〇y, ZrxOy, Cux〇y, and the like. The deposition is usually carried out at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve filling performance. To improve the filling performance, a DC bias of several tens of volts to several hundred volts can also be used. If necessary, use a combination of DC bias and collimator on the same day. 18 13135 &9〇84 17261twf.doc/006 It is optional to perform post-deposition annealing treatment in a vacuum or in a NZ environment or a 〇ζ/Ν2 mixed environment to improve the oxygen distribution of the metal oxide. The annealing temperature is usually varied from 400 ° C to 600 ° C and the annealing time is less than 2 hours. The alternative formation method uses a PVD splash bond or magnetron sputtering method in which the reaction gas is Ar/02, Ar/N2/02, pure ruthenium 2, He/02, He/N2/〇, etc., and the pressure is 1 mTorr. To 100 mTorr, a dry metal oxide is used, such as Ni, Ti, Al, W, Zn, Zr or Cu, and the like. The deposition is usually carried out at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve fill performance. To improve the filling performance, a bias voltage of several tens of volts to several hundreds of volts can also be used. A combination of DC bias and collimator can be used at the same time if desired. Annealing after deposition in a vacuum or in an N2 environment or a 〇2/N2 mixing ring can be optionally performed to improve the oxygen distribution of the metal oxide. The annealing temperature is usually between 400 〇C and 600. The range of (: varies, the annealing time is less than 2 hours. Also - the formation method uses a high temperature oxidation system (such as a furnace or rapid heat pulse ("RTP") system) for oxidation. The temperature is between 2 〇〇〇 c and 7 〇〇. 〇c varies within the range of 'the pure 〇2 or n2/〇2 mixed gas pressure is a few millitorr to i standard atmosphere Μ. The time can vary from a few minutes to a few hours: another - oxidation method is plasma oxidation Pure 〇 2 or 丨 托 〇〇 ; ; ; ; 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆For example, Ni, Ti, Al, W, the emulsion varies from room temperature to temperature, depending on the degree of plasma oxidation of the electricity 19 Ι 3135 Θ 9 〇 84 1726Itwf. doc / 006. The fourth type of memory material is a polymer material, such as doping. Cu, Ag, etc. TCNQ ' or PCBM_TCNQ mixed polymer. The method uses thermal evaporation, electron beam evaporation or molecular beam epitaxy ("fine / f system. In a single chamber t co-evaporated egg g τ described solid TCNQ and blended The dopant ball is placed in a boat or a boat, and a high current or electron beam is applied to convert the source, so that Material mixing: Sub-deposit on the wafer. There is no anti-touch chemical f or gas. Deposition is carried out under the pressure of the two-hopper. The wafer temperature varies from room temperature to 200 C. The composition of the polymer material at the annealing after deposition in a vacuum or in an n2 environment. The annealing temperature is less than 1 hour from room temperature to 内 within the anneal. The structure of the Iffield PCRAM cell. The cell is formed on a semi-conductance estimator. For example, a shallow trench isolation STI dielectric (not shown) is separated by a pair of memory cell access transistors in pairs. By acting as a common two, V": 26 n-type terminal And forming the access transistor as a bungee region 25 2^ in the p-type substrate 20. The eutectic second word line m2 draws the idle pole of the transistor. The dielectric filled layer (not shown) On-line, patterned layer and conductive structure, including co-tungsten or quotient for i-field plug structures 2 9 and 3 G. The conductive material can be ^ 〇 σ and fill the common source along the columns in the array Line. Plug, ·, .29 and 3G contact the miscellaneous areas 25 and 26, respectively. 20 I313509〇84 17261twf.d〇c/006 Source line 28 and plug structure 29 with a substantially flat top σ卩 surface suitable for forming electrode layer 31. ΓIncluding electrode material 32, 33, crucible and base member 39. Separating the electrode material, the insulating member includes, for example, by the sidewall treatment described below. In the embodiment, the base member 39 can be stacked, thickened, and separated from the source line 28 The base member can be made to be much narrower because the capacitance between the common source wood wire 28 and the electrode member 33 needs to be reduced. In the description =J block 35a, 35b is included in the electrode part % side ^

= :=: A film bridge 36 made of a certain electrode J on the side wall (for example, (10)) is positioned on the traversing electrode layer 31 to form a first memory unit, and The film bridge 37 is positioned on the electrode layer 31 on the other side of the enclosure to form a second memory unit. A dielectric fill layer (not shown) is located on the film bridge 36, and the dielectric fill layer comprises a dioxide dioxide and a polyimide II dielectric fill material. In an embodiment, the dielectric is charged with a thermal and electrical insulator to provide heat to the bridge; and the second::: 38 contacts the electrode member 33. A patterned conductive conductor comprising a bit line in a metal or other bird interposer structure is placed on the lightning array layer and contacts the plug 38 to provide access to an oppositely filled memory cell. Domain, Yulai Bridge 36 and film bridge 37 21 1313508 (10) 1726ltwf.d〇c/〇〇6 ^ show the semiconductor substrate of Figure 5 in a decorative diagram, along the common source (four) of the memory cell array Structure. Because of the common source line 28, the layout word line is largely parallel to the t pole 3; the conductor base "the terminal of the lion transistor is on the households ^32, 33 and 34, and the insulating barriers 35a, 35t enable The electrode members are separated. The lower side of the electrode _OFF = 3 b between the contact film bridges 36 and 37 is transparent (the transparent material in the human center plug 38 is connected to the substrate). Array decoration bureau. Wei Yuemeng is located in the line 42 (not in operation, through the word line 23 film bridge 36 on the library of the 罝 四 (4) 饴 不 成 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The word line 23 passes the common source line 28 through the drain region film #3rf29 and the electrode member 32 to the thin 40 Φ contact plug 38 to lightly match the electrode member 33 to the f-read of the patterned guide. The general character line 24 applies the control signal U to the access of the memory unit corresponding to the (four) difficulty 37. It is understood that the various materials can be used to implement the junction shown in Figures 5 and 6 to use copper metallization. Other crack-like metallization, =, titanium nitride and tungsten-based materials can also be utilized. Similarly, for example, doped polycrystalline H metal conductive materials can be used. It can be cut or nitrided by oxygen dioxide; ^, Al2 (33' or other low dielectric constant dielectric. ° The interelectrode insulating layer can comprise from Si, Ti, Al, Ta, N, 〇 and c. The selected one or more elements in the group. Figure 7 is a schematic illustration of a memory array, which can be implemented by referring to Figure 5 and Figure 6 22 13135 Ω9. 084 726] fwf.doc/006 In the memory array, in the Y direction, the unintentional illusion and word line 24 of Figure 7 are generally parallel. In the square, the source, line 28, and word line are set, so the solution in block 45 is solved. ^^亍Configure bit line 41 and: element line 23, 24. Block in block 46: driver, combined to bit line 41 and 42. Common horse. and sense amplifier group coupled: 5 The source terminal is: =^^ Take;:=. The closed-pole turn of the access transistor 51: to the word:, the gate of the combined transistor 52 is consumed to the word] the sub-twist line 24. To the word line 闸, the gate member for accessing the electric transistor 53 is used for the thin bridge 36, the thin body and the pole are coupled to the electrode portion, and the access electrode m is bonded to the electrode member 33. 37, θ7 ^ is not coupled to the electrode member 34 For the thin _ 赖 bridge 37 is again consuming to the electrode parts. Electrical, bridge ~ line 41. For illustrative purposes, electricity; cattle 3: merging to: the separation position on line 41. will understand, and he 4? 电极 The electrode parts can be used for single (4) memory single 'single 42 yuan sharing common source line 28, which in the illustrated diagram see the same 'in the row in the array, two memory units total two four, of which In the illustrated diagram, a simplified block diagram of the integrated circuit of the embodiment of the invention in the X direction of the red phase is used. Each of the present inventions is included in the semiconductor substrate using a thin film phase change memory cell. Body array 6〇. Column decoder 61 _ combined into multiple word lines 23 131353⁄43⁄4 084 17261twf.doc/006 6 columns in 6G to configure. The line solution (4) 63 is merged into the ^ strip line 64, along the line in the memory _ 6 (), the multi-gate memory unit (4) in the seed is read and the address is supplied to the line decoder. 63 and column deconstruction row 67 (four) into the sense amplifier and data registration structure through the accumulation of electricity: 7 =: = to = _ record line - in the illustrated embodiment, the integrated circuit includes shell It= as a processor or dedicated application circuit, or a module that provides film phase change = system functionality = internal or external data = 阜, or supplied to integrated circuit 75 control = : = = : The implemented controller divides, erases the checksum, and programmatically, n, like, stylize, and narrate the controller =;::=. In the case of a general-purpose processor, which implements a computer integrated circuit, the implementation of the = example, dedicated logic, is performed in the other controllers. The combination of general processing can be used to implement Figure 9 to illustrate the formation of the matrix shown in Figure 7 in the previous stage process: the sub-read, source line and access in the illustrated embodiment 24 13 1 3 5 Ofi) 84 17261twf.d〇c/〇〇6 Corresponding common CMOS components. In FIG. 9, the source line 106 is located on the impurity region 103 in the semiconductor substrate, wherein the doped region 1〇3 corresponds to the source terminal of the first access transistor on the left side of the figure and the right side of the figure. The source terminal of the second access transistor. In this embodiment, the source line 106 extends onto the top surface of the structure 99. In other embodiments, the source lines do not extend all the way to the surface. The doped region 1 〇 4 corresponds to the 汲 terminal of the first access transistor. A word line including a polysilicon 107 and a silicide cap 1 〇 8 serves as a gate of the first access transistor. The dielectric layer 1 〇 9 is on the polysilicon 107 and the breaking cover 1 〇 8. The plug no contacts the holding area 1〇4 and mentions a conductive path to the surface of the structure 99 for contacting the memory cell electrodes as described below. The doped region 105 provides the drain terminal of the second access transistor. A word line including a polycrystalline ridge 111 and a lithograph cover (not shown) serves as a gate of the second access transistor. Plug 112 contacts doped region 105 and provides a conductive path to the top surface of structure 99 for contacting the memory cell electrodes as described below. Isolation trenches 1〇1 and 1〇2 isolate the dual transistor structure coupled to plugs 11〇 and 112 from adjacent dual crystal structures. On the left, the word line polysilicon 117 and the plug U4 are displayed. The word line polysilicon 118 and plug in are shown on the right. The structure 99 illustrated in Figure 9 provides a substrate for forming a memory cell element, including first and second electrodes, and a bridge made of memory material' as described in more detail below. Figures 10 through 18 illustrate phase change bridge devices and stages in the fabrication of electrode layers implemented using multilayer dielectrics. Figure 1 illustrates the stages in the fabrication process after forming a multilayer dielectric fill. Figure 1A shows an array area 31" and a peripheral area 320 separated by a section 33" for the purpose of illustrating the method of forming a memory device and forming a peripheral circuit 25 0084 17261 twf.doc/006. Combine. This section 33〇 is retained in all of Figs. 10 to 18. In array region 310, the substrate formed with the multilayer dielectric fill includes an array of contact windows defined by the top surface of conductive plugs 110, 112 and other similar plugs on the device. These contact windows are used to access memory cells as described below. In this embodiment, the multilayer dielectric fill includes a bottom etch stop layer 2, a first dielectric fill layer 202, a second etch stop layer 2〇3, a second dielectric fill layer 204, and a second dielectric fill layer 2〇4. The upper protective layer 2〇5. In a representative embodiment, the bottom etch stop layer 2〇1, the second button ^205 202, 204 comprise a oxidized ash. According to the need for compatibility with the manufacturing steps described below, the bottom side stop layer 201, the first dielectric filling layer 2, the second stop layer 2〇3, and the second dielectric filling may be selected in the multilayer dielectric f-filled towel (10). The material of layer 204 and protective layer 205. Also, if (4) of the manufacturing step described below is not necessarily determined, the bottom button stop layer 2〇1 and the protective layer 205 can be removed in the embodiment. Figure 11 illustrates the next stage of the manufacturing process towel. This phase occurs after the lithography step. The lithography step defines the opening of the contact array in the contact substrate and is aligned with the contact plugs 110, 112. Applying a side process or a plurality of side processes (eg, CFX or CxFy based reactive ion etching for the dioxide dioxide tantalum nitride material) within the opening to remove multiple layers of the trenches 206, 207 The bottom etch stop layer 2 includes a first dielectric fill layer 202, a second button stop layer 2〇3, a second electrical layer 204, and a protective layer 205' and exposes a top surface of the contact window, package 26 131350a 〇δ4 17261 Twf.doc/006 includes the contact window plug 11G _ surface. In this implementation, the bottom, Μτ stop layer 201 is used to prevent the over-cutting into the electrical "fill" around the conductive plug 11 。. In other embodiments, if such over-etching is not possible, then Removing the bottom etch stop layer. After the button, the trenches 206, 207, the dielectric layer is conformally deposited on the structure, and the isotropic side is defined by the trench 2, and the sidewall structure (10) in the trench 21^ In the example, the sidewall structure to 211 comprises a nitrogen cut. The representative thickness of the sidewall structure varies from about 3G to 5G. In some implementations, if possible, the structure used in the structure described herein. Or the 'creation process' of the surrounding structure is even thinner. Wall structures are preferred. Other materials can be used, which contain good electrical insulators in thin materials, and can be selectively etched in the manufacturing process described below. 215 ^Describe the next stage in the manufacturing process. This stage occurs after the deposition of the sacrificial material, 216, and the sacrificial material 2i5, 216 is polymerized (similar to the photoresist material). or others The material 'the other (4) is as thin as 211 with respect to the sidewall structure, and the second dielectric fill == = Γ1 尔. In the deposition of the sacrificial material 21 shirt '218' 219J ^ the electrode area (example = 冓 = 51) and the side wall Structure Xie, 210 exposed openings. Use based on: back: and, eight, on top of the fill, for example;: protect = or first electric; | shell fill layer 204 on top. Subsequently, application _ 27 I3135Q9 〇 84 1726liwf .doc/006 layer 205 and second dielectric filling layer 204 in the opening, so that the sidewall spacers 2〇9, 21 in the trench 251 are violent. Figure 13 5 shows the application of dry/wet stripping One stage, example = dry stripping with oxygen ashing, followed by wet stripping of chemical shells or other chemicals, which are typically used after the use of photoresist to form vias In addition to this material, the photoresist 217, 218, 219 and the sacrificial material 215, 216 are removed, wherein the sacrificial material comprises a polymer similar to the hetero-phase in the same manner. The resulting structure includes trenches 206 and 207. a first electrode contact window for the lower access structure, the lower access node A top surface including the conductive plug 11A, and a trench 251 for the second electrode contact window with the sidewall structures 209, 210 therebetween. Figure 14 shows the result of the process of filling the conductive material into the trenches 206, 2, 7, and 251. For example, it can be metallized using a commonly applied copper or copper alloy for filling small vias with a conductive material. The applied technique can be the same as that used for the metallization layer described below to improve the use in metallization. The processability of the process is reduced when the critical dimension of the process is shortened. Examples of alternative methods include tungsten or metallization. After deposition of the conductive material, etch back or chemical mechanical polishing techniques are applied to planarize the structure, with sidewall structures 209, 210 isolate the conductive members 220, 221, 222. The protective layer 205 in the multilayer dielectric fill is utilized in the case of copper metallization to prevent copper from diffusing into the structure. For other metallization techniques, the protective layer 205 can be removed. Processes for depositing copper include electrochemical, mechanical deposition techniques using techniques available from NuTool, Inc. of Milpitas, California. 28 13135 θδ) 〇 84 17261t\vf.doc/006 Figure 15 illustrates the lower-stage after the application-process to remove the guide-portion near the surface. For example, the guide material may include a wet process to remove the top surface of the material (eg, 5 nanometers, such that the sidewall structures 209, 21〇 remain protruding from the formed surface. Chemical low-stress electrochemical polishing · chemical machine jECMD) back and forth to leave grooves in the trench. For example, the steel is removed in the ^ stage (by planarization) by detecting oxygen ❹ = a dielectric fill layer 204) or the SiN layer (protective layer 2 〇 5) (as in). Subsequently, in the second stage, after changing the different or having a higher selectivity for copper to oxide wire n, after the grinding head, the copper in the through hole is selectively (four) copper dished (dish) . Offset/ft, depositing electrode material (eg, plus or TM) to fill the trench by the return: selecting the electrode material for use with the programmable resistor and acting as a conductive material and phase change material The electrode material may be TiAIN or TaAIN, or may comprise (for further examples) selected from the group consisting of mm-kLa, Nl and Ru and alloys thereof; : Two i elements. After depositing the electrode material, if necessary, the sister layer + several abrasives or otherwise remove the protective layer 205 and expose the sidewall surfaces to flatten the structure. The 22/out/pear component comprises a film 223, 224 made of an electrode material, and the film TIT_'210 isolates the film. "" A film made of a programmable resistive material is subsequently made of wax, serra, and patch made of a protective material (such as nitriding enamel). Stylization === patterning to define the process after the bridge 220 made of the octagonal resistor material = two stages 'where the patch 227 is made of a material that protects the programmable resistive material from etching chemicals. In this example, the two memory cells and at this stage are extended from the *-electrode part (_223) on the left side of the first memory cell 7L to the first electrode part (_225) on both sides, crossing the first A second electrode member (film 224) shared between the two units. Bridge 226 may be patterned using one or more conventional lithography steps to define a rectangular patch. === technology to reduce the width of the patch. A reduced representative technique is described in co-pending U.S. Patent Application Serial No. 11/155, filed hereby incorporated herein by reference. Further, Fig. 17 illustrates the structure after depositing the inter-metal dielectric 23 on the memory cell structure in the array region and in the peripheral region. The through hole to the electrode member (thin 224) is opened as shown in the figure, followed by if2; charging, such as copper filling and chemical mechanical polishing to form a plug, said ecmp. In the implementation of the treatment, copper is used to pattern the conductive layer, and _glass (G) is deposited on the surface of the chrome chrome' and then at =. Application _ In addition to the exposed FSG, and along with two: 2 lining the seed layer. The steel ore is then applied to fill the pattern. An annealing step is applied after the electromineralization, followed by a grinding process. A thin film bridge 226β and a patch 227B spanning the dielectric sidewall structure 21〇 on the right side are formed on the thin film bridge of the 2G9 across the dielectric side (4), and the complement is = 30 1313 5 gas 17261 twf.d〇c/〇〇6. After chemical mechanical polishing, the patterned conductive layer is defined, including bit lines 232 in the column regions, and other metallization forming devices in the peripheral regions are operated through a current path from the bit lines 232 Through the electrode member (film and film bridge m component (film 223), conductive member 22〇, enter the conductive plug 11 〇 = structurally through below the common source line 1 〇 6. In the programmable resistance = $ phase Change, one (for example, when the phase change material is in the yang U, ' έ recall unit memory one element, such as logic 〇, and when the material is polycrystalline, the memory unit memorizes another bit, For example, the processing steps described in this article are easily related to the standard Cm〇s manufacturing technology: the critical dimension of the small metallization can be better scaled, especially in the electrode parts (conductive parts (10), 22i 1 222). Used for filling metallization for the upper layer, for example for bit line characterization. Metallization techniques that are not required to be developed for contact with metal layers in multilayer metallization technology can be used. One. The ί i, the transverse through hole works well. The technique is to deposit the electrode material coating (4) film, including the electrode parts (films 223, 224, 225). In the case of the essay 15 early 7 ° contains two bottom electrodes, the dielectric gap wall span = = = phase change material The fabricated bridge cross-section process CMOS logic and dielectric_wall are formed on the electrode layer 1335353⁄4 084 17261 twf.doc/006 on the front structure or other functional circuit structure and provide easy support on a single ^ (10) human style The structure of the power circuit P, the single wafer is a chip of the GPU device. Although the film is actually reduced, the financial and (4) to Ben Maoming, anyone familiar with this skill. In ===: The present invention = [Schematic Description] Figure 1 illustrates an embodiment of a thin-bridged phase change memory device. Figure 2. illustrates the current in the thin film bridge phase change memory device shown in Figure! The mains of the road = the phase transition used in the thin film bridge phase change memory element shown in Figure 1. Figure 4 illustrates the dimensions of the thin film bridge phase change memory element shown in Figure 1. Figure 5 illustrates the structure of the phase change memory element, Wherein access is below an electrode layer and bit lines are above the electrode layer. The layout or plan view of the structure illustrated in Fig. 5. Fig. 7 is a diagram showing the phase change memory element. The integrated circuit diagram of the road-mounted thin film phase change memory array and other circuits includes the memory formed by the front end process. The access circuit is made in the manufacturing process based on the junction === shown in the figure. "Development of the use of an electrode layer based on a multilayer insulator in Fig. 10 to Fig. 18 BISSON 17261twf.doc/006 Device and stage in the device manufacturing method. [Main component symbol description] 10: Memory unit 1 226: Bridge 12: First electrode 12a, 13a, 14a, 209A, 210A: Top surface 13 Second electrode 14 Insulation member 15 Current Path 16 Active Channel 20 Substrate 23, 24, 62: Word Line 25, 27: Drain Region 2 6 · Source Region 28: Common Source Line 29, 30: Plug Structure 31: Electrode Layers 32, 33, 34 : Electrode members 35a, 35b: fences 36, 37, 226A, 226B: film bridges 38, 110, 112, 113, 114: plug 39: base member 40: patterned conductive layers 41, 42, 64, 232: bit Line 33 1313m 17261 twf.doc/006 45, 46, 66: Blocks 50, 51, 52, 53: Transistor 60: Memory array 61: Column decoder 63: Row decoder 65, 67: Bus bar 68: Bias configuration Power supply voltage 69: Bias configuration state machine #71: Data registration line 72: Data output line 74: Other circuit 75 Integrated circuit 99: structure 101, 102: isolation trenches 103, 104, 105: doped region 106: source line • 107, 118 · polysilicon 108: germanide mask 109: dielectric layer 111: polysilicon line 117: word Meta-line polysilicon 201: bottom etch stop layer 202: first dielectric fill layer 203: second etch stop layer 34 I3135Q9〇b4 17261twf.doc/006 204: second dielectric fill layer 205: protective layer 206, 207, 251: trench 208, 209, 210, 211 · sidewall structure 215, 216: sacrificial material 217, 218, 219: photoresist 220, 22 222: conductive members 223, 224, 225: film # 227, 227A, 227B: patch 230 : inter-metal dielectric 233, 234: metallization 310: array area 320: peripheral area 330: section L. length T: thickness win W: width 35

Claims (1)

I3135ft9〇84 17261twf.doc/〇〇6 X. Patent Application Range: 1 A method for manufacturing a memory device, comprising: forming a circuit in a substrate - a circuit on the two surfaces of the circuit package a first contact window array; an earth electrode layer is formed on the bottom of the soil, the electrode layer has a top surface, and the electrode layer includes an electrode pair. Forming an individual insulating member between the electrodes. The corresponding contact window in the first contact window array is connected to the first electrode and the second electrode and the insulating member I extends to the top of the f-pole layer. And the insulating member has a top surface of the electrode layer, a width Between 8 and +, β jin is formed on the top surface of the electrode layer by the 苐-electrode and the second electrode (5) an array of memory materials, the bridge array including bridges for each of the electrode pairs in the array of electrode pairs, contacting the individual first and second electrodes and spanning the individual insulating members Extendingly, the bridge includes a patch of the memory chair. The patch has a first side and a second side, and the first side contacts the individual first electrode and the first side. a second electrode, the bridge defining an inter-electrode path between the first electrode and the second electrode across the insulating member. The inter-electrode path has a defined extent by the degree of the insulating member a path length, wherein the memory material is at least a solid phase; and, using the metallization process, forming a patterned conductive layer 36 I 135 〇 a 〇 17 17 17 17 doc doc doc doc doc , , , , , , , , , , , , , , , , , , , A second contact window array is formed between the patterned conductive layers. 2. The method for manufacturing a memory device according to claim 1, wherein the forming the electrode layer comprises: forming a multilayer structure including a first dielectric filling layer, filling the dielectric material a side stop layer on the layer, and a second dielectric fill layer on the rice stop layer; etching the multilayer structure in a pattern including a contact via, the contact window a selected one of the first contact arrays on the lining surface of the substrate; a sidewall dielectric spacer formed on a sidewall of the contact via; and - covering the plurality of layers with a sacrificial material a structure for filling the contact via hole; selectively etching the sacrificial material in a pattern including an opening, an opening, an electrode region on the multilayer structure, and the sidewall dielectric spacer, Stopping near the top surface level of the second dielectric fill layer; removing the second dielectric fill layer in the electrode region, stopping = the (4) stop layer, in the Forming an electrode trench in the layer structure, and causing the sidewall dielectric spacer to be located on a side of the electrode trench; 攸 the (four) via removing the sacrificial material, arbitrarily selecting the touch window and making the The sidewall dielectric_wall is located between the pair of openings, 13135 (3⁄43⁄4. 084 17261 twf.d〇c/〇〇6, the opening pair includes the contact window via and the electrode trench, the ancestral conductive material] Illustrating the conductive wire structure, the contact window through hole and the electrode trench to form a filling and filling method, and the method for manufacturing a memory device according to item 2 of the second aspect Forming a bottom etch stop layer in the multi-layer structure, and wherein the contact window through-hole patent axis of the selected contact window is included in the bottom of the pattern I including the contact window via hole The method for manufacturing a memory device according to item 2 includes: forming a protective layer on the second dielectric filling layer in the multilayer structure, and removing the protection after the thunder is used The conductive material is filled in the square of the electrode trench, and the second is The method for manufacturing a memory spread, wherein the sacrificial material comprises an organic polymer. 6. The method for manufacturing a memory according to the second aspect of the Japanese Patent Application Serial No. 2, wherein the capping sacrificial material comprises an anti- The method for manufacturing a memory device according to Item 2 of the Japanese Patent Application No. 2, comprising: returning the contact hole in the contact window and the conductive material in the electrode trench to silver An electrode groove is formed on the surface of the wall of the wall dielectric wall. The electrode material is selected by the heart to be compatible with the programmable electric material. 38 I3135ft^084 17261twf.doc/006 I3135ft^084 17261twf.doc/006 Φ 0 filling the electrode recess until a level of an individual top surface of the sidewall dielectric spacer between the pair of electrodes is included, wherein the pair of electrodes includes a separate fill contact window that acts as the first electrode a hole and a conductive material that fills the electrode trench as a second electrode. 8. A method of manufacturing a memory device by applying full-time (4) 2, wherein the conductive material comprises copper. 9. A method for fabricating a memory device as described in claim 7 of the invention, wherein the towel (four) electrode (four) & contains a diffusion barrier between the conductive (four) and the programmable resistive material. The apparatus for manufacturing a memory device according to the seventh aspect of the invention, wherein the electrode material is a conductive nitride comprising one or both of Ti#nTa. The __1st rhyme-like slave is placed in a /, W, the pair of electrodes in the array is arranged in two pairs; two two: in the first pair of the pair of electrodes The first and second through holes in the second pair of the pair of electrode pairs. Α 的 真 ι ι ι ι ι ι ι 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利In the method of claim 1, the m-neighbor is used for money and money devices. The material of the r's material contains Ge, Sb, Te, Se, Tti, a, Sn, Cu, 39 I3135Q9〇84 1726ltwf.d〇c/〇〇6 combination of two or more materials in the group of pd, pb, Ag, s, and Au. 14. A method for fabricating a process comprising: ??? a memory of a resistive material mounted on a substrate having a top surface comprising two and two J-paths on a top surface of the substrate, the circuit package forming a multilayer structure comprising a -1; 1 & true charge layer on a first first dielectric-filled layer, a second dielectric fill layer; a τ stop layer, and a pattern of etch stop layers in the via hole _ the multilayer structure, the array 2: the contact window on the top surface of the substrate a selected contact window of the 丨 夕 〒 ;; 阁 彳; 彳 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触Selectively (4) the sacrificial material in the pattern of opening σ, the electrode region and the sidewall dielectric gap wall on the exposed layer structure stop at the surface of the second dielectric filling layer And the second dielectric filling layer in the electrode region is stopped on the money stopping layer to form an electrode trench in the multilayer structure, and the sidewall dielectric spacer is located in the Removing the sacrificial material from the contact window via to expose the selected 40 丨 084 17261 twf.doc/006 contact window and aligning the _ dielectric f (four) with the opening Pair of open contact windows a hole-and-opening electrode trench. a deposition-conducting material, filling the contact via and the electrode trench with the conductive material to form a filling structure; and the contact window via and the electrode trench Retrieving the level below the surface of the sidewall dielectric spacers, forming an electrode recess; and arranging the battery to be compatible with the programmable resistive material Having the _electrode pair table r level, wherein the electrode=pole of a filled electrode is drawn: two, the contact window via hole and the conductive material in the second electric two channel, and providing an array including the electrode pair a top surface of an electrode layer; a bridge forming the pair of programmable resistors on a top surface of the layer, contacting each of the first electrode and the household defining an insulating member across the first Two 'core == diameter', the path between the electrodes has a path length bounded by ι, and 连, 5::2======================================= a method comprising σ hidden, including in the The multilayer structure 41 Γ3135β§084 1726 ltwf.doc/006 forms a bottom etch stop layer, and the pattern of Α 令 令 : : : : : : : : : : : : : : : : 2 2 2 2 2 2 2 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定The manufacturing process described in item 14 of the patent window of the above-mentioned contact window through-hole is included in the first step, including the multilayer structure electrode material layer And removing the protective layer after filling the electrode recess with the true one. The method for manufacturing a device containing a material that can be included in the method of claim 14, wherein the material of the sacrificial material is as described in Item 14 of the patent scope for manufacturing A method of containing materials, wherein the sacrificial material package program is specifically designed to contain copper as described in item 14. A method of a memory device of the material, wherein the conductive material comprises a method of manufacturing a memory device comprising a material of 1, 5, or 5 as described in claim 14 wherein the electrode material comprises a barrier. A diffusion between the electrical material and the programmable resistive material. The stylized thunder is as described in the 14th chapter. The manufacturing process includes a "material 5 method" in which the electrode material is 42 13135. 084 17261 twf.doc/006 Includes one of Ti and Ta or rain. 22·If you apply for a patent, the 4th 'Electro-rat compound. The memory of the stylized resistive material can be made in ^^7T^^ The method of arh^'+' ^ /ir, wherein the circuit comprises a plurality of bits, and the image "the number of isolations controlled by the signal on the line of word 70 is set and the patterned conductive layer comprises a plurality of bit lines . The two electrode pairs comprising the array-array include the first one of the -th pair of the pair of electrodes facing the pair, the first one serving as the two electrodes a first fill contact window of the electrode is filled with the said second electrode of the pair of electrodes, the tenth: flute, and the second pair of the two electrode pairs The shirt is electrically _- the second filling contact window through hole. The method for manufacturing a memory device comprising a second resistive material according to the invention of claim 14, wherein the memory material comprises a combination of 3 e, Sb and Te. Borrowing ~ν, Γ·+ as described in claim 14 for manufacturing a memory device comprising a VIII-resistive material, the memory material package A=Sb, Te, Se, A combination of two or more materials in the group of In, ^, and Au. 43