CN102254864A - Method for manufacturing phase change memory element - Google Patents
Method for manufacturing phase change memory element Download PDFInfo
- Publication number
- CN102254864A CN102254864A CN2010101827776A CN201010182777A CN102254864A CN 102254864 A CN102254864 A CN 102254864A CN 2010101827776 A CN2010101827776 A CN 2010101827776A CN 201010182777 A CN201010182777 A CN 201010182777A CN 102254864 A CN102254864 A CN 102254864A
- Authority
- CN
- China
- Prior art keywords
- phase change
- layer
- opening
- bottom electrode
- insulating barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for manufacturing a phase change memory element, which comprises the steps of: providing a front-end device structure, wherein the front-end device structure is provided with a conductive safety pin exposed out of the surface; forming a dielectric layer on the front-end device structure; forming an insulation layer with a first opening on the dielectric layer, wherein the first opening is positioned right above the conductive safety pin; forming a space wall on the side wall of the first opening; by taking the insulation layer with the first opening where the space wall is arranged as a mask, etching the dielectric layer to form a second opening, exposing the upper surface of the conductive safety pin; forming a bottom electrode with a height smaller than that of the insulation layer in the second opening; and forming a phase change layer on the bottom electrode. Therefore, according to the method, the problem of inaccurate position possibly generated when the phase change layer is patterned can be solved, the contact area between the bottom electrode and the phase change layer can be reduced through reducing the size of the bottom electrode, and the read-white speed of a phase change memory is increased.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly make the method for phase change memory component structure.
Background technology
The phase change memory device technology is based on that conception that phase-change thin film layer that Ovshinsky proposes at beginning of the seventies late 1960s can be applied to the phase change memory medium sets up, have competitive characteristics such as speed, power, capacity, reliability, process integration degree and cost, for being fit to be used as the stand alone type or the Embedded memory application of higher density.Because the unique advantage of phase change memory device technology, make it be considered to might replace very much the highly competititve crystalline state memory SRAM of present commercialization and dynamic memory DRAM volatile storage, flash memory Flash non-volatility memorizer technology, be expected to become the new generation semiconductor memory part that will have potentiality future.
Phase change memory component is the mechanism that the resistance value difference of utilizing phase-change material to be caused in crystalline state and amorphous reversible Structure Conversion is used as storage.Writing, wiping or during read operation, mainly be to utilize the control of electric current pulse wave to reach, for example, fashionable when writing, one short time (for example 50 nanoseconds) and higher relatively electric current (for example 0.6 milliampere) can be provided, make phase change layer melt also cooling fast and formation amorphous state.Because the amorphous state phase change layer has higher resistance (for example 10
5-10
7Ohm), make it when read operation, the voltage that provides is higher relatively.In the time will wiping, a long period (for example 100 nanoseconds) and relatively low electric current (for example 0.3 milliampere) can be provided, make the amorphous state phase change layer convert crystalline state to because of crystallization.Because the crystalline state phase change layer has lower resistance (for example 10
2～10
4Europe), it is when read operation, and the voltage that provides is relatively low.In view of the above, can carry out the operation of phase change memory component.
Shown in Figure 1A to 1C, be the method for traditional making phase change memory component structure.
Shown in Figure 1A, front end device architecture 101 is provided, this front end device architecture 101 can be a front end device architecture of having finished the CMOS FEOL, for example comprises structures such as substrate, isolation structure, electric capacity, diode, and is all not shown in the drawings.On front end device architecture 101, form dielectric layer 102, adopt the first mask plate (not shown) pattern dielectric layer 102 then, form dielectric layer 102 with opening 103.
Shown in Figure 1B, in opening 103, form the bottom electrode material layer, remove the part that the bottom electrode material floor height goes out dielectric layer 102 by for example CMP (chemico-mechanical polishing) technology then, form bottom electrode 104.
Shown in Fig. 1 C, on dielectric layer 102 and bottom electrode 104, form phase-change material layers, adopt the second mask plate (not shown) patterning phase-change material layers to form to be positioned at the phase change layer 105 directly over the bottom electrode 104 then.Next, finish follow-up technologies such as formation top electrodes, finish the making of whole phase change memory component structure.
But, the method of above-mentioned traditional making phase change memory component structure, need in the patterning phase change layer, define the position of phase change layer, that is to say if the location definition of phase change layer is inaccurate, the situation that appearance can not cover fully on the bottom electrode or not contact fully with bottom electrode, can the overall performance of phase change memory device be affected, for example can reduce the reliability of semiconductor device.In addition, in phase change memory device, phase change layer needs higher temperature from crystalline state to amorphous transition process, by bottom electrode phase change layer is heated generally speaking, top electrodes only plays the effect of interconnection, therefore, bottom electrode directly has influence on the read-write speed of phase transition storage to the quality of the heats of phase change layer.In order to obtain good heats, phase transition storage is general to adopt bigger drive current, but drive current can not unrestrictedly rise, and this is because excessive drive current can cause the problems such as small-sized difficulty of peripheral drive circuit and logical device.Because phase-change material is changed into the size that the required electric current of amorphous state depends on the contact surface of bottom electrode and phase change layer from crystalline state, that is to say, contact area is more little, therefore it is more little that phase-change material is changed into the required electric current of amorphous state from crystalline state, and the contact area that reduces bottom electrode and phase change layer by the size that reduces bottom electrode also is a kind of method that improves heats with the raising contact resistance.But existing processes often is subjected to the restriction of photoetching process, can not form the bottom electrode of reduced size, and the diameter dimension of bottom electrode is about 80～100 nanometers generally speaking.
Therefore, need a kind of method, the coarse problem in the position that may exist in the time of can either solving the phase change layer patterning can reduce the contact area of bottom electrode and phase change layer, the read or write speed of raising phase transition storage again by the size that reduces bottom electrode.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The invention provides a kind of method of making the phase change memory component structure, comprising: the front end device architecture is provided, and described front end device architecture has the conduction latch of exposing surface; On described front end device architecture, form dielectric layer; On described dielectric layer, form insulating barrier with first opening, described first opening be positioned at described conduction latch directly over; On the sidewall of described first opening, form clearance wall; With the insulating barrier with first opening that has formed described clearance wall is mask, and the described dielectric layer of etching forms second opening, exposes the upper surface of described conduction latch; In described second opening, form the bottom electrode that highly is lower than described insulating barrier; On described bottom electrode, form phase change layer.
Preferably, the material of described dielectric layer is an oxide.
Preferably, described insulating barrier is single layer structure or sandwich construction.
Preferably, described insulating barrier is nitride layer or comprises nitride layer and be formed at oxide skin(coating) on the described nitride layer.
Preferably, the material of described clearance wall is a nitride.
Preferably, the material of described clearance wall is a silicon nitride.
Preferably, the material of described bottom electrode is polysilicon, W, TiN, TiAlN or WSi.
Preferably, the height of described phase change layer is higher than described insulating barrier or flushes with the top of described insulating barrier.
Phase change memory component structure according to the invention making, adopting self aligned mode to make between phase change layer and the bottom electrode aims at fully, the problem that phase change layer does not cover bottom electrode fully can not appear, also reduced the use of mask plate further, promptly when forming phase change layer, do not need to re-use mask plate, reduce processing step, improved production efficiency.Because the cost of mask plate is very expensive, therefore also further reduced production cost.And, because the existence of clearance wall, the size of the feasible final bottom electrode that forms is less than the size of traditional handicraft, therefore reduced the contact area of bottom electrode and phase change layer, thereby make bottom electrode have good heats, improved the read or write speed of phase transition storage, and both contacts area can be adjusted by technology phase change layer, simple and convenient, be easy to manufacture.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 C is the generalized section of traditional making phase change memory component structure;
Fig. 2 A to 2F is a schematic diagram of making the phase change memory component structure according to one embodiment of the invention;
Fig. 3 is a process chart of making the phase change memory component structure according to one embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention makes semiconductor device structure.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to following explanation, advantages and features of the invention will be clearer.Need to prove that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention clearly.Should understand, when mention one deck another the layer " on " time, this layer can perhaps can have one or more intermediate layers directly in the above.In addition, be also to be understood that mention one deck two layers " between " time, it can be just layer between two layers, or also one or more intermediate layers can be arranged.
Shown in Fig. 2 A, provide substrate 201.Be formed with grid, source/structures such as drain electrode in the substrate 201, for simplicity, these structures are all not shown in the drawings.Form interlayer dielectric layer 202 in substrate 201, material can be chosen as low k (dielectric constant) material.Has the conduction latch of making by electric conducting material 203 that at least one exposes upper surface in the interlayer dielectric layer 202, for example the tungsten latch.Substrate 201, interlayer dielectric layer 202 and conduction latch 203 common formation front end device architectures 241.Surface at front end device architecture 241 forms dielectric layer 204.The material of dielectric layer 204 can be an oxide, silica for example, and generation type can be CVD (chemical vapour deposition (CVD)) method.On dielectric layer 204, form insulating barrier 205, the structure of insulating barrier 205 can single layer structure, for example for only being one deck nitride, nitride can be a silicon nitride, also can be sandwich construction, for example comprise nitride layer that is formed on the dielectric layer 204 and the oxide skin(coating) that is formed on the nitride layer.Then, adopt mask plate (not shown) patterned insulation layer 205, form insulating barrier 205 with first opening 206.The size of first opening is generally 80～100 nanometers, the position be positioned at the conduction latch 203 directly over.The material that it is pointed out that dielectric layer 204 and insulating barrier 205 can adopt identical materials, for example is oxide.Adopting dielectric layer 204 in the present embodiment is the different materials of nitride for oxide insulating barrier 205, can control the degree of depth of etching like this by selective etching gas, promptly can when etching forms first opening 206, rest on dielectric layer 204 surfaces, overetch takes place and etch into interlayer dielectric layer 202 interlayer dielectric layer 202 is caused certain injury thereby be unlikely.
Shown in Fig. 2 B, on the structure shown in Fig. 2 A, promptly form spacer material layer 207 in first opening 206 and on the insulating barrier 205, thickness is approximately 40～50 nanometers, and generation type can be the CVD method, and material can be nitride, for example silicon nitride.But, because when forming spacer material layer 207, can reduce the size of first opening 206 indirectly, the size of first opening 206 is more little, the difficulty that forms the spacer material layer in it is big more, therefore can not form blocked up spacer material layer 207 in first opening 206.
Shown in Fig. 2 C, adopt modes such as CMP or etching to remove the spacer material layer 207 on insulating barrier 205 surfaces and dielectric layer 204 surfaces, remaining spacer material layer 207 forms clearance wall 208A and 208B on the sidewall of insulating barrier 205.The size of first opening 206 has further been dwindled in the existence of clearance wall 208A and 208B, and for example the size with first opening 206 narrows down to 30～60 nanometers.Be mask with insulating barrier 205 and clearance wall 208A and 208B then, etching dielectric layer 204 forms second opening 209, i.e. the upper surface of exposed portions serve conduction latch 203.
Shown in Fig. 2 D, form bottom electrode material layer 210 on the structure shown in Fig. 2 C, promptly form bottom electrode material layer 210 on the insulating barrier 205 and in second opening 209.Material can be doped polycrystalline silicon, W, TiN or TiAlN, it can also be other silicide material, this silicide material can also be to comprise the silicide that is selected from least a metallic element in the group of being made up of Ag, Au, Al, Cu, Cr, Co, Ni, Ti, Sb, V, Mo, Ta, Nb, Ru, W, Pt, Pd, Zn and Mg, be preferably WSi, generation type can be CVD method or PVD (physical vapour deposition (PVD)) method etc.
Shown in Fig. 2 E, form the step of bottom electrode 211, form the 3rd opening 212 simultaneously.Can select for use the etching mode to eat-back bottom electrode material layer 210, make it highly be lower than insulating barrier 205, also can adopt the CMP mode to remove the part that bottom electrode material layer 210 exceeds insulating barrier 205 earlier, eat-back bottom electrode material layer 210 by the etching mode then, make it highly be lower than insulating barrier 205.Adopt the speed of CMP method removal part bottom electrode material layer 210 very fast, can shorten the production cycle to enhance productivity.
Shown in Fig. 2 F, in the 3rd opening 212, form phase change layer 213, to finish the making of phase change memory component structure.When forming phase change layer 213 can be sediment phase change layer 213 on the structure shown in Fig. 2 E, and phase change layer 213 is higher than insulating barrier 205, and its patterning process can be carried out with follow-up technology, to save processing step.Choose the concordant mode of phase change layer 213 and insulating barrier 205 in the present embodiment, its part that exceeds insulating barrier 205 can remove by modes such as CMP.The mode that forms phase change layer 213 can be CVD method or PVD method.
The material of phase change layer 213 can be a chalcogenide alloy, such as germanium-antimony-tellurium (Ge-Sb-Te), nitrogen-germanium-antimony-tellurium (N-Ge-Sb-Te), arsenic-antimony-tellurium (As-Sb-Te), indium-antimony-tellurium (In-Sb-Te), germanium-bismuth-tellurium (Ge-Bi-Te), tin-antimony-tellurium (Sn-Sb-Te), silver-arsenic-antimony-tellurium (Ag-As-Sb-Te), gold-arsenic-antimony-tellurium (Au-As-Sb-Te), germanium-arsenic-antimony-tellurium (Ge-As-Sb-Te), selenium-antimony-tellurium (Se-Sb-Te), tin-arsenic-antimony-tellurium (Sn-As-Sb-Te) or arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te).Alternatively, phase-change material can comprise the element-antimony-tellurium in the VA family, such as tantalum-antimony-tellurium (Ta-Sb-Te), niobium-antimony-tellurium (Nb-Sb-Te) or vanadium-antimony-tellurium (V-Sb-Te), can also be the element-antimony-selenium in the VA family, for example tantalum-antimony-selenium (Ta-Sb-Se), niobium-antimony-selenium (Nb-Sb-Se) or vanadium-antimony-selenium (V-Sb-Se) etc.In addition, phase-change material can comprise the element-antimony-tellurium in the VIA family, for example tungsten-antimony-tellurium (W-Sb-Te), molybdenum-antimony-tellurium (Mo-Sb-Te) or chromium-antimony-tellurium (Cr-Sb-Te) etc., element-antimony in the VIA family-selenium, for example tungsten-antimony-selenium (W-Sb-Se), molybdenum-antimony-selenium (Mo-Sb-Se) or chromium--antimony-selenium (Cr-Sb-Se) can also for example be Ga-Sb, Ge-Sb, In-Sb, In-Se, Sb
2-Te
3Or one or more kinds in the Ge-Te alloy, maybe can comprise Ag-In-Sb-Te, (Ge-Sn)-Sb-Te, Ge-Sb-(Se-Te) or Te
81-G
15-Sb
2-S
2One or more kinds in the alloy.The material of phase change layer 213 also can be made by the transition metal oxide with a plurality of resistance states, and for example, the material of phase change layer 213 can comprise NiO, TiO by being selected from
2, HfO, Nb
2O
5, ZnO, WO
3With CoO or GST (Ge
2Sb
2Te
5) or PCMO (Pr
xCa
1-xMnO
3) group at least a material make.In the present embodiment, the material of phase change layer 213 is chosen as Ge
2Sb
2Te
5(GST).
Then, carry out technologies such as follow-up formation protective layer and top electrodes, finish the making of whole phase change memory device.
Phase change memory component structure according to the present embodiment making, adopting self aligned mode to make between phase change layer and the bottom electrode aims at fully, the problem that phase change layer does not cover bottom electrode fully can not appear, also reduced the use of mask plate further, promptly when forming phase change layer, do not need to re-use mask plate, reduce processing step, improved production efficiency.Because the cost of mask plate is very expensive, therefore also further reduced production cost.And, because the existence of clearance wall, the size of the feasible final bottom electrode that forms is less than the size of traditional handicraft, the size that is bottom electrode is probably between 30～60nm, be far smaller than the size of the formed bottom electrode of traditional handicraft, therefore, reduced the contact area of bottom electrode and phase change layer, thereby make bottom electrode have good heats to phase change layer, improved the read or write speed of phase transition storage, and both contacts area can adjust by technology, and are simple and convenient, are easy to manufacture.
As shown in Figure 3, be process chart according to the making phase change memory component structure of the embodiment of the invention.In step 301, the front end device architecture is provided, the front end device architecture has the conduction latch of at least one exposing surface.In step 302, on the front end device architecture, form dielectric layer.In step 303, on dielectric layer, form insulating barrier with first opening, first opening be positioned at the conduction latch directly over.In step 304, on the sidewall of first opening, form clearance wall.In step 305, be mask with insulating barrier with first opening that has formed clearance wall, the etching dielectric layer forms second opening, exposes to conduct electricity the upper surface of latch.In step 306, in second opening, form the bottom electrode that highly is lower than insulating barrier.In step 307, on bottom electrode, form phase change layer.
Phase change memory component structure according to aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type dynamic random access memory), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. method of making the phase change memory component structure comprises:
The front end device architecture is provided, and described front end device architecture has the conduction latch of exposing surface;
On described front end device architecture, form dielectric layer;
On described dielectric layer, form insulating barrier with first opening, described first opening be positioned at described conduction latch directly over;
On the sidewall of described first opening, form clearance wall;
With the insulating barrier with first opening that has formed described clearance wall is mask, and the described dielectric layer of etching forms second opening, exposes the upper surface of described conduction latch;
In described second opening, form the bottom electrode that highly is lower than described insulating barrier;
On described bottom electrode, form phase change layer.
2. the method for claim 1 is characterized in that, the material of described dielectric layer is an oxide.
3. the method for claim 1 is characterized in that, described insulating barrier is single layer structure or sandwich construction.
4. method as claimed in claim 3 is characterized in that, described insulating barrier is nitride layer or comprises nitride layer and be formed at oxide skin(coating) on the described nitride layer.
5. the method for claim 1 is characterized in that, the material of described clearance wall is a nitride.
6. method as claimed in claim 5 is characterized in that the material of described clearance wall is a silicon nitride.
7. the method for claim 1 is characterized in that, the material of described bottom electrode is polysilicon, W, TiN, TiAlN or WSi.
8. the method for claim 1 is characterized in that, the height of described phase change layer is higher than described insulating barrier or flushes with the top of described insulating barrier.
9. integrated circuit that comprises the phase change memory component structure that is formed by each described method in the claim 1～8, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type dynamic random access memory and radio-frequency devices.
10. electronic equipment that comprises the phase change memory component structure that is formed by each described method in the claim 1～8, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101827776A CN102254864A (en) | 2010-05-20 | 2010-05-20 | Method for manufacturing phase change memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101827776A CN102254864A (en) | 2010-05-20 | 2010-05-20 | Method for manufacturing phase change memory element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102254864A true CN102254864A (en) | 2011-11-23 |
Family
ID=44982027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101827776A Pending CN102254864A (en) | 2010-05-20 | 2010-05-20 | Method for manufacturing phase change memory element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102254864A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060138467A1 (en) * | 2004-12-29 | 2006-06-29 | Hsiang-Lan Lung | Method of forming a small contact in phase-change memory and a memory cell produced by the method |
| CN1960020A (en) * | 2005-11-02 | 2007-05-09 | 尔必达存储器株式会社 | Non-volatile memory element and method of manufacturing the same |
| CN1988200A (en) * | 2005-12-20 | 2007-06-27 | 财团法人工业技术研究院 | Gas wall electrode side connection phase shift storage and its producing method |
| US20070155172A1 (en) * | 2005-12-05 | 2007-07-05 | Macronix International Co., Ltd. | Manufacturing Method for Phase Change RAM with Electrode Layer Process |
| CN101567420A (en) * | 2009-06-02 | 2009-10-28 | 中国科学院上海微系统与信息技术研究所 | Method for preparing phase transition storage |
-
2010
- 2010-05-20 CN CN2010101827776A patent/CN102254864A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060138467A1 (en) * | 2004-12-29 | 2006-06-29 | Hsiang-Lan Lung | Method of forming a small contact in phase-change memory and a memory cell produced by the method |
| CN1960020A (en) * | 2005-11-02 | 2007-05-09 | 尔必达存储器株式会社 | Non-volatile memory element and method of manufacturing the same |
| US20070155172A1 (en) * | 2005-12-05 | 2007-07-05 | Macronix International Co., Ltd. | Manufacturing Method for Phase Change RAM with Electrode Layer Process |
| CN1988200A (en) * | 2005-12-20 | 2007-06-27 | 财团法人工业技术研究院 | Gas wall electrode side connection phase shift storage and its producing method |
| CN101567420A (en) * | 2009-06-02 | 2009-10-28 | 中国科学院上海微系统与信息技术研究所 | Method for preparing phase transition storage |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10522757B2 (en) | Dual resistive-material regions for phase change memory devices | |
| CN101241966B (en) | Resistor random access memory cell device | |
| KR100668824B1 (en) | Phase-change memory device and method for manufacturing the same | |
| US7993962B2 (en) | I-shaped phase change memory cell | |
| CN102097587B (en) | Memory device having wide area phase change element and small electrode contact area | |
| US7514705B2 (en) | Phase change memory cell with limited switchable volume | |
| US7956358B2 (en) | I-shaped phase change memory cell with thermal isolation | |
| US7863596B2 (en) | Ring heater for a phase change memory device | |
| US7879692B2 (en) | Programmable resistive memory cell with self-forming gap | |
| US7709822B2 (en) | Phase change memory and manufacturing method thereof | |
| US9747975B2 (en) | Multi-level phase change memory | |
| US9196827B2 (en) | Non-volatile memory devices having dual heater configurations and methods of fabricating the same | |
| US9048423B2 (en) | Memory storage device and method of manufacturing the same | |
| KR100842903B1 (en) | Phase change RAM device and method of manufacturing the same | |
| US8525144B2 (en) | Programmable via devices | |
| JP2010087007A (en) | Phase change memory device and method of manufacturing the same | |
| CN102347442A (en) | Method for making phase change memory structure | |
| US20090101885A1 (en) | Method of producing phase change memory device | |
| US7985693B2 (en) | Method of producing phase change memory device | |
| CN102403454A (en) | Method for making phase change memory component | |
| CN102254864A (en) | Method for manufacturing phase change memory element | |
| US20070241385A1 (en) | Phase change memory device for optimized current consumption efficiency and operation speed and method of manufacturing the same | |
| KR100650719B1 (en) | Phase-change memory device and method for manufacturing the same | |
| KR100997785B1 (en) | Phase-change memory device and method for manufacturing the same | |
| KR100728984B1 (en) | Phase change ram device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130106 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130106 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20111123 |