CN102347442A - Method for making phase change memory structure - Google Patents

Method for making phase change memory structure Download PDF

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CN102347442A
CN102347442A CN201010245459XA CN201010245459A CN102347442A CN 102347442 A CN102347442 A CN 102347442A CN 201010245459X A CN201010245459X A CN 201010245459XA CN 201010245459 A CN201010245459 A CN 201010245459A CN 102347442 A CN102347442 A CN 102347442A
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layer
bottom electrode
phase change
material
etching
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CN201010245459XA
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Chinese (zh)
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洪中山
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中芯国际集成电路制造(上海)有限公司
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Publication of CN102347442A publication Critical patent/CN102347442A/en

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Abstract

The invention provides a method for making a phase change memory structure. The method is characterized in that: a front-end device structure with a conductive plug is provided; a top surface of the front-end device structure exposes an upper surface of the conductive plug; a bottom electrode material layer is formed on the top surface of the front-end device structure and the upper surface of the conductive plug; a sacrificial layer is formed on the upper surface of the bottom electrode material layer; etching is performed to the bottom electrode material layer or firstly the etching is performed to the bottom electrode material layer and then oxidation is performed so as to form a bottom electrode which is located right above the conductive plug; an insulating layer is formed on the surface of the front-end device structure; the insulating layer surrounds the bottom electrode and the sacrificial layer and exposes the upper surface of the sacrificial layer; a phase change layer is formed on a vacancy where the sacrificial layer is removed; a top of the phase change layer flushes with the top of the insulating layer. By using the method of the invention, a contact area between the bottom electrode and the phase change layer can be reduced through making the bottom electrode with a small size so as to acquire a good heating effect and easily generate crystalline state conversion. Finally, a read-write speed of the phase change memory can be raised.

Description

一种制作相变存储器件结构的方法 A method of fabricating a phase change memory device structure

技术领域 FIELD

[0001] 本发明涉及半导体制造工艺,特别涉及制作相变存储器件结构的方法电极层。 [0001] The present invention relates to semiconductor manufacturing processes, and more particularly to an electrode layer made of a phase change memory device structure. 背景技术 Background technique

[0002] 相变存储器件技术是基于Ovshinsky在20世纪60年代末70年代初提出的相变薄膜层可以应用于相变存储介质的构想建立起来的,是一种价格便宜、性能稳定的存储器件。 [0002] phase change memory device technology is based on thin film Ovshinsky phase in the late 1960s early 1970s proposed the idea can be applied to set up a phase change storage media, is a cheap, stable performance of the memory device . 相变存储器件可以做在硅晶片衬底上,其关键材料是可记录的相变层(GST)、加热电极材料、绝缘材料和引出电极材料,近年来研究热点围绕着其器件工艺展开。 The phase change memory device can be done on a silicon wafer substrate in which the key material is a phase change layer (GST) can be recorded by heating the electrode material, the insulating material and the lead electrode materials, recent studies about its focus device technology to expand. 相变存储器件的基本原理是利用电脉冲信号作用于器件单元上,使相变层在非晶态与多晶态之间发生可逆相变,通过分辨非晶态时的高阻与多晶态时的低阻,可以实现信息的写入、擦除和读出操作。 The basic principles of phase-change memory device is to use an electrical pulse signal is applied to a device unit, the phase change layer in the amorphous state reversible phase change between the crystalline state and the occurrence of multiple, distinguished by high resistance when the amorphous polycrystalline when the low resistance can be achieved writing, erasing and reading operations. 基于相变存储器件具有高速读取、高可擦写次数、非易失性、元件尺寸小、低功耗、抗强震动和抗辐射等优点,被广泛应用于现代工业中。 Based on the phase change memory device having high-speed reading, rewritable high frequency nonvolatile small element size, low power consumption, strong anti-vibration and anti-radiation, etc., it is widely used in modern industry.

[0003] 在相变存储器件中,相变层从晶态到非晶态的转变过程需要较高的温度,一般情况下通过底部电极对相变层进行加热,顶部电极仅仅起到互连的作用,因此,底部电极对相变层的加热效果的好坏直接影响到相变存储器件的读写速率。 [0003] In the phase change memory device, the phase-change layer from the crystalline to amorphous transition requires a higher temperature, heating the phase change layer in general through the bottom electrode, the top electrode only functions interconnected effect, therefore, the quality of the bottom electrode layer, the heating effect of the phase change directly affects the rate of a phase change memory device reader. 为了获得良好的加热效果, 相变存储器件一般采用较大的驱动电流,但是驱动电流不能无限制地上升,这是由于过大的驱动电流会造成外围驱动电路以及逻辑器件的小尺寸化困难等问题。 In order to obtain a good heating effect, phase change memory device typically uses a large drive current, the drive current can not rise indefinitely, this is due to an excessive drive current will result in the downsizing difficult peripheral driver circuits and logic devices, etc. problem. 由于把相变材料从晶态转变为非晶态时所需的电流取决于底部电极和相变层的接触表面的大小,也就是说, 接触面积越小,把相变材料从晶态转变为非晶态所需的电流越小,因此减小底部电极与相变层的接触面积以提高接触电阻也是一种提高加热效果的方法。 Since the phase change material from a crystalline state into an amorphous state current required depends on the size of the contact surface of the bottom electrode and the phase change layer, i.e., the smaller the contact area, the phase change material from a crystalline state into the smaller the current required for the amorphous, thus reducing the contact area of ​​the bottom electrode and the phase change layer to improve the contact resistance is also a method to improve the heating effect. 现有工艺中,底部电极的形成过程一般是先在介质层中形成孔,然后在孔中填充金属,但是现有技术中所形成的孔的顶部宽度总是大于底部宽度,所以难以缩小底部电极与相变层的接触面积。 In the conventional process, the formation of the bottom electrode is generally formed in the first hole in the dielectric layer, the metal in the hole and then filled, but the top width of the hole formed in the prior art is always greater than a bottom width, it is difficult to reduce the bottom electrode the contact area of ​​the phase change layer.

[0004] 因此,需要一种新的制作相变存储器件结构的方法,可通过制作小尺寸的底部电极来减小底部电极与相变层的接触面积,从而获得良好的加热效果以较容易地发生晶态的转变,最终提高相变存储器的读写速度。 Method [0004] Accordingly, a need for a new production phase change memory device structure, a contact area can be reduced and the phase change layer, the bottom electrode through the bottom electrode of a small size, thereby obtaining a good heating effect to more easily crystalline transition occurs, ultimately improve the phase change memory read and write speeds.

发明内容 SUMMARY

[0005] 在发明内容部分中引入了一系列简化形式的概念,这将在具体实施方式部分中进一步详细说明。 [0005] introduced the concept of a series of simplified form in the Summary section, which will be described in further detail in the Detailed Description. 本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征,更不意味着试图确定所要求保护的技术方案的保护范围。 This summary of the present invention is not intended to identify key features or essential features of the claimed technical solutions, nor is it intended to determine the scope of the claimed technical solution.

[0006] 为了形成小尺寸的底部电极以减小底部电极与相变层的接触面积,本发明提供了一种制作相变存储器件结构的方法,包括:(a)提供前端器件结构,所述前端器件结构中具有至少一个导电插塞,所述导电插塞的上表面在所述前端器件结构的顶面露出,在所述前端器件结构的顶面和所述导电插塞的上表面形成底部电极材料层,在所述底部电极材料层的上表面形成牺牲层;(b)对所述底部电极材料层进行刻蚀或者先刻蚀再氧化以形成底部电极,所述底部电极位于所述导电插塞的正上方;(c)在所述前端器件结构的表面形成绝缘层,所述绝缘层包围所述底部电极和所述牺牲层且露出所述牺牲层的上表面;(d)去除所述牺牲层;(e)在去除所述牺牲层后留下的空位处形成相变层,所述相变层的顶部与所述绝缘层的顶部齐平。 [0006] To form the bottom electrode is small-sized to reduce the contact area of ​​the bottom electrode and the phase change layer, the present invention provides a method of making a phase change memory device structure, comprising: (a) providing a front end device structure, the device structure having at least one electrically conductive distal plug, the upper surface of the conductive plug is exposed at the top surface of the front end of the device structure, the top surface and the front end of the device structure on the surface of the conductive plug formed in the bottom electrode material layer is formed on the bottom surface of the electrode material layer, the sacrificial layer; (b) for the bottom electrode material layer is etched or etched first and then oxidized to form the bottom electrode, the bottom electrode located on said conductive plug plug directly above; (c) forming a front end surface of the device structure of the insulating layer, the insulating layer surrounds the bottom electrode and the sacrificial layer and the exposed surface of the sacrificial layer; (d) removing said sacrificial layer; (e) form a phase change layer in the space left after the removal of the sacrificial layer, the top of the top of the phase change layer and the insulating layer flush.

[0007] 优选地,所述底部电极材料层的材料是硅化物。 [0007] Preferably, the bottom electrode material layer material is a silicide.

[0008] 优选地,所述底部电极材料层的材料是包含选自由Ag、Au、Al、Cu、Cr、Co、Ni、Ti、 Sb、V、Mo、Ta、Nb、Ru、W、Pt、Pd、Zn和Mg中的至少一种金属元素的硅化物。 [0008] Preferably, the bottom electrode material layer comprising a material selected from the group consisting of Ag, Au, Al, Cu, Cr, Co, Ni, Ti, Sb, V, Mo, Ta, Nb, Ru, W, Pt, Pd, a metal silicide of at least one element of Zn and Mg.

[0009] 优选地,所述底部电极材料层的材料是多晶硅、非晶硅、TiN, TiAlN, WSi或W中的 [0009] Preferably, the material of the bottom electrode material layer is a polycrystalline silicon, amorphous silicon, TiN, TiAlN, WSi or W is

一种或组合。 One or a combination thereof.

[0010] 优选地,所述牺牲层的材料是SiN。 [0010] Preferably, the material of the sacrificial layer is SiN.

[0011] 优选地,所述(b)步骤的刻蚀为干法刻蚀、湿法刻蚀或干法刻蚀与湿法刻蚀的结 [0011] Preferably, the etching step (b) is a dry etching, wet etching or dry etching and wet etching junction

I=IO I = IO

[0012] 优选地,所述干法刻蚀采用的气体为含有卤族元素的气体。 [0012] Preferably, the gas used in the dry etching gas containing a halogen element.

[0013] 优选地,所述底部电极材料层的材料是多晶硅或非晶硅,所述(b)步骤的刻蚀为干法刻蚀或干法刻蚀与湿法刻蚀的结合,其中,所述干法刻蚀采用的气体包含Cl2、HBr 和SF6,且所述干法刻蚀采用的功率为100〜1000W,偏压为0〜100W,反应室压强为5〜 IOOmtorr, Cl2、HBr 和SF6 的流量均为10 〜lOOsccm。 [0013] Preferably, the material of the bottom electrode material is polysilicon or amorphous silicon layer, the etching step (b) is a dry etching or a combined dry etching and wet etching, wherein the dry etching using a gas containing Cl2, HBr, and SF6, and the power used for the dry etching 100~1000W, bias 0~100W, a reaction chamber pressure of 5~ IOOmtorr, Cl2, HBr, and traffic SF6 are 10 ~lOOsccm.

[0014] 优选地,所述底部电极材料层的材料是多晶硅或非晶硅,所述(b)步骤的刻蚀为干法刻蚀或干法刻蚀与湿法刻蚀的结合,其中,所述干法刻蚀采用的气体包含He、HBr 和SF6,且所述干法刻蚀采用的功率为200〜700W,偏压为40〜200W,反应室压强为4〜 20mtorr,HBr的流量为100〜300sccm,SF6的流量为O〜20sccm,He的流量为5〜40sccm。 [0014] Preferably, the material of the bottom electrode material is polysilicon or amorphous silicon layer, the etching step (b) is a dry etching or a combined dry etching and wet etching, wherein the etching gas used in dry comprise He, HBr, and SF6, and the power used for the dry etching 200~700W, bias 40~200W, a reaction chamber pressure of 4~ 20mtorr, the flow rate of HBr 100~300sccm, SF6 flow is O~20sccm, the flow rate He was 5~40sccm.

[0015] 优选地,所述底部电极材料层的材料是掺杂多晶硅且所述湿法刻蚀采用的溶液是HNO3和HF的混合溶液。 [0015] Preferably, the material of the bottom electrode layer is a doped polysilicon material and said solution is a wet etching using a mixed solution of HNO3 and HF.

[0016] 优选地,所述底部电极材料层的材料是W或WSi且所述湿法刻蚀采用的溶液是NH3 和H2A的混合溶液,温度为50〜70摄氏度。 [0016] Preferably, the material of the electrode material layer is a W or WSi, and the bottom of the wet etching solution used was a mixed solution of NH3 and H2A, the temperature is 50~70 ° C.

[0017] 优选地,所述相变层的材料选自GexSbyTe [0017] Preferably, the phase change material layer is selected from GexSbyTe

(ι-xy) > SixSbyTe(1_x_y)、SexSbyTe(1_x_y)、 PbxSbyTeAgxInyTe(1_x_y), AgxSbyTe(1_x_y)或GexAsJe(1_x_y)中的一种或组合,其中O < χ < 1,0 < y < 1 且O < x+y < 1 (Ι-xy)> SixSbyTe (1_x_y), SexSbyTe (1_x_y), PbxSbyTeAgxInyTe (1_x_y), AgxSbyTe (1_x_y) or GexAsJe (1_x_y) in one or a combination, where O <χ <1,0 <y <1, and O <x + y <1

[0018] 优选地,所述绝缘层的材料是氧化物。 [0018] Preferably, the insulating material is an oxide layer.

[0019] 优选地,所述绝缘层的材料是低介电常数材料。 [0019] Preferably, the insulating layer material is a low dielectric constant material.

[0020] 优选地,形成所述绝缘层的方法是快速退火氧化法或炉管氧化法。 Method [0020] Preferably, the insulating layer is formed rapid annealing oxidation or furnace oxidation process.

[0021] 根据本发明,可通过制作小尺寸的底部电极来减小底部电极与相变层的接触面积,从而获得良好的加热效果以较容易地发生晶态的转变,最终提高相变存储器的读写速度。 [0021] According to the present invention, the bottom electrode can be reduced contact area with the phase change layer through the bottom electrode of a small size, thereby obtaining a good heating effect to crystalline transition occurs relatively easily, and ultimately improve the phase change memory read and write speed.

附图说明 BRIEF DESCRIPTION

[0022] 本发明的下列附图在此作为本发明的一部分用于理解本发明。 [0022] The following figures of the present invention is used herein as part of the present invention to understand the invention. 附图中示出了本发明的实施例及其描述,用来解释本发明的原理。 In the embodiment shown and described embodiments of the present invention are shown, serve to explain the principles of the invention. 在附图中, In the drawings,

[0023] 图IA至IE是根据本发明的一个实施例制作相变存储器件结构的示意图; [0023] FIGS. IA through IE are schematic configuration of a memory device in accordance with one embodiment of the present invention produced a phase change;

[0024] 图2A至2E是根据本发明的另一个实施例制作相变存储器件结构的示意图;[0025] 图3A至3E是根据本发明的再一个实施例制作相变存储器件结构的示意图 [0024] FIGS. 2A to 2E are schematic configuration of a memory phase transition member according to another embodiment of the present invention produced; [0025] FIGS. 3A to 3E are schematic configuration of a memory device according to a further embodiment of the present invention produced a phase change

[0026] 图4是根据本发明一个方面的实施例制作相变存储器件结构的工艺流程图。 [0026] FIG. 4 is a process flow diagram of a phase change memory device according to the embodiment of the configuration of one aspect of the present invention is produced.

具体实施方式 Detailed ways

[0027] 在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。 [0027] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. 然而,对于本领域技术人员来说显而易见的是,本发明可以无需一个或多个这些细节而得以实施。 However, the skilled person it will be apparent that the present invention may be practiced without one or more of these details are implemented. 在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。 In other examples, in order to avoid confusion with the present invention, known in the art for some of the technical features are not described.

[0028] 为了彻底了解本发明,将在下列的描述中提出详细的步骤,以便说明本发明是如何来制作相变存储器件结构的。 [0028] For a thorough understanding of the present invention will be set forth in the following detailed description of the steps in order to explain how the present invention is to make the structure of the phase change memory device. 显然,本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。 Obviously, the purposes of the present invention is not limited to the specific details of the semiconductor skilled in the art are familiar with. 本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。 As described in detail preferred embodiments of the present invention, however, in addition to the detailed description, the present invention also may have other embodiments.

[0029] 在下列段落中参照附图以举例方式更具体地描述本发明。 [0029] In the present invention, by way of example with reference to the drawings more particularly described in the following paragraphs. 根据下列说明,本发明的优点和特征将更清楚。 The following description, features and advantages of the present invention will be apparent. 需要说明的是,附图均采用非常简化的形式且均使用非精准的比率,仅用以方便、清晰地辅助说明本发明实施例的目的。 Incidentally, the drawings are used in very simplified form and are using a non-precise ratio, only convenient, clearly the purpose of assistance in explaining an embodiment of the present invention. 应该明白,当称如层、区域或衬底这样的元件在另一个元件“上”时,它可以直接在其它元件上或者可以存在居间元件。 It should be understood that, when a layer such as, region or substrate such elements, it may or intervening elements may be present in the "on" another element directly on the other element. 相反, 当称一个元件“直接在”另一元件上时,不存在居间元件。 In contrast, when an element is referred to as being "directly on" another element, no intervening elements present.

[0030] 实施例1 [0030] Example 1

[0031] 如图IA所示,提供基底101。 [0031] As shown in FIG IA, a substrate 101 provided. 基底101上形成有栅极、源/漏极等结构,在图中均未示出。 Forming a gate on the substrate 101, source / drain structures and the like, not shown in FIG. 在基底101上形成层间介质层102,材料可以选择为低k(介电常数)材料,例如k<3。 The interlayer dielectric layer 102 is formed, the material may be selected as a low k (dielectric constant) material, for example, k <3 on the substrate 101. 层间介质层102中具有至少一个由导电材料做成的导电插塞103,例如钨插塞。 The interlayer dielectric layer 102 having at least one electrically conductive material is made of a conductive plug 103 such as tungsten plugs. 基底101、层间介质层102和导电插塞103共同构成前端器件结构141,导电插塞103的上表面在前端器件结构141的顶面露出。 Substrate 101, an interlayer dielectric layer 102 and the conductive distal plug 103 together constitute a device structure 141, the upper surface of the conductive plug 103 is exposed at the top surface of the front end of device structure 141. 在前端器件结构141的顶面以及导电插塞103的上表面形成底部电极材料层104,材料可以是硅化物材料,该硅化物材料的实例包括含有选自由Ag、Au、Al、Cu、Cr、Co、Ni、Ti、Sb、V、Mo、Ta、Nb、Ru、W、Pt、Pd、Zn 禾口Mg 中的至少一种金属元素的硅化物。 Forming a material layer 104 is a bottom electrode on a top surface of the front end of device structure 141 and the conductive plug 103 and the upper surface of the material may be a silicide material, examples of the silicide material comprises a gas such as Ag, Au, Al, Cu, Cr, Co, Ni, Ti, Sb, V, Mo, Ta, Nb, Ru, W, Pt, Pd, silicide of at least one metal element of Mg Zn Wo port. 优选地,底部电极材料层104的材料是多晶硅、非晶硅、TiN, TiAlN, WSi 或W中的一种或组合。 Preferably, the material of the bottom electrode material layer 104 is polysilicon, amorphous silicon, TiN, TiAlN, WSi or W is one or a combination of. 底部电极材料层104的形成方式可以是CVD(化学气相沉积)法或PVD(物理气相沉积)法等。 Bottom electrode layer 104 is formed so the material may be a CVD (Chemical Vapor Deposition) method or a PVD (physical vapor deposition) method or the like. 接着,在底部电极材料层104的表面形成第一绝缘层105。 Next, the first insulating layer 105 is formed on the bottom surface of the electrode material layer 104. 第一绝缘层105的材料可以是氧化物,例如低温氧化物,还可以是低k材料,本实施例中第一绝缘层105的材料选择为氮化物,例如为SiN,形成方式可以是CVD法或PVD法。 Material of the first insulating layer 105 may be an oxide, for example, low temperature oxide, may also be a low-k material, the insulating material of the first embodiment selected as the nitride layer 105 of the present embodiment, for example, SiN, is formed so it may be a CVD method or PVD.

[0032] 如图IB所示,在第一绝缘层105的表面形成光刻胶,通过曝光显影等方式形成具有图案的光刻胶层106,光刻胶层106位于导电插塞103的正上方,光刻胶层106的尺寸可以大于、等于或小于导电插塞103的尺寸,优选为小于导电插塞103的尺寸。 [0032] As shown in FIG the IB, a photoresist is formed on a surface of the first insulating layer 105, a photoresist layer 106 having a pattern by exposure and development, etc., photoresist layer 106 is located directly above the conductive plug 103 , the size of the photoresist layer 106 may be greater than, equal to or less than the size of the conductive plug 103, preferably less than 103, the size of the conductive plug.

[0033] 如图IC所示,进行刻蚀形成小尺寸的底部电极108的工艺步骤,底部电极108位于导电插塞103的正上方。 [0033] the IC shown in FIG., The process steps for etching the bottom electrode 108 is formed of a small size, the bottom electrode 108 is located directly above the conductive plug 103. 可以采用干法刻蚀形成底部电极108,也可以采用湿法刻蚀形成底部电极108,还可以先采用干法刻蚀再采用湿法刻蚀来形成底部电极108。 Dry etching may be employed to form the bottom electrode 108 may be wet etching the bottom electrode 108 is formed, may also be employed to dry etching and then wet etching of the bottom electrode 108 is formed. 所选择的刻蚀方法应该使得底部电极材料层104对第一绝缘层105的刻蚀选择比较高,例如刻蚀选择比大于或等于10。 The etching method should be selected such that the bottom electrode material layer 104 etch selection of the first insulating layer 105 is relatively high, for example, an etching selection ratio equal to or greater than 10. 其中,刻蚀选择比=刻蚀底部电极材料层104的速率/刻蚀第一绝缘层105的速率,刻蚀选择比的数值越大,刻蚀选择比越高。 Wherein the etching selection ratio = etch rate of the bottom electrode material layer 104 / a first etching rate of the insulating layer 105, the greater the etching selectivity value, the higher the etching selectivity. 刻蚀选择比不仅可以通过刻蚀工艺来调整,还可以通过底部电极材料层104和第一绝缘层105的材料的选择来进行调整。 Etching selection ratio can be adjusted only by an etching process, can be adjusted by a bottom electrode material layer 104 and the first insulating material layer 105 is selected. 以光刻胶层106为掩膜,刻蚀第一绝缘层105以形成牺牲层107,刻蚀底部电极材料层104以形成底部电极108。 In the photoresist layer 106 as a mask, the first insulating layer 105 is etched to form the sacrificial layer 107, the bottom electrode material layer 104 is etched to form a bottom electrode 108. 牺牲层107用于对其所覆盖的底部电极108进行保护,以防止最终所形成的底部电极108的上表面由于刻蚀工艺对其造成损伤而破坏了其导电性能。 Sacrificial layer 107 to protect its bottom electrode 108 is covered to prevent the upper surface of the bottom electrode 108 is formed ultimately causing damage due to the etching process and the damage of its conductive properties. 由于底部电极108对牺牲层107具有较高的刻蚀选择比,当形成底部电极108的时候,能够最大限度的保留牺牲层107,使得牺牲层107能够完全覆盖底部电极108以保护最终所形成的底部电极108的上表面。 Since the bottom electrode 108 sacrificial layer 107 has a higher etching selection ratio, when forming the bottom electrode 108, it is possible to maximize the retention of the sacrificial layer 107, such that the sacrificial layer 107 can completely cover the bottom electrode 108 is formed to protect the final upper surface of the bottom electrode 108. 最后采用例如灰化方法去除光刻胶层106。 Finally, for example, ashing photoresist layer 106 is removed.

[0034] 单独地采用干法刻蚀进行刻蚀来形成底部电极108 :选用含有卤族元素的气体, 例如包含Cl2、HBr和SF6的混合气体进行各向同性刻蚀。 [0034] alone is etched by dry etching to form the bottom electrode 108: selection of a gas containing a halogen element, for example comprising Cl2, HBr, and a mixed gas of SF6 isotropic etching. 具体工艺参数例如为,底部电极材料层104的材料选择采用多晶硅或非晶硅时,选择:功率为100〜1000W,优选为150〜 300W ;偏压为0〜IOOff ;反应室压强为5〜IOOmtorr,优选为10〜50mtorr ;Cl2,HBr和SF6 的流量均为10〜lOOsccm。 Specific process parameters, for example, when the material of the bottom electrode layer 104 is selected using polysilicon or amorphous silicon, select: power 100~1000W, preferably 150~ 300W; bias 0~IOOff; 5~IOOmtorr pressure of the reaction chamber preferably 10~50mtorr; flow Cl2, HBr and SF6 are 10~lOOsccm. 其中,sccm是标准状态下,也就是1个大气压、25摄氏度下每分钟1立方厘米(lml/min)的流量,ltorr ^ 133. 32帕斯卡。 Wherein, sccm is the standard state, i.e. 1 atm, 1 cubic centimeter per minute flow rate (lml / min) at 25 ° C, ltorr ^ 133. 32 Pascals.

[0035] 单独地采用湿法刻蚀进行各向同性刻蚀来形成底部电极108 :所用到的溶液可以根据底部电极108的材料不同从而选择不同的溶液。 [0035] separately isotropic wet etching to etch the bottom electrode 108 is formed: The solution may be used to select different solutions depending on the material of the bottom electrode 108. 例如,底部电极108的材料是掺杂多晶硅,可以选用HNO3和HF的混合溶液;底部电极108的材料是W或WSi,可以选用热的NH3 和H2A的混合溶液,温度例如在50〜70摄氏度。 For example, the material of the bottom electrode 108 is doped polysilicon, you can use a mixed solution of HNO3 and HF; material of the bottom electrode 108 is W or WSi, can use a mixed solution of NH3 and H2A of heat, for example at a temperature of 50~70 ° C.

[0036] 先采用干法刻蚀再采用湿法刻蚀来形成底部电极108 :选用含有卤族元素的气体进行各向同性或各向异性刻蚀。 [0036] first and then dry etching using a wet etching to form the bottom electrode 108: selection of a gas containing a halogen element isotropic or anisotropic etching. 各向同性刻蚀的具体参数与上述一致,各向异性刻蚀的具体工艺参数例如为:底部电极材料层104的材料选择为多晶硅或非晶硅时,选择:功率为200〜700W,优选为150〜550W ;偏压为40〜200W ;反应室压强为4〜20mtorr,优选为12 〜18mtorr ;选用气体HBr 为100 〜300sccm,优选为150 〜240sccm,SF6 为O 〜20sccm, 优选为7〜lkccnuHe为5〜40sCCm。 Isotropic etching of specific parameters and specific process parameters consistent with the above, anisotropic etching is, for example: selecting the material of the bottom electrode material layer 104 is polysilicon or amorphous silicon, select: power 200~700W, preferably 150~550W; bias 40~200W; a reaction chamber pressure of 4~20mtorr, preferably 12 ~18mtorr; HBr gas is selected 100 ~300sccm, preferably 150 ~240sccm, SF6 is O ~20sccm, preferably 7~lkccnuHe as 5~40sCCm. 再采用湿法刻蚀进行各向同性刻蚀,所用到的溶液可以根据底部电极108的材料不同进行选择。 Then isotropically etched using wet etching, the used solution can be selected according to the different material of the bottom electrode 108. 例如,底部电极108的材料是掺杂多晶硅,可以选用HNO3和HF的混合溶液;底部电极108的材料是W或WSi,可以选用热的NH3和H2A 的混合溶液(SCl溶液),温度例如在50〜70摄氏度。 For example, the material of the bottom electrode 108 is doped polysilicon, can use a mixed solution of HNO3 and HF; material of the bottom electrode 108 is W or WSi, can use a mixed solution of NH3 and heat of H2A (SCl2 solution), temperature, for example at 50 ~ 70 degrees Celsius.

[0037] 如图ID所示,在前端器件结构141的表面形成第二绝缘层109,即第二绝缘层109 包围底部电极108和牺牲层107,材料可以是氧化物,如低温氧化物,还可以是低k材料等, 形成方式可以是CVD法或PVD法,然后采用CMP方法去除部分第二绝缘层109以使第二绝缘层109中的牺牲层107露出上表面。 [0037] As shown in FIG. ID, a second insulating layer formed on a surface of the distal end 141 of device structure 109, i.e., the second insulating layer 109 surrounds the bottom electrode 108 and the sacrificial layer 107 may be an oxide material, such as low temperature oxide, further may be a low k material, may be formed so PVD method or a CVD method, a CMP method and then removing portions of the second insulating layer 109 such that the second insulating layer 109, the sacrificial layer 107 is exposed on the surface.

[0038] 如图IE所示,通过刻蚀的方法去除牺牲层107。 [0038] As shown in FIG. IE, the sacrificial layer 107 is removed by means of etching. 然后在底部电极108的表面且去除牺牲层107后留出的空位中形成相变层110,形成方式可以选择为CVD法或PVD法,并通过例如CMP等方式去除相变层110高出第二绝缘层109的部分,使相变层110的顶部与第二绝缘层109的顶部齐平。 Then the surface of the bottom electrode 108 and the sacrificial layer 107 is removed leaving a gap is formed in the phase change layer 110, forming mode may be selected to CVD or PVD, and the like by way of example, CMP removal comparing the second phase change layer 110 portion of the insulating layer 109, the top of the phase change layer and the second insulating layer 110 of the top 109 is flush.

[0039] 相变层110的材料可以是硫族化物合金,诸如锗-锑-碲(Ge-Sb-Te)、 氮-锗-锑-碲(N-Ge-Sb-Te)、砷-锑-碲(As-Sb-Te)、铟-锑-碲Qn-Sb-Te)、锗-铋-碲(Ge-Bi-Te)、锡-锑-碲(Sn-Sb-Te)、银-砷-锑-碲(Ag-As-Sb-Te)、金-砷-锑-碲(Au-As-Sb-Te)、锗-砷-锑-碲(Ge-As-Sb-Te)、硒-锑-碲(Se-Sb-Te)、锡-砷-锑-碲(Sn-As-Sb-Te)或砷-锗-锑-碲(As-Ge-Sb-Te)。 [0039] The material 110 phase change layer may be a chalcogenide alloy, such as germanium - antimony - tellurium (Ge-Sb-Te), N - Ge - Sb - Te (N-Ge-Sb-Te), arsenic - antimony - tellurium (As-Sb-Te), indium - antimony - tellurium Qn-Sb-Te), germanium - Bi - tellurium (Ge-Bi-Te), tin - antimony - tellurium (Sn-Sb-Te), silver - arsenic - antimony - tellurium (Ag-As-Sb-Te), gold - arsenic - antimony - tellurium (Au-As-Sb-Te), germanium - arsenic - antimony - tellurium (Ge-As-Sb-Te), selenium - antimony - tellurium (Se-Sb-Te), tin - arsenic - antimony - tellurium (Sn-As-Sb-Te) or arsenic - germanium - antimony - tellurium (As-Ge-Sb-Te). 替代地,相变材料可包括VA族中的元素-锑-碲,诸如钽-锑-碲(Ta-Sb-Te)、铌-锑-碲(Nb-Sb-Te)或钒-锑-碲(V-Sb-Te), 还可以是VA族中的元素-锑-硒,例如钽-锑-硒(Ta-Sb-Se)、铌-锑-硒(Nb-Sb-Se)或钒-锑-硒(V-Sb-Se)等。 Alternatively, the phase change material may include Group VA of elements - antimony - tellurium, such as tantalum - antimony - tellurium (Ta-Sb-Te), niobium - antimony - tellurium (Nb-Sb-Te) or vanadium - antimony - tellurium (V-Sb-Te), may also be VA group elements - Sb - Se, e.g., tantalum - Sb - Se (Ta-Sb-Se), niobium - Sb - Se (Nb-Sb-Se) or vanadium - antimony - selenium (V-Sb-Se) and the like. 另外,相变材料可包括VIA族中的元素-锑-碲,例如钨-锑-碲(W-Sb-Te)、钼-锑-碲(Mo-Sb-Te)或铬-锑-碲(Cr-Sb-Te)等,VIA族中的元素-锑-硒, 例如钨-锑-硒(W-Sb-Se)、钼-锑-硒(Mo-SbIe)或铬一锑-硒(Cr-SbIe),还可以例如是fei-Sb、Ge-Sb、In-Sb, In-Se, Sb2-I^3或Ge-Te合金中的一种或更多种,或可以包括Ag4n-Sb-Te、(Ge-Sn)-Sb-Te、Ge-Sb-(Se-Te)或iTe81-G15-Sb2I2 合金中的一种或更多种。 Further, the phase change material may include Group VIA elements in - antimony - tellurium such as tungsten - antimony - tellurium (W-Sb-Te), molybdenum - antimony - tellurium (Mo-Sb-Te) or chromium - antimony - tellurium ( Cr-Sb-Te) and the like, VIA family of elements - antimony - selenium, for example, W - Sb - Se (W-Sb-Se), molybdenum - Sb - Se (Mo-SbIe) or Cr-antimony - selenium (Cr -SbIe), for example, it may also be fei-Sb, Ge-Sb, in-Sb, in-Se, Sb2-I ^ 3 or one of Ge-Te alloy or more, or may comprise Ag4n-Sb- Te, (Ge-Sn) -Sb-Te, Ge-Sb- (Se-Te) or one iTe81-G15-Sb2I2 or more alloys. 相变层110的材料还可由具有多个电阻状态的过渡金属氧化物制成,例如,相变层110 的材料可以由选自包括NiO、TiO2, HfO, Nb2O5, ZnO、WO3 和CoO 或GST (Ge2StVTe5)或PCM0(PrxCal-xMn03)的组中的至少一种材料制成。 The phase change material layer 110 may be made of a transition metal oxide having a plurality of resistance states, e.g., a phase change material layer 110 may include selected from NiO, TiO2, HfO, Nb2O5, ZnO, WO3, and CoO or GST ( made of at least one material Ge2StVTe5) or PCM0 (PrxCal-xMn03) in the group. 本实施例中,相变层110的材料选择选自GexSbyTe (1_x_y)、SixSbyTe (1_x_y)、SexSbyTe (1_x_y)、PbxSbyTe (1_x_y)、AgxInyTe (1_x_y)、AgxSbyTe (1_x_y)或GexAsyTe (lTy)中的一种或组合,其中0<x<l,0<y<l且0<x+y<l。 In this embodiment, the phase change material layer 110 is selected to select GexSbyTe (1_x_y), SixSbyTe (1_x_y), SexSbyTe (1_x_y), PbxSbyTe (1_x_y), AgxInyTe (1_x_y), AgxSbyTe (1_x_y) or GexAsyTe (lTy) of one or a combination, where 0 <x <l, 0 <y <l, and 0 <x + y <l. 至此,完成相变存储器件结构的制作。 This completes the phase change memory device structure produced.

[0040] 接着,进行后续的例如形成顶部电极等工艺制作,完成整个相变存储器件的制作。 [0040] Next, the subsequent production process, for example, a top electrode or the like is formed, complete the entire phase-change memory device.

[0041] 根据本发明制作的相变存储器件结构,能够通过简单的刻蚀工艺形成较小尺寸的底部电极,减小了底部电极与相变层的接触面积,从而使得底部电极对相变层具有良好的加热效果,提高了相变存储器的读写速度,而且两者的接触面积可以通过工艺进行调整,简单方便,易于生产制造。 [0041] The phase change memory device structure fabricated according to the present invention, the bottom electrode can be formed smaller size by a simple etching process, reduce the contact area of ​​the bottom electrode and the phase change layer, so that the phase change layer on the bottom electrode It has a good heating effect to improve the phase change memory read and write speed, and contact area between the two can be adjusted by the process is simple and convenient, easy to manufacture.

[0042] 实施例2 [0042] Example 2

[0043] 如图2A所示,具有与图IB相同的结构,即具有基底201,基底201上形成有层间介质层202,层间介质层202中具有至少一个露出上表面的由导电材料做成的导电插塞203。 [0043] As shown in FIG. 2A, FIG. IB having the same structure, i.e. having a substrate 201, a substrate 201 is formed on the interlayer dielectric layer 202, the interlayer dielectric layer 202 having at least one exposed surface made of an electrically conductive material, into the conductive plug 203. 基底201、层间介质层202和导电插塞203共同构成前端器件结构Ml。 Between the substrate 201, dielectric layer 202 and the conductive distal plug 203 together constitute a device structure Ml. 前端器件结构241 顶面以及导电插塞203的上表面具有底部电极材料层204、位于底部电极材料层204表面的第一绝缘层205以及位于导电插塞203正上方的具有图案的光刻胶层206。 The front end surface of the device structure 241 and the conductive plug 203 with a bottom surface of the upper electrode material layer 204, a first insulating layer located on the bottom surface of the electrode material layer 204 and a photoresist layer 205 having a pattern of conductive plug 203 is located directly above the 206. 其形成方式与所选择的材料与图IA至图IB所示的一致。 Way formed material selected consistent with FIG IA to FIG IB.

[0044] 如图2B所示,以光刻胶层206为掩膜,刻蚀第一绝缘层205以形成牺牲层207,刻蚀底部电极材料层204以形成第一底部电极208。 As shown in [0044] FIG. 2B, photoresist layer 206 as a mask, the first insulating layer 205 is etched to form the sacrificial layer 207, the bottom electrode material layer 204 is etched to form the first bottom electrode 208. 刻蚀可以是各向异性刻蚀,例如选用含有卤族元素的气体,例如包含He、HBr和SF6的混合气体进行各向异性刻蚀。 Etching may be anisotropic etching, for example, the choice of a gas containing a halogen element, for example, a mixed gas comprising He, HBr and SF6 are anisotropically etched. 具体工艺参数例如为,底部电极材料层204的材料选择为多晶硅或非晶硅时,选择:功率为200〜700W,优选为150〜550W ;偏压为40〜200W ;反应室压强为4〜20mtorr,优选为12〜18mtorr ; 选用气体HBr为100〜300sccm,优选为150〜MOsccm,SF6为0〜20sccm,优选为7〜 15sccm, He 为5 〜40sccmo When the specific process parameters, for example, a material selected bottom electrode material layer 204 is a polysilicon or amorphous silicon, select: power 200~700W, preferably 150~550W; bias 40~200W; 4~20mtorr pressure of the reaction chamber preferably 12~18mtorr; HBr gas is selected 100~300sccm, preferably 150~MOsccm, SF6 is 0~20sccm, preferably 7~ 15sccm, He is 5 ~40sccmo

[0045] 如图2C所示,采用例如灰化方法去除光刻胶层206之后,进行对第一底部电极208 减小尺寸以形成小尺寸的第二底部电极209的工艺步骤。 [0045] As shown in FIG. 2C, for example, using an ashing method after removing the photoresist layer 206, a second bottom electrode of the first bottom electrode 208 to form a small size to reduce the size of the process of step 209. 本实施例中采用氧化方法来减小第一底部电极208的尺寸。 Examples oxidation method employed to reduce the size of the first bottom electrode 208 of the present embodiment. 选取能够与第一底部电极208进行反应的并且能够形成绝缘材料的气体,通过消耗第一底部电极208本身的材料来达到减小第一底部电极208尺寸的目的。 208 can be selected to react with the first bottom electrode and a gas capable of forming an insulating material, the first bottom electrode 208 by consuming the material itself to achieve the purpose of reducing the size of the first bottom electrode 208. 例如,可以选取O2或O3气体来与第一底部电极208进行反应,能够在第二底部电极209 的侧壁上生成氧化物层220A与220B。 For example, O2 or O3 can be selected gas 208 reacts with the first bottom electrode, capable of generating an oxide layer 220A and 220B on the side wall 209 of the second bottom electrode. 需要指出的是,第二底部电极209位于导电插塞203 的正上方。 It should be noted that the positive conductive plug 203 is located above the second bottom electrode 209. [0046] 如图2D所示,在前端器件结构241的表面形成第二绝缘层210,即第二绝缘层210 包围第二底部电极209和牺牲层207,材料可以是氧化物,如低温氧化物,还可以是低k材料等,形成方式可以是CVD法或PVD法,然后采用例如CMP方法去除部分第二绝缘层210以使第二绝缘层210中的牺牲层207露出上表面。 [0046] As shown in FIG. 2D, a second insulating layer 210 is formed on the front end 241 of the device surface configuration, i.e., the second insulating layer 210 surrounds the second bottom electrode 209 and the sacrificial layer 207 may be an oxide material, such as low temperature oxide , may also be a low-k material or the like, the way may be formed CVD or PVD method, and then using a CMP method, for example, removing portions of the second insulating layer 210 so that the sacrificial layer 210 in the second insulating layer 207 is exposed on the surface.

[0047] 如图2E所示,通过刻蚀的方法去除牺牲层207。 [0047] FIG. 2E, the sacrificial layer 207 is removed by means of etching. 然后在第二底部电极209的表面且去除牺牲层207后留出的空位中形成相变层211,形成方式可以选择为CVD法或PVD法, 并通过CMP等方式去除相变层211高出第二绝缘层210的部分,使相变层211的顶部与绝缘层210的顶部齐平。 And comparing the first phase change layer is formed 211, forming mode may be selected as CVD or PVD, and the like is removed by a CMP embodiment phase change layer 211 at the slot 207 after leaving the surface of the sacrificial layer 209 is removed and the second bottom electrode portion of the second insulating layer 210, the phase change layer 211 and a top insulating layer 210 is flush with the top. 相变层211的材料的选择与实施例1中所描述的一致。 Selecting the phase change layer in Example 1 is consistent with the described embodiments the material 211. 至此,完成相变存储器件结构的制作。 This completes the phase change memory device structure produced.

[0048] 接着,进行后续的例如形成顶部电极等工艺制作,完成整个相变存储器件的制作。 [0048] Next, the subsequent production process, for example, a top electrode or the like is formed, complete the entire phase-change memory device.

[0049] 根据本发明制作的相变存储器件结构,能够通过简单的各向异性刻蚀和氧化工艺形成较小尺寸的底部电极,减小了底部电极与相变层的接触面积,从而使得底部电极对相变层具有良好的加热效果,提高了相变存储器的读写速度,而且两者的接触面积可以通过工艺进行调整,简单方便,易于生产制造。 [0049] The phase change memory device structure fabricated according to the present invention, the bottom electrode can be formed by a smaller size and a simple anisotropic etch oxidation process, reduce the contact area of ​​the bottom electrode and the phase change layer, so that the bottom phase change layer electrode having a good heating effect to improve the phase change memory read and write speed, and contact area between the two can be adjusted by the process is simple and convenient, easy to manufacture. 由于最终所形成的底部电极,即本实施例中的第二底部电极209的侧壁上生成的氧化物为绝缘物,可以减少形成第二绝缘层210所用到的材料,同时也避免了刻蚀工艺在层间介质层202中形成凹陷而产生的可靠性问题,不仅降低了生产成本,使产品具有竞争力,而且提升了存储器件的整体性能。 Because ultimately the bottom electrode is formed, the oxide generated on the sidewalls of the second bottom electrode 209, i.e., in the embodiment of the present embodiment is an insulating material, the material may reduce the formation of the second insulating layer 210 is used, while avoiding etching a recess formed in the process reliability of the interlayer dielectric layer 202 is generated, not only reduces production costs, competitive products, and improve the overall performance of the memory device. 由于氧化物是通过消耗第一底部电极208本身的材料而直接生长在第二底部电极209的侧壁上的,与第二底部电极209的结合紧密,避免了在形成第二绝缘层210时不能与第二底部电极209紧密贴合而可能产生的可靠性问题。 Since the oxide is consumed by the first bottom electrode 208 material itself is directly grown on the sidewalls of the second bottom electrode 209, the second bottom electrode 209 in conjunction with the close, it can not be avoided when the second insulating layer 210 is formed and the second bottom electrode 209 in close contact and bonding reliability issues may arise.

[0050] 实施例3 [0050] Example 3

[0051] 如图3A所示,具有与图IB相同的结构,即具有基底301,基底301上形成有层间介质层302,层间介质层302中具有至少一个露出上表面的由导电材料做成的导电插塞303。 [0051] As shown in FIG. 3A, FIG. IB having the same structure, i.e. having a substrate 301, a substrate 301 is formed on the interlayer dielectric layer 302, an interlayer dielectric layer 302 having a conductive material on at least one surface is exposed to do into the conductive plug 303. 基底301、层间介质层302和导电插塞303共同构成前端器件结构341。 Substrate 301, an interlayer dielectric layer 302 and the conductive distal plug 303 together constitute a device structure 341. 前端器件结构341 顶面以及导电插塞303上表面具有底部电极材料层304、位于底部电极材料层304表面的第一绝缘层305以及位于导电插塞303正上方的具有图案的光刻胶层306。 The front end surface of the device structure 341 and a first insulating layer on the conductive plug 303 having a bottom surface of the electrode material layer 304 located on the bottom surface 305 of the electrode material layer 304 and the conductive plug 303 is located immediately above the photoresist layer 306 has a pattern . 其形成方式与所选择的材料与图IA至图IB所示的一致。 Way formed material selected consistent with FIG IA to FIG IB.

[0052] 如图;3B所示,以光刻胶层306为掩膜,刻蚀第一绝缘层305以形成牺牲层307,刻蚀底部电极材料层304以形成第一底部电极308。 [0052] FIG.; FIG. 3B, the photoresist layer 306 as a mask, the first insulating layer 305 is etched to form the sacrificial layer 307, the bottom electrode material layer 304 is etched to form a first bottom electrode 308. 刻蚀方法选用实施例1中可采用的各向同性刻蚀来减小底部电极108的方法。 Selected etching method employed in Example 1, an isotropic etching method to reduce the bottom electrode 108. 需要指出的是,第一底部电极308位于导电插塞303 的正上方。 It should be noted that the first bottom electrode 308 is located directly above the conductive plug 303.

[0053] 如图3C所示,采用氧化方法进一步减小第一底部电极308的尺寸,以形成第二底部电极309,并在第二底部电极309的侧壁上生成氧化层320A和320B。 [0053] As shown in FIG. 3C, using the oxidation method further reduction in size of the first bottom electrode 308, to form a second bottom electrode 309, and the formation of an oxide layer on the sidewalls 320A and 320B in the second bottom electrode 309. 氧化方法选用实施例2中氧化减小第一底部电极208的方法。 Example 2 Methods oxide oxidation reducing the first bottom electrode 208 of the embodiment method. 需要指出的是,第二底部电极309位于导电插插塞303的正上方。 It should be noted that the second bottom electrode 309 positioned directly above a conductive plug 303 of the plug.

[0054] 如图3D所示,在前端器件结构341的表面形成第二绝缘层310,即第二绝缘层310 包围第二底部电极309和牺牲层307,材料可以是氧化物,如低温氧化物,还可以是低k材料等,形成方式可以是CVD法或PVD法,然后采用例如CMP的方法去除部分第二绝缘层310以使第二绝缘层310中的牺牲层307露出上表面。 [0054] shown in Figure 3D, a second insulating layer 310 is formed on the front end 341 of the device surface configuration, i.e., the second insulating layer 310 surrounds the second bottom electrode 309 and the sacrificial layer 307, the material may be an oxide, such as low temperature oxide , may also be a low-k material or the like, the way may be formed CVD or PVD method, and then using a CMP method, for example, removing portions of the second insulating layer 310 so that the sacrificial layer 310 in the second insulating layer 307 is exposed on the surface. [0055] 如图3E所示,通过刻蚀的方法去除牺牲层307。 [0055] FIG. 3E, a sacrificial layer 307 is removed by means of etching. 然后在第二底部电极309的表面且去除牺牲层307后留出的空位中形成相变层311,形成方式可以选择为CVD法或PVD法, 并通过CMP等方式去除相变层311高出第二绝缘层310的部分,使相变层311的顶部与绝缘层310的顶部齐平。 Then the surface of the second bottom electrode 309 and the sacrificial layer 307 is removed leaving a gap is formed in the phase change layer 311, may be formed so as to select a CVD method or a PVD method, and the phase change layer 311 is removed by CMP or the like manner of comparing portion of the second insulating layer 310, the phase change layer 311 and a top insulating layer 310 is flush with the top. 相变层311的材料的选择与实施例1中所描述的一致。 Selecting the phase change layer in Example 1 is consistent with the described embodiment the material 311. 至此,完成相变存储器件结构的制作。 This completes the phase change memory device structure produced.

[0056] 接着,进行后续的例如形成顶部电极等工艺制作,完成整个相变存储器件的制作。 [0056] Next, the subsequent production process, for example, a top electrode or the like is formed, complete the entire phase-change memory device.

[0057] 通过各向同性刻蚀方法与氧化方法的结合来减小第一底部电极308形成第二底部电极309,具有极佳的效果:先各向同性刻蚀方法快速减小第一底部电极308的尺寸,再采用氧化方法进一步减小第一底部电极308的尺寸,能够形成尺寸很小的第二底部电极。 [0057] The first bottom electrode is reduced through a combination of isotropic etching method and the oxidation method 308 second bottom electrode 309, with excellent results: isotropic etching method to rapidly reduced first bottom electrode size 308, and then further reduced in size by oxidation of the first bottom electrode 308 can be formed small in size a second bottom electrode. 并在第一底部电极308的侧壁上生成一层氧化物,与第二底部电极309的结合紧密,同时补偿了由于刻蚀工艺对层间介质层302造成的凹陷,使得最终形成的底部电极(本实施例中为第二底部电极309)对相变层具有良好的加热效果,提高了相变存储器的读写速度,提升了相变存储器的整体性能。 And generating a layer of oxide on the sidewalls of the first bottom electrode 308, and the second bottom electrode 309 in conjunction with the close, while compensating due to the recess etching process caused by the interlayer dielectric layer 302 such that the final form of the bottom electrode (second bottom electrode 309 of the present embodiment) having a good heating effect on the phase change layer to improve the phase change memory read and write speeds, the phase change memory to enhance overall performance.

[0058] 对底部电极材料层进行刻蚀、或者先刻蚀再氧化以形成最终的底部电极所采用的时间可以根据实际工业中最终形成的底部电极的尺寸来选择,例如将最终形成的底部电极的尺寸定为传统工艺中底部电极尺寸的1/10〜3/4。 [0058] The bottom electrode material layer is etched, or etching the first time and then oxidized to form a final bottom electrode employed may be selected, will eventually form the bottom electrode according to the size of the bottom electrode, for example, the actual industrial finally formed sized to conventional processes bottom electrode size 1 / 10~3 / 4. 当然,所形成的底部电极的尺寸越小越好,即最后底部电极与后续形成的相变层的接触面积越小越好。 Of course, the size of the bottom electrode to be formed as small as possible, i.e. the contact area of ​​the phase change layer and finally the bottom electrode and the subsequently formed as small as possible.

[0059] 如图4所示,根据本发明一个方面的一个实施例制作相变存储器件结构的工艺流程图。 [0059] As shown in FIG 4, the phase change process flow diagram structure of a memory element in accordance with one aspect of a production embodiment of the present invention. 在步骤401中,提供前端器件结构,前端器件结构中具有至少一个导电插塞,导电插塞的上表面在前端器件结构的顶面露出,在前端器件结构的顶面和导电插塞的上表面形成底部电极材料层,在底部电极材料层的上表面形成牺牲层。 In step 401, there is provided a front end device structure, the device structure of the distal end having at least one conductive plug, the conductive surface of the plug in a top surface of a tip device structure is exposed, the top surface and the conductive front end of the device structure of the plug upper surface forming a bottom electrode material layer, forming a sacrificial layer on the bottom surface of the electrode material layer. 在步骤402中,对底部电极材料层进行刻蚀或者先刻蚀再氧化以形成底部电极,底部电极位于导电插塞的正上方。 In step 402, the bottom of the electrode material layer is etched or etched first and then oxidized to form the bottom electrode, the bottom electrode is located directly above the conductive plug is inserted. 在步骤403中,在前端器件结构的表面形成绝缘层,绝缘层包围底部电极和牺牲层且露出牺牲层的上表面。 In step 403, the insulating layer is formed on the front end surface of the device structure, the bottom electrode and the insulating layer surrounding the exposed surface of the sacrificial layer and the sacrificial layer. 在步骤404中,去除牺牲层。 In step 404, the sacrificial layer is removed. 在步骤405中,在去除牺牲层后留下的空位处形成相变层,相变层的顶部与绝缘层的顶部齐平。 In step 405, after removing the sacrificial layer remaining vacancy phase change layer is formed at the top of the phase change layer and a top insulating layer flush.

[0060] 根据如上所述的实施例制造的相变存储器件结构可应用于多种集成电路(IC) 中。 [0060] According to the embodiment described above manufacturing phase change memory device structure can be applied in a variety of integrated circuit (IC). 根据本发明的IC例如是存储器电路,如随机存取存储器(RAM)、动态RAM(DRAM)、同步DRAM (SDRAM)、静态RAM(SRAM)、或只读存储器(ROM)等等。 The IC according to the present invention, for example, memory circuits such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or read only memory (ROM) and the like. 根据本发明的IC还可以是逻辑器件,如可编程逻辑阵列(PLA)、专用集成电路(ASIC)、合并式DRAM逻辑集成电路(掩埋式动态随机存取存储器)、射频器件或任意其他电路器件。 The IC according to the present invention may also be logic devices such as programmable logic arrays (PLA), application specific integrated circuit (ASIC), a merged DRAM-logic IC (embedded Dynamic Random Access Memory), a radio frequency device, or any other circuit devices . 根据本发明的IC芯片可用于例如用户电子产品,如个人计算机、便携式计算机、游戏机、蜂窝式电话、个人数字助理、摄像机、 数码相机、手机等各种电子产品中,尤其是射频产品中。 The IC chip according to the present invention can be used, for example, consumer electronic products, such as personal computers, portable computers, game machines, cellular phones, personal digital assistants, cameras, digital cameras, mobile phones and other electronic products, especially in RF products.

[0061] 本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。 [0061] The present invention has been described by the above embodiments, it should be understood that the above examples are only for purposes of illustration and description, and are not intended to limit the invention within the scope of the described embodiments. 此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。 Moreover, those skilled in the art will be appreciated that the present invention is not limited to the above embodiment, in accordance with the teachings of the present invention may be made more of the variations and modifications, all such variations and modifications fall within the invention as claimed within the range. 本发明的保护范围由附属的权利要求书及其等效范围所界定。 The scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (17)

1. 一种制作相变存储器件结构的方法,包括:(a)提供前端器件结构,所述前端器件结构中具有至少一个导电插塞,所述导电插塞的上表面在所述前端器件结构的顶面露出,在所述前端器件结构的顶面和所述导电插塞的上表面形成底部电极材料层,在所述底部电极材料层的上表面形成牺牲层;(b)对所述底部电极材料层进行刻蚀或者先刻蚀再氧化以形成底部电极,所述底部电极位于所述导电插塞的正上方;(c)在所述前端器件结构的表面形成绝缘层,所述绝缘层包围所述底部电极和所述牺牲层且露出所述牺牲层的上表面;(d)去除所述牺牲层;(e)在去除所述牺牲层后留下的空位处形成相变层,所述相变层的顶部与所述绝缘层的顶部齐平。 CLAIMS 1. A method of making a phase change memory device structure, comprising: (a) providing a front end device structure, the device structure having a front end at least one conductive plug, said conductive plug on the distal surface of the device structure the top surface is exposed, the bottom electrode material layer is formed on a top surface of the front end of the device structure and the upper surface of the conductive plug, forming a sacrificial layer on the bottom surface of the electrode material layer; (b) the bottom etching the electrode material layer is then etched or oxidized to form a first bottom electrode, the bottom electrode is located directly above the conductive plug insertion; (c) forming an insulating layer on the surface of the front end of the device structure, surrounding the insulating layer the bottom electrode and the sacrificial layer and the exposed surface of the sacrificial layer; (d) removing the sacrificial layer; (e) form a phase change layer in the space left after the removal of the sacrificial layer, the top of the phase change layer and the top of the insulating layer flush.
2.如权利要求1所述的方法,其特征在于,所述底部电极材料层的材料是硅化物。 2. The method according to claim 1, characterized in that the material of the bottom electrode material layer is a silicide.
3.如权利要求1所述的方法,其特征在于,所述底部电极材料层的材料是包含选自由Ag、Au、Al、Cu、Cr、Co、Ni、Ti、Sb、V、Mo、Ta、Nb、Ru、W、Pt、Pd、Zn 禾口Mg 中的至少一种金属元素的硅化物。 3. The method according to claim 1, wherein the bottom electrode material layer comprising a material selected from the group consisting of Ag, Au, Al, Cu, Cr, Co, Ni, Ti, Sb, V, Mo, Ta at least one metal silicide elements Nb, Ru, W, Pt, Pd, Zn or Mg Wo port.
4.如权利要求1所述的方法,其特征在于,所述底部电极材料层的材料是多晶硅、非晶硅、TiN、TiAlN、WSi或W中的一种或组合。 4. The method according to claim 1, characterized in that the material of the bottom layer of the electrode material is polysilicon, amorphous silicon, TiN, TiAlN, WSi or W is one or a combination of.
5.如权利要求1所述的方法,其特征在于,所述牺牲层的材料是SiN。 5. The method according to claim 1, characterized in that the material of the sacrificial layer is SiN.
6.如权利要求1所述的方法,其特征在于,所述(b)步骤的刻蚀为干法刻蚀、湿法刻蚀或干法刻蚀与湿法刻蚀的结合。 6. The method according to claim 1, wherein said etching step (b) is combined dry etching, wet etching or dry etching and wet etching.
7.如权利要求6所述的方法,其特征在于,所述干法刻蚀采用的气体为含有卤族元素的气体。 7. The method according to claim 6, characterized in that the gas used in the dry etching gas containing a halogen element.
8.如权利要求6或7所述的方法,其特征在于,所述底部电极材料层的材料是多晶硅或非晶硅,所述(b)步骤的刻蚀为干法刻蚀或干法刻蚀与湿法刻蚀的结合,其中,所述干法刻蚀采用的气体包含Cl2、HBr和SF6,且所述干法刻蚀采用的功率为100〜1000W,偏压为0〜 100W,反应室压强为5〜lOOmtorr,Cl2, HBr和SF6的流量均为10〜lOOsccm。 8. The method of claim 6 or claim 7, characterized in that the base material of the electrode material layer are polycrystalline or amorphous silicon, the etching step (b) is a dry etching or a dry engraved etching and wet etching in combination, wherein said dry etching using a gas containing Cl2, HBr and of SF6, and the power used for the dry etching 100~1000W, bias 0~ 100W, the reaction chamber pressure is 5~lOOmtorr, flow Cl2, HBr and SF6 are 10~lOOsccm.
9.如权利要求6所述的方法,其特征在于,所述底部电极材料层的材料是多晶硅或非晶硅,所述(b)步骤的刻蚀为干法刻蚀或干法刻蚀与湿法刻蚀的结合,其中,所述干法刻蚀采用的气体包含He、HBr和SF6,且所述干法刻蚀采用的功率为200〜700W,偏压为40〜 200W,反应室压强为4〜20mtorr,HBr的流量为100〜300sccm,SF6的流量为0〜20sccm, He的流量为5〜40sccm。 9. The method according to claim 6, characterized in that the base material of the electrode material layer are polycrystalline or amorphous silicon, the etching step (b) is a dry etching or a dry etching and binding wet etching, wherein the dry etching using gas containing He, HBr and of SF6, and the power used for the dry etching 200~700W, bias 40~ 200W, the reaction chamber pressure for the flow 4~20mtorr, HBr is 100~300sccm, SF6 flow is 0~20sccm, the flow rate He was 5~40sccm.
10.如权利要求6所述的方法,其特征在于,所述底部电极材料层的材料是掺杂多晶硅且所述湿法刻蚀采用的溶液是HNO3和HF的混合溶液。 10. The method according to claim 6, characterized in that the material of the bottom electrode layer is a doped polysilicon material and said solution is a wet etching using a mixed solution of HNO3 and HF.
11.如权利要求6所述的方法,其特征在于,所述底部电极材料层的材料是W或Wsi且所述湿法刻蚀采用的溶液是NH3和H2A的混合溶液,温度为50〜70摄氏度。 11. The method according to claim 6, characterized in that the base material of the electrode material layer is a W or Wsi and the wet etching solution used was a mixed solution of NH3 and H2A, the temperature is 50~70 degrees Celsius.
12.如权利要求1所述的方法,其特征在于,所述相变层的材料选自GexSbyTe(1_x_y)、 SixSbyTe (1_x_y)、SexSbyTe (1—x—y)、PbxSbyTe (1—x—y)、 AgxInyTe (1_x_y) > AgxSbyTe (1_x_y)或GexAsyTe (1_x_y)中的一种或组合,其中0 < χ < 1,0 < y < 1且0 < x+y < 1。 12. The method according to claim 1, wherein said phase change material layer is selected from GexSbyTe (1_x_y), SixSbyTe (1_x_y), SexSbyTe (1-x-y), PbxSbyTe (1-x-y ), the AgxInyTe (1_x_y)> AgxSbyTe (1_x_y) or GexAsyTe (1_x_y) one or a combination, where 0 <χ <1,0 <y <1 and 0 <x + y <1.
13.如权利要求1所述的方法,其特征在于,所述绝缘层的材料是氧化物。 13. The method according to claim 1, characterized in that the material of the insulating layer is an oxide.
14.如权利要求1所述的方法,其特征在于,所述绝缘层的材料是低介电常数材料。 14. The method according to claim 1, characterized in that the material of the insulating layer is a low dielectric constant material.
15.如权利要求1所述的方法,其特征在于,形成所述绝缘层的方法是快速退火氧化法或炉管氧化法。 15. The method according to claim 1, characterized in that the method of forming the insulating layer is a rapid annealing oxidation or furnace oxidation process.
16. 一种包含由权利要求1〜15中任一项所述的方法形成的相变存储器件结构的集成电路,其中所述集成电路选自随机存取存储器、动态随机存取存储器、同步随机存取存储器、静态随机存取存储器、只读存储器、可编程逻辑阵列、专用集成电路、掩埋式动态随机存取存储器和射频器件。 16. A method comprising 1~15 according to any one of claims phase change memory device formed in an integrated circuit structure, wherein the integrated circuit is selected from a random access memory, dynamic random access memory, synchronous random access memory, static random access memory, read only memory, programmable logic arrays, application specific integrated circuits, buried and the RF dynamic random access memory device.
17. 一种包含由权利要求1〜15中任一项所述的方法形成的相变存储器件结构的电子设备,其中所述电子设备选自个人计算机、便携式计算机、游戏机、蜂窝式电话、个人数字助理、摄像机和数码相机。 17. A method according to any one of claims 1~15 claims formed by a phase change element structure of a memory electronic device, wherein said electronic device is selected from a personal computer, a portable computer, a game machine, a cellular phone, personal digital assistants, camcorders and digital cameras.
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