TWI311822B - - Google Patents
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- TWI311822B TWI311822B TW95134167A TW95134167A TWI311822B TW I311822 B TWI311822 B TW I311822B TW 95134167 A TW95134167 A TW 95134167A TW 95134167 A TW95134167 A TW 95134167A TW I311822 B TWI311822 B TW I311822B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Led Device Packages (AREA)
Description
1311822 九、發明說明: 【發明所屬之技術領域】 本發明係有關-種利用晶片直接封裝技術(Chip Qn BQard)之咖封裝 結構,適用於發光二極體或類似結構者。 【先前技術】 ' ㈣發光二減為-種可將電能轉換為光能之高效率冷光發光元件, -並具有耗電量低、壽命長等優點,故發光二極體多半用於電子產品指示用 嫌途者。 一般而言,習用發光二極體結構,請參第5圖,主要係設有一具凹槽 八1之基座六,該凹槽厶1内結合有—晶)^,該晶0再透過一連結線 C與另-支架D連結,最後再藉—透光層E的射出成型,將基座a、晶片 B、連結線C及另-支架D結合為-體,完成發光二極體的製作。 然,上述傳統之發光二極體,不論基座A的體積多小,當透光層㈣ 各凡件包覆結合成-體後’仍具有一定的體積,而在科技日新月異的現代, 籲每-種電子產品均標謗輕、薄、短、小,因此傳統之發光二極體結構已不 符現代產品的需求。 • 彳餅此,本侧人舰提供-種LED之封賴構,令發光二極體之 體積大幅職,乃㈣研思、設計域,啸供㈣从朗,為本發明 所欲研創之創作動機者。 【發明内容】 本發明之主要目的’在提供賴層絲板取代支架,而可大幅 縮減體積的LED之封裝結構者。 1311822
為達上述目的,本發明包括:一雙層式基板、至少一晶片、至少二連 結導線、軟膠體以及硬膠體;其中該雙層式基板主要係於一絕緣基板上設 置有導電圖案,該圖案頂面塗佈一層隔離膠’且塗佈隔離膠時係預留導電 圖案之結合區及數個電極區,該晶片則結合於結合區中,同時該晶片透過 二連結導線與導電圖案連結導通,其中,該硬膠體係環設於該晶片周圍, 並使該晶片結合區形成一凹杯狀,令軟膠體可順利地封合該發光晶片及該 等連接導線,且不虞溢出該結合區之外,以完成LED封裝結構者。 本發明之其他特點及具體實施例可於以下配合附圖之詳細說明中,進 一步瞭解。 【實施方式】 請參第1〜2圖,係為本發明之較佳實施例,該發光二極體丄主要設 有-雙層式基板、-發光晶片2〇、二連結導線3 〇以及—膠體,該發光 二極體1的表面中央適處設有一結合區工1χ,且於二端各設有一正電極 112與二負電極113之電極區’請同參第3圖,該雙層式基板主要設 有、”邑緣基板1 〇(其中該絕緣基板1 〇係為印刷電路板細竟基板),該 絕緣基板1 G頂部結合導電層,該導電層並藉侧的技術,侧出所需的 導電圖案1 1,並於塗佈—層PlWf所製成之隔離膠丄2,塗佈該 層隔離膠1 2時絲預留數個部位,如結合區1 1 1、正電極丄i 2與負 電極113等部位不需塗佈隔離膠12。 請同參第3、4圖,該發光晶片2 〇結合於雙層式基板的結合區工工 1 ’並於該發光晶片2 Q下以銀職定於結合區111上之導電圖案丄工 1311822 介年㈠ (正雷 …, 極112)透過連結導線3 〇將發光晶片2 〇與另一極之導電圖案 電極1 1 3)被連接’該發光“ 2㈣直接結合在導電圖案 ,電極1i 2)上,但可進—步同樣藉由連接打線3◦加以連接, ii合時,_ ^硬度較高的硬膠體4 Q,將其觀在結合區1 U_,令該結合 區形成~购造型,亦即,使得位在結合區1 1 1内部之發光晶片2 〇周 2具有1形擋牆’而後’使用軟膠體4丄由硬膠體4 Q上方封合,於封 錄膠體4 1會被舰在難所形成之封裝輯内部,不 、、、而7發光曰曰片2 ◦以及二連結導線3 0可被穩固地封裝在雙層式 基板上,即完成發光二極體之封裝結構。 再者,上述塗佈於頂面的隔離膠丄2,係用以保護導電圖案u,以 及杜絕不柄令導電_短路的輯者。另外紐光晶# 2 G可為藍光晶 片’同時該硬膠體40、軟膠體41之中亦可設為混置有營光粉的硬膠體 4 0、軟膠體4 χ,藉此令製作完成的發光二極體成為—白光發光二極體 者。 - 由上可知,本發明之裝置係具有如下實用優點: • 1、利用雙層式基板取代傳統發光二極體的支架,故可有效且大幅度縮減 發光二極體的體積者。 2、§亥發光晶片與連結導線透過膠體的封合,不僅令將發光晶片與連結導 線更緊密結合於雙層式基板上,並可透過膠體保護發光晶片與連結導 線不受破壞者。 1311822 对 ^ JS' = 准以上所述者’僅為本發明之較佳實施例,當不能肋限定本發明可 實施之範圍,LH+卿謂慨娜冑,議為柳 本發明之實質内容。 綜上所述,本發明柯達到創作之預期目的,提供_種⑽之封裝結 冓,具有實闕值紐,銳法提出發明專利申請。 1311822 【圖式簡單說明】 第1圖係為本發明實施例之立體外觀圖。 第2圖係為本發明實施例之俯視圖。 第3圖係為本發明雙層式基板之平面示意圖。 第4圖係為本發明實施例之組合剖示圖。 第5圖係為習用發光二極體之側示圖。 【主要元件符號說明】
1、發光二極體 10、 絕緣基板 11、 導電圖案 1 1 1、結合區 112、 正電極 113、 負電極 12、 隔離膠 2 0、晶片 3 〇、連結導線 4 0、硬膠體 41、軟膠體 A、基座 A 1、凹槽 B、晶片 9 1311822 c、連接線 D、 支架 E、 透光層
10
Claims (1)
1311822 十、申請專利範園: 1 一一 1.-種LED之封裝結構,係包括: 又層式基板,係由一絕絲板以及一具有導電圖案之導電層所構 成’、中''有導電圖案之導電層上之除了晶片結合區及正、負極電極 區以外之區域係塗饰一隔離膠; 、 光曰曰片,係女裝於該雙層式基板的晶片結合區内; 一硬膠體層,係環設於該晶諸合區厢,俾使該㈣#合區形成 一凹杯狀; 以 ^條連、、Q導線,用以使該發光晶片與該正負極電極區連接; 及 軟膠體係包覆該由硬膠體層形成凹杯狀的晶片結合區内,用以 封裝該發光晶片及該等連結導線。 士申明專利I巳圍第1項所述之LED之封裝結構,其中該隔離膠為隔 離膠。 ί構,其中該軟硬膠體内摻設 3.如申請專利範圍第i項所述之LED之封袭結構, 有螢光粉者。 4·如申請專鄕®第1或3酬狀㈣之封裝結構,其巾鱗膠體為石夕 膠材質。 5·如申請專利範圍第i或3項所述之之封缝構,其帽轉體為環 氧樹脂材質。 6.如申請專利範圍第i項所述之⑽之封裝結構,其中該絕緣基板為印刷 電路板者。 11 1311822 7.如申請專利範圍第1項所述之LED之封裝結構,其中該絕緣基板為陶瓷 基板者。 12 1311822 七、指定代表圖: (一) 本案指定代表圖為:第(1 )圖。 (二) 本代表圖之元件符號簡單說明: 1、發光二極體 10、 絕緣基板 11、 導電圖案 12、 隔離膠 1 12、正電極 1 1 3、負電極 4 0、硬膠體 41、軟膠體 八、本案若有化學式時,請揭示最能顯示發明特徵的化學式:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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TW95134167A TW200814367A (en) | 2006-09-15 | 2006-09-15 | Package structure of light emitting diode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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TW95134167A TW200814367A (en) | 2006-09-15 | 2006-09-15 | Package structure of light emitting diode |
Publications (2)
Publication Number | Publication Date |
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TW200814367A TW200814367A (en) | 2008-03-16 |
TWI311822B true TWI311822B (zh) | 2009-07-01 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW95134167A TW200814367A (en) | 2006-09-15 | 2006-09-15 | Package structure of light emitting diode |
Country Status (1)
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TW (1) | TW200814367A (zh) |
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2006
- 2006-09-15 TW TW95134167A patent/TW200814367A/zh not_active IP Right Cessation
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TW200814367A (en) | 2008-03-16 |
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