TWI311369B - Method for fabricating identification code on a substrate - Google Patents

Method for fabricating identification code on a substrate Download PDF

Info

Publication number
TWI311369B
TWI311369B TW095110225A TW95110225A TWI311369B TW I311369 B TWI311369 B TW I311369B TW 095110225 A TW095110225 A TW 095110225A TW 95110225 A TW95110225 A TW 95110225A TW I311369 B TWI311369 B TW I311369B
Authority
TW
Taiwan
Prior art keywords
identification code
substrate
identification
line
circuit board
Prior art date
Application number
TW095110225A
Other languages
English (en)
Other versions
TW200737484A (en
Inventor
Kuang-Lin Lo
Yung-Hui Wang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW095110225A priority Critical patent/TWI311369B/zh
Priority to US11/467,568 priority patent/US20070220742A1/en
Publication of TW200737484A publication Critical patent/TW200737484A/zh
Application granted granted Critical
Publication of TWI311369B publication Critical patent/TWI311369B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/46Bases; Cases
    • H01R13/465Identification means, e.g. labels, tags, markings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • H05K1/0269Marks, test patterns or identification means for visual or optical inspection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09927Machine readable code, e.g. bar code
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936Marks, inscriptions, etc. for information
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Description

’f-doc/g 九、發明n明: 【發::屬之技術領域】 板上开種基板,且特別是有關於—種於基 辨4碼的製作方法。 【先前技術】 的構Hi半物封裝製程中,_封裝基板是經常使用 成。^丰1之―’其係由多個帶狀分佈的陣列基板所構 成電體70件(例如晶片)與陣列基板中的子基板完 件’以形成陣列封裝型態之晶片封裝結構。 切割每—㈣基板的子基板及其對應的封膠體,以 y立刀開的晶片封裝單元,數量約有數百個之多。 一值得注意的是,生產陣列封裝基板的製程中,僅對同 一批生產的產品分別給個批號以及—檢查號,但未給 予陣列基板(或母板)巾每-個子基板—個可供辨識其來 源或生產日期_識碼。因^,當陣列基板被切割成數量 龐大且獨立純的子基板時,就失去躺各個子基板的任 何參考資料,只有在出貨的晶片封裝產品上貼上出貨的序 號(ID number)而已。這對生產管理、品質控管以及後續 的產απ可罪度分析上,均有明顯不足的地方,一旦發生子 基板線路故障時,則無法追溯其根源的母板,找出可能故 障的原因。 【發明内容】 本發明的目的就是在提供一種基板辨識碼的製作方 13113氣- 吏基板上形成可供辨識其來源及相關資料 一从提昇生產管理及品質控管的效力。 勺辨識 本發明的再一目的是提供— 板’:追溯其根源,並可依此找出可能故= 提出-種基板韻碼的製作方法 :薄:先,提供-基板線路所需之-金屬薄膜 接著於非線路線路區及-竭區, 介電種具顺碼之線路基板,其包括多個 二電層之間’而金屬薄膜包含—線路區及—非線=鄰 卜,辨識碼形成於非線路區上。 品。 ,照本發日所述,基板具衫個介電展, 、’涛膜的線路11及非線路區配置於相鄰二介電層:而 此金屬薄膜例如是—表面金屬層絲置於基板之二心^。 的一内連線金屬層。 增上 2照本發明的實施例所述,非線路區上的辨識碼以雷 射,二形成包括條碼或序號碼等可供電腦辨識的圖案或 數字。 ’' / …本發明之基板具有不同序號或相關資料的辨識碼,其 形成於基板的麵路區上,作為辨識之用。因此當陣列基 板(或母板)被切割為多數個子基板時,也能根據基板上 的辨識碼來得知其根源,故可提昇生產管理及品質控管的 效力。 13113 鯓 twf.doc/g w ίΓί”和其他目的、特徵和優點能更明顯 重下文寸车乂么貫施例,並配合所附 明如下。 τ 凡 【實施方式】 圖1〜圖3緣示形忐_抛立址 _ ^ ^ 成辨硪碼於—金屬薄膜上的流程 ,提供—層板1〇0,該層板100具有 二i二'ηη層110上的二金屬薄膜120、130,此二 ί,Γ膜金屬為銅箔或電鑛的銅層’亦可為其他金 ?二:宏Λ 3〇可藉由曝光、顯影以及卿 热知的圖案化線路技_成圖2 ^ 124’在此不再詳述其圖荦 降及接口塾 _液及其清潔的溶液。在本實施;先::薄:=二 ==一卜,更特別保== m所在的區域線=二圖3之_馬 蛳踩制於〜 α之綠路I作亦可在圖3之辨 i實施性叙後再進行’不受其__序而影響 d2 v金屬薄膜120具有—線路區ai以及-非 及Ϊ= ίΓ A1包含所有線路122、接合塾Μ以 的巫 荨線路傳輸結構,而非線路區A2為一完整 、+面,故可在此完整的平面上製作所 ; 以形成如圖3A之序號碼論或如 ,案或數子丄 關序號碼128a或條碼128b的編碼^之條碼腸。有 檢杳泸、母姑沾/ 谷可包括生產批號、 -就母_序如及彳目賴料 131131 f.doc/g 列方式可自行設定,以利於生產管理及品質控管 圖3C緣示的另-f施例,是以麵續性_方式將 ΐ束打在非線路區A2上,進而將多個辨識用的數字i文 子鎮空成為一辨識碼128c。 凊茶考圖4,在完成圖2之線路以及圖3 ,,於核4 11Q及其金㈣膜上依序形成介電層ai4〇、 又面金屬層150以及防鋒層16〇,以使金屬薄膜⑶、⑽ 位在相鄰二介電層11G、_之間,並以導電孔123或導通 m?至表面金屬層150的接點152 ’以對外傳輸訊 唬。、在本貫施例中,雖然辨識碼128 {形成於核心層㈣ (或稱核心介電層)上的金屬薄膜120 ’但亦可形成於表 面金屬層150或其他層數的金屬層上,在此不以為限。^ 辨識碼128可隱藏在線路基板2〇〇的防銲層16〇下方, 當以具有透視能力的X射線照射時,仍可清楚得知辨識碼 128’進而得知線路基板2〇〇的相關資訊。因此,在現有技 術的配合下,隱藏式的辨識碼128可取代現行在出貨的晶 片封衣產πσ表面貼上序號,不亦被發現故可提高機密性。 匕外富陣列基板(或母板)被切割為多數個子基板時, 也能根據線路基板200上的辨識碼128來得知其根源,— 旦發生基板線路故障時,則可根據辨識碼追溯其根源的母 板,找出可能故障的原因及批號,以改善產品的品質。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 1311 撒_ 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1〜圖3繪示形成一辨識碼於一金屬薄膜上的流程 示意圖。 圖3A〜圖3C繪示三種辨識碼的示意圖。 圖4繪示本發明之具辨識碼的線路基板示意圖。 【主要元件符號說明】 100 :層板 • 110:核心層 120、130 :金屬薄膜 122 :線路 123 :導電孔 124 :接合墊 125 :導通孔 126 :未被圖案化的區域 128 :辨識碼 12 8 a :序號碼 128b :條碼 128c :鏤空辨識碼 140 :介電層 150 :表面金屬層 152 :接點 160 :防銲層 200 :線路基板 I3113^2twfdoc/g A1 :線路區 A2 :非線路區

Claims (1)

1311369 f-12-03 十、申請專利範圍: 一 ^ —種基板辨識碼的製作方法,包括: 進行^彳卜2線路所需之—金屬薄臈’並對該金屬薄膜 介電ί 「上形成—辨識碼’其令該基板具有^個 間。曰以線路區及該非線路區配置於相鄰二介電層之 、土 ϋ申明專利範圍第1項所述之基板辨識碼的製作方 路_於為核心層’而該線路區及該非線 3·如申明專利範圍第丨項所述之基板辨識碼的製作方 法,其中形成該辨識碼的方法包括以雷射將該辨識 形成於該非線路區上。 工 、4·如申明專利範圍第1項所述之基板辨識碼的製作方 法,其中该辨識媽包括條碼或序號石馬。 5. —種具辨識碼之線路基板,包括: 多個介電層; 一金屬薄膜,配置於相鄰二介電層之間,該金屬薄犋 包含一線路區及—非線路區;以及 、 一辨識碼,形成於該非線路區上。 6. 如申凊專利範圍第5項所述之具辨識碼之線路基 板’其中该辨識碼是以雷射將其鏤空形成於該非線路區上。 7. 如申请專利範圍第5項所述之具辨識碼之線路基 板’其中δ亥辨識碼包括條碼或序號碼。 11 1311369 97-12-03 8.如申請專利範圍第5項所述之具辨識碼之線路基 板,其中該些介電層之一為核心層。
12
TW095110225A 2006-03-24 2006-03-24 Method for fabricating identification code on a substrate TWI311369B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW095110225A TWI311369B (en) 2006-03-24 2006-03-24 Method for fabricating identification code on a substrate
US11/467,568 US20070220742A1 (en) 2006-03-24 2006-08-28 Method for fabricating identification code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095110225A TWI311369B (en) 2006-03-24 2006-03-24 Method for fabricating identification code on a substrate

Publications (2)

Publication Number Publication Date
TW200737484A TW200737484A (en) 2007-10-01
TWI311369B true TWI311369B (en) 2009-06-21

Family

ID=38531815

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095110225A TWI311369B (en) 2006-03-24 2006-03-24 Method for fabricating identification code on a substrate

Country Status (2)

Country Link
US (1) US20070220742A1 (zh)
TW (1) TWI311369B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7884472B2 (en) * 2008-03-20 2011-02-08 Powertech Technology Inc. Semiconductor package having substrate ID code and its fabricating method
DE102009017266A1 (de) * 2009-01-30 2010-08-05 Weidmüller Interface GmbH & Co. KG Verfahren und Vorrichtung zum Markieren von Reihenklemmen
ATE540451T1 (de) * 2009-03-18 2012-01-15 Alcatel Lucent Identifizierung passiver bauteile für elektronische vorrichtungen
GB2485337A (en) * 2010-11-01 2012-05-16 Plastic Logic Ltd Method for providing device-specific markings on devices
US9589900B2 (en) * 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9666522B2 (en) 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
JP6503813B2 (ja) * 2015-03-19 2019-04-24 日本電気株式会社 識別装置、識別方法およびトレーサビリティシステム
CN111128963B (zh) 2018-10-30 2022-04-26 成都京东方光电科技有限公司 一种显示基板母板及其制作方法
DE102020111701A1 (de) * 2020-04-29 2021-11-04 Rogers Germany Gmbh Trägersubstrat, Verfahren zur Herstellung eines solchen Trägersubstrats und Verfahren zum Auslesen einer Kodierung im Trägersubstrat

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4802944A (en) * 1986-09-29 1989-02-07 Monarch Marking Systems, Inc. Method of making deactivatable tags
US5342498A (en) * 1991-06-26 1994-08-30 Graves Jeffrey A Electronic wiring substrate
GB9202940D0 (en) * 1992-02-12 1992-03-25 Amblehurst Ltd Image enchancement
US6087940A (en) * 1998-07-28 2000-07-11 Novavision, Inc. Article surveillance device and method for forming
US8009348B2 (en) * 1999-05-03 2011-08-30 E Ink Corporation Machine-readable displays

Also Published As

Publication number Publication date
TW200737484A (en) 2007-10-01
US20070220742A1 (en) 2007-09-27

Similar Documents

Publication Publication Date Title
TWI311369B (en) Method for fabricating identification code on a substrate
TWI300320B (en) Substrate embedded with passive device
CN102891131B (zh) 用于制造半导体封装元件的半导体结构及其制造方法
US6855626B2 (en) Wiring substrate having position information
JP5212549B2 (ja) リジッド−フレキシブル多層配線基板の製造方法および集合基板
JP5960389B2 (ja) 半導体集積回路チップを分離および搬送する方法
JP2011066340A5 (zh)
JP2012512541A5 (zh)
TW201216379A (en) Leadframe package structure and manufacturing method thereof
JP2009075059A (ja) プローブカード・アセンブリ用基板、プローブカード・アセンブリおよび半導体ウエハの検査方法
JP2008160051A (ja) 製作情報の識別できるプリント回路基板
TWI381780B (zh) 可辨識印刷電路板之製造方法
CN103898498B (zh) 黑化药水及透明印刷电路板的制作方法
CN101483158A (zh) 芯片、芯片制造方法以及芯片封装结构
KR20100056004A (ko) 전자 태그가 내장된 인쇄회로기판 및 제조방법
Bakr et al. Over-molding of flexible polyimide-based electronic circuits
CN108346640B (zh) 半导体结构及其制作方法
CN106920464A (zh) 一种可折叠显示屏的背板结构及其制备方法
TW202414726A (zh) 半導體的封裝結構及其封裝方法
JP2003086735A (ja) 位置情報付配線基板及びその製造方法並びに半導体装置の製造方法
JP2008028426A (ja) 半導体装置の製造方法
TW508768B (en) Multi-layer interconnect
JP2008052492A (ja) 非接触データキャリア、非接触データキャリア用配線基板
JP3617264B2 (ja) プラスチック回路基板の電解めっき方法
JP2014127634A (ja) 配線板の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees