1309829 九、發明說明： 【發明所屬之技術領域】 本發明係關於快閃記憶體裝置’且更特定言之，本發明 係關於-種NAND型快閃記憶體裝置，其經級態以防止鄰 近汲極及源極選擇電晶體之記憶體單元處㈣式化干㈣ 改良記憶體單元之程式化速度。 【先前技術】 快閃記憶體被稱為可操作而未有更新功能之裝置，其已 知為甚至當電源在其中被中斷時仍能夠保持資料的非揮發 性記憶體裝置之類型。在快閃記憶體中，"程式化，，係指一 用於在記憶體單元中寫入資料之操作。"擦除"係指一用於 自士記憶體單元消除資料之操作。此等記憶體單元根據單元 結構及操作條件被粗略地分類為n〇r型及NAND型。 型快閃圮憶體（其中記憶體單元電晶體之源極耦接至一接 地電壓）可使用隨機位址程式化記憶體單元之擦除資料， 且可用於為尚操作速度所需之應用中。NAND型快閃記憶 體組態有串聯耦接之複數個記憶體單元電晶體組態以形成 一在一汲極選擇電晶體與一源極選擇電晶體之間連接的單 元串’其可用於高密度資料儲存。 圖1展示了 一習知NAND型快閃記憶體裝置。 參看圖1 ’ 一定數目之記憶體單元MC0〜MC3 1在—汲極 選擇電晶體DST與一源極選擇電晶體ssir之間串聯耦接。 慮及裝置拓撲及密度，典型設計涉及丨6、32、或64個記惊 體單元。 ~ I07205.doc 1309829 在圖1中’存在複數個單元串，每一者均包含32個記憶 體單元。由一單個字線（例如，WL0)控制之記憶體單元（例 如’ MC0)形成一個頁（其為一組記憶體單元）。圖1例示性 地展示了 3 2個頁。 然而’如圖1所示之NAND型快閃記憶體裝置易受由記憶 體單元MC0(其耦接至鄰近源極選擇線SSL之第一字線WL0 及一取消選定之位元線（例如，BL0)而產生之程式干擾及 來自麵接至鄰近汲極選擇線DSL之最後字線及取消選定之 位元線BL0的記憶體單元MC3 1之程式干擾的損害。由於當 一接地電壓0 V、一電源電壓Vcc及一程式抑制電壓vpass 分別施加於源極選擇線SSL、汲極選擇線DSL及剩餘字線 WL1〜WL31時，源極選擇電晶體SST、汲極選擇電晶體 DST及该寻記憶體單元MC0〜MC3 1分別被升壓至〇 v、1 V 及約8 V，所以發生了此等程式干擾。 更具體言之，歸因於源極選擇電晶體SST與記憶體單元 MC0之間通道電壓（意即〇 ¥與8 v之間）之差異，一橫向電 場在源極選擇電晶體SST與記憶體單元MC〇之間強烈形 成。歸因於汲極選擇電晶體DST與記憶體單元厘(：31之間通 道電壓(意即i 乂與8 V之間)之差#，一橫向電場亦在汲極 選擇電晶體DST與記憶體單元河口丨之間形成。若此等電壓 差異導致橫向之強烈電場，則在源極選擇電晶體sst之一 閘極氧化物薄膜與一矽基板Si_Sub之間的邊界處所產生之 電子沿該石夕基板Si_Sub之表面向記憶體單元mc〇移動，從 而產生熱電子。所產生之彼等熱電子在—橫向方向上移動 107205.doc 1309829 並流入記憶體單元MC0及MC3 1之浮動閘極中，從而程式 化記憶體單元MC0及MC31。 同時，耦接至一選定之位元線BL1及第一及最後字線 WL0及WL31之記憶體單元MC0及MC31的程式化速度慢於 其它記憶體單元MCI〜MC30之程式化速度。該等較慢程式 化速度之原因係因為耦接至第一及最後字線WL0及WL3 1 與選定之位元線BL1的記憶體單元MC0及MC31之臨限電壓 Vt低於耦接至剩餘字線WL1〜WL30之記憶體單元 > MC卜MC30的臨限電壓使得在源極選擇線SSL與第一字線 WL0之間以及在汲極選擇線DSL與最後字線WL3 1之間存在 電壓差異。 換言之，記憶體單元MC0及MC31受源極選擇電晶體SST 及汲極選擇電晶體DST之電位的影響，使得記憶體單元 MC0及MC3 1之臨限電壓變得低於其它記憶體單元 MCI〜MC30之臨限電壓。結果，記憶體單元MC0及MC31 具有慢於其它記憶體單元MCI〜MC30之程式化速度的程式 ’化速度。 圖2為一展示在圖1之NAND型快閃記憶體裝置中一具有 由熱電子引起之程式干擾之字線的圖表，其說明了記憶體 單元MC0、MC31與程式抑制電壓Vpass之間的關係。 如圖2所示，分別耦接至第一及最後字線WL0及WL3 1之 記憶體單元MC0及MC3 1具有不同於分別耦接至剩餘字線 WL卜WL30之其它記憶體單元MCI〜MC30之臨限電壓的臨 限電壓。此由如前所述之熱電子引起的程式干擾而產生。 I07205.doc 1309829 圖3為一展示記憶體單元MC〇〜mC3丨之臨限電壓Vt之分 佈輪廓的圖表，同時以相同電壓對耦接至選定之位元線 BL 1之§己憶體單元MC0〜MC3 1的字線WL0〜WL3 1執行一程 式操作。此處，較低臨限電壓產生較慢之程式化速度。 如圖3所示’可看出’與其它記憶體單元wl1〜wl30之 私式化速度相比，歸因於分別耦接至第一及最後字線wL〇 及WLM之記憶體單元MC0及MC3 1的較低臨限電壓，程式 化速度變得更慢。 如圖2所示之程式干擾及如圖3所示之程式化速度之降級 的影響隨記憶體單元之大小變得更小而變得更加嚴重。 且，一多級單元與一單級單元相比更易受上述故障之損 ° 果’此程式干擾及程式化速度之降級可降低NAND 型快閃記憶體裝置之效能。 【發明内容】 本發明係針對一快閃記憶體裝置，其經組態以防止在一 取消選定之單元串中在鄰近汲極及源極選擇電晶體之記憶 體單元處之程式干擾的效應。 、本發明亦係針對—快閃記憶體裝置，其經組態以防止程 弋化速度在選疋之單元串中在鄰近汲極及源極選擇電晶 體之記憶體單元處降級。 本發明之一態樣為提供一快閃記憶體裝置，其包含：第 一選擇電晶體，其各自耦接至複數個位元線；第二選擇電 曰曰體其耦接至一共用源極線；及複數個記憶體單元，其 各自耗接於第-與第二選擇電晶體之間且各自麵接至複數 I07205.doc 1309829 個字線。該等複數個記憶體單元包括在連接至一第一字線 之記憶體單元與第二選擇電晶體之間耦接的虛設記憶體單 元，該等虛設記憶體單元不具有一程式化操作。 在此實施例中，耦接至第一字線及複數個位元線之一取 消選定之位元線的記憶體單元免於由虛設記憶體單元引起 之程式干擾的效應。 在此實施例中，該等虛設記憶體單元用虛設電晶體來替 代。 在此實施例中，一耦接至該等虛設電晶體之虛設字線在 程式化及讀取操作中供應有一電源電壓，且在一擦除操作 中供應有一接地電壓。 在此實施例中’一耦接至該等虛設記憶體單元之虛設字 線供應有一高於兩倍電源電壓並低於施加至該等複數個字 線之程式抑制電壓的電壓。 在此實施例中，一耦接至該等虛設記憶體單元之虛設字 線在一程式操作中供應有一施加至該等複數個字線之程式 抑制電壓。 在此實施例中，一耦接至該等虛設記憶體單元之虛設字 線在一擦除操作中供應有一接地電壓且在一讀取操作中供 應有一施加至該等複數個字線之讀取電壓。 在此實施例中，該等虛設記憶體單元以與待程式化之記 憶體單元之相同大小而形成。 在此貫施例中，除該等複數個記憶體單元中第一及第二 組之虛設記憶體單元外的記憶體單元為多級單元。 I07205.doc 1309829 在本發明之另一態樣中，一快閃記憶體裝置包含：第一 選擇電晶體’其各自耦接至複數個位元線；第二選擇電晶 體’其耗接至一共用源極線；及複數個記憶體單元，其各 自在第一與第二選擇電晶體之間耦接且各自耦接至複數個 字線。該等複數個記憶體單元包括在連接至一最後字線之 S己憶體單元與第一選擇電晶體之間輕接的虛設記憶體單 元’ δ亥寻虛设g己憶體早元不具有一程式操作。 在此實施例中，耦接至最後字線及該等複數個位元線之 > 一選定之位元線的記憶體單元之臨限電壓等於在虛設記憶 體單元附近之其它記憶體單元的臨限電壓。 本發明之另一態樣中，一快閃記憶體裝置包含：第一選 擇電曰a體，其各自搞接至複數個位元線；第二選擇電晶 體，其耦接至一共用源極線；及複數個記憶體單元，其各 自在第一與第二選擇電晶體之間耦接且各自耦接至複數個 字線。該等複數個記憶體單元包括在連接至一第一字線之 記憶體單元與第二選擇電晶體之間耦接的第一組之虛設記 憶體單元，該第一組之虛設記憶體單元不具有一程式操 作，且該等複數個記憶體單元包括在連接至一最後字線之 記憶體單元與第一選擇電晶體之間耦接的第二組之虛設記 憶體單元，該第二組之虛設記憶體單元不具有一程式操 作。 在此實她例中，耦接至第一及第二字線及複數個位元線 之一取消選定之位元線的記憶體單元免於由第一及第二組 之虛設記憶體單元引起的程式干擾之效應。 I07205.doc 1309829 在此實施例中，第一組之虛設記憶體單元用第一組之虛 設電晶體來替代且第二組之虛設記憶體單元用第二組之虛 設電晶體來替代。 在此實施例中，一耦接至第一組之虛設電晶體的第一虛 設字線及一耦接至第二組之虛設電晶體的第二虛設字線在 程式化及讀取操作中供應有一電源電壓且在一擦除操作中 供應有一接地電壓。 在此實施例中，一耦接至第一組之虛設電晶體的第一虛 設字線及一耦接至第二組之虛設電晶體的第二虛設字線在 一程式操作期間供應有一高於兩倍電源電壓並低於一施加 至該等複數個字線之程式抑制電壓的電壓。 在此實施例中，一耦接至第一組之虛設電晶體的第一虛 設字線及一耦接至第二組之虛設電晶體的第二虛設字線在 一程式操作中供應有一施加至該等複數個字線之程式抑制 電壓。 在此實施例中，一耦接至第一組之虛設電晶體的第—虛 設字線及一耦接至第二組之虛設電晶體的第二虛設字線在 一擦除操作中供應有一接地電壓且在一讀取操作中供應有 一施加至該等複數個字線之讀取電壓。 在此實施例中’第—及第二組之虛設記憶體單元以與待 程式化之記憶體單元之相同大小而形成。 、 【實施方式】 將參看隨附圖式在下文中更詳細地描述本發明之實施 例。然而，本發明可以不同形式體現且不應被建構為限制 I07205.doc •12· 1309829 於本文所闡明之實施例。相反，提供此等實施例使得此揭 不内容將為詳盡且完全的，且將完全向熟習此項技術者傳 達本發明之範疇。相似數字在整篇本說明書係指相似元 件。 下文中，將結合該等隨附圖式描述有關本發明之一例示 性實施例。 圖4A說明了根據本發明之一實施例之nanD型快閃記憶 體裝置的記憶體區塊，其提供了一結構以防止連接至第一 字線之記憶體單元處之程式干擾的效應。 參看圖4A，該NAND型快閃記憶體裝.置包括數目為n(n 為正整數）的複數個單元串10-1〜l〇-n，其中每一單元串 包括32個記憶體單元。由一字線（例如，WL〇)控制之記憶 體單元（例如，MC0)形成一單位頁，意即，一組記憶體單 元。忒專單元串1 〇_〇〜1 〇_n之每一者均包括一麵接至一共用 源極線CSL之源極選擇電晶體SSt、一耦接至位元線 BL0〜BLn之每一者的汲極選擇電晶體dST、一虛設記憶體 單元DMC及在源極選擇電晶體SST與汲極選擇電晶體DST 之間搞接的έ己憶體單元MC0〜MC3 1。此處，該虛設記憶體 單元DMC在源極選擇電晶體與記憶體單元mc〇之間耗接。 及極選擇電晶體DST之閘極柄接至一沒極選擇線dsl，且 源極選擇電晶體sst之閘極耦接至源極選擇線SSL。該等 §己憶體單元MC0〜MC3 1之控制閘極耗接至第一條至第三十 一條字線WL0〜WL3 1，且虛設記憶體單元DMC之閘極耦接 至虛設字線D WL。提供該等虛設記憶體單元DMC以防止在 I07205.doc -13 - 1309829 一取消選定之單元串（例如，1(M)中耦接至第一字線wl〇 之記憶體單元MC0處的程式干擾。 儘管在虛設記憶體單元DMC及記憶體單元 MC0〜MC31(其在源極選擇電晶體SST與汲極選擇電晶體 DST之間串聯耗接）之一條位元線中之總數目如圖4a所示 為3 3 ’但疋應瞭解’記憶體單元之數目可變化。 圖4B展示了在一程式操作中被施加至取消選定之單元串 1 0-1之每一線的電壓。 如圖術斤說明，該取消選定之單元争1(M經由取消選定 之位7G線BL0而供應有一電源電壓vcc以便防止其之記憶 體單元MC0〜MC31在程式操作期間被程式化。在該程式操 作中，將一程式電壓施加至一耦接至待程式化之記憶體單 元的字線（例如’ WL2)，@時將—程式抑制電壓施加 至剩餘字線（例如，WL0、WL1、及WL3〜WL31)。虛設字 線DWL供應有該程式抑制電壓Vpass。在替代性實施例 中，虛及字線DWL供應有另一高於兩倍之VCc電壓但低於 Vpass的程式抑制電壓Vpass2。源極選擇線供應有一接 地電壓〇 V，汲極選擇線DSL供應有電源電壓vcc，且共用 源極線CSL供應有電源電壓VCC1。 圖4C展示了施加至圖4A中之線的程式化電壓、讀取電 壓及擦除電壓之條件。 參看圖4C ,在程式操作期間，虛設字線dwl供應有程 式抑制電壓Vpass或程式抑制電壓Vpass2。在讀取操作 中，虛設子線供應有-施加至取消冑$ <字線的讀取電壓 107205.doc 13098291309829 IX. Description of the Invention: [Technical Field] The present invention relates to a flash memory device and, more particularly, to a NAND type flash memory device, which is conditioned to prevent proximity The memory cells of the drain and source select transistors (4) dry (4) improve the stylized speed of the memory cells. [Prior Art] A flash memory is referred to as a device that is operable without an update function, and is known to be a type of non-volatile memory device capable of retaining data even when the power source is interrupted therein. In flash memory, "programming," refers to an operation for writing data in a memory unit. "Erase" refers to an operation used to eliminate data from a memory unit. These memory cells are roughly classified into n〇r type and NAND type according to cell structure and operating conditions. The flash memory (where the source of the memory cell transistor is coupled to a ground voltage) can be used to program the erased data of the memory cell using a random address, and can be used in applications that are required for operating speed. . The NAND type flash memory configuration has a plurality of memory cell transistor configurations coupled in series to form a cell string connected between a drain select transistor and a source select transistor. Density data storage. Figure 1 shows a conventional NAND type flash memory device. Referring to Figure 1, a certain number of memory cells MC0 to MC3 1 are coupled in series between a drain-select transistor DST and a source select transistor ssir. Typical design involves 丨6, 32, or 64 stunner units, taking into account device topology and density. ~ I07205.doc 1309829 In Figure 1, there are a plurality of cell strings, each of which contains 32 memory cells. A memory cell (e.g., 'MC0) controlled by a single word line (e.g., WL0) forms a page (which is a group of memory cells). Fig. 1 exemplarily shows 32 pages. However, the NAND type flash memory device as shown in FIG. 1 is susceptible to the memory cell unit MC0 (which is coupled to the first word line WL0 adjacent to the source select line SSL and a deselected bit line (eg, Program disturb caused by BL0) and damage from the program interference of the memory cell MC3 1 which is connected to the last word line adjacent to the drain select line DSL and the deselected bit line BL0. Since a ground voltage is 0 V, When a power supply voltage Vcc and a program suppression voltage vpass are respectively applied to the source select line SSL, the drain select line DSL, and the remaining word lines WL1 WL WL31, the source select transistor SST, the drain select transistor DST, and the seek memory The body cells MC0 to MC3 1 are boosted to 〇v, 1 V and about 8 V, respectively, so these program disturbances occur. More specifically, due to the source-selective transistor SST and the memory cell MC0. The difference between the channel voltage (meaning between 〇¥ and 8 v), a transverse electric field is strongly formed between the source-selective transistor SST and the memory cell MC〇. Due to the drain-selective transistor DST and memory cell PCT (: 31 channel voltage (meaning i 乂 and 8 V a difference #, a transverse electric field is also formed between the drain-selective transistor DST and the memory cell estuary. If these voltage differences result in a strong lateral electric field, then one of the source-selective transistors sst is gate-oxidized. The electrons generated at the boundary between the film and the substrate Si_Sub move along the surface of the substrate Si_Sub to the memory cell mc〇, thereby generating hot electrons. The generated hot electrons move in the lateral direction 107205 .doc 1309829 flows into the floating gates of memory cells MC0 and MC3 1 to program memory cells MC0 and MC31. At the same time, it is coupled to a selected bit line BL1 and first and last word lines WL0 and WL31. The memory speed of the memory cells MC0 and MC31 is slower than the stylized speed of the other memory cells MCI~MC30. The reason for the slower programming speed is because of the coupling to the first and last word lines WL0 and WL3 1 and The threshold voltage Vt of the memory cells MC0 and MC31 of the selected bit line BL1 is lower than the threshold voltage of the memory cell coupled to the remaining word lines WL1 WL WL30 > MC Bu MC30 so that the source select line SSL and First word line There is a voltage difference between WL0 and between the drain select line DSL and the last word line WL3 1. In other words, the memory cells MC0 and MC31 are affected by the potentials of the source select transistor SST and the drain select transistor DST, The threshold voltages of the memory cells MC0 and MC3 1 become lower than the threshold voltages of the other memory cells MCI to MC30. As a result, the memory cells MC0 and MC31 have a slower stylized speed than the other memory cells MCI to MC30. The program's speed. 2 is a diagram showing a word line having a program disturb caused by hot electrons in the NAND type flash memory device of FIG. 1, illustrating the relationship between the memory cells MC0, MC31 and the program suppression voltage Vpass. . As shown in FIG. 2, the memory cells MC0 and MC3 1 respectively coupled to the first and last word lines WL0 and WL3 1 have different memory cells MCI to MC30 than the respective remaining word lines WL WL30. The threshold voltage of the threshold voltage. This is caused by program disturb caused by the hot electrons as described above. I07205.doc 1309829 FIG. 3 is a graph showing the distribution profile of the threshold voltage Vt of the memory cells MC〇~mC3丨, while the same voltage pair is coupled to the selected bit line BL1. The word lines WL0 to WL3 1 of the MC3 1 perform a program operation. Here, the lower threshold voltage produces a slower stylized speed. As shown in FIG. 3, 'can be seen' is compared with the memory speeds of the other memory cells wl1 to wl30, due to the memory cells MC0 and MC3 respectively coupled to the first and last word lines wL and WLM. The lower threshold voltage of 1 makes the stylized speed slower. The effect of the program disturb shown in Figure 2 and the degradation of the stylized speed shown in Figure 3 becomes more severe as the size of the memory unit becomes smaller. Moreover, a multi-level cell is more susceptible to the above-mentioned failures than a single-level cell. The degradation of the program and the degradation of the programming speed can reduce the performance of the NAND-type flash memory device. SUMMARY OF THE INVENTION The present invention is directed to a flash memory device configured to prevent the effects of program disturb at memory cells adjacent to the drain and source select transistors in a deselected string of cells. The present invention is also directed to a flash memory device that is configured to prevent degradation in the selected cell string at the memory cells adjacent to the drain and source select transistors. An aspect of the present invention provides a flash memory device including: a first selection transistor coupled to a plurality of bit lines; and a second selected electrode coupled to a common source And a plurality of memory cells, each of which is connected between the first and second selection transistors and each of which is connected to a plurality of I07205.doc 1309829 word lines. The plurality of memory cells include dummy memory cells coupled between the memory cells connected to a first word line and the second selection transistor, the dummy memory cells not having a stylized operation. In this embodiment, the memory cell coupled to one of the first word line and the plurality of bit lines cancels the selected bit line from the effect of program disturb caused by the dummy memory unit. In this embodiment, the dummy memory cells are replaced with dummy transistors. In this embodiment, a dummy word line coupled to the dummy transistors is supplied with a power supply voltage during program and read operations, and a ground voltage is supplied during an erase operation. In this embodiment, a dummy word line coupled to the dummy memory cells is supplied with a voltage higher than twice the power supply voltage and lower than the program rejection voltage applied to the plurality of word lines. In this embodiment, a dummy word line coupled to the dummy memory cells is supplied with a program inhibit voltage applied to the plurality of word lines in a program operation. In this embodiment, a dummy word line coupled to the dummy memory cells is supplied with a ground voltage in an erase operation and a read applied to the plurality of word lines in a read operation. Voltage. In this embodiment, the dummy memory cells are formed in the same size as the memory cells to be programmed. In this embodiment, the memory cells other than the dummy memory cells of the first and second groups of the plurality of memory cells are multi-level cells. In another aspect of the invention, a flash memory device includes: a first selection transistor 'each coupled to a plurality of bit lines; and a second selection transistor 'which is consuming one a common source line; and a plurality of memory cells each coupled between the first and second selection transistors and each coupled to a plurality of word lines. The plurality of memory cells include a dummy memory cell that is lightly connected between the S-resonance cell connected to a last word line and the first selection transistor. A program operation. In this embodiment, the threshold voltage of the memory cell coupled to the last word line and the plurality of bit lines is equal to the other memory cells in the vicinity of the dummy memory cell. Threshold voltage. In another aspect of the present invention, a flash memory device includes: a first selection cell, each of which is connected to a plurality of bit lines; and a second selection transistor coupled to a common source And a plurality of memory cells each coupled between the first and second selection transistors and each coupled to a plurality of word lines. The plurality of memory cells include a first set of dummy memory cells coupled between the memory cells connected to a first word line and the second selection transistor, the first group of dummy memory cells not Having a program operation, and the plurality of memory cells include a second set of dummy memory cells coupled between the memory cells connected to a last word line and the first selection transistor, the second group The dummy memory unit does not have a program operation. In this example, the memory unit coupled to one of the first and second word lines and the plurality of bit lines to cancel the selected bit line is prevented from being caused by the dummy memory cells of the first and second groups. The effect of program interference. I07205.doc 1309829 In this embodiment, the first set of dummy memory cells are replaced with a first set of dummy transistors and the second set of dummy memory cells are replaced with a second set of dummy transistors. In this embodiment, a first dummy word line coupled to the dummy transistors of the first group and a second dummy word line coupled to the dummy transistors of the second group are supplied in a program and read operation. There is a supply voltage and a ground voltage is supplied during an erase operation. In this embodiment, a first dummy word line coupled to the dummy transistors of the first group and a second dummy word line coupled to the dummy transistors of the second group are supplied with a higher value during a program operation. Two times the supply voltage is lower than a voltage applied to the program suppression voltage of the plurality of word lines. In this embodiment, a first dummy word line coupled to the dummy transistors of the first group and a second dummy word line coupled to the dummy transistors of the second group are supplied in a program operation to be applied to The program of the plurality of word lines suppresses the voltage. In this embodiment, a first dummy word line coupled to the dummy transistors of the first group and a second dummy word line coupled to the dummy transistors of the second group are supplied with a ground in an erasing operation. The voltage is supplied with a read voltage applied to the plurality of word lines in a read operation. In this embodiment, the dummy cells of the first and second groups are formed in the same size as the memory cells to be programmed. [Embodiment] Embodiments of the present invention will be described in more detail hereinafter with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limiting the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully disclosed by those skilled in the art. Like numbers refer to like elements throughout the specification. Hereinafter, an exemplary embodiment of the present invention will be described in conjunction with the accompanying drawings. 4A illustrates a memory block of a nanD type flash memory device in accordance with an embodiment of the present invention that provides a structure to prevent effects of program disturb at the memory cells connected to the first word line. Referring to Fig. 4A, the NAND type flash memory device includes a plurality of cell strings 10-1 to l〇-n of a number n (n is a positive integer), wherein each cell string includes 32 memory cells. A memory unit (e.g., MC0) controlled by a word line (e.g., WL〇) forms a unit page, i.e., a group of memory cells. Each of the plurality of cell strings 1 〇 _ 〇 〜 1 〇 _n includes a source selection transistor SST connected to a common source line CSL, and a coupling to each of the bit lines BL0 BLBLn The bungee selection transistor dST, a dummy memory cell DMC, and the memory cell MC0~MC3 1 connected between the source selection transistor SST and the drain selection transistor DST. Here, the dummy memory cell DMC is consumed between the source selection transistor and the memory cell mc〇. The gate of the transistor DST is connected to a gateless selection line dsl, and the gate of the source select transistor sst is coupled to the source select line SSL. The control gates of the memory cells MC0 to MC3 1 are connected to the first to thirty-first word lines WL0 to WL3 1, and the gates of the dummy memory cells DMC are coupled to the dummy word lines D. WL. Providing the dummy memory cells DMC to prevent program disturb at the memory cell MC0 coupled to the first word line w1〇 in the unselected cell string (for example, 1(M) in I07205.doc -13 - 1309829 Although the total number of bit lines in the dummy memory cell DMC and the memory cells MC0 to MC31 (which are connected in series between the source selection transistor SST and the drain selection transistor DST) is as shown in FIG. 4a. Shown as 3 3 'but 疋 should understand that the number of memory cells can vary. Figure 4B shows the voltage applied to each line of the unselected cell string 1 0-1 in a program operation. The deselected cell 1 (M is supplied with a power supply voltage vcc via the deselected bit 7G line BL0 to prevent its memory cells MC0 to MC31 from being programmed during program operation. In the program operation, one will be The program voltage is applied to a word line (eg, 'WL2) coupled to the memory cell to be programmed, and the @ program inhibit voltage is applied to the remaining word lines (eg, WL0, WL1, and WL3 WL WL31). Word line DWL is supplied with this program to suppress electricity Vpass. In an alternative embodiment, the dummy and word line DWL is supplied with another program suppression voltage Vpass2 that is higher than twice the VCc voltage but lower than Vpass. The source select line is supplied with a ground voltage 〇V, the drain select line The DSL is supplied with a power supply voltage vcc, and the common source line CSL is supplied with a power supply voltage VCC1. Figure 4C shows the conditions of the stylized voltage, the read voltage, and the erase voltage applied to the line in Figure 4A. Referring to Figure 4C, During the program operation, the dummy word line dwl is supplied with the program suppression voltage Vpass or the program suppression voltage Vpass2. In the read operation, the dummy sub-line supply has a read voltage applied to the cancel 胄$ < word line 107205.doc 1309829
Vread°在擦除操作中，虛設字線隱供應有接地電壓ov。 下文中’將參看圖4D描述藉由圖4C所示之取消選定之 單元串20]中的虛言史記憶冑單元DMc來防止在記憶體單元 MC0處之程式干擾的機制。 —參看圖4D ’藉由在源極選擇電晶體sst中之閑極氧化物 溥膜與發基板Si-Sub之間的邊界表面處產生電子_電洞對 (ΕΗΡ) ϋ現-漏電流。自此產生之電洞流至石夕基板& Sub中同時電子沿石夕基板之表面向記憶體單元 MC0移動。在此過程中，該等電子遷移至記憶體單元MC〇 而穿過虛設字線DWL之虛設記憶體單元DMC。該虛設記憶 體單元DMC發揮作用以轉移該等電子，其不可藉由程式操 作而程式化。如圖4D所說明，虛設記憶體單元dmc有助 於延長電子向記憶體單元]^“遷移之範圍。因此，當該等 電子向記憶體單元MC0轉移時，該等電子之能量變得更 弱’彳心而減小了此等電子變成熱電子之可能性。儘管具有 較弱能量之電子散佈在記憶體單元MC0周圍，但其不可流 至記憶體單元MC0之浮動閘極FG中，因為該等電子之能量 不具有足夠能量來縱向移動。結果，在記憶體單元MC〇處 不存在程式干擾。 下一步’將參看圖5A及5C描述在虛設字線上安置一虛 設電晶體而非虛設記憶體單元之狀況。Vread° In the erase operation, the dummy word line is implicitly supplied with the ground voltage ov. The mechanism for preventing program disturb at the memory cell MC0 by the virtual history memory unit DMc in the deselected cell string 20] shown in Fig. 4C will be described hereinafter with reference to Fig. 4D. - Referring to Fig. 4D', an electron-hole pair (ΕΗΡ) current-leakage current is generated at a boundary surface between the idler oxide tantalum film in the source selective transistor sst and the emitter substrate Si-Sub. The holes generated therefrom flow to the Si Xi substrate & Sub and simultaneously the electrons move toward the memory cell MC0 along the surface of the Shishi substrate. During this process, the electrons migrate to the memory cell MC〇 and pass through the dummy memory cell DMC of the dummy word line DWL. The dummy memory unit DMC functions to transfer the electrons, which cannot be programmed by program operations. As illustrated in Fig. 4D, the dummy memory cell dmc helps to extend the range of electron migration to the memory cell. Therefore, when the electrons are transferred to the memory cell MC0, the energy of the electrons becomes weaker. 'Heart reduces the possibility that these electrons become hot electrons. Although electrons with weaker energy are scattered around the memory cell MC0, they cannot flow into the floating gate FG of the memory cell MC0 because The energy of the isoelectronics does not have sufficient energy to move longitudinally. As a result, there is no program disturb at the memory cell MC〇. Next, 'will describe a dummy transistor on the dummy word line instead of the dummy memory as described with reference to FIGS. 5A and 5C. The condition of the unit.
圖5 A為一說明根據本發明之另一實施例之nAND螌快閃 記憶體裝置的圖，該裝置經組態以防止耦接至第一字線 WL0之記憶體單元的程式干擾。圖5 a之特徵不同於圖4 A 107205.doc •15- 1309829 之處在於虛設字線DWL包括一虛設電晶體DTR而非虛設記 憶體單元DMC。在一實施例中，DTR可大於或小kDMC。 圖5B說明了施加至取消選定之單元串2〇_丨中之線的電 壓。圖5B之特徵不同於圖4A之處在於虛設字線dwl在圖 5B中供應有電源電壓vcc，而圖4B之虛設字線dwl則供 應有程式抑制電壓Vpass或Vpass2。當將電源電壓vcc施 加至虛設字線DWL時，虛設電晶體DTR僅作為一傳輸電晶 體而操作。 圖5C展示了在圖5A中之NAND型快閃記憶體裝置的程式 化操作、讀取操作及擦除操作中施加至該等線的電壓。 參看圖5C，虛設字線DWL在讀取及程式操作中供應有 電源電壓VCC。虛設字線DWL在一浮動狀態下得以調節。 下文中，將描述藉由圖5C所示之取消選定之單元串π」 中的虛設記憶體單元DMC來防止記憶體單元河(：〇處之程式 干擾的機制。 士在圖4D所示之狀况中，藉由在源極選擇電晶體中 之閘極氧化物薄膜與矽基板S i _ S u b之間的邊界表面處產生 電子-電洞對（EHP)H漏電流1等電子沿石夕基板 Si-Sub之表面向記憶體單元MC〇移動而穿過虛設電晶體 DTR。該虛設電晶體DTR發揮作用以轉移該等電子。在此 過程期間，安置於源極選擇電晶體SST與記憶體單元mc〇 之間的虛設電晶體DTR有助於延長電子向記憶體單元1^以 遷移之fe圍。因此’當該等電子向記憶體單元mc〇轉移 時，該等電子之能量變得更弱，從而減小了此等電子變成 I07205.doc •16- 1309829 熱電子之可能性。儘管具有較弱能量之電子散佈在記憶體 單元MC0周圍，但是其不可流至記憶體單元MC0之浮動閘 極FG中，因為該等電子不具有足夠能量來縱向移動。結 果，在記憶體單元MC0處不存在程式干擾。 圖6 A說明了根據本發明之另一實施例之NAND型快閃記 憶體裝置，該裝置經組態以防止在耦接至第一及最後字線 之記憶體單元處之程式干擾。 在圖6A中，為了防止在記憶體單元MC0及MC31處之程 > 式干擾的目的，將第一組虛設記憶體單元DMC1插入於源 極選擇電晶體SST與記憶體單元MC0之間，且將第二組虛 設記憶體單元DMC2插入於汲極選擇電晶體DST與記憶體 單元MC3 1之間。此處，儘管在一位元線中記憶體單元 MC0〜MC31及虛設記憶體單元DMC1及DMC2之總數目為 34，但是應瞭解，該總單元數目可變化。 圖6B說明了在程式操作期間施加至圖6A所示的取消選 定之單元串3 0-1之線的電壓。圖6B之特徵不同於圖4B之特 B 徵之處在於第二虚設記憶體單元DMC2被插入於汲極選擇 電晶體DST與記憶體單元MC31之間。 在圖6A所示之NAND型快閃記憶體裝置之程式化操作、 讀取操作及擦除操作期間施加至線的電壓與圖4C所示之電 壓條件相同。 如上陳述，圖6B所示之取消選定之單元串30-1的記憶體 單元MC0及MC31並不涉及於由如圖4D所說明之虛設記憶 體單元DMC1及DMC2之效應所引起的程式干擾中。在記憶 107205.doc -17· 1309829 體單元MC0及MC31處產生程式干擾之機制可不難參看先 前所述之圖4D來理解，所以將省略進一步之描述。 圖7A s兒明了根據本發明之另一實施例之NAND型快閃記 憶體裝置，該裝置經組態以防止耦接至第一及最後字線之 記憶體單元處的程式干擾。 在圖7A中，為防止記憶體單元14(：〇及MC31處之程式干 擾之目的，將虛設電晶體〇1^1插入於源極選擇電晶體SST 與記憶體單元MC0之間，且將虛設電晶體DTR2插入於汲 極選擇電晶體DST與記憶體單元MC3 1之間。 圖7B說明了在程式操作期間施加至圖7a所示之取消選 定之單元串40-1之線的電壓。圖7B之特徵不同於圖5B之特 徵之處在於一虛設記憶體單元DMC2被進一步插入於汲極 選擇電晶體DST與記憶體單元MC3 1之間。 在圖7A所示之NAND型快閃記憶體裝置中於程式化操 作、讀取操作及擦除操作期間施加至線的電壓與圖5C所示 之電壓條件相同。 如上陳述，圖7B所示之取消選定之單元串4〇-1的記憶體 單元MC0及MC31並不涉及於由如經由圖5C所示之實施例 說明充當類似傳輸電晶體的虛設電晶體DTR1及DTR2之效 應所引起的程式干擾中。在記憶體單元MC0及MC31處產 生程式干擾之機制可不難參看圖5C所示之實施例來被理 解，所以將省略進一步之描述。 下文中，將描述一用於改良一耦接至第一或最後字線之 記憶體單元之程式化速度、用於改良耦接至第一及最後記 107205.doc -18- 1309829 憶體單元之記憶體單元之程式化速度的實施例。 圖8 A說明了根據本發明之另一實施例之naND型快閃記 憶體裝置，該裝置經組態以改良一耦接至最後字線之記憶 體单元的程式化速度。 在圖8A中’將虛設記憶體單元dmC插入於汲極選擇電 晶體DST與記憶體單元MC3丨之間。提供虛設記憶體單元 DMC以防止耦接至最後字線WL3 1之記憶體單元mc3 1以慢 於其匕3己憶體单元MC0〜MC30之速度被程式化。 圖8B說明了在程式操作期間施加至圖8a所示之選定之 單元串50-2之線的電壓。 如圖8B所示，在程式操作期間將程式傳輸電壓¥1^^施 加至虛设字線DWL。因此，使記憶體單元MC3丨之耦合比 保持在一恆定水平，其與其它記憶體單元MC〇〜MC3丨之耦 合比相同。換言之，由於虛設記憶體單元DMC安置於該記 憶體單元MC3 1之側面處’因此記憶體單元MC3丨不受汲極 選擇電晶體DST之電位影響。因此，記憶體單元Μ(：3丨經調 節而以與其它記憶體單元MC0〜MC30同樣作用。結果，使 記憶體單S Μ⑶之臨限電壓v t上升而與其它記憶體單元 MC0〜Μ⑶之臨限電壓相同，從而使得在程式化速度方面 記憶體單元MC31與其它記憶體單sMC〇〜MC3〇相同。 圖8C展示了在程式化操作、讀取操作及擦除操作期間施 加至線之電壓的條件。 參看圖8C，虛設字線DWL在程式操作中供應有程式抑 制電壓Vpass，且在讀取操作中供應有讀取電壓心㈣。虛 I07205.doc •19- 1309829 設字線DWL在擦除操作中供應有接地電壓0 V。 如圖8C之表格所示，當虛設字線DWL及其它字線供應 有一程式擦除電壓Ο V時，記憶體單元MC3 1不受汲極選擇 電晶體DST之電位影響。因此，記憶體單元MC3 1經調節而 以與其它記憶體單元MCO〜MC30同樣作用。結果，在程式 化速度方面，記憶體單元MC3 1與其它記憶體單元 MCO〜MC30相同。 圖9Α說明了根據本發明之另一實施例之NAND型快閃記 憶體裝置，該裝置經組態以改良耦接至第一及最後字線之 記憶體單元的程式化速度。 在圖9Α中，將虛設記憶體單元DMC2插入於汲極選擇電 晶體DST與記憶體單元MC3 1之間，且將虛設記憶體單元 DMC1插入於源極選擇電晶體SST與記憶體單元MC31之 間。提供虛設記憶體單元DMC以防止程式化速度降低至低 於其它記憶體單元MCO〜MC30之程式化速度。 圖9Β說明了在程式操作期間施加至圖9 Α所示的選定之 單元串60-2之線的電壓。 如圖9B所示，在程式操作期間將程式傳輸電壓Vpass施 加至虛設字線DWL1及DWL2。因此，使記憶體單元MC3 1 之搞合比保持在一恒定水平，其與其它記憶體單元 MCO〜MC3 1之耦合比相同。換言之，由於虛設記憶體單元 DMC1及DMC2安置於記憶體單元MCO及MC31之側面處， 所以記憶體單元MCO及MC31不受源極選擇電晶體SST及汲 極選擇電晶體DST之電位影響。因此，記憶體單元MCO及 107205.doc -20 - 1309829 MC31經調節而以與其它記憶體單元MCI〜MC30同樣作 用。結果，記憶體單元MC0及MC31之臨限電壓Vt上升而 與其它記憶體單元MCI〜MC31之臨限電壓相同，從而使得 在程式化速度方面，記憶體單元MC0及MC3 1與其它記憶 體單元MC卜MC30相同。 在圖9A所示之NAND型快閃記憶體裝置中在程式化操 作、讀取操作及擦除操作期間該等線之電壓條件與圖8(：所 示之電壓條件相同。Figure 5A is a diagram illustrating a nAND(R) flash memory device configured to prevent program disturb coupled to a memory cell of a first word line WL0, in accordance with another embodiment of the present invention. The feature of Figure 5a differs from that of Figure 4A 107205.doc • 15-1309829 in that the dummy word line DWL includes a dummy transistor DTR instead of the dummy memory cell DMC. In an embodiment, the DTR may be larger or smaller than the kDMC. Fig. 5B illustrates the voltage applied to the line in the deselected cell string 2〇_丨. The feature of Fig. 5B differs from that of Fig. 4A in that the dummy word line dw1 is supplied with the power supply voltage vcc in Fig. 5B, and the dummy word line dw1 of Fig. 4B is supplied with the program suppression voltage Vpass or Vpass2. When the power supply voltage vcc is applied to the dummy word line DWL, the dummy transistor DTR operates only as a transfer transistor. Fig. 5C shows the voltages applied to the lines in the program operation, the read operation, and the erase operation of the NAND type flash memory device of Fig. 5A. Referring to Fig. 5C, the dummy word line DWL is supplied with a power supply voltage VCC during reading and program operation. The dummy word line DWL is adjusted in a floating state. Hereinafter, a mechanism for preventing the memory unit river (the program disturbing at the 〇) by the dummy memory unit DMC in the deselected cell string π" shown in Fig. 5C will be described. The shape shown in Fig. 4D is shown in Fig. 4D. In the case, an electron-hole pair (EHP) H leakage current 1 and the like are generated at the boundary surface between the gate oxide film and the germanium substrate S i _ S ub in the source selective transistor. The surface of the substrate Si-Sub moves toward the memory cell MC〇 and passes through the dummy transistor DTR. The dummy transistor DTR functions to transfer the electrons. During this process, the source selection transistor SST and the memory are disposed. The dummy transistor DTR between the cells mc〇 helps to extend the electrons to the memory cell 1^. Therefore, when the electrons are transferred to the memory cell mc〇, the energy of the electrons becomes more Weak, which reduces the possibility that these electrons become I07205.doc •16-1309829 hot electrons. Although electrons with weaker energy are scattered around the memory cell MC0, they cannot flow to the floating gate of the memory cell MC0. Extremely FG, because of the electricity There is not enough energy to move longitudinally. As a result, there is no program disturb at the memory cell MC0. Figure 6A illustrates a NAND-type flash memory device configured to prevent it in accordance with another embodiment of the present invention. Program disturb at the memory unit coupled to the first and last word lines. In FIG. 6A, the first set of dummy memory is used for the purpose of preventing the > type interference at the memory cells MC0 and MC31. The unit DMC1 is inserted between the source selection transistor SST and the memory unit MC0, and the second group of dummy memory unit DMC2 is inserted between the drain selection transistor DST and the memory unit MC3 1. Here, although The total number of memory cells MC0 to MC31 and dummy memory cells DMC1 and DMC2 in one bit line is 34, but it should be understood that the total number of cells can vary. Figure 6B illustrates the application to Figure 6A during program operation. The voltage of the selected line 3 0-1 line is different. The characteristic of FIG. 6B is different from that of FIG. 4B in that the second dummy memory unit DMC2 is inserted in the drain selection transistor DST and the memory. Between units MC31 The voltage applied to the line during the stylized operation, the read operation, and the erase operation of the NAND type flash memory device shown in Fig. 6A is the same as the voltage condition shown in Fig. 4C. As stated above, the cancellation shown in Fig. 6B The memory cells MC0 and MC31 of the selected cell string 30-1 are not involved in program disturb caused by the effects of the dummy memory cells DMC1 and DMC2 as illustrated in Fig. 4D. In memory 107205.doc -17· 1309829 The mechanism for generating program disturb at the body cells MC0 and MC31 can be easily understood by referring to FIG. 4D previously described, so further description will be omitted. Figure 7A illustrates a NAND type flash memory device in accordance with another embodiment of the present invention that is configured to prevent program disturb at the memory cells coupled to the first and last word lines. In FIG. 7A, in order to prevent the program interference at the memory unit 14 (: 〇 and MC31), the dummy transistor 〇1^1 is inserted between the source selection transistor SST and the memory cell MC0, and is dummy. The transistor DTR2 is inserted between the drain selection transistor DST and the memory cell MC3 1. Fig. 7B illustrates the voltage applied to the line of the deselected cell string 40-1 shown in Fig. 7a during the program operation. The feature is different from that of FIG. 5B in that a dummy memory cell DMC2 is further inserted between the drain selection transistor DST and the memory cell MC3 1. In the NAND type flash memory device shown in FIG. 7A The voltage applied to the line during the stylization operation, the read operation, and the erase operation is the same as the voltage condition shown in Fig. 5C. As described above, the memory cell MC0 of the deselected cell string 4〇-1 shown in Fig. 7B is set. And MC31 are not involved in the program disturb caused by the effects of the dummy transistors DTR1 and DTR2 acting as similar transmission transistors as illustrated by the embodiment shown in Fig. 5C. Program disturb is generated at the memory cells MC0 and MC31. The mechanism is not difficult It will be understood with reference to the embodiment shown in FIG. 5C, so further description will be omitted. Hereinafter, a stylized speed for improving a memory unit coupled to the first or last word line will be described for improvement. An embodiment of the stylized speed of the memory unit coupled to the first and last records 107205.doc -18- 1309829. Figure 8A illustrates a naND type flash memory in accordance with another embodiment of the present invention. The device is configured to improve the stylized speed of a memory cell coupled to the last word line. In Figure 8A, the dummy memory cell dmC is inserted in the drain select transistor DST and the memory cell MC3. The dummy memory cell DMC is provided to prevent the memory cell mc3 1 coupled to the last word line WL3 1 from being programmed at a slower speed than its 己3 memory cell MC0~MC30. Figure 8B illustrates the program The voltage applied to the line of the selected cell string 50-2 shown in Fig. 8a during operation. As shown in Fig. 8B, the program transfer voltage ¥1^^ is applied to the dummy word line DWL during the program operation. Memory unit MC3丨 coupling ratio guarantee At a constant level, it has the same coupling ratio with other memory cells MC〇~MC3丨. In other words, since the dummy memory cell DMC is disposed at the side of the memory cell MC3 1 'the memory cell MC3 is not subject to 汲The pole selects the influence of the potential of the transistor DST. Therefore, the memory cell Μ (:3丨 is adjusted to function in the same manner as the other memory cells MC0 to MC30. As a result, the threshold voltage vt of the memory single S Μ(3) rises and The threshold voltages of the other memory cells MC0 to Μ(3) are the same, so that the memory cell MC31 is identical to the other memory cells sMC〇 to MC3〇 in terms of the stylization speed. Figure 8C shows the conditions applied to the voltage of the line during the stylized operation, the read operation, and the erase operation. Referring to Fig. 8C, the dummy word line DWL is supplied with the program suppression voltage Vpass in the program operation, and the read voltage core (4) is supplied in the read operation. Virtual I07205.doc • 19- 1309829 The word line DWL is supplied with a ground voltage of 0 V during the erase operation. As shown in the table of Fig. 8C, when the dummy word line DWL and other word lines are supplied with a program erase voltage Ο V, the memory cell MC3 1 is not affected by the potential of the drain selection transistor DST. Therefore, the memory cell MC3 1 is adjusted to function in the same manner as the other memory cells MCO to MC30. As a result, the memory cell MC3 1 is identical to the other memory cells MCO to MC30 in terms of the programming speed. Figure 9A illustrates a NAND type flash memory device in accordance with another embodiment of the present invention configured to improve the stylized speed of memory cells coupled to the first and last word lines. In FIG. 9A, the dummy memory cell DMC2 is inserted between the drain select transistor DST and the memory cell MC3 1 , and the dummy memory cell DMC1 is inserted between the source select transistor SST and the memory cell MC31. . A dummy memory unit DMC is provided to prevent the stylized speed from being reduced to a lower programmed speed than the other memory units MCO~MC30. Figure 9 illustrates the voltage applied to the line of the selected cell string 60-2 shown in Figure 9 during program operation. As shown in Fig. 9B, the program transfer voltage Vpass is applied to the dummy word lines DWL1 and DWL2 during the program operation. Therefore, the matching ratio of the memory cells MC3 1 is maintained at a constant level, and the coupling ratio with the other memory cells MCO to MC3 1 is the same. In other words, since the dummy memory cells DMC1 and DMC2 are disposed at the sides of the memory cells MCO and MC31, the memory cells MCO and MC31 are not affected by the potentials of the source selection transistor SST and the cathode selection transistor DST. Therefore, the memory cells MCO and 107205.doc -20 - 1309829 MC31 are adjusted to function in the same manner as the other memory cells MCI to MC30. As a result, the threshold voltage Vt of the memory cells MC0 and MC31 rises to be the same as the threshold voltage of the other memory cells MCI to MC31, so that the memory cells MC0 and MC3 1 and other memory cells MC are in terms of stylized speed. Bu MC30 is the same. The voltage conditions of the lines during the stylized operation, the read operation, and the erase operation in the NAND type flash memory device shown in Fig. 9A are the same as those shown in Fig. 8 (:.
在圖9A中，當在擦除操作期間將程式擦除電壓〇 v施加 至虛設字線DWL1及DWL2時，記憶體單元]^(：〇及]^(：31不 文源極選擇電晶體SST及汲極選擇電晶體DST之電位影 響。因此，記憶體單元MC0及MC3 1經調節而以與其它記 憶體單元MCI〜MC30同樣作用。結果，記憶體單元MC〇及 MC3 1具有與其它記憶體單元MC 相同之擦除速 度。 圖10A說明了一 NAND型快閃記憶體裝置之單元串， 中將-虛設電晶體經由—虛設字線而插人於耦接至源極 擇線之源極選擇電晶體與—㈣至第—字線之記憶體單 之間。圖10B說明了沿圖1〇A之線A_A，所戴取之一區段。 在圖1〇八及_中，參考數字1、2、3、4、5、6、7 及9分別指不.一穿隱氧化私锋时， * 、虱化物溥膜1、一浮動閘極2(多晶 薄骐）、一絕緣薄膜3、一 _ k制閘極4(多晶矽薄膜）、一金 或金屬矽化物薄膜5、_層門 層間絕緣薄膜6、一活性區域] —浮動閘極8及一在淫魚fc 予動閘極與控制閘極之間之一絕緣 彳 07205.doc -21 - 1309829 膜移除區域中的浮動閘極移除區域9 β 首先’進行-隔離過程以形成活性區域。在沈積一將用 於穿隧氧化物薄臈i及浮動閘極2之多晶體矽(下文中，多 晶帽，藉由-光微影及敍刻過程選擇性地移除該多： 石夕涛膜。下—步，在沈積絕緣薄膜3以隔離浮動問極⑽控 制閉極4之間的一_ ’部分地或完全地移除虛設電晶 體跟之絕緣薄膜3以及源極選擇電晶體奶之絕緣薄膜In FIG. 9A, when the program erase voltage 〇v is applied to the dummy word lines DWL1 and DWL2 during the erase operation, the memory cell]^(:〇和]^(:31 does not select the source select transistor SST And the drain selects the potential of the transistor DST. Therefore, the memory cells MC0 and MC3 1 are adjusted to function in the same manner as the other memory cells MCI to MC30. As a result, the memory cells MC〇 and MC3 1 have other memory. The same erase speed of the cell MC. Figure 10A illustrates a cell string of a NAND-type flash memory device, the source-dummy transistor is inserted into the source-selected source via a dummy word line Between the transistor and the memory block of - (4) to the first word line. Figure 10B illustrates a section taken along line A_A of Figure 1A. In Figure 1 and _, reference numeral 1 2, 3, 4, 5, 6, 7, and 9 respectively mean that when a hidden oxide private front is worn, *, a germanide film 1, a floating gate 2 (polycrystalline thin crucible), an insulating film 3 , a _ k gate 4 (polycrystalline germanium film), a gold or metal germanide film 5, _ layer gate interlayer insulating film 6, an active region] - floating The movable gate 8 and one of the insulation between the premature gate and the control gate of the squid fc 07205.doc -21 - 1309829 The floating gate removal area in the membrane removal area 9 β First 'perform-isolation The process is to form an active region. In the deposition, a polycrystalline germanium for tunneling the oxide thin layer i and the floating gate 2 (hereinafter, the polycrystalline cap is selectively moved by the photolithography and the lithography process) In addition to the more: Shi Xitao film. Next step, in the deposition of insulating film 3 to isolate the floating pole (10) between the control of the closed pole 4 - 'partially or completely remove the dummy transistor and the insulating film 3 and Insulation film for source selection transistor milk
3(圖心及_中由參考數字9指示之部分）。雖然本文經說 明使得虛設電晶體DTR之絕緣薄膜得以部分地移除，但是 虛設電晶體DTR之絕緣薄膜亦可完全移除。在移除絕緣薄 膜3後’為控制閘極4而沈積一多晶矽薄膜、一金屬矽化物 薄膜或金屬薄膜5。在完成該等沈積過程後，繼續進行一 微影及餘刻過程以完成整個閉極形成過程。在完成該閉極 形成過耘後，層間絕緣薄膜6得以沈積且共用源極線 之-接點形成於其中。在形成該等閘極後，進行隨後之金 屬互連過程。 圖11A s兒明了一 N AND型快閃記憶體裝置之單元串，其 中將-虛設記憶體單元經由一虛設字線而插入於耦接至源 極认擇線之源極選擇電晶體與一耦接至第一字線之記憶體 單元之間。圖11B說明了沿圖丨丨A之線A_A，所截取的一區 段。 在圖11A及116中，其中絕緣薄膜3被移除之部分包括在 移除將浮動閘極2與控制閘極4隔離之絕緣薄膜3的過程 中之源極選擇電晶體SST(該部分由圖1〇及11中之參考數字 i07205.doc 22- 1309829 9指示）。添加至此之虛設記憶體單元dmC在相同過程及具 有記憶體單元MC0〜MC3 1之結構中形成。 在一實施例中，虛設記憶體單元DMC、DMC0及 DMC1、以及虛設電晶體DTR、DTR1及DTR2具有與記憶 體單元MC0〜MC3 1相同之大小。在替代性實施例中，虛設 記憶體單元DMC、DMC0及DMC1、以及虛設電晶體 DTR、DTR1及DTR2具有在記憶體單sMC〇〜MC31之大小 的3 0 %内變化之大小。3 (the part indicated by reference numeral 9 in the figure and _). Although it has been described herein that the insulating film of the dummy transistor DTR is partially removed, the insulating film of the dummy transistor DTR can be completely removed. After the insulating film 3 is removed, a polysilicon film, a metal halide film or a metal film 5 is deposited for controlling the gate 4. After completion of the deposition process, a lithography and residual process is continued to complete the entire closed-pole formation process. After the completion of the closed-pole formation, the interlayer insulating film 6 is deposited and the contacts of the common source line are formed therein. After the formation of the gates, a subsequent metal interconnection process is performed. 11A shows a cell string of an N AND type flash memory device, wherein the dummy memory cell is inserted into a source select transistor coupled to the source select line via a dummy word line and a coupling Connected to the memory cells of the first word line. Fig. 11B illustrates a section taken along line A_A of Fig. A. In FIGS. 11A and 116, a portion in which the insulating film 3 is removed includes a source selective transistor SST in the process of removing the insulating film 3 which isolates the floating gate 2 from the control gate 4 (this portion is illustrated by Reference numerals in 1〇 and 11 are indicated by i07205.doc 22- 1309829 9). The dummy memory cells dmC added thereto are formed in the same process and in the structure having the memory cells MC0 to MC3 1. In one embodiment, the dummy memory cells DMC, DMC0, and DMC1, and the dummy transistors DTR, DTR1, and DTR2 have the same size as the memory cells MC0 to MC3 1. In an alternative embodiment, the dummy memory cells DMC, DMC0, and DMC1, and the dummy transistors DTR, DTR1, and DTR2 have a magnitude that varies within 30% of the size of the memory cells sMC〇~MC31.
如上所述，本發明利用該等虛設記憶體單元或該等虛設 電晶體以用&在與耦接至其它字線之其它記憶體單元相同 的環忧中设定耦接至第一及最後字線之記憶體單元。該等 虛設記憶體單元及電晶體藉由與記憶體單元則〇〜紙31相 同之處理方法而形成。 此外:本發明使用與臨限電壓輪廓之窄分佈間隙相關聯 的多級單元及一單元串中之增加數目的記憶體單元。 根據本發明，由於麵接至第一及最後字線之記憶體單元 可在與其它記憶體單元之相同特徵中操作，所以本發明可 防止在取消敎之單4中㈣至卜及最後字線之記怜 體早-處的程式干擾。此外，本發明可提高在一選定之單 兀串中耦接至第一及最後字線之記憶體單元As described above, the present invention utilizes the dummy memory cells or the dummy transistors to be coupled to the first and the last in the same ringing condition as the other memory cells coupled to other word lines. The memory unit of the word line. The dummy memory cells and the transistors are formed by the same processing method as the memory cells 〇 to 31. In addition: the present invention uses a multi-level cell associated with a narrow distribution gap of a threshold voltage profile and an increased number of memory cells in a cell string. According to the present invention, since the memory cells surfaced to the first and last word lines can operate in the same features as the other memory cells, the present invention can prevent the (4) to the last word line in the canceled single 4 The memory of the pity is early - the program interferes. In addition, the present invention can improve the memory unit coupled to the first and last word lines in a selected single string
除速度。 U 儘管已結合隨㈣式中所說明的本發明之實施例而描述 :本發明’但是其並不被限制於此。普通的熟 者將顯而易見，可在不背離本發明之範_及精神的前^ i07205.doc -23· 1309829 對其·進行各種替代、修改及改變。 【圖式簡單說明】 圖1為一展示一習知NAND型快閃記憶體裝置之圖； 圖2為一展示一字線之圖表’其中在圖jiNAND型快閃 記憶體裝置中發生程式干擾； 圖3為一展示在該N AND型快閃記憶體裝置中具有較慢程 式化迷度之字線的圖表； 圖4A為一說明根據本發明之一實施例之NAND型快閃記 憶體裝置的圖； 圖4B為一說明圖4A所示之取消選定之單元串的結構的 圖； 圖4C為一展示圖4A中之程式化電壓、讀取電壓及擦除 電壓之條件的表； 圖4D為一說明在囷4A之取消選定之單元串中一移動方 向之圖； 圖5 A為一說明根據本發明之另一實施例之nand型快閃 記憶體裝置的圖； 圖5B為一說明圖5 a所示之取消選定之單元串的結構的 圖； 圖5C為—展示圖5A中之程式化電壓、讀取電壓及擦除 電壓之條件的表格； 圖6 A為—說明根據本發明之再一實施例之NAND型快閃 記憶體裝置的圖； 圖6B為—說明圖6A所示之取消選定之單元串的結構的 107205.doc • 24· 1309829 圖； 圖7A為一說明根據本發明之另—實施例2NAND型快閃 記憶體裝置的圖； 圖7B為一說明圖7A所示之取消選定之單元串的結構的 圖； 圖8 A為一說明根據本發明之再—實施例之nand型快閃 記憶體裝置的圖； 圖8B為一說明圖8A所示之選定之單元串的結構的圖； > 圖8C為-展示圖8八中之程式化電壓、讀取電壓及擦除 電壓之條件的表格；In addition to speed. U has been described in connection with the embodiments of the invention as illustrated in the formula (IV): however, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes can be made thereto without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a conventional NAND flash memory device; FIG. 2 is a diagram showing a word line in which program disturb occurs in a jiNAND type flash memory device; 3 is a diagram showing a word line having a slower stylized faintness in the N AND type flash memory device; FIG. 4A is a view illustrating a NAND type flash memory device according to an embodiment of the present invention; Figure 4B is a diagram illustrating the structure of the deselected cell string shown in Figure 4A; Figure 4C is a table showing the conditions of the stylized voltage, the read voltage, and the erase voltage in Figure 4A; Figure 4D is a table; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5A is a diagram illustrating a nand-type flash memory device according to another embodiment of the present invention; FIG. 5B is a diagram illustrating FIG. Figure 5C is a table showing the conditions of the stylized voltage, the read voltage, and the erase voltage in Figure 5A; Figure 6A is a diagram illustrating the re-according to the present invention. Figure of a NAND type flash memory device of an embodiment; Figure 6B - Figure 107A is a diagram illustrating the structure of the deselected cell string shown in Figure 6A. Figure 24A is a diagram illustrating another embodiment of the NAND type flash memory device in accordance with the present invention; Figure 7B is a diagram illustrating A diagram illustrating the structure of the deselected cell string shown in FIG. 7A; FIG. 8A is a diagram illustrating a nand type flash memory device according to a further embodiment of the present invention; FIG. 8B is a view illustrating FIG. 8A A diagram showing the structure of the selected cell string; > Figure 8C is a table showing the conditions of the stylized voltage, the read voltage, and the erase voltage in Figure 8;
圖9A為一說明根據本發明之另一實施例之NAND型快閃 記憶體裝置之圖； 、A 圖9B為一說明圖9 A所示之選定之單元串的結構的圖； 圖10A為一包括虛設記憶體單元之NAND型快閃記憶體 裝置之一單元串的布局圖； _ 圖108為由圖i〇A之A-A'截取的剖視圖； 圖11 A為一包括虛設記憶體單元之nand型快閃 裝置之一單元串的布局圖；及 °隐體 圖11B為由圖iiA之A-A’截取的剖視圖。 【主要元件符號說明】 30-1 取消選定之單元串 30-2 選定之單元串 BL 位元線 CSL 共用選擇線 107205.doc -25- 1309829 DMC 虛設 記 憶 體 單 元 DSL 汲極 選 擇 線 DST >及極 選 擇 電 晶 體 DWL 虛設 字 線 MC 記憶 體 單 元 SSL 源極 選 擇線 SST 源極 選 擇 電 晶 體 WL 字線 107205.doc -26-FIG. 9A is a view illustrating a NAND type flash memory device according to another embodiment of the present invention; and FIG. 9B is a view for explaining a structure of a selected cell string shown in FIG. 9A; FIG. A layout diagram of a cell string of a NAND type flash memory device including a dummy memory cell; _ FIG. 108 is a cross-sectional view taken along line A-A' of FIG. 1A; FIG. 11A is a virtual memory cell including A layout diagram of a cell string of a nand type flash device; and a hidden body diagram 11B is a cross-sectional view taken by AA' of FIG. iiA. [Main component symbol description] 30-1 Deselected cell string 30-2 Selected cell string BL bit line CSL shared select line 107205.doc -25- 1309829 DMC dummy memory cell DSL drain select line DST > Pole select transistor DWL dummy word line MC memory cell SSL source select line SST source select transistor WL word line 107205.doc -26-