CN107958689B

CN107958689B - Operation method of memory array

Info

Publication number: CN107958689B
Application number: CN201610900915.7A
Authority: CN
Inventors: 陈永翔; 张耀文; 杨怡箴
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2016-10-17
Filing date: 2016-10-17
Publication date: 2020-08-18
Anticipated expiration: 2036-10-17
Also published as: CN107958689A

Abstract

The memory array comprises a first memory cell, a second memory cell and a third memory cell, which share a grid and are sequentially arranged along the extending direction of the grid. The method of operating a memory array includes the following steps. A first bias voltage is applied to a channel of the first memory cell to program the first memory cell. A second bias voltage is applied to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias voltage is provided to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias voltage is different from the third bias voltage.

Description

Operation method of memory array

Technical Field

The present invention relates to a method for operating a memory array, and more particularly, to a method for operating a NAND flash memory.

Background

As the critical dimensions of devices in integrated circuits have been scaled to the limits perceived by the manufacturing process, designers have begun searching for technologies that achieve greater memory densities, thereby achieving lower bit costs (costs per bit). Technologies currently being focused on include NAND memory (NAND memory) and its operation. However, the states of adjacent memory cells can be subject to disturb (disturb) one another affecting the properties. The problem becomes more severe, particularly as the trend is toward shrinking the size and pitch of the memory cells.

Disclosure of Invention

The invention relates to an operation method of a memory array.

According to one aspect of the present invention, a method of operating a memory array is provided. The memory array comprises a first memory cell, a second memory cell and a third memory cell, which share a grid and are sequentially arranged along the extending direction of the grid. The method of operating a memory array includes the following steps. A first bias voltage is applied to a channel of the first memory cell to program the first memory cell. A second bias voltage is applied to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias voltage is provided to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias voltage is different from the third bias voltage.

According to another aspect of the present invention, a method of operating a memory array is provided, which includes the following steps. A first bit line bias is provided to place a first memory cell of a first memory string in a programmed state. A second bit line bias is provided to place a second memory cell of a second memory string in a program inhibit state. Providing a third bit line bias to make a third memory cell of a third memory string in a programmed state or a program-inhibited state. The first bitline bias is different from the third bitline bias. The first memory cell, the second memory cell and the third memory cell are sequentially arranged on a page of the memory array.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings, in which:

drawings

FIG. 1 illustrates a memory array in accordance with an embodiment.

FIG. 2 illustrates a partial structure of a memory array in accordance with one embodiment.

FIG. 3 illustrates a method of operation according to an embodiment.

FIG. 4 illustrates a method of operation according to an embodiment.

FIG. 5 illustrates a method of operation according to an embodiment.

FIG. 6 illustrates a method of operation according to an embodiment.

FIG. 7 illustrates a method of operation according to a comparative example.

Description of reference numerals:

102. 104, 106, 108, 110, 112: bit line

222. 224, 226, 228, 330, 350: grid electrode

352: source electrode

404. 406, 408, 410, 412: memory cell

504. 506, 508, 510, 512: floating gate

P, P': programmed state

I: the programmed state is inhibited.

Detailed Description

Embodiments of the present invention provide a method for operating a memory array, which can improve the performance of the memory array.

It should be noted that the present invention is not intended to show all possible embodiments, and other embodiments not suggested by the present invention may also be applicable. Moreover, the dimensional proportions shown in the drawings are not to scale with actual products. Accordingly, the description and drawings are only for the purpose of illustrating embodiments and are not to be construed as limiting the scope of the invention. Moreover, the descriptions of embodiments, such as specific structures, process steps, and material applications, are merely illustrative and are not intended to limit the scope of the present disclosure. Various details of the steps and structures of the embodiments may be changed and modified as required by the actual manufacturing process without departing from the spirit and scope of the invention. The following description will be given with the same/similar reference numerals as used for the same/similar elements.

In one embodiment, having a higher channel bias on one of two memory cells on opposite sides of a program-inhibited memory cell within the same page (e.g., a gate or word line extension direction) can help raise the channel potential of the program-inhibited memory cell, thereby stabilizing the program-inhibited state. For example, one of two memory cells on opposite sides of a program-inhibited memory cell is made program-inhibited while the other memory cell is made program. Alternatively, two memory cells on opposite sides of a program-inhibited memory cell are programmed by different channel/bit line biases, respectively, with one bias being greater than the other.

The following examples illustrate methods of operation of memory arrays according to the present invention. For clarity of understanding, the nomenclature of elements in the following description depends on the block in which the method of operation is discussed, the bias voltage applied, and/or the state of the memory cell. For example, the bias voltage V1 may also be referred to as a first bias voltage or a first bit line bias voltage, and the memory cell corresponding to the bias voltage V1 may also be referred to as a first memory cell or a first memory cell corresponding to a first memory string. And so on.

FIG. 1 illustrates a memory array in accordance with an embodiment. For example, several NAND strings correspond to different bit lines (or channels) 102, 104, 106, 108, 110, 112, respectively, and memory cells (e.g., 404, 406, 408, 410, 412, etc.) are defined between the

bit lines

102, 104, 106, 108, 110, 112 and the

gates

222, 224, 226, 228. The memory cell string groups of the NAND strings may have string select transistors corresponding to

gates

330, 350 coupled to both sides. One end of the NAND strings with respect to the

bit lines

102, 104, 106, 108, 110, 112 can be coupled to the source 352.

FIG. 2 illustrates portions of

memory cells

404, 406, 408, 410, 412 in the memory array of FIG. 1 that are on the same page, share gate 224, and are arranged along the direction of extension of gate 224.

Memory cells

404, 406, 408, 410, 412 are defined at the intersections of gates 224 and

bitlines

104, 106, 108, 110, 112. The memory array may include a dielectric (e.g., a memory film, not shown) disposed between the gate 224, the

bit lines

104, 106, 108, 110, 112, and the floating

gates

504, 506, 508, 510, 512. The dielectric (or memory film) may comprise a suitable material such as silicon oxide, silicon nitride, etc., such as an ONO, ONONO, etc. memory structure, etc.

Fig. 7 shows the operation method of a comparative example.

Memory cells

404 and 408 are in program state P by biasing the bit line/channel (0V). The memory cell 406 in the program-inhibited state I by the bit line/channel bias (3.3V) is affected by the

memory cells

404 and 408 in the program state P by the low bias 0V on both sides, so that the boosting (boost) level of the channel potential (channel potential) is reduced, as shown, the ground-biased potential line (ground-biased equivalent-potential line) becomes shallower, which compresses the depletion depth (depletion) and increases the electric field, which increases the leakage current and reduces the boosted channel potential, and thus the inhibit condition becomes unstable. Parasitic capacitance between bit lines also reduces the bit energy lift-off rate.

Referring to fig. 3, in a method of operation according to an embodiment, the (first) memory cell 404 is programmed at the programmed state P by a bias voltage (first bias voltage or first bit line bias voltage) V1 provided to the bit line 104 (corresponding to the channel or first bit line of the first memory string). The (second) memory cell 406 is program inhibited by a bias (second bias or second bit line bias) V2 provided to the bit line 106 (corresponding to the channel or second bit line of the second memory string), in program inhibit state I. The (third) memory cell 408 is programmed at the programmed state P' by providing a bias voltage (third bias voltage or third bitline bias voltage) V3 to the bitline 108 (corresponding to the channel or third bitline of the third memory string) that is different from the bias voltage V1. In one embodiment, for example, the bias voltage V2 is greater than the bias voltages V1 and V3, and the bias voltage V3 is greater than the bias voltage V1. The bias voltage V1 may be a positive voltage or 0V. In one embodiment, for example, the bias voltage V1 is 0V, the bias voltage V2 is Vcc, such as 3.3V, and the bias voltage V3 is 1V. The bias V3, which is higher than the bias V1, of the memory cell 408 in the programmed state P' causes the bit line depth of the ground bias of the neighboring memory cell 406 to be deeper, thereby raising the channel potential of the memory cell 406 and enabling a more stable program-inhibited state than the comparative example.

Referring to FIG. 4, in a method of operation according to one embodiment, memory cell 404 is in a programmed state P. Memory cell 406 is in program inhibit state I. Memory cell 408 is in program inhibit state I. In one embodiment, for example, the bias V2 for inhibiting programming of the memory cell 406 is equal to the bias V3 for inhibiting programming of the memory cell 408 and is greater than the bias V1 for programming the memory cell 404. The bias voltage V1 may be a positive voltage or 0V. In one embodiment, for example, the bias V1 is 0V, and the bias V2 and the bias V3 are Vcc, such as 3.3V. In the program-inhibited state I, the bias V3, which is higher than the bias V1, causes the bit line depth of the ground bias of the neighboring memory cell 406 to be deeper, thereby raising the channel potential of the memory cell 406, and thus having a more stable program-inhibited state than the comparative example.

Referring to fig. 5, in a method of operation according to an embodiment, the (first) memory cell 406 is programmed at the programmed state P by a bias voltage V1 (first bias voltage or first bit line bias voltage) provided to the bit line 106 (corresponding to the channel or first bit line of the first memory string). The (second) memory cell 408 is program inhibited by a bias voltage V2 (second bias voltage or second bit line bias) provided to the bit line 108 (corresponding to the channel or second bit line of the second memory string), in program inhibit state I. The (third) memory cell 410 is programmed at the programmed state P' by a bias voltage (third bias voltage or third bitline bias voltage) V3 that is different from the bias voltage V1, provided to the bitline 110 (corresponding to the channel or third bitline of the third memory string). In one embodiment, for example, the bias voltage V2 is greater than the bias voltages V1 and V3, and the bias voltage V3 is greater than the bias voltage V1. The bias voltage V1 may be a positive voltage or 0V. In one embodiment, for example, the bias voltage V1 is 0V, the bias voltage V2 is Vcc, such as 3.3V, and the bias voltage V3 is 1V. The bias V3, which is higher than the bias V1, of the memory cell 410 in the programmed state P' causes the bit line depth of the ground bias of the neighboring memory cell 408 to be deeper, thereby raising the channel potential of the memory cell 408, and thus providing a more stable program-inhibited state than the comparative example (the memory cell 406 of FIG. 7).

Referring to fig. 6, in a method of operation according to one embodiment, (first) memory cell 410 is in a programmed state P'. The (second) memory cell 408 is in program inhibit state I. The (third) memory cell 406 is in program inhibit state I. In one embodiment, for example, the bias V2 for inhibiting programming of the memory cell 408 is equal to the bias V3 for inhibiting programming of the memory cell 406 and is greater than the bias V1 for programming the memory cell 410. The bias voltage V1 may be a positive voltage or 0V. In one embodiment, for example, the bias voltage V1 is 1V, and the bias voltages V2 and V3 are Vcc, such as 3.3V. The

memory cells

410 and 406 in the programmed state P' and the program-inhibited state I, respectively, have a more stable program-inhibited state than the comparative example (the memory cell 406 of FIG. 7) because the higher biases V1, V3 than normally cause the programmed state P deepens the line depth of the ground bias of the neighboring memory cell 408, thereby raising the channel potential of the memory cell 408.

The operation method according to the embodiment can cause a higher degree of channel potential rise to the middle memory cell compared to the comparative example, and thus can be in a more stable program-inhibited state.

In one embodiment, the bit lines providing the biases V1, V2, and V3 belong to different bit line groups. For example, the bit lines may be designed in groups of 3n +1, 3n +2, 3n +3 arrangements, or in groups of 4n +1, 4n +2, 4n +3, 4n +4 arrangements, n being a positive integer such as 0, 1, 2. The bit lines in the same group are coupled to a common bit line or voltage source.

The operation method according to the embodiment can be applied to selected pages of a memory array of a two-dimensional NAND memory string or a three-dimensional NAND memory string.

While the invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Various modifications and alterations may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method of operating a memory array, wherein the memory array includes a first memory cell, a second memory cell, and a third memory cell sharing a gate and sequentially arranged along an extending direction of the gate, the method comprising:

providing a first bias voltage to a channel of the first memory cell to program the first memory cell;

providing a second bias to a channel of the second memory cell to inhibit programming of the second memory cell; and

providing a third bias voltage to a channel of the third memory cell to program or inhibit programming of the third memory cell, wherein the first bias voltage is different from the third bias voltage;

the third bias voltage is used for programming the third memory cell, the third bias voltage is larger than the first bias voltage, and the second bias voltage is larger than the third bias voltage.

2. The method of claim 1, wherein the second bias voltage is greater than the first bias voltage and greater than or equal to the third bias voltage.

3. The method of claim 1, wherein the first bias voltage, the second bias voltage and the third bias voltage are 0V or positive bias voltage.

4. The method of claim 1, wherein the first memory cell is in a programmed state and the third memory cell is in a program-inhibited state or a programmed state while the second memory cell is in a program-inhibited state.

5. A method of operating a memory array, comprising:

providing a first bit line bias voltage to enable a first memory cell of a first memory string to be in a programming state;

providing a second bit line bias to enable a second memory cell of a second memory string to be in a program-inhibited state; and

providing a third bitline bias to place a third memory cell of a third memory string in a programmed state or a program-inhibited state, wherein the first bitline bias is different from the third bitline bias, the first memory cell, the second memory cell, and the third memory cell are sequentially arranged on a page of the memory array;

the third bit line bias voltage is used to make the third memory cell in a programmed state, the third bit line bias voltage is greater than the first bit line bias voltage, and the second bit line bias voltage is greater than the third bit line bias voltage.

6. The method of claim 5, wherein the second bit line bias voltage is greater than the first bit line bias voltage and greater than or equal to the third bit line bias voltage.