1309452 98-1-17 六、發明說明： 【發明所屬之技術領域】 本發明是有關一種快問記憶體兀件（FLASH mem〇ry device)的製程，且特別是有關於一種快閃記憶體元件的平 坦化方法。 【先前技術】 目前快閃記憶體元件的平坦化方法有一種是免用化 學機械硏磨（chemical mechanical polishing，簡稱CMP) 製程的平坦化方法，其製程大多是在基底上先形成一層穿 隧氧化層(tunneling oxide layer) ’再於穿隨氧化層上形成 一浮置閘極(floating gate)，並於浮置閘極上形成一層氮化 層（nitride layer)。然後，於基底上形成一層高密度電漿 (high density plasma，簡稱HDP)氧化層（oxide layer)去覆 蓋上述元件。接著，去除部分高密度電漿氧化層，以暴露 出氮化層之頂邊(top edge)。隨後，去除氮化層，並同時去 除位於氮化層上的部分高密度電漿氧化層。 然而，習知技術在形成高密度電漿氧化層時，因爲採 用非等向性沉積製程（anisotropic deposition)之高密度電 漿製程，因此會造成如第1A圖所示之缺陷發生，更甚者會 造成快閃記憶體元件如第1B圖所示發生元件故障的問題。 第1A圖至第1B圖是習知一種快閃記憶體元件之製造 流程剖面圖。 請參照第1A圖與第1B圖，在基底100已形成包括穿 隧氧化層102與浮置閘極104的結構。並根據上述的習知 3 .1309452 98-1-17 技術於基底100上形成一層高密度電漿氧化層106。然而， 因爲採用非等向性沉積製程來形成這層高密度電漿氧化層 106，所以會在接近晶圓（wafer)外圍的快閃記憶體元件產 生缺口（breach)120，在後續製程流程中經過濕式蝕刻後甚 至會形成貫穿整層高密度電漿氧化層106的開口 130。因 而導致如第1B圖所示，在陸續形成閘極間介電層108與 較大面積的控制閘極(control gate)110之後，因其中的控 制閘極110與基底1〇〇相接觸，而發生短路(short)的問題。 此外，習知採用高密度電漿氧化層106作爲介電層用，所 以容易有移動離子（mobile ion)或雜質（impurity)存在，進而 降低元件之可靠度（「eliability)。 另外，上述習知技術還有其他缺點，譬如記憶體元件 在進行初期操作時，往往會因爲採用高密度電漿氧化層106 作爲介電層用，而有快速抹除(fast-erase)的問題發生。目 前爲解決上述的快速抹除缺點，通常是在出貨(delivery)前 先進行數次程式化/抹除(program/erase)的操作，然而這又 導致耗時的缺點。 【發明内容】 因此，本發明的目的在提供一種快閃記憶體元件的平 坦化方法，以避免快閃記憶體元件產生缺口，甚至是形成 貫穿整層高密度電漿氧化層的開口。 本發明的再一目的在提供一種快閃記憶體元件的平 坦化方法，以避免發生短路的問題。 本發明的另一目的在提供一種快閃記憶體元件的平 4 1309452 98-1-17 坦化方法，以防止有移動離子或雜質的存在。 本發明的又一目的在提供一種快閃記憶體元件的平 坦化方法，增進元件之可靠度。 本發明的又一目的在提供一種快閃記憶體元件的平 坦化方法，以避免快速抹除的問題發生。 本發明的又一目的在提供一種快閃記憶體元件的平 坦化方法，以節省出貨前進行程式化/抹除的操作時間。 根據上述與其它目的，本發明提出一種快閃記憶體元 件的平坦化方法，包括於基底上先形成一層穿隧氧化層， 再於穿隧氧化層上形成一浮置閘極，並於浮置閘極上形成 一層頂蓋層（capping layer)，其中穿隧氧化層、浮置閘極以 及頂蓋層組成一堆疊結構(stacked structure)。然後，於堆 疊結構上沉積一氧化層，再於基底上形成一層高密度電漿 憐石夕玻璃（HDP phosphosilicate glass，簡稱 HDP PSG)， 以覆蓋堆疊結構。接著，去除(dip)部分高密度電漿磷矽玻 璃與氧化層，以暴露出頂蓋層之頂邊。隨後，去除頂蓋層， 其中位於頂蓋層上的部分高密度電漿磷矽玻璃與部分氧化 層也將被同時去除。 本發明另外提出一種快閃記憶體元件的平坦化方 法，包括於基底上形成一層穿隧氧化層，再於穿隧氧化層 上形成一浮置閘極，並於浮置閘極上形成一氧化層，其中 穿隧氧化層、浮置閘極以及氧化層組成一堆疊結構。然後， 於基底上形成一高密度電漿氮化層，以覆蓋堆疊結構。接 著，去除部分高密度電漿氮化層，以暴露出氧化層之頂邊。 1309452 98-1-17 最後，去除氧化層，而位於氧化層上的部分高密度電紫氮 化層也會同時被去除。 本發明係藉由形成於基底上覆盖堆置結構的一層氧 化層，來避免快閃記憶體元件產生缺口，甚至是形成貫穿 整層高密度電漿氧化層的開口。而且，藉由這層高密度的 氧化層之保護，也可避免基底因暴露出來，而在形成控制 閘極後發生短路的問題。同時，由於本發明採用高密度電 漿磷矽玻璃作爲介電層用，所以可防止移動籬子或雜質的 存在，進而增進元件之可靠度。 此外，本發明還包括採用高密度電漿氮化層取代習知 以氧化層作爲介電層之用，故可防止快速抹除的問題發 生，也就可以節省出貨前進行程式化/抹除的操作時間。 爲讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 【實施方式】 第一實施例 第2A圖至第2E圖是依照本發明之一第一實施例之快 閃記憶體元件(FLASH memory device)的平坦化製造流程 圖。 請參照第2A圖，於基底200上先形成一層穿險氧化 層202 ’再於穿隧氧化層202上形成一層材質爲複晶砂的 浮置閘極204，並於浮置閘極204上形成一層譬如是氮化 層的頂蓋層(capping layer)206，其中穿隧氧化層2〇2、浮 6 1309452 98-1-17 置閘極204以及頂蓋層206組成一堆疊結構（stacked structure)208。 然後，請參照第2B圖，於基底200上沉積一層氧化 層210，並覆蓋上述堆疊結構208，以避免基底200於後 續蝕刻製程後暴露出來，其中氧化層210的厚度約200埃。 之後，還可以施行一回火處理（annealing treatment)，以密 實化氧化層210，藉以增進氧化層210的抗蝕刻能力 (etch-resistant capability) ° 接著，請參照第2C圖，於基底200上形成一層高密 度電獎（high density plasma，簡稱HDP)磷砂玻璃 (phosphosilicate glass ’ 簡稱 PSG)212，以覆蓋堆疊結構 208,其中高密度電漿磷矽玻璃212的厚度較浮置閘極204 厚以及較堆疊結構208薄，且其厚度約在1500埃至30〇〇 埃之間。由於採用高密度電漿磷矽玻璃212作爲介電層 用，所以本發明可以避免移動離子（mobile ion)或雜質 (impurity)，進而增進可靠度（reliability)。 然後，請參照第2D圖，去除(dip)部分高密度電漿磷 矽玻璃212與氧化層210，直到暴露出頂蓋層206之頂邊 (top edge)，以使高密度電漿磷矽玻璃212以及氧化層21〇 分爲位在頂蓋層206上方的高密度電漿磷矽玻璃212a與 氧化層210a，以及位在浮置閘極204間的高密度電漿磷矽 玻璃212b以及氧化層210b之兩個部分，其中去除的方法 譬如是以氫氟酸（HF)溶液或緩衝氧化矽蝕刻（buffered oxide etch ’簡稱BOE)溶液去除。 7 1309452 98-1-17 之後，請參照第2E圖，去除頂蓋層206，同時位於 頂蓋層206上方的高密度電漿磷矽玻璃212a與氧化層 210a也將被去除，而留下位在浮置閘極204間的高密度電 漿磷矽玻璃212b以及氧化層210b，其中去除的方法譬如 是以熱憐酸(hot H3PO4)溶液去除。 第二實施例 第3A圖至第3D圖是依照本發明之一第二實施例之快 閃記憶體元件的平坦化製造流程圖。 請參照第3A圖，於基底300上形成一層穿隧氧化層 302’其厚度約在70埃至1〇〇埃之間。再於穿隧氧化層302 上形成一材質爲複晶矽的浮置閘極304,其厚度約1000 埃。接著，於浮置閘極304上形成一氧化層306，其厚度 約2000埃。其中穿隧氧化層302、浮置閘極304以及氧化 層306組成一堆疊結構308。 然後，請參照第3B圖，於基底300上形成一高密度 電漿氮化層（HDP nitride layer)312，以覆蓋堆疊結構 308，其中高密度電漿氮化層312的厚度較浮置閘極304 厚以及較堆疊結構308薄，且其厚度約在1500埃至3000 埃之間。由於本發明採用高密度電漿氮化層312取代習知 以氧化層作爲介電層之用，故可防止快速抹除(fast-erase) 的問題發生。 接著’請參照第3C圖，去除部分高密度電漿氮化層 312 ’直到暴露出氧化層306之頂邊，以使高密度電漿氮化 層312分爲位在氧化層306上方的高密度電漿氮化層312a 8 1309452 98-1~17 與位在浮置閘極304間的尚密度電漿氮化層312b兩個部 分，其中去除的方法譬如是以熱磷酸溶液去除。 然後，請參照第3D圖，去除氧化層306，同時位於 氧化層306上方的高密度電漿氮化層312a也將被去除， 而留下位在浮置閘極304間的高密度電獎氮化層312b，其 中去除的方法譬如是以氫氟酸溶液去除。 綜上所述，本發明之特徵包括： 1·本發明係藉由形成於基底上覆蓋堆疊結構的—層氧 化層，來避免快閃記憶體元件產生缺口，甚至是形成售穿 整層高密度電漿氧化層的開口。 2_本發明藉由高密度的氧化層之保護，可避免基底因 暴露出來，而在形成控制閘極後發生短路的問題。 3 _本發明由於用局密度電粟憐砂玻璃作爲介電芦^ 用，所以.可防止移動離子或雜質的存在，進而增進元件之 可靠度。 4_本發明還可選擇採用高密度電漿氮化層取代習知以 氧化層作爲介電層之用，以防止快速抹除的問題發生，也 就可以節省出貨前進行程式化/抹除的操作時間。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1Α圖至第1Β圖是習知一種快閃記憶體元件之製造 9 1309452 98-1-17 流程剖面圖； 第2A圖至第2E圖是依照本發明之一第一實施例之快 閃記憶體元件的平坦化製造流程圖；以及 第3A圖至第3D圖是依照本發明之一第二實施例之快 閃記憶體元件的平坦化製造流程圖。 【主要元件符號說明】 100，200，300 :基底 102，202，302 :穿隧氧化層 104，204，304 :浮置閘極 106 :高密度電漿氧化層 108 :閘極間介電層 110 :控制閘極 120 :缺口 130 :開口 206 :頂蓋層 208，308 :堆疊結構 210，210a，210b，306 :氧化層 212，212a，212b :高密度電漿磷矽玻璃 312，312a，312b :高密度電漿氮化層 101309452 98-1-17 VI. Description of the Invention: [Technical Field] The present invention relates to a process for a FLASH mem〇ry device, and more particularly to a flash memory device The method of flattening. [Prior Art] At present, there is a planarization method for chemical memory polishing (CMP) process, which is a method of planarization of a chemical mechanical polishing (CMP) process. A tunneling oxide layer 'forms a floating gate on the oxide layer and forms a nitride layer on the floating gate. Then, a high density plasma (HDP) oxide layer is formed on the substrate to cover the above elements. Next, a portion of the high density plasma oxide layer is removed to expose the top edge of the nitride layer. Subsequently, the nitride layer is removed and a portion of the high density plasma oxide layer on the nitride layer is removed simultaneously. However, in the formation of high-density plasma oxide layers, conventional techniques use a high-density plasma process of anisotropic deposition, which causes defects such as those shown in FIG. 1A, and even worse. This can cause problems with component failures in the flash memory component as shown in Figure 1B. 1A to 1B are cross-sectional views showing a manufacturing process of a conventional flash memory device. Referring to FIGS. 1A and 1B, a structure including a tunnel oxide layer 102 and a floating gate 104 has been formed on the substrate 100. A high density plasma oxide layer 106 is formed on the substrate 100 in accordance with the above-described conventional 3.1309452 98-1-17 technique. However, since the high-density plasma oxide layer 106 is formed by an anisotropic deposition process, a gap 120 is generated in a flash memory component near the periphery of the wafer, in a subsequent process flow. An opening 130 through the entire high density plasma oxide layer 106 is formed even after wet etching. Thus, as shown in FIG. 1B, after the inter-gate dielectric layer 108 and the larger-area control gate 110 are successively formed, the control gate 110 is in contact with the substrate 1〇〇, A short circuit problem has occurred. Further, since the high-density plasma oxide layer 106 is conventionally used as a dielectric layer, it is easy to have mobile ions or impurities, thereby reducing the reliability of the device ("eliability"). There are other disadvantages to the technique. For example, when the memory device is initially operated, the high-density plasma oxide layer 106 is often used as the dielectric layer, and a fast-erase problem occurs. The short erase defect described above is usually performed several times of program/erase operations before shipping, which in turn leads to time-consuming disadvantages. [Invention] Therefore, the present invention The object of the present invention is to provide a method for planarizing flash memory components to avoid gaps in the flash memory components, or even to form openings through the entire high-density plasma oxide layer. A further object of the present invention is to provide a fast A method of planarizing flash memory components to avoid the problem of short circuits. Another object of the present invention is to provide a flash memory component of flat 4 1309452 98-1-17 The method is to prevent the presence of mobile ions or impurities. A further object of the present invention is to provide a method for planarizing a flash memory device, which improves the reliability of the device. A further object of the present invention is to provide a flash memory. The planarization method of the body element avoids the problem of rapid erasing. It is still another object of the present invention to provide a method of planarizing a flash memory element to save operation time for staging/erasing before shipment. According to the above and other objects, the present invention provides a method for planarizing a flash memory device, comprising: forming a tunnel oxide layer on a substrate, forming a floating gate on the tunnel oxide layer, and floating on the substrate; A capping layer is formed on the gate, wherein the tunneling oxide layer, the floating gate and the cap layer form a stacked structure. Then, an oxide layer is deposited on the stacked structure, and then on the substrate. Form a layer of high-density plasma HDP phosphosilicate glass (HDP PSG) to cover the stacked structure. Then, remove (dip) part of the high density The phosphorous bismuth glass and the oxide layer are smeared to expose the top edge of the cap layer. Subsequently, the cap layer is removed, and a portion of the high density plasma bismuth glass and the partial oxide layer on the cap layer are also simultaneously removed. The invention further provides a planarization method for a flash memory device, comprising forming a tunnel oxide layer on a substrate, forming a floating gate on the tunnel oxide layer, and forming an oxide layer on the floating gate. The tunneling oxide layer, the floating gate and the oxide layer form a stacked structure. Then, a high-density plasma nitride layer is formed on the substrate to cover the stacked structure. Then, part of the high-density plasma nitride layer is removed. To expose the top edge of the oxide layer. 1309452 98-1-17 Finally, the oxide layer is removed and a portion of the high-density electro-purinated nitrogen layer on the oxide layer is also removed. The present invention avoids the formation of gaps in the flash memory device by forming a layer of oxide layer overlying the stacked structure on the substrate, or even forming an opening through the entire layer of high density plasma oxide layer. Moreover, by the protection of this high-density oxide layer, it is also possible to avoid the problem that the substrate is exposed and the short circuit occurs after the gate is formed. At the same time, since the present invention uses high-density plasma bismuth glass as the dielectric layer, the presence of moving fences or impurities can be prevented, thereby improving the reliability of the element. In addition, the present invention also includes the use of a high-density plasma nitride layer instead of the conventional oxide layer as a dielectric layer, thereby preventing the problem of rapid erasing, thereby saving stylization/erasing before shipment. Operating time. The above and other objects, features, and advantages of the present invention will become more apparent and understood. Figures 2E are flow diagrams showing the planarization of a flash memory device in accordance with a first embodiment of the present invention. Referring to FIG. 2A, a layer of through-hole oxide layer 202' is formed on the substrate 200, and a floating gate 204 made of a polycrystalline sand is formed on the tunnel oxide layer 202 and formed on the floating gate 204. A layer such as a capping layer 206 of the nitride layer, wherein the tunneling oxide layer 2 浮 2, the floating 6 1309452 98-1-17 gate electrode 204 and the cap layer 206 form a stacked structure 208. Then, referring to FIG. 2B, an oxide layer 210 is deposited on the substrate 200 and covers the stacked structure 208 to prevent the substrate 200 from being exposed after the subsequent etching process, wherein the oxide layer 210 has a thickness of about 200 angstroms. Thereafter, an annealing treatment may be performed to densify the oxide layer 210 to enhance the etch-resistant capability of the oxide layer 210. Next, please refer to FIG. 2C to form on the substrate 200. a high density plasma (HDP) phosphosilicate glass (PSG) 212 to cover the stacked structure 208, wherein the high density plasma phosphor glass 212 is thicker than the floating gate 204 and It is thinner than the stacked structure 208 and has a thickness of between about 1500 angstroms and 30 angstroms. Since the high-density plasma-phosphorus glass 212 is used as the dielectric layer, the present invention can avoid mobile ions or impurities, thereby improving reliability. Then, referring to FIG. 2D, a portion of the high-density plasma phosphor glass 212 and the oxide layer 210 are removed (dip) until the top edge of the cap layer 206 is exposed to enable the high-density plasma phosphorous glass. The 212 and the oxide layer 21 are divided into a high-density plasma phosphor glass 212a and an oxide layer 210a positioned above the cap layer 206, and a high-density plasma phosphor glass 212b and an oxide layer positioned between the floating gates 204. Two portions of 210b, wherein the removal method is removed, for example, by a hydrofluoric acid (HF) solution or a buffered oxide etch (BOE) solution. 7 1309452 98-1-17 Afterwards, please refer to FIG. 2E to remove the cap layer 206, while the high-density plasma phosphor glass 212a and the oxide layer 210a located above the cap layer 206 will also be removed, leaving The high-density plasma phosphor glass 212b and the oxide layer 210b between the floating gates 204 are removed by, for example, a hot acid (hot H3PO4) solution. SECOND EMBODIMENT Figs. 3A to 3D are flowcharts showing the planarization manufacturing of a flash memory device in accordance with a second embodiment of the present invention. Referring to Figure 3A, a tunneling oxide layer 302' is formed on the substrate 300 to a thickness of between about 70 angstroms and about 1 angstrom. A floating gate 304 of a polycrystalline germanium is formed on the tunnel oxide layer 302 to a thickness of about 1000 angstroms. Next, an oxide layer 306 is formed on the floating gate 304 to a thickness of about 2000 angstroms. The tunnel oxide layer 302, the floating gate 304 and the oxide layer 306 form a stacked structure 308. Then, referring to FIG. 3B, a high-density plasma nitride layer (HDP nitride layer) 312 is formed on the substrate 300 to cover the stacked structure 308, wherein the high-density plasma nitride layer 312 is thicker than the floating gate. The 304 is thicker and thinner than the stacked structure 308 and has a thickness between about 1500 angstroms and 3000 angstroms. Since the present invention uses the high-density plasma nitride layer 312 instead of the conventional oxide layer as the dielectric layer, the problem of fast-erase can be prevented from occurring. Next, please refer to FIG. 3C to remove a portion of the high-density plasma nitride layer 312' until the top edge of the oxide layer 306 is exposed to divide the high-density plasma nitride layer 312 into a high density above the oxide layer 306. The plasma nitride layer 312a 8 1309452 98-1~17 is separated from the still-concentrated plasma nitride layer 312b between the floating gates 304, and the removal method is, for example, removed by a hot phosphoric acid solution. Then, referring to FIG. 3D, the oxide layer 306 is removed, and the high-density plasma nitride layer 312a located above the oxide layer 306 is also removed, leaving a high-density electro-nickel nitridation between the floating gates 304. Layer 312b, wherein the method of removal is removed, for example, with a hydrofluoric acid solution. In summary, the features of the present invention include: 1. The present invention avoids the occurrence of gaps in the flash memory component by forming a layer of oxide layer on the substrate overlying the stacked structure, or even forming a high density through the entire layer. The opening of the plasma oxide layer. 2_ The present invention protects against the occurrence of a short circuit after the formation of the control gate due to the exposure of the high-density oxide layer. 3 _ The present invention uses the local density electro-optical glass as a dielectric reed, so that the presence of mobile ions or impurities can be prevented, thereby improving the reliability of the component. 4_ The invention may also choose to use a high-density plasma nitride layer instead of a conventional oxide layer as a dielectric layer to prevent the problem of rapid erasing, thereby saving stylization/erasing before shipment. Operating time. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 1 are a cross-sectional view showing the manufacture of a flash memory device 9 1309452 98-1-17; FIG. 2A to FIG. 2E are the first in accordance with the present invention. A planarization manufacturing flowchart of a flash memory device of an embodiment; and FIGS. 3A to 3D are flowcharts showing planarization manufacturing of a flash memory device in accordance with a second embodiment of the present invention. [Main component symbol description] 100,200,300: substrate 102, 202, 302: tunneling oxide layer 104, 204, 304: floating gate 106: high-density plasma oxide layer 108: inter-gate dielectric layer 110 : Control gate 120: notch 130: opening 206: cap layer 208, 308: stack structure 210, 210a, 210b, 306: oxide layer 212, 212a, 212b: high density plasma phosphor glass 312, 312a, 312b: High-density plasma nitride layer 10