JP4882055B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semi-conductor device, in particular, it relates to the invention that possible to prevent an increase in contact resistance.

  A conventional bit line contact plug forming process will be described. Bit lines are formed so as to be embedded in the silicon substrate, and an interlayer insulating film is deposited on the silicon substrate. Then, a hard mask or a resist mask is formed on the interlayer insulating film. Thereafter, contact holes are formed on the bit lines by anisotropic dry etching.

Patent Documents 1 and 2 are disclosed as the above-described related art.
JP 2007-173761 A JP 2000-150463 A

  In anisotropic dry etching, a silicon substrate (bit line) functions as an etching stopper. Therefore, the silicon substrate (bit line) at the bottom of the contact hole is damaged by overetching. This is a problem because contact resistance increases due to etching damage.

The present invention is the has been made in view of the background art, and an object thereof is to provide a method of manufacturing a semi-conductor device which can prevent an increase in contact resistance.

In order to achieve the above object, a method of manufacturing a semiconductor device of the present invention includes a step of forming a first amorphous carbon layer on a base layer, a step of forming an insulating film on the first amorphous carbon layer, Forming a second amorphous carbon layer on the film; patterning the second amorphous carbon layer; etching the insulating film until the first amorphous carbon layer is exposed using the second amorphous carbon layer as a hard mask; and exposing And ashing the first amorphous carbon layer and the second amorphous carbon layer , wherein the second amorphous carbon layer is thicker than the first amorphous carbon layer. In the ashing step, the first amorphous carbon layer is ashed. The carbon layer is removed and the second amorphous carbon layer is made thinner Re wherein the Rukoto.

  Thereby, the first amorphous carbon layer acts as an etching stopper layer. Therefore, the underlying layer is prevented from being damaged by overetching.

  In the ashing step, the first amorphous carbon layer that is an etching stopper layer and the second amorphous carbon layer that is a hard mask can be simultaneously ashed. Therefore, it is not necessary to separately remove the etching stopper layer and the hard mask, so that the number of steps can be reduced. Moreover, the amorphous carbon layer which is an etching stopper layer can be removed by ashing. Therefore, it is possible to prevent the underlayer from being damaged when the etching stopper layer is removed.

According to the present invention, it is possible to provide a manufacturing how a semiconductor device capable of preventing an increase in contact resistance.

A semiconductor device manufacturing method according to the first embodiment will be described with reference to FIGS. In the first embodiment, a contact hole forming process in a MirrorBit (registered trademark) flash memory having a single-layer gate electrode will be described as an example.

  FIG. 1 is a partial plan view of a cell array portion of the semiconductor device according to the first embodiment. The silicon substrate 1 includes a plurality of embedded bit lines 10 extending in parallel to each other. A plurality of word lines 9 extending in parallel to each other are provided above the bit line 10 so as to be orthogonal to the bit line 10. A contact plug 33 is formed on the bit line 10. Then, as will be described later, the first amorphous carbon film 24 is formed in a region including the contact plug 33 and extending in parallel with the word line 9.

  The contact hole forming process in the cross-sectional view taken along the line AA in FIG. 1 will be described below with reference to FIGS. As shown in FIG. 2, ion implantation is performed on the silicon substrate 1 to form an impurity diffusion region, whereby a buried bit line 10 is formed. As shown in FIG. 1, a first amorphous carbon film 24 is formed by a CVD method on the silicon substrate 1 in a region extending in parallel with the word line 9 including the contact formation region. Here, the contact formation region is a region of the bit line 10 where the contact plug 33 is formed. The first amorphous carbon film 24 is a film that can be removed by ashing. An ONO layer is formed on the silicon substrate 1 outside the region where the first amorphous carbon film 24 is formed. Here, the ONO layer is a charge trapping dielectric layer, and is generally configured by sequentially depositing three layers, a first insulating layer, a charge trapping layer, and a second insulating layer. The first and second insulating layers are made of an oxide dielectric such as silicon dioxide, and the charge trapping layer is made of a nitride dielectric such as silicon nitride. Note that the method of selectively forming the first amorphous carbon film 24 and the ONO layer on the silicon substrate 1 can be realized by using a general semiconductor manufacturing process, and thus detailed description thereof is omitted here. .

  As shown in FIG. 3, a BPSG (boron phosphorus silicate glass) film 13 which is an interlayer insulating film is formed on the first amorphous carbon film 24 by the CVD method.

  As shown in FIG. 4, a second amorphous carbon film 16 is formed on the BPSG film 13 by a CVD method. The film thickness of the second amorphous carbon film 16 is made larger than the film thickness of the first amorphous carbon film 24. In the present embodiment, a case where the thickness of the second amorphous carbon film 16 is increased to 4000 angstroms will be described. A resist layer 25 is formed on the second amorphous carbon film 16. Then, a resist mask having contact-shaped openings is formed by a well-known photolithography technique. The resist mask opening is transferred to the second amorphous carbon film 16 by a known dry etching technique. Thereby, an opening 31 for forming a contact hole is formed in the second amorphous carbon film 16.

  As shown in FIG. 5, the contact hole 32 is formed by anisotropic etching using the second amorphous carbon film 16 having the opening 31 formed as a hard mask. At this time, the first amorphous carbon film 24 acts as an etching stopper film, and the etching stops at the first amorphous carbon film 24. Therefore, the bit line 10 is prevented from being over-etched.

  The film thickness of the second amorphous carbon film 16 serving as a hard mask is as thick as 4000 angstroms. This prevents the shoulder BPSG film 13 from being exposed even if the shoulder portion of the opening portion 31 of the second amorphous carbon film 16 progresses during anisotropic etching. Therefore, since the opening diameter of the upper part of the contact hole 32 is prevented from expanding, the hole diameter of the contact hole can be controlled with high accuracy.

  As shown in FIG. 6, the first amorphous carbon film 24 at the bottom of the contact hole 32 is removed by O 2 plasma ashing. At the same time, the second amorphous carbon film 16 as a hard mask is thinned by O 2 plasma ashing. The film thickness control of the second amorphous carbon film 16 by O 2 plasma ashing can be performed by, for example, a method of designating the processing time from the removal rate by ashing and the remaining film amount of the second amorphous carbon film 16.

  The reason why the thickness of the second amorphous carbon film 16 is reduced is that the second amorphous carbon film 16 is also used as a CMP stopper layer as will be described later. By reducing the thickness of the CMP stopper layer, the amount of protrusion of the contact plug from the surface of the BPSG film 13 can be suppressed as will be described later, so that flatness can be ensured.

  The thickness of the second amorphous carbon film 16 after thinning is preferably in the range of 100 to 500 angstroms. The upper limit value of 500 angstroms is determined from the viewpoint of preventing scratches. That is, 500 angstroms is considered to be a film thickness equal to or larger than the secondary particle size of abrasive grains causing scratches.

  As shown in FIG. 7, a barrier metal layer 21 and a tungsten layer 22 are sequentially formed on the entire surface of the wafer by a CVD method. Therefore, the barrier metal layer 21 and the tungsten layer 22 are embedded in the contact hole 32.

  As shown in FIG. 8, the tungsten layer 22 and the barrier metal layer 21 are polished by tungsten CMP using the second amorphous carbon film 16 as a CMP stopper film until the second amorphous carbon film 16 is exposed. As a result, the barrier metal layer 21 and the tungsten layer 22 on the second amorphous carbon film 16 are removed, and the barrier metal layer 21 and the tungsten layer 22 are selectively left inside the contact hole 32, whereby the contact plug 33 is formed. Is done.

The function of the second amorphous carbon film 16 as a CMP stopper layer will be described. FIG. 25 shows the polishing rate of the second amorphous carbon film 16, the tungsten layer 22, and the cap SiO ₂ film 15 when the tungsten slurry is used. The tungsten slurry used here is a general tungsten polishing slurry containing a tungsten oxidizing agent (for example, iron nitrate and hydrogen peroxide) and abrasive grains (for example, alumina) for scraping off the oxide. . CMP conditions such as polishing load and polishing rate are also general conditions. Therefore, it goes without saying that the present invention does not require a specific slurry or polishing condition and can be applied to a general tungsten process.

  From FIG. 25, the polishing rate (1 (Angstrom / second)) of the amorphous carbon film is very low with respect to the polishing rate (45 (Angstrom / second)) of the tungsten film. Therefore, by using the second amorphous carbon film 16 as a CMP stopper, the BPSG film 13 is prevented from being exposed even when overpolishing. Thereby, the generation of scratches on the surface of the BPSG film 13 can be prevented, and the deterioration of the film thickness uniformity of the BPSG film 13 can be prevented.

  As shown in FIG. 9, the second amorphous carbon film 16 remaining after tungsten CMP is removed by O 2 plasma ashing. Thereby, the scratch 35 (FIG. 8) generated in the second amorphous carbon film 16 is removed together with the second amorphous carbon film 16. Therefore, the generation of scratches on the surface of the BPSG film 13 is prevented. In addition, since the BPSG film 13 is prevented from being polished by tungsten CMP, the BPSG film 13 can maintain good film thickness uniformity obtained at the time of film formation by the CVD method. From the above, the second amorphous carbon film 16 functions as a sacrificial film for protecting the BPSG film 13. The uppermost surface of the contact plug 33 protrudes from the surface of the BPSG film 13 by a height H.

  The description of the steps after the formation of the contact plug 33 in FIG.

  As is apparent from the above description, according to the first embodiment, the first amorphous carbon film 24 functions as an etching stopper layer during contact formation. Therefore, the bit line 10 is prevented from being damaged by overetching.

  In the first embodiment, the first amorphous carbon film 24 that can be removed by O 2 ashing is used for the etching stopper layer. Therefore, when the first amorphous carbon film 24 is removed, it is possible to prevent damage to the bottom of the contact hole 32 and adverse influence on the contact shape.

  In the ashing process, the first amorphous carbon film 24 as an etching stopper layer and the second amorphous carbon film 16 as a hard mask can be simultaneously ashed. Therefore, it is not necessary to separately remove the etching stopper layer and the hard mask, so that the number of steps can be reduced.

  In the first embodiment, the film thickness of the second amorphous carbon film 16 is larger than the film thickness of the first amorphous carbon film 24. Therefore, the first amorphous carbon film 24 can be removed and the second amorphous carbon film 16 can be thinned and left by the ashing process. That is, the thick second amorphous carbon film 16 used as a hard mask can be thinned and used as a CMP stopper film. Therefore, it is not necessary to form the hard mask and the CMP stopper film separately, so that the process can be omitted.

  In the first embodiment, the second amorphous carbon film 16 having a very low polishing rate as compared with the polishing rate of the tungsten layer 22 is used for the CMP stopper film at the time of tungsten CMP. This can also prevent the occurrence of scratches on the surface of the BPSG film 13 and the deterioration of the film thickness uniformity of the BPSG film 13.

  A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. In the second embodiment, as an example, a contact hole forming process in a MirrorBit (registered trademark) flash memory having a dual gate electrode will be described. FIG. 10 is a partial plan view of the cell array portion of the semiconductor device according to the second embodiment. The silicon substrate 1 includes a plurality of embedded bit lines 10 and a plurality of word lines 9. As will be described later, the first amorphous carbon film 24a is formed only in the contact formation region. As shown in FIG. 10, the contact formation region has a rectangular shape. The length in the X direction of the contact formation region is the same as the width of the bit line 10, and the length in the Y direction is slightly larger than the length in the Y direction of the contact plug 33.

  The contact hole forming process in the cross-sectional view taken along the line BB in FIG. 10 will be described below with reference to FIGS. As shown in FIG. 11, an ONO film 26 and a first polysilicon layer 27 are sequentially formed on the silicon substrate 1. A resist mask (not shown) is formed, and the first polysilicon layer 27 and the ONO film 26 in the contact formation region are removed by anisotropic dry etching. Then, the bit line 10 is formed by ion implantation.

  Then, the first amorphous carbon film 24a is formed by the CVD method in the stopper region 52 (FIG. 10) that extends in parallel with the word line 9 including the contact formation region. As a result, as shown in FIGS. 10 and 12, a first amorphous carbon film 24a is formed on the silicon substrate 1 in the contact formation region. An ONO film 26 is formed on the silicon substrate 1 outside the contact formation region.

  The process of FIG. 13 will be described. An insulating film 28 is formed on the entire surface of the first amorphous carbon film 24a by the CVD method. The insulating film 28 is polished by the oxide film CMP until the first amorphous carbon film 24a is exposed. Therefore, the insulating film 28 is embedded in the recess on the bit line 10. Thereafter, the exposed first amorphous carbon film 24a is removed by ashing. Thereby, the cross-sectional structure of FIG. 13 is obtained. Further, as shown in FIG. 10, the first amorphous carbon film 24a is formed only in the contact formation region.

  Next, a second polysilicon layer (not shown) is deposited. A resist mask is formed on the second polysilicon layer, and the second polysilicon layer is patterned by anisotropic dry etching to form a word line. At this time, the portion of the first polysilicon layer 27 where the word line is not formed is exposed and is removed by etching. Therefore, as shown in FIG. 14, the first polysilicon layer 27 in the contact region 51 is removed.

As shown in FIG. 15, BPSG (boron phosphorus silicate glass) which is an interlayer insulating film
) A film 13 and a second amorphous carbon film 16a are sequentially formed by a CVD method. The film thickness of the second amorphous carbon film 16a is made larger than the film thickness of the first amorphous carbon film 24a. In the present embodiment, a case where the thickness of the second amorphous carbon film 16a is increased to 4000 angstroms will be described. A resist layer 25 is formed on the second amorphous carbon film 16a. Then, a resist mask having contact-shaped openings is formed by a well-known photolithography technique. The opening of the resist mask is transferred to the second amorphous carbon film 16a by a known dry etching technique. Thereby, an opening 31 for forming a contact hole is formed in the second amorphous carbon film 16a.

  As shown in FIG. 16, a contact hole 32 is formed by anisotropic etching using the second amorphous carbon film 16 with the opening 31 formed as a hard mask. At this time, since the first amorphous carbon film 24a functions as an etching stopper film, the bit line 10 is prevented from being over-etched.

  As shown in FIG. 17, the first amorphous carbon film 24a at the bottom of the contact hole 32 is removed by O 2 plasma ashing. At the same time, the second amorphous carbon film 16a, which is a hard mask, is thinned by O 2 plasma ashing.

  As shown in FIG. 18, a barrier metal layer 21 and a tungsten layer 22 are sequentially formed on the entire surface of the wafer by a CVD method. Therefore, the barrier metal layer 21 and the tungsten layer 22 are embedded in the contact hole 32.

  As shown in FIG. 19, the tungsten layer 22 and the barrier metal layer 21 are polished by tungsten CMP using the second amorphous carbon film 16a as a CMP stopper film until the second amorphous carbon film 16a is exposed. Thereby, the contact plug 33 is formed.

  As shown in FIG. 20, the second amorphous carbon film 16a remaining after tungsten CMP is removed by O 2 plasma ashing. Therefore, the second amorphous carbon film 16 a functions as a sacrificial film for protecting the BPSG film 13. The description of the steps after the formation of the contact plug 33 in FIG.

  As is clear from the above description, according to the second embodiment, after the ONO film 26 in the contact formation region on the bit line 10 is removed, the first amorphous carbon film 24a is formed in the contact formation region. Thereby, it is possible to realize a structure in which the first amorphous carbon film 24a is formed on the silicon substrate 1 in the contact formation region and the ONO film 26 is formed on the silicon substrate 1 outside the contact formation region.

  A method of manufacturing a semiconductor device according to the third embodiment will be described with reference to FIGS. In the third embodiment, the film thickness value and film thickness uniformity of the hard mask after thinning can be controlled with higher accuracy.

  FIG. 21 is a cross-sectional view in which a composite amorphous carbon layer 18 is formed instead of the second amorphous carbon film 16 in FIG. 4 of the first embodiment. The composite amorphous carbon layer 18 is formed by sequentially depositing a lower amorphous carbon film 16c, an insulating film 17, and an upper amorphous carbon film 16d on the BPSG film 13 by a CVD method. The lower amorphous carbon film 16c functions as a stopper film in a CMP process, which will be described later, and has a thickness in the range of 100 to 500 angstroms. A silicon oxide film is used for the insulating film 17 and its film thickness is in the range of 100 to 500 angstroms. The upper amorphous carbon film 16d functions as a hard mask in an etching process described later. The film thickness of the composite amorphous carbon layer 18 is increased to 4000 angstroms.

  A resist mask (not shown) having contact-shaped openings is formed on the upper amorphous carbon film 16d by a well-known photolithography technique. Then, the opening of the resist mask is transferred to the composite amorphous carbon layer 18 by a known dry etching technique. As a result, as shown in FIG. 22, an opening 31 for forming a contact hole is formed in the composite amorphous carbon layer 18.

  As shown in FIG. 23, the contact hole 32 is formed by anisotropic etching using the composite amorphous carbon layer 18 in which the opening 31 is formed as a hard mask. At this time, the first amorphous carbon film 24 functions as an etching stopper film. Further, since the film thickness of the composite amorphous carbon layer 18 as a hard mask is increased to 4000 angstroms, the opening of the contact hole 32 is prevented from expanding as described above.

  As shown in FIG. 24, the first amorphous carbon film 24 at the bottom of the contact hole 32 is removed by O 2 ashing. Further, since the insulating film 17 serves as a stopper film for O2 ashing, the upper amorphous carbon film 16d is removed by O2 ashing. Therefore, the composite amorphous carbon layer 18 as a hard mask is thinned to a thickness of two layers of the lower amorphous carbon film 16c and the insulating film 17 by O2 ashing.

  Since the subsequent steps are the same as those in FIG. 7 and thereafter in the first embodiment, detailed description thereof is omitted here.

  As is apparent from the above description, according to the third embodiment, the composite amorphous carbon layer 18 can be thinned simultaneously with the removal of the first amorphous carbon film 24 by the ashing process. Then, by using the insulating film 17 as a stopper film for O 2 ashing, the thickness of the composite amorphous carbon layer 18 after thinning becomes the total value of the thickness of the lower amorphous carbon film 16 c and the thickness of the insulating film 17. . The film thickness value and film thickness uniformity of the lower amorphous carbon film 16c and the film thickness value and film thickness uniformity of the insulating film 17 can be controlled with high accuracy during film formation by the CVD method. Therefore, it becomes possible to control the film thickness value and film thickness uniformity of the composite amorphous carbon layer 18 after thinning with higher accuracy.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. In the first embodiment, the case where the first amorphous carbon film 24 is removed and the second amorphous carbon film 16 is thinned simultaneously with the ashing process has been described. However, the present invention is not limited to this embodiment. The second amorphous carbon film 16 may be removed together with the first amorphous carbon film 24 by an ashing process. Thereby, since the removal of the etching stopper layer and the removal of the hard mask can be performed at the same time, the number of steps can be reduced.

  In addition, the present invention has a point in that the second amorphous carbon layer is used for both the hard mask and the CMP stopper layer by thinning the second amorphous carbon layer. Therefore, the present invention can be applied to any process as long as it includes a pattern formation by etching and a wiring formation by CMP. For example, the present invention can also be applied to a multilayer wiring process by a damascene process. Needless to say, the conductive layer is not limited to tungsten, and various conductive materials such as copper and aluminum can be used. Needless to say, various types of slurry such as Cu-CMP slurry and Al-CMP slurry can be used as the slurry.

  The material used for the hard mask, the etch stopper, and the CMP stopper layer is not limited to the amorphous carbon film. Any material can be used as long as it is a material that can be easily removed without using etching or the like and has a sufficiently low CMP polishing rate as compared with the conductive layer. For example, a material that can be easily removed with a resist stripping solvent can be used.

  The film thicknesses of the second amorphous carbon film 16 and the composite amorphous carbon layer 18 are 4000 angstroms, but are not limited to these film thicknesses. It goes without saying that these film thickness values differ depending on various conditions such as the opening diameter of the contact hole 32, the film type and film thickness of the interlayer insulating film.

  In the first and second embodiments, the process of forming a contact hole in a MirrorBit (registered trademark) flash memory is exemplified, but it goes without saying that the present invention can be applied to other than the MirrorBit (registered trademark) flash memory.

  The silicon substrate 1 is an example of a base layer, the bit line 10 is an example of a diffusion region, and the ONO film 26 is an example of an insulating layer.

The fragmentary top view of the cell array part of the semiconductor device which concerns on 1st Embodiment AA line sectional view concerning the 1st embodiment (the 1) AA line sectional view concerning the 1st embodiment (the 2) AA line sectional view concerning a 1st embodiment (the 3) AA line sectional view concerning the 1st embodiment (the 4) AA line sectional view concerning the 1st embodiment (the 5) AA line sectional view concerning the 1st embodiment (the 6) AA line sectional view concerning the 1st embodiment (the 7) AA line sectional view concerning the 1st embodiment (the 8) The fragmentary top view of the cell array part of the semiconductor device which concerns on 2nd Embodiment BB line sectional view concerning a 2nd embodiment (the 1) BB line sectional view concerning the 2nd embodiment (the 2) BB line sectional view concerning a 2nd embodiment (the 3) BB line sectional view concerning a 2nd embodiment (the 4) BB line sectional view concerning the 2nd embodiment (the 5) BB line sectional view concerning a 2nd embodiment (the 6) BB line sectional view concerning the 2nd embodiment (the 7) BB line sectional view concerning a 2nd embodiment (the 8) BB sectional view concerning the 2nd embodiment (the 9) BB line sectional view concerning the 2nd embodiment (the 10) Sectional drawing based on 3rd Embodiment (the 1) Sectional drawing based on 3rd Embodiment (the 2) Sectional drawing based on 3rd Embodiment (the 3) Sectional drawing based on 3rd Embodiment (the 4) Diagram of tungsten CMP polishing rate for each film type

1 silicon substrate 10 bit line 13 BPSG film 16, 16a second amorphous carbon film 18 composite amorphous carbon layer 22 tungsten layer 24, 24a first amorphous carbon film 26 ONO film 32 contact hole 33 contact plug 35 scratch

Claims (12)

Forming a first amorphous carbon layer on the underlayer;
Forming an insulating film on the first amorphous carbon layer;
Forming a second amorphous carbon layer on the insulating film;
Patterning the second amorphous carbon layer, etching the insulating film using the second amorphous carbon layer as a hard mask until the first amorphous carbon layer is exposed; and
Ashing the exposed first amorphous carbon layer and the second amorphous carbon layer ,
The film thickness of the second amorphous carbon layer is made larger than the film thickness of the first amorphous carbon layer,
Wherein in the ashing method of manufacturing a semiconductor device wherein the second amorphous carbon layer with the first amorphous carbon layer is removed, characterized in Rukoto thinned. Forming a first conductive layer on the thinned second amorphous carbon layer;
Polishing the first conductive layer by CMP until the second amorphous carbon layer is exposed;
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the exposed second amorphous carbon layer. In the step of etching the insulating film, a plurality of contact holes are formed,
Wherein the first amorphous carbon layer manufacturing method of the semiconductor device according to claim 1 or claim 2, characterized in that it is selectively formed in a region where the plurality of contact holes are formed. The underlayer is a silicon substrate;
A plurality of conductive regions are formed in the silicon substrate,
Wherein the first amorphous carbon layer manufacturing method of the semiconductor device according to claim 1 to claim 3, characterized in that it is selectively formed on the plurality of conductive regions. The second amorphous carbon layer is
A lower amorphous carbon film formed on the insulating film;
An interlayer film formed on the lower amorphous carbon film;
An upper amorphous carbon film formed on the interlayer film,
Wherein the step of the second amorphous carbon layer is thinned, the manufacturing method of a semiconductor device according to claim 1 to claim 4, characterized in that is carried out by removing the upper amorphous carbon film. The upper amorphous carbon film is removed by a step of removing the first amorphous carbon layer,
6. The method of manufacturing a semiconductor device according to claim 5 , wherein the lower amorphous carbon film is removed by a step of removing the second amorphous carbon layer. The method of manufacturing a semiconductor device according to claim 5 or claim 6 wherein the lower amorphous carbon film is characterized by being formed thinner than the upper amorphous carbon film. The method of manufacturing a semiconductor device according to claims 5 to 7 wherein the lower amorphous carbon film is characterized by being formed below 500 Angstroms. Thickness value of thinned second amorphous carbon layer, a method of manufacturing a semiconductor device according to claim 1 to claim 8, characterized in that 500 Å. In the step of etching the insulating film, a plurality of contact holes are formed,
The method of manufacturing a semiconductor device according to claims 1 to 9 wherein the conductive layer is characterized in that it comprises tungsten. In the step of etching the insulating film, a plurality of damascene wirings are formed,
The method of manufacturing a semiconductor device according to claim 1 to claim 10 wherein the conductive layer is characterized by containing copper. Polishing rate of the amorphous carbon layer, a method of manufacturing a semiconductor device according to claims 1 to 11, characterized in that it is lower than the polishing rate of the conductive layer.

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