TWI306647B - Method of fabricating flash memory device - Google Patents
Method of fabricating flash memory device Download PDFInfo
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- TWI306647B TWI306647B TW094120676A TW94120676A TWI306647B TW I306647 B TWI306647 B TW I306647B TW 094120676 A TW094120676 A TW 094120676A TW 94120676 A TW94120676 A TW 94120676A TW I306647 B TWI306647 B TW I306647B
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- film
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- 238000004519 manufacturing process Methods 0.000 title description 4
- 238000000034 method Methods 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 150000002500 ions Chemical class 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- KHYBPSFKEHXSLX-UHFFFAOYSA-N iminotitanium Chemical compound [Ti]=N KHYBPSFKEHXSLX-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910001000 nickel titanium Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- 235000011114 ammonium hydroxide Nutrition 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000004313 glare Effects 0.000 claims 1
- 230000000717 retained effect Effects 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 210000004027 cell Anatomy 0.000 description 9
- 125000004122 cyclic group Chemical group 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 210000004692 intercellular junction Anatomy 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000283690 Bos taurus Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- QAVFANVPBSEGTQ-UHFFFAOYSA-N boron;yttrium Chemical compound [Y]#B QAVFANVPBSEGTQ-UHFFFAOYSA-N 0.000 description 1
- WYEMLYFITZORAB-UHFFFAOYSA-N boscalid Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC=C1NC(=O)C1=CC=CN=C1Cl WYEMLYFITZORAB-UHFFFAOYSA-N 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 108090000765 processed proteins & peptides Proteins 0.000 description 1
- 239000010902 straw Substances 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
1306647 九、發明說明： 【發明所屬之技術領域】 本專利係關於一種用以製造快閃記憶體裝置之方法，且 ，體言之，本專利係關於一種其中改良了快閃記憶體裝 置之_環耐久力（Cycling endura叫特徵（意即，刪除/寫入 /w)循環特徵）的製造快閃記憶體裝置之方法。 【先前技術】 ''半導體記憶體裝置之快閃記憶體裝置具有即使在移除電 源時儲存於記憶單元中之資訊亦不吾失的特性。因此，快 :記憶體裝置已廣泛用於電腦所用之記憶卡及其類似物1306647 IX. Description of the Invention: [Technical Field of the Invention] This patent relates to a method for manufacturing a flash memory device, and, in a word, the patent relates to a device in which a flash memory device is improved. A method of fabricating a flash memory device by Cycling endura (characteristic (ie, delete/write/w) loop feature). [Prior Art] The flash memory device of the ''semiconductor memory device' has a characteristic that the information stored in the memory cell is lost even when the power source is removed. Therefore, fast: memory devices have been widely used in memory cards used in computers and the like.
作：：閃記憶體裝置之單位單元，具有一其中以連續 、⑽疊浮動閘極之導電腹及控制閘極之導電膜的結構之 憶早凡係廣泛已知的。多晶㈣廣泛用作浮動閘極之導 膜及控制閘極之導電膜。更特定言之，多晶♦膜及石夕化 (wsix)之雙重結構通常用作控制閘極之導電膜。 /而’隨著快閃記憶體裝置之整合度（integrati()n level) 存在之問題在於·多晶⑪膜結構及^Mb n膜結構中 之電阻變得極高。 /因此，已提議-金屬間極結構，在該金屬閉極結構中， 形成諸如氮化鶴膜（WN)之反應障壁層代㈣化鶴膜（w队) 且在该虱化鎢膜上形成諸如鎢（w)膜之金屬電極膜。 藉由在半導肽基板上連續地堆疊穿遂介電膜、浮動間 極之多日日日㈣ '層間介電膜、控制間極之多晶碎膜、反應 102486.doc 1306647 障壁層及金屬電極膜，並隨後藉由光微影過程圖案化該金 屬電極膜、該反應障壁層、控制閘極之該多晶矽膜、該層 間介電膜、浮動閘極之該多晶矽膜來製造具有此金屬閘極 結構之快閃記憶體裝置。 一旦圖案化該金屬閘極，則產生蝕刻損害。為減輕此等 蝕刻損害，執行選擇性氧化過程，且在包含該金屬閘極之 整個表面上形成密封氮化膜使得該金屬電極膜不被氧化。 密封氮化膜形成之原因如下所述。若在隨後熱過程（意 即，合有氧化物材料之熱處理過程）中，於金屬電極膜中產 生異常氧化，則由於污染了設備腔室而導致一問題。另外， 曝露之金屬電極膜之橫截面由於氧化而減小，從而導致電 阻的增加。因此訊號轉移延遲時間由於單元之字元線的電 阻增加而增加。此導致讀取速度之全面降低並因此使產品 之質降級。因此，為防止此等問題，形成密封氮化膜。 接著，為形成源極/汲極接面，在一半導體基板上執行植 入（接面）過程，意即，將金屬開極用作遮罩之雜質離子植入 過程。隨後執行用於激活所植入之雜質離子的熱處理過程 以形成該源極/汲極接面。 圖1為一展示取決於用於現有快閃記憶體單元之源極/汲 極接面之雜質離子劑量的循環耐久力特徵之圖表。 自圖1之E/W 100 K循環過程結果可見，隨著循環增加， 突然產生單元之臨限電壓改變，意即，嚴重降低了循環期 限（Cycling window)。 — 自快閃記憶體單元之特性的觀點而言，其應具有能夠承 102486.doc 1306647 受100 K循環之耐久力特徵。自圖丨可見，不可在藉由現有 過程而製造之單元中達到耐久力特徵。 同時，可藉由增加單元接面植入劑量之量來改良E/w循 環特徵。然而’此並不非常有效。此外，若用於源極/沒極 接面之雜質劑量增加，則存在之問題在於：漏電流由於閉 極誘發之汲極降低（GIDL)效應而增加’且因此使程式干擾 特性降級。鑒於以上所述，不能隨意增加用於源極/汲極接 φ 面之雜質離子劑量以改良耐久力特徵。 於現有快閃記憶體單元中降低耐久力特徵之原因可包含 兩個主要類型。 第一，密封氮化膜中固有之抗張應力影響矽表面以禁止 源極/汲極接面之雜質離子砷（As)、磷（p)或硼（B)的平行擴 散。因此期望，因為源極/汲極接面與閘極之間的不充分， 故臨限電壓由於單元電流之減少而增加。 此可自圖1以間接方式自E/w循環特徵藉由單元接面植 Φ 入劑量之增加而得以改良的事實看出。 第二，存在密封氮化膜本身固有之材料的問題。通常，所 植入之氮化膜充當捕集源極。因此預期產生許多捕集電荷。 然而，自非植入金屬閘極之觀點考慮密封氮化膜之循環 特徵，在耐久力特徵方面氦化膜與氧化膜之間不存在顯著 差異。因此，在此狀況下不存在顯著效應。因此需要不植 入密封氦化膜。 【發明内容】 因此，本專利處理上述問題，並揭示一種其中可改良耐久 102486.doc 1306647 力特徵而不使程式干擾特徵 Λ ^ ^ a ., 之I垃快閃記憶體的方法。 、種1坆快閃記憶體裝置之 ^ ^ P. 等體基板之一區域上形成 極之多晶侧案、層間介電膜f穿遂介電膜、浮動問 ^ ^ M 匕制閘極之多晶矽膜圖 ^ ^ ,. 兩側處將雜質離子植入該 牛導體基板中；及在包含哕掩蟲μ上 … 閘極之整個表面上形成- 抗異常氧化膜。 可藉由以下步驟形成堆疊閘 ^ •在铸體基板上連續地 =穿遂：電膜、浮動閉極之…膜、層間介電膜、控 二之夕曰曰石夕膜，及金屬膜;及選擇性地蝕刻該金屬膜、 曰^ 赝間；丨電膑，及浮動閘極之該多 日日石夕膜使得其保留於該區域上。 该方法可進一步包含在該金屬膜 成隹屬膜上形成一硬式遮罩膜的 少驟。 較佳藉由堆疊-反應障壁層及一金屬電極膜來形成該金 屬膜。 車交佳使用Wn 壁層。 丁aN、™及M〇n中的-者來形成該反應障The unit cell of the flash memory device has a structure in which a conductive film of a continuous (10) floating gate and a conductive film for controlling the gate are widely known. Polycrystalline (4) is widely used as a conductive film for floating gates and as a conductive film for controlling gates. More specifically, the dual structure of polycrystalline ♦ film and wsix is commonly used as a conductive film for controlling gates. The problem with the integration degree of the flash memory device (integrati()n level) is that the resistance in the polycrystalline 11 film structure and the ^Mb n film structure becomes extremely high. / Therefore, an intermetallic structure has been proposed in which a reaction barrier layer such as a nitride film (WN) is formed and formed on the tungsten carbide film. A metal electrode film such as a tungsten (w) film. By continuously stacking the dielectric film, the floating interpole, and the inter-layer dielectric film, controlling the intergranular polycrystalline film, reacting 102486.doc 1306647 barrier layer and metal on the semi-conducting peptide substrate An electrode film, and then patterned by the photolithography process, the metal electrode film, the reaction barrier layer, the polysilicon film of the gate, the interlayer dielectric film, and the floating gate of the polysilicon film to fabricate the metal gate A flash memory device with a polar structure. Once the metal gate is patterned, etch damage is created. To mitigate such etching damage, a selective oxidation process is performed, and a sealing nitride film is formed on the entire surface including the metal gate so that the metal electrode film is not oxidized. The reason why the sealing nitride film is formed is as follows. If abnormal oxidation occurs in the metal electrode film in the subsequent thermal process (i.e., the heat treatment process in which the oxide material is incorporated), a problem is caused due to contamination of the equipment chamber. In addition, the cross section of the exposed metal electrode film is reduced by oxidation, resulting in an increase in resistance. Therefore, the signal transfer delay time increases due to the increase in the resistance of the word line of the cell. This results in a overall reduction in read speed and thus degrades the quality of the product. Therefore, in order to prevent such problems, a sealing nitride film is formed. Next, in order to form the source/drain junction, a implantation (junction) process is performed on a semiconductor substrate, that is, a metal opening is used as an impurity ion implantation process of the mask. A heat treatment process for activating the implanted impurity ions is then performed to form the source/drain junction. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a graph showing cyclic endurance characteristics depending on the impurity ion dose used for the source/drain junction of an existing flash memory cell. As can be seen from the E/W 100 K cycle process in Figure 1, as the cycle increases, the threshold voltage of the cell suddenly changes, meaning that the cycle is severely reduced (Cycling window). – From the point of view of the characteristics of the flash memory unit, it should have the endurance characteristics capable of undergoing a 100 K cycle with 102486.doc 1306647. It can be seen from the figure that the durability characteristics cannot be achieved in units manufactured by existing processes. At the same time, the E/w cycle characteristics can be improved by increasing the amount of implanted dose on the cell junction. However, this is not very effective. In addition, if the dose of the impurity for the source/depolar junction is increased, there is a problem in that the leakage current increases due to the gate induced buckling reduction (GIDL) effect, and thus the program disturbance characteristic is degraded. In view of the above, the impurity ion dose for the source/drain φ face cannot be arbitrarily increased to improve the durability characteristics. There are two main types of reasons for reducing the durability characteristics of existing flash memory cells. First, the tensile stress inherent in the sealed nitride film affects the tantalum surface to inhibit parallel diffusion of impurity ions arsenic (As), phosphorus (p) or boron (B) at the source/drain junction. Therefore, it is desirable that the threshold voltage increases due to a decrease in cell current because of insufficient contact between the source/drain junction and the gate. This can be seen from Figure 1 in an indirect manner from the fact that the E/w cycle feature is improved by the increase in the dose of the cell junction. Second, there is a problem of sealing the material inherent to the nitride film itself. Typically, the implanted nitride film acts as a capture source. It is therefore expected that many trapped charges will be generated. However, considering the cycle characteristics of the sealed nitride film from the viewpoint of non-implanted metal gate, there is no significant difference between the film and the oxide film in terms of durability characteristics. Therefore, there is no significant effect in this situation. Therefore, it is necessary to not implant the sealing film. SUMMARY OF THE INVENTION Accordingly, this patent addresses the above problems and discloses a method in which the durability of the 102486.doc 1306647 force feature can be improved without causing the program to interfere with the feature Λ ^ ^ a . , a type of flash memory device ^ ^ P. One of the body substrate is formed on the polycrystalline side of the case, the interlayer dielectric film f through the dielectric film, floating ^ ^ M 匕 gate Polycrystalline ruthenium film ^ ^ ,. Impurity ions are implanted into the bovine conductor substrate on both sides; and an anti-abnormal oxide film is formed on the entire surface of the gate including the 哕 哕 μ μ. The stacking gate can be formed by the following steps: • continuously on the cast substrate: through the film: the film, the floating closed film, the interlayer dielectric film, the control layer, and the metal film; And selectively etching the metal film, the 赝 赝 丨 丨 丨 丨 丨 及 及 及 及 及 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The method may further comprise the step of forming a hard mask film on the metal film to form a film. Preferably, the metal film is formed by a stack-reaction barrier layer and a metal electrode film. The car is best to use the Wn wall layer. Ding aN, TM and M〇n to form the reaction barrier
Ni-Ti及 Ta-Pt 中的一 較佳使用 W、Co、Ti、Mo、Ru-Ta、 者來形成該金屬電極膜。 #方法可進一步包含以下步驟：在形成堆疊閘極之後， 稭由：以禁止金屬膜之氧化的選擇性氧化過程來於浮動開 極之多晶矽膜圖案及控制閘極之多晶矽膜圖案的側向部分 102486.doc 1306647 膜15及硬式遮罩膜16。金屬膜可較佳採用反應障壁層之堆 疊膜及金屬電極膜。 可使用（例如）WN、TaN、TiN及MoN中的一者來形成反應 障壁層。可使用 W、Co、Ti、Mo、Ru-Ta、Ni-Ti及 Ta-Pt 中 的一者來形成金屬電極膜。One of Ni-Ti and Ta-Pt is preferably formed by using W, Co, Ti, Mo, or Ru-Ta. The method may further comprise the steps of: after forming the stacked gate, the straw is: a selective oxidation process for inhibiting oxidation of the metal film to float the open polysilicon film pattern and control the lateral portion of the polysilicon film pattern of the gate 102486.doc 1306647 Membrane 15 and hard mask film 16. As the metal film, a stack film of a reaction barrier layer and a metal electrode film can be preferably used. The reaction barrier layer can be formed using, for example, one of WN, TaN, TiN, and MoN. The metal electrode film can be formed using one of W, Co, Ti, Mo, Ru-Ta, Ni-Ti, and Ta-Pt.
如圖1 a所示，藉由光微影過程連續地蝕刻硬式遮罩膜 16、金屬膜15、控制閘極之多晶矽膜、層間介電膜η，及 浮動閘極之多晶矽膜，⑼而形成具有堆疊膜之堆疊閘極， 該堆疊膜由位於半導體基板1G之—區域上的浮動閘極之多 晶石夕膜圖案12、層間介電膜13、控制閘極之多晶㈣圖案 14、金屬膜15及硬式遮罩膜16組成，其中穿遂介電膜_ 成於半導體基板10之該區域中。 雖然未展示於圖式中，但可藉由執行用於禁止金屬膜Μ 之氧化的選擇性氧化過程而於浮動閑極之多晶石夕膜圖案匕 及控制閘極之多晶矽膜圖案14的側向部分上形成二氧化矽 膜（Si〇2)以減輕在形成堆疊閘極時的蝕刻損害。 隨後，將光阻塗布於整個表面上。在藉由曝光及顯影過 程而曝露單元區域之後，植入雜質離子以形成單元接面。 關於雜質離子，可將麟（P)或珅（As)用作η型源極，且可將 硼（Β)用作ρ型源極。As shown in FIG. 1a, the hard mask film 16, the metal film 15, the polysilicon film for controlling the gate, the interlayer dielectric film η, and the polysilicon film of the floating gate, (9) are continuously etched by the photolithography process. a stacked gate having a stacked film consisting of a polysilicon film pattern 12 of a floating gate located on a region of the semiconductor substrate 1G, an interlayer dielectric film 13, a polycrystalline (tetra) pattern 14 for controlling the gate, and a metal The film 15 and the hard mask film 16 are formed, wherein the through dielectric film is formed in the region of the semiconductor substrate 10. Although not shown in the drawings, the side of the polysilicon film pattern of the floating idler and the polysilicon film pattern 14 of the control gate can be performed by performing a selective oxidation process for inhibiting oxidation of the metal film ruthenium. A ruthenium dioxide film (Si 〇 2) is formed on the portion to alleviate etching damage at the time of forming the stacked gate. Subsequently, a photoresist is applied over the entire surface. After the cell regions are exposed by the exposure and development processes, impurity ions are implanted to form cell junctions. As for the impurity ions, lin (P) or yttrium (As) can be used as the n-type source, and boron (yttrium) can be used as the p-type source.
KeV且離子 在植入離子 在植入雜誌離子時，離子植入能量為1〇至5〇 植入之劑量為5Ε12至5Ε13 [i〇ns/cm2]。另外， 時’傾角為0至1 〇度。 隨後移除光阻並執行清洗過程。 102486.doc 10· 1306647 使循環耐久力特徵降級之問題。 接著，甚至可在不用增加雜皙 女六姓一 曰加雜負離子劑量的情況下解決耐 特徵。 个〜低干擾特徵以改良耐久力 普 圍 、之、已參看較佳實施例進行了先前描述，但應瞭解 通熟習此項技術者可在不偏離本發明及附加冑請專利; 之精神及範疇的情況下對本發明進行改變及修正。KeV and ions implanted ions When implanted in a journal ion, the ion implantation energy is 1〇 to 5〇. The implant dose is 5Ε12 to 5Ε13 [i〇ns/cm2]. In addition, the hour angle is 0 to 1 〇. The photoresist is then removed and the cleaning process is performed. 102486.doc 10· 1306647 The problem of degrading the cycle endurance feature. Then, the resistance characteristics can be solved even without increasing the dose of the mixed cations. The low-interference characteristics to improve the durability of the force, and have been previously described with reference to the preferred embodiments, but it should be understood that those skilled in the art can devise the spirit and scope of the invention without departing from the invention and additional patents. Changes and modifications of the invention are possible in the case of the invention.
【圖式簡單說明】 > β圖1為一展示取決於現有快閃記憶體單元之雜質離子劑 量之循環耐久力特徵的圖表； 圖2a至2b為說明用以製造快閃記憶體裝置之例示性方法 中之過程步驟的橫截面圊；且 ' 圓3為一展示根據本發明之例示性快閃記憶體裝置之循 環耐久力特徵的圖表。 【主要元件符號說明】 10 半導體基板 11 穿遂介電膜 12 多晶碎膜圖案 13 層間介電膜 14 多晶矽膜圖案 15 金屬膜 16 硬式遮罩膜 17 抗異常氧化膜 18 源極/汲極接面 102486.doc •12-BRIEF DESCRIPTION OF THE DRAWINGS > β Figure 1 is a graph showing the cyclic endurance characteristics depending on the impurity ion dose of the existing flash memory cell; Figures 2a to 2b are diagrams illustrating the fabrication of a flash memory device. The cross-section of the process steps in the method is 圊; and 'circle 3 is a graph showing the cyclic endurance characteristics of an exemplary flash memory device in accordance with the present invention. [Main component symbol description] 10 Semiconductor substrate 11 Transmitting dielectric film 12 Polycrystalline chip pattern 13 Interlayer dielectric film 14 Polycrystalline film pattern 15 Metal film 16 Hard mask film 17 Anti-anode film 18 Source/drain Face 102486.doc •12-
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| CN101635278B (en) * | 2008-07-22 | 2011-11-30 | 中芯国际集成电路制造(上海)有限公司 | Ion doping method for memory cell in DRAM |
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