CN1099705C - Manufacture of flash memory unit - Google Patents
Manufacture of flash memory unit Download PDFInfo
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- CN1099705C CN1099705C CN98115229.5A CN98115229A CN1099705C CN 1099705 C CN1099705 C CN 1099705C CN 98115229 A CN98115229 A CN 98115229A CN 1099705 C CN1099705 C CN 1099705C
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 32
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 238000007667 floating Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000000376 reactant Substances 0.000 claims 1
- 150000003839 salts Chemical class 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 51
- 238000003860 storage Methods 0.000 description 4
- 238000012217 deletion Methods 0.000 description 3
- 230000037430 deletion Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Non-Volatile Memory (AREA)
Abstract
The present invention relates to a manufacturing method of a flash memory unit, which comprises the following steps that a semiconductor substrate provided with at least one multi-layer grid structure is provided, and the grid structure comprises a first conducting layer, a dielectric layer, a second conducting layer and a silicon nitride layer; a first gap wall is formed around the grid structure; a polycrystalline silicon layer is formed on the grid structure and the substrate; a second gap wall is formed around the side edge of the polycrystalline silicon layer; ions are implanted by using the second gap wall as a mask, and a drain region is formed on the substrate; the second gap wall is removed; the mask is defined, ions are implanted, and a source region is formed on the substrate; a third conducting layer is formed on the substrate and the grid structure.
Description
The present invention relates to the manufacture method of a kind of flash memory cell (FLash Memory Cell), particularly relate to a kind of manufacture method with flash memory cell of separated grid (Split-Gate).
(Read Only Memory ROM) is a kind of permanent memory (Non-volatile Memory) to read-only memory, and information that is deposited in or data can not disappear because of the interruption of power supply supply.Erasable Programmable Read Only Memory EPROM (Erasable Programmable ROM, ERPOM) then be with the application of read-only memory to the deletion that can carry out data with write again, but the action of deletion need be used ultraviolet ray, so the packing cost of EPROM is higher.In addition, when EPROM carries out the data deletion, will be stored in all program or the data full scale clearance of EPROM, this makes needs reprogramming when doing data modification at every turn, quite consuming time.
Another kind of the erasable of data local modification that can allow removes and programmable read only memory (Electrically Erasable Programmable ROM, EEPROM) then no this item shortcoming, when carrying out data dump and re-entering, can " bit of a bit " carry out, data can be carried out operations such as depositing in, read and remove repeatedly (Bit By Bit).And the structure of flash memory (Flash Memory) is identical with EEPROM, when just carrying out the work of storage, clearing, be to carry out in the mode of " then " (Block By Bolck), very fast of speed, can finish the work of storage, clearing between about 1 to 2 second, in order to the cost of saving time and making.
Usually the grid of flash memory cell comprises double-layer structure, one for the polysilicon made be used for the floating grid (Floating Gate) of stored charge, and be used for the control gate (Control Gate) of control data access.Floating grid is positioned at the control gate below, and it is in the state of " floating " usually, do not join with any circuit, and control gate is common and word line joins.Document relevant for flash memory is a lot, and for example the paper " A new flash-erase EEPROM cell with a sidewallselect-gate on its source side " delivered on Technical Digest of IEEE Electron DeviceMeeting in 1988 of Naruke et al. is described is a kind of follow-on flash memory.
Please refer to Figure 1A and Figure 1B, it illustrates to according to above-mentioned paper, a kind of section of flash memory unit structure and vertical view.Wherein, floating grid 11 and control gate 12 were arranged on the semiconductor-based end 10, selection grid (Select Gate) 13 are arranged, the common structure that constitutes separated grid 14 (SplitGate) with isolating construction at side.In the semiconductor-based end 10 of piled grids 14 both sides, the source area 15 and drain region 16 of dopant ion arranged respectively, select grid 13 to be positioned at a side of source area 15, form with the method for eat-backing (Etch Back), so be parallel to control gate 12.The characteristic of this flash memory cell is to utilize to select grid to prevent to ooze out over-erasure (Over-Erasing) phenomenon that electric current causes improperly, to keep the normal operation of memory.But, on circuit elements design, have problem because select grid parallel with the position of control gate; And,, when data programing (Program), there is the serious disturbance phenomenon to produce so the characteristic of memory can't be done effective adjustment because of the length of selecting grid must be fixed.
In order to address the above problem, in the paper that Y.Ma delivers " A novel high density contactless flash memory array using split-gatesource-side injection cell for 5V-only application ", mention the flash memory of another kind of improvement type in the symposium of VLSI technology in 1994.
Please refer to Fig. 2, it illustrates the structural profile schematic diagram of a kind of improvement type flash memory in the above-mentioned paper.Floating grid 21, control gate 22 are arranged in semiconductor substrate 20 and select grid 23, collective stack becomes to have the separated grid 24 of isolating construction, in the semiconductor-based end 20 of separated grid 24 both sides, be formed with the source area 25 and drain region 26 of ion doping respectively, wherein select grid 23 to be covered in control gate 22 tops and side.The interference phenomenon when though this structure can be improved data programing, the requirement for accurate lithography step when forming the selection grid uprises, and therefore can consume a large amount of spaces.
In addition, the mode of EEPROM storage data is to utilize the tunneling effect of electronics (TunnelingEffect) to make charge storage in floating grid, during the operation of programming, impose voltage, produce tunneling effect via the grid oxic horizon under the floating grid at control gate and source/drain regions.The grid oxic horizon that is provided can change the required voltage of programming, if grid oxic horizon is thin excessively, then can reduce the stability of memory because of excessive electric leakage.
Therefore, main purpose of the present invention just provides a kind of manufacture method with flash memory cell of separated grid, carries out ion in the mode of automatic aligning (Self Aligned) and injects, and forms separated grid structure, save lithography step one, to simplify manufacture craft.
Another main purpose of the present invention provides a kind of manufacture method with flash memory cell of separated grid, source area is to carry out with different implantation steps with the drain region, uses to make the parameter of injecting ion can be according to different character and desired characteristic changing.
A main purpose more of the present invention provides a kind of manufacture method with flash memory cell of separated grid, forms a fixed dimension and has high-quality gate oxide, and control channel (Channel) length exactly is to keep the stability of memory.
According to above-mentioned and other purpose of the present invention, a kind of manufacture method with flash memory cell of separated grid is proposed, the method is summarized as follows: the semiconductor substrate is provided, floating grid and control gate structure have been formed on it, and form first clearance wall at the sidewall of floating grid and control gate structure, cover one deck first polysilicon layer at the semiconductor-based end and superstructure.Then, cover layer of oxide layer above polysilicon layer, eat-back and form second clearance wall, provide the function of similar mask with second clearance wall, the ion that the drain region is carried out in the semiconductor substrate by polysilicon layer injects, and removes second clearance wall afterwards again.Then, above polysilicon layer, form one deck photoresist layer,, expose the part polysilicon layer, by polysilicon layer ion is carried out at the semiconductor-based end in this zone and inject, form source area to form mask; Remove the photoresist layer afterwards, cover one deck conductive layer again, conductive layer and polysilicon layer are combined into the selection grid, with the structure of the flash memory cell of finishing separated grid.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Figure 1A and Figure 1B illustrate the section and the vertical view of existing a kind of flash memory unit structure;
Fig. 2 illustrates the generalized section into existing another kind of flash memory unit structure; And
Fig. 3 A to Fig. 3 H illustrates the manufacturing process generalized section according to a kind of flash memory unit structure of a preferred embodiment of the present invention.
Please be simultaneously with reference to Fig. 3 A to Fig. 3 H, it illustrates the manufacturing process generalized section of a kind of flash memory unit structure according to a preferred embodiment of the invention.
Please refer to Fig. 3 A, on the semiconductor-based end 30, form first conductive layer 31, dielectric layer 32, second conductive layer 33 and silicon nitride layer 34 successively, and, form structure as shown in Figure 3A its composition; Wherein, first conductive layer 31 is as floating grid, and second conductive layer 33 is a control gate, and dielectric layer 32 is the structure of silicon oxide/silicon nitride/silicon oxide (ONO), and is formed with the grid oxic horizon of skim in advance at the semiconductor-based end 30.
Then, please refer to Fig. 3 B, form first oxide layer on this semiconductor-based end 30 and silicon nitride layer 34, the sidewall that eat-backs at said structure forms first clearance wall 35; Form polysilicon layer 36 more thereon, shown in Fig. 3 C, the thickness of polysilicon layer 36 is about 200～500 dusts.
Afterwards, please refer to Fig. 3 D, on polysilicon layer 36, form second oxide layer, thickness is about 2000～4000 dusts, the formation method for example is the plasma reinforced chemical vapour deposition method, or tetraethyl orthosilicate salt (Tetra-Ethyl-Ortho-Silicate, TEOS) reaction generates; Remove part second oxide layer again, expose polysilicon layer 36, and form second clearance wall 37 at first polysilicon layer, 36 sides; Wherein, the method for removing part second oxide layer for example is the method for eat-backing, and is preferably anisotropic and eat-backs method.Because second oxide layer is thicker at polysilicon layer 36 sides, so second oxide layer of polysilicon layer 36 sides can not removed fully during etching.
Then, please refer to Fig. 3 E, be used as mask (Mask) with second clearance wall 37 and carry out the ion injection, ion is injected the semiconductor-based end 30 by polysilicon layer 36, form drain region 38.Afterwards, remove second clearance wall 37 again, the removal method for example is a wet etching, forms the structure shown in Fig. 3 F.
Then, please refer to Fig. 3 G, on polysilicon layer 36, cover last layer photoresist layer 39, composition is to remove part photoresist layer 39, expose the zone that desire forms source electrode, ion carried out in this zone inject, by polysilicon layer 36 with in the ion-implanted semiconductor substrate 30, form common source 40 (Common Source), again photoresist layer 39 is removed.
Afterwards, please refer to Fig. 3 H, on polysilicon layer 36, form the 3rd conductive layer 41, and to its composition, to finish the flash memory unit structure with separated grid; Wherein, the 3rd conductive layer 41 may be formed by one deck second polysilicon layer and the metallic combination of one deck tungsten silicide, and itself and polysilicon layer 36 are combined into separated grid.
When present embodiment injects the formation drain region at ion, as mask, carry out self-aligning ion and inject, save the step of utilizing photoresist mask to mix together, make manufacture craft be simplified with second clearance wall; And source area is to separate to carry out with the ion doping of drain region, can distinguish the amount of controlled doping, the convenient parameter of adjusting flash memory.In addition, the passage length of second clearance wall control tunnelling be can utilize,, function and the stability of keeping memory used with the polysilicon layer that is positioned at second clearance wall below protective layer as the separated grid passage; Polysilicon layer also has conduction property, merges into the selection grid with conductive layer.
Therefore, feature of the present invention provides a kind of manufacture method with flash memory cell of separated grid, as mask, the ion that the semiconductor substrate is carried out the drain region injects with second clearance wall, and need not to re-use photoresist or other masks carry out the step that ion injects.
Another feature of the present invention provides a kind of manufacture method with flash memory cell of separated grid, with second clearance wall as mask, the ion that the semiconductor substrate is carried out the drain region injects, and the passage length of may command separated grid is used the usefulness of keeping element.
A feature more of the present invention provides a kind of manufacture method with flash memory cell of separated grid, as a protective layer, makes the unlikely passage that has influence on of each step that forms second clearance wall and ion injection with polysilicon layer, uses the usefulness of keeping element.
A feature more of the present invention provides a kind of manufacture method with flash memory cell of separated grid, the step of source ion implantation polar region and drain region is carried out respectively, make it possible to adjust respectively the parameter of source area and drain region, use obtaining memory cell device of different nature.
Though disclosed the present invention in conjunction with a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be defined by accompanying Claim.
Claims (12)
1. manufacture method with flash memory cell of separated grid may further comprise the steps:
The semiconductor substrate is provided, has been provided with at least one stacked gate structure on this semiconductor-based end, wherein this stacked gate structure comprises one first conductive layer, a dielectric layer, one second conductive layer and a silicon nitride layer;
Form one first clearance wall at this stacked gate structure periphery;
On this stacked gate structure and this semiconductor-based end, form one first polysilicon layer;
Around the side of this polysilicon layer, form one second clearance wall;
, carry out ion and inject as a mask with this second clearance wall, in this semiconductor-based end, form a drain region;
Remove this second clearance wall;
Limit mask, carry out ion and inject, in this semiconductor-based end, form the one source pole district; And
On this semiconductor-based end and this stacked gate structure, form one the 3rd conductive layer.
2. the method for claim 1, wherein the generation type of this stacked gate structure may further comprise the steps:
On this semiconductor-based end, form a grid oxic horizon;
On this grid oxic horizon, form this first conductive layer, as a floating grid;
On this first conductive layer, form this dielectric layer;
On this dielectric layer, form this second conductive layer, as a control gate;
On this second conductive layer, form this silicon nitride layer; And
Limit mask, remove this silicon nitride layer of part, this second conductive layer, this dielectric layer, this first conductive layer and this grid oxic horizon, expose this semiconductor-based end of part, form this stacked gate structure.
3. method as claimed in claim 2, wherein, this dielectric layer is one oxide layer/silicon nitride layer/oxide layer structure.
4. the method for claim 1, wherein the generation type of this first clearance wall is as follows:
On this stacked gate structure and this semiconductor-based end, form an oxide layer; And
Carry out etching step, this oxide layer of etching forms this first clearance wall.
5. the method for claim 1, wherein this first polysilicon layer thickness is about 200～500 dusts.
6. the method for claim 1, wherein the generation type of this second clearance wall is as follows:
On this first polysilicon layer, form an oxide layer; And
Carry out etching step, this oxide layer of etching forms this second clearance wall.
7. method as claimed in claim 6, wherein, this etching step is that anisotropy is eat-back method.
8. method as claimed in claim 6, wherein, this oxidated layer thickness scope is about 2000～4000 dusts.
9. method as claimed in claim 6, wherein, this oxide layer forms with the tetraethyl orthosilicate reactant salt.
10. method as claimed in claim 6, wherein, this oxide layer forms with Plasma Enhanced Chemical Vapor Deposition (PECVD).
11. the method for claim 1, wherein this source area formation step also further comprises the following steps:
On this polysilicon layer, form a photoresist layer;
Limit mask, expose the zone that a desire forms source electrode;
Carry out ion and inject, form this source area; And
Remove this photoresist layer.
12. the method for claim 1, wherein forming the step of the 3rd conductor layer comprises:
On this first polysilicon layer, form one second polysilicon layer; And
On this second polysilicon layer, form a tungsten silicide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98115229.5A CN1099705C (en) | 1998-06-24 | 1998-06-24 | Manufacture of flash memory unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98115229.5A CN1099705C (en) | 1998-06-24 | 1998-06-24 | Manufacture of flash memory unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1239827A CN1239827A (en) | 1999-12-29 |
| CN1099705C true CN1099705C (en) | 2003-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98115229.5A Expired - Lifetime CN1099705C (en) | 1998-06-24 | 1998-06-24 | Manufacture of flash memory unit |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100635201B1 (en) * | 2005-03-10 | 2006-10-16 | 주식회사 하이닉스반도체 | Method for fabricating flash memory device |
| KR100843054B1 (en) * | 2006-06-28 | 2008-07-01 | 주식회사 하이닉스반도체 | Method of forming a gate in the flash memory device |
| CN104465522B (en) * | 2013-09-22 | 2017-07-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of flash memories |
| CN110211875B (en) * | 2019-06-06 | 2021-11-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
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1998
- 1998-06-24 CN CN98115229.5A patent/CN1099705C/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| CN1239827A (en) | 1999-12-29 |
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Granted publication date: 20030122 |