CN1096708C - Manufacture of tunneling oxide unit for EPROM - Google Patents

Manufacture of tunneling oxide unit for EPROM Download PDF

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Publication number
CN1096708C
CN1096708C CN 98115225 CN98115225A CN1096708C CN 1096708 C CN1096708 C CN 1096708C CN 98115225 CN98115225 CN 98115225 CN 98115225 A CN98115225 A CN 98115225A CN 1096708 C CN1096708 C CN 1096708C
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polysilicon layer
manufacture method
oxide
layer
substrate
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CN 98115225
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CN1239825A (en
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陈志民
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

The present invention relates to a method for manufacturing a tunneling oxide unit of an erasable programmable read only memory (EPROM). The method comprises the following steps: arranging a substrate on which an element region is arranged; forming an ion-implanted region in the element region; subsequently, forming a gate oxidizing layer on the substrate; forming a floating gate, a control gate and an oxidizing layer on the substrate. The present invention comprises that before the gate oxidizing layer is formed, ions with high concentration are injected in the element region, and thus, gate oxidizing layers which are subsequently produced on the element region have large thickness. Meanwhile, when a first polycrystalline silicon layer is etched with automatic alignment to form a common source region, the ions can be used as a protecting layer of the source region.

Description

The manufacture method of Erasable Programmable Read Only Memory EPROM tunneling oxide unit
The present invention relates to a kind of eeprom structure, particularly a kind of ETOX unit gets final product the manufacture method of tunneling oxide unit for EPROM (EPROM Tunnel Oxide Cell).
EEPROM (Electrically Erasable programmable ROM; The electro-erasable programmable read-only memory) is the memory circuitry that computer and electronic product often use, its advantage is wherein stored program and data, under normal circumstances can not disappear, but if will erase described program and data, then can utilize current conduction a period of time, stored in the past data just can disappear, and then can write new program and data more again.EEPROM carries out data when revising in addition, can one one (Bit by Bit) do, this makes that the better function ratio of EEPROM is that disc driver (Disk Drive) is general, the data that deposited in can't disappear because of interruption of current, and data can be carried out depositing in repeatedly, read, with action such as removing.A kind ofly developed by Intel Company, be called quickflashing (Flash) memory, its structure is identical with EEPROM, obtained ardent the echoing in market, flash memory can't carry out the core dump memory clear work of " one one ", but allows the data can local modification in the mode of " one one " (Block by Block).
Figure 1A is a vertical view, the manufacturing flow chart of the existing a kind of ETOX unit of expression.Please refer to Figure 1A, 1B and 1C, at first, provide a substrate 10.For example use regional oxidizing process (LOCOS) in substrate 10, to form field oxide 12 then, use limiting element region.
Please refer to Figure 1B and 1C then, wherein, Figure 1B is the profile of AA ' direction gained from Figure 1A, and Fig. 1 C is the profile of BB ' direction gained from Figure 1A.Form a grid oxic horizon 14 (Tunnel Oxide) on the surface of substrate 10 with thermal oxidation method.Then for example with Low Pressure Chemical Vapor Deposition, the polycrystalline silicon substances that deposit thickness is about 1000 dusts covers whole underlying structure.Then, form dielectric layer 18 and cover polycrystalline silicon substances, wherein the material of dielectric layer 18 for example is oxide/nitride/oxide (ONO) layer.To dielectric layer 18 and polycrystalline silicon substances composition, use dielectric layer 18 and the polycrystalline silicon substances of removing the cladding element district, and form first polysilicon layer 16 then.So far the vertical view of whole underlying structure is shown in Figure 1A.
Please refer to Fig. 2 A and Fig. 2 B then, wherein Fig. 2 A and Fig. 2 B represent the manufacturing process profile of existing ETOX unit, and the profile direction of Fig. 2 A is AA ' direction, and the profile direction of Fig. 2 B is BB ' direction.Make ion implantation, the denseer ion of implantation concentration in the element source area, and form flush type heavy doping ion injection region 19.
Then, use thermal oxidation method, by in the growth grid oxic horizon, because source area has denseer ion doping, so the thermal oxide layer of source area can be thicker.Then, for example with Low Pressure Chemical Vapor Deposition, the polycrystalline silicon substances that deposit thickness is about 3000 dusts covers whole underlying structure, and forms second polysilicon layer 21.And for example with the aumospheric pressure cvd method, deposited oxide layer 22 covers second polysilicon layer 21, and this oxide for example is the TEOS oxide.
Then with traditional little shadow and etching technique to second polysilicon layer 21 and oxide layer 22 compositions, and make second polysilicon layer 21 form a control gate, and make etching step terminate in dielectric layer 18.Then, carry out the follow-up source etch of aligning voluntarily step, first polysilicon layer, 16 compositions forming floating grid, and are formed source area altogether in substrate 10.So far, the vertical view of whole underlying structure is shown in Fig. 2 C.In this structure, dielectric layer 18 can't be protected first polysilicon layer 16 fully, and causes the problem in data (Data) preservation.How present manufacturing process of flash memory does not use.
In the prior art, can form irrigation canals and ditches on the common source polar region of substrate 10, these irrigation canals and ditches can interrupt the connection of common source polar region, and cause the malfunction of ETOX unit.Moreover even still there is connection the common source polar region, yet the damaged phenomenon that etching produced can improve resistance, and reduces the usefulness of ETOX unit when read-write operation.
For the injury of irrigation canals and ditches is lowered, often must add the degree of depth that deep source region connects face, so but make the effective channel length of ETOX unit elements shorten, cause the size of ETOX unit to be difficult to reduce.Therefore, main purpose of the present invention just provides the manufacture method of a kind of ETOX unit, to improve the shortcoming of prior art.
According to purpose of the present invention, a kind of ETOX is provided the manufacture method of unit, comprise the following steps, a substrate at first is provided, be formed with field oxide in this substrate, in order to limit element region.Form ion implanted region then in the element source area, cover substrate to form a grid oxic horizon.Then form the first polysilicon layer cover gate oxide layer.To the first polysilicon layer composition.
Form dielectric layer and cover first polysilicon layer and the grid oxic horizon that exposes.Form second polysilicon layer then and cover dielectric layer.And the formation oxide layer covers second polysilicon layer.Then to the second polysilicon layer composition forming control gate, approximately expose dielectric layer flush type ion implanted region at source area this moment.Then utilize automatic etched in alignment to the dielectric layer and the first polysilicon layer composition; use and make the polysilicon layer of winning form floating grid; and in substrate, form the common source polar region; the grid oxic horizon of looking thicker in the source area wherein; when automatic etched in alignment first polysilicon layer, can avoid forming irrigation canals and ditches in order to the substrate in the protection source area.
Before the invention is characterized in that grid oxic horizon forms, the ion denseer prior to implantation concentration in the element region, using the thickness that makes generate subsequent be formed in the grid oxic horizon on the source area can be thicker.And use and making automatic etched in alignment when forming piled grids (Stack-gate), the usefulness as the protective layer of source area produces the irrigation canals and ditches phenomenon to avoid source area because of over etching.And avoid damaged phenomenon that etching produces to cause the usefulness of ETOX unit when the read-write operation to reduce because of improving resistance.
So the present invention before long tunnel oxide, promptly injects denseer ion prior to source area, be different from traditional approach in the intact just injection of the first polysilicon layer composition, and the latter's the practice easily causes the bad problem of data preservation characteristics.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, below especially exemplified by a preferred embodiment, and cooperate appended each figure, be described in detail below, wherein:
Figure 1A is a vertical view, the manufacturing flow chart of the existing ETOX unit of expression;
Figure 1B is a profile, and its profile direction is AA ' direction among Figure 1A;
Fig. 1 C is a profile, and its profile direction is BB ' direction among Figure 1A;
Fig. 2 A is a profile, the manufacturing flow chart of the existing ETOX unit of expression, and its profile direction is AA ' direction;
Fig. 2 B is a profile, the manufacturing flow chart of the existing ETOX unit of expression, and its profile direction is BB ' direction;
Fig. 2 C is a vertical view, the manufacturing flow chart of the existing ETOX unit of expression;
Fig. 3 A is a vertical view, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention;
Fig. 3 B is a profile, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention, and its profile direction is AA ' direction among Fig. 3 A;
Fig. 3 C is a profile, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention, and its profile direction is BB ' direction among Fig. 3 A;
Fig. 4 A is a profile, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention, and its profile direction is AA ' direction among Fig. 3 A;
Fig. 4 B is a profile, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention, and its profile direction is BB ' direction;
Fig. 5 A is a profile, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention, and its profile direction is BB ' direction; And
Fig. 5 B is a profile, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention.
Please refer to Fig. 3 A, Fig. 3 A is a vertical view, exempts to injure the manufacturing flow chart of source electrode in a kind of ETOX unit of expression one embodiment of the present invention.And Fig. 3 A to Fig. 5 represents to exempt to injure in a kind of ETOX unit of one embodiment of the present invention the manufacturing flow chart of source electrode.At first, provide a substrate 30, for example use regional oxidizing process in substrate 30, to form field oxide 32 then, use limiting element region.
Please refer to Fig. 3 B and Fig. 3 C, wherein the profile direction of Fig. 3 B is AA ', and the profile direction of Fig. 3 C is BB '.Then, use ion implantation, the denseer ion of implantation concentration in described element region, and form flush type heavy doping ion injection region 34.Form a grid oxic horizon 36 with thermal oxidation method then, cover the surface of underlying structure.Be doped with the quite dense ion of concentration because of in the flush type heavy doping ion injection region 34 again, so the thickness of its lip-deep grid oxic horizon 36 can be thicker.Then for example with Low Pressure Chemical Vapor Deposition, the polycrystalline silicon substances that deposit thickness is about 1000 dusts covers whole underlying structure, then for the first time to the polycrystalline silicon substances composition, and forms first polysilicon layer 38.
Please refer to Fig. 4 A and Fig. 4 B, then, form dielectric layer 40 and cover whole underlying structure, its material is oxide/nitride/oxide (ONO) layer for piling up for example.And for example with Low Pressure Chemical Vapor Deposition, the polycrystalline silicon substances that deposit thickness is about 1000 dusts covers whole underlying structure, and forms second polysilicon layer 42.And for example with the aumospheric pressure cvd method, deposited oxide layer 44 covers second polysilicon layer 42, and this oxide for example is the TEOS oxide.Then with traditional little shadow and etching technique to oxide layer 44 and second polysilicon layer, 42 compositions, and make second polysilicon layer 42 form a control gate, and make etching step terminate in dielectric layer 40.
Please refer to Fig. 5 A, then according to the structure shown in Fig. 4 B, is mask with oxide layer 44, carries out etched in alignment method voluntarily, for example uses the dry ecthing method of high selectivity or uses wet etch method, removes the dielectric layer 40 that exposes.And further with this etching method, first polysilicon layer, 38 compositions to not covered by second polysilicon layer 42 are used making the polysilicon layer 38 of winning form a floating grid, and limit the common source district in substrates 30 for the second time.So far, the vertical view of whole underlying structure is shown in Fig. 5 B.
And in the cross-section structure shown in Fig. 4 A because there is not first polysilicon layer 38 on it, thus thicker grid oxic horizon 36 on the element region among the present invention, can avoid this voluntarily the etched in alignment step in source area, cause the irrigation canals and ditches phenomenon.Be positioned at the grid oxic horizon 36 on the flush type heavy doping ion injection region 34 in the present invention, can in the step of etching first polysilicon layer 38, protect source area, produce irrigation canals and ditches because of over etching to avoid source area.
Then, carry out follow-up manufacture craft, to finish the manufacturing of ETOX unit.Yet the manufacture craft that this is follow-up is irrelevant with feature of the present invention, so locate to repeat no more.
Feature of the present invention ties up to before grid oxic horizon 36 formation, elder generation's denseer ion of implantation concentration in element region, and using the thickness that makes generate subsequent be formed in the grid oxic horizon on the source area can be thicker.And use and making automatic etched in alignment when forming piled grids, the usefulness as the protective layer of source area produces irrigation canals and ditches to avoid source area because of over etching.And avoid damaged phenomenon that etching produces to cause the usefulness of ETOX unit when the read-write operation to reduce because of improving resistance.
Though the present invention is illustrated by a preferred embodiment, so it is not in order to qualification the present invention, to those skilled in the art, and without departing from the spirit and scope of the present invention, can make various improvement.

Claims (12)

1. the manufacture method of an Erasable Programmable Read Only Memory EPROM tunneling oxide unit comprises the following steps:
One substrate is provided, is formed with a field oxide in this substrate, in order to limit an element region;
In the described element region of substrate, form an ion implanted region;
Form a grid oxic horizon and cover described substrate, the thickness of grid oxic horizon that wherein covers described ion implanted region is thicker;
Form one first polysilicon layer and cover described grid oxic horizon;
To the described first polysilicon layer composition, in order to expose the described grid oxic horizon in the described ion notes district;
Form a dielectric layer and cover described first polysilicon layer and the described grid oxic horizon that exposes;
Form one second polysilicon layer and cover described dielectric layer;
Form an oxide layer and cover described second polysilicon layer;
The described second polysilicon layer composition to form a control gate, is approximately exposed the described dielectric layer on the described ion implanted region; And
To described dielectric layer and the described first polysilicon layer composition, use making described first polysilicon layer form a floating grid, and in described substrate, limit source area altogether.
2. manufacture method as claimed in claim 1, the method that wherein forms described ion implanted region comprises ion implantation.
3. manufacture method as claimed in claim 1, the method that wherein forms described ion implanted region comprises with ion implantation denseer ion of implantation concentration in described element region.
4. manufacture method as claimed in claim 1, the method that wherein forms described grid oxic horizon comprises thermal oxidation method.
5. manufacture method as claimed in claim 1, the method that wherein forms described first polysilicon layer comprises Low Pressure Chemical Vapor Deposition.
6. manufacture method as claimed in claim 1, the method that wherein forms described second polysilicon layer comprises Low Pressure Chemical Vapor Deposition.
7. manufacture method as claimed in claim 1, the method that wherein forms described oxide layer comprises the aumospheric pressure cvd method.
8. manufacture method as claimed in claim 1, the thickness of wherein said grid oxic horizon is about 90 dusts.
9. manufacture method as claimed in claim 1, the thickness of wherein said first polysilicon layer is about 1000 dusts.
10. manufacture method as claimed in claim 1, the thickness of wherein said second polysilicon layer is about 1000 dusts.
11. manufacture method as claimed in claim 1, wherein said dielectric layer are the oxide/nitride/oxide structure that piles up.
12. manufacture method as claimed in claim 1, the material of wherein said oxide layer are the TEOS oxide.
CN 98115225 1998-06-24 1998-06-24 Manufacture of tunneling oxide unit for EPROM Expired - Lifetime CN1096708C (en)

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Application Number Priority Date Filing Date Title
CN 98115225 CN1096708C (en) 1998-06-24 1998-06-24 Manufacture of tunneling oxide unit for EPROM

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Application Number Priority Date Filing Date Title
CN 98115225 CN1096708C (en) 1998-06-24 1998-06-24 Manufacture of tunneling oxide unit for EPROM

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CN1096708C true CN1096708C (en) 2002-12-18

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6624027B1 (en) * 2002-05-09 2003-09-23 Atmel Corporation Ultra small thin windows in floating gate transistors defined by lost nitride spacers
CN101308786B (en) * 2007-05-15 2010-12-22 中芯国际集成电路制造(上海)有限公司 Ion injection method of semiconductor device
CN102104025B (en) * 2009-12-18 2013-06-12 上海华虹Nec电子有限公司 Method for manufacturing gate oxide layer of EEPROM and gate oxide layer manufactured thereby

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