CN1131559C - Manufacture of the separated grid structure for flash memory - Google Patents
Manufacture of the separated grid structure for flash memory Download PDFInfo
- Publication number
- CN1131559C CN1131559C CN 98115228 CN98115228A CN1131559C CN 1131559 C CN1131559 C CN 1131559C CN 98115228 CN98115228 CN 98115228 CN 98115228 A CN98115228 A CN 98115228A CN 1131559 C CN1131559 C CN 1131559C
- Authority
- CN
- China
- Prior art keywords
- polysilicon layer
- area
- dielectric
- grid
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a manufacturing method for a separated grid structure of a fast flash memory. The original rugged surface of a separated grid is flatted by an inner dielectric layer deposition method and a chemically machinery trituration method, and thereby, the deposition and etching quality of a selecting grid is enhanced. The present invention can simplify a fabrication process technique, can also effectively reduce the sizes of a memory cell, and simultaneously have high programmable efficiency of the separated grid. The present invention has high memory cell electric current, but can avoid the relevant influence of excess erasing.
Description
Technical field
The present invention relates to a kind of manufacture method of flash memory, particularly relate to the manufacture method of a kind of flash memory separated grid (Split Gate) structure.
Background technology
Permanent memory (Nonvolatile memory) is applied on the various electronic installations, as storage organization data, routine data and other can repeated access data.And on programmable permanent memory, more emphasize recently as flash memory (flash memory) structure wipe and programmable read only memory (Erasable Programmable Read-Only Memory, EPROM) or erasable removing and the application of programmable read only memory (Electrically Erased Programmable ROM).Usually flash memory has two grids, wherein is divided into polysilicon (Poly-Silicon) made being used for the floating grid (Floating Gate) of stored charge (Charge), and is used for the control gate (Control Gate) of control data access.Floating grid is positioned at the control gate below, and is in the state of " floating " usually, be connected with any circuit, and control gate is common and word line (Word Line) joins.Because therefore operations such as the data in the flash memory can repeatedly deposit in, read and remove become the product rather fast of growing up on the semi-conductor market.
Utilize the source side of a kind of separated grid in the flash memory to inject the mode of unit (Spilt-gatesource-side-injection cell), can make memory cell have higher programming efficiency and the lower write current (write current) of depositing.And the memory cell formant of this high injection efficiency serve as reasons along the passage of conducting one a little less than open (weakly-on) and form with the zone of a Gao Qi (hifhly-on), but by stenosis area significantly the energy drop will cause source electrode place to produce a large amount of hot electrons near floating grid.And most source side is injected the problem that Frash memory in separate grids mostly has high-resistance phenomenon or over-erasure (over-erase) takes place.
Therefore recently, problem at the element over-erasure, develop and a kind of highdensity flash memory of tri-layer grid that has, " A novel high density contactless flash memory array using split-gatesource-side injection cell for 5V-only applications (source side that adopts separated grid of working under 5V is injected the contactless flash memory of novel high-density of unit) " of on a VLSI technical seminar in 1994, being delivered as Y.Ma.Please refer to Fig. 1, this flash memory has tunnel oxide (Tunnelling oxide) 11 on the silicon substrate 10 of P type, and the floating grid 12 and control gate 13 that form with polysilicon, and floating grid 12 is positioned at the below of control gate 13.After floating grid 12 and control gate 13 form,,, and after maximum difference is formation source/ drain region 14,15, form a polysilicon layer more thereon, as selecting grid (Select Gate) 16 with formation source/ drain region 14,15 at substrate 10 implanted dopants.
The zone of wherein selecting grid when programming operation carries out, to open a little less than the may command, and prevent that unselected memory cell conducts from being programming and the form that reads.Select grid to carry out along the direction of wearing tunnel, this can satisfy the diminishing demand of polysilicon size, reduces the delay of selecting grid simultaneously, and promotes the speed of selecting grid to cross abutment wall.And select the formation of grid that memory cell also can be operated under suppression mode (depletion mode).
In structure shown in Figure 1, because the shared drain region 14 of two separated grids, therefore the distance between two separated grids is less, make when the polysilicon layer of grid is selected in the deposition conduct, it is good to cover (step coverage) ability because of ladder, be positioned at polysilicon layer deposition inferior quality between two separated grids and make, even form hole (void) and the conductivity of reduction polysilicon layer, on the other hand, between different selection grid, because high low head is excessive, when photoresist exposure and etching, can cause the phenomenon of short circuit.
Summary of the invention
Therefore, main purpose of the present invention is to take into account the usefulness high able to programme that separated grid has, having high memory cell current but can not cause and cross and to wipe (over-erase) relevant influence, and can dwindle under the prerequisite of memory cell size, by the rugged surface of deposition one dielectric layer flatening script, and then improve the deposition quality of selecting grid, except that simplifying the manufacture craft, can also dwindle the size of memory cell.
For achieving the above object, the invention provides a kind of manufacture method of separated grid structure for flash memory, it comprises the following steps: at first to provide a substrate at least, and substrate comprises a first area and a second area at least.On substrate, form a tunnel oxide, one first polysilicon layer and a dielectric layer successively.Then, form a photoresist layer, cover the dielectric layer of top, first area, remove the dielectric layer and first polysilicon layer that are not covered, and expose the tunnel oxide on the second area by photoresist.Afterwards, on substrate, form one second polysilicon layer and a mask layer successively, and limit the first area, remove first area part mask layer, second polysilicon layer, dielectric layer and first polysilicon layer, and form one first separated grid and one second separated grid.Limit second area simultaneously, remove the second area part mask layer and second polysilicon layer, form a grid.Side at first separated grid, second separated grid and first grid forms a clearance wall, and to the substrate implanted dopant, form first source/drain region and second source/drain region in first area and second area respectively, wherein first separated grid and this second separated grid have source area altogether.Form an inner-dielectric-ayer on substrate, limit inner-dielectric-ayer, remove top, first area inner-dielectric-ayer, this inner-dielectric-ayer is all kept in each follow-up step.At last, on substrate, form one the 3rd polysilicon layer, limit the 3rd polysilicon layer, remove the 3rd polysilicon layer on the second area, to finish separated grid structure for flash memory.
For realizing above-mentioned purpose, the present invention also provides a kind of manufacture method of separated grid structure for flash memory, and it comprises the following steps: at first to provide a substrate at least, and substrate comprises a first area and a second area at least.On substrate, form a tunnel oxide, one first polysilicon layer and a dielectric layer, one second polysilicon layer and a mask layer successively, and qualification first area, remove first area part mask layer, second polysilicon layer, dielectric layer and first polysilicon layer and remove second area mask layer, second polysilicon layer, dielectric layer and first polysilicon layer, on the first area, form one first separated grid and one second separated grid, and expose this tunnel oxide of second area.Then, form a clearance wall, and to the substrate implanted dopant of first area, to form first source/drain region, wherein first separated grid and this second separated grid has a common source at first separated grid and the second separated grid side.Afterwards, on substrate, form an inner-dielectric-ayer, and limit inner-dielectric-ayer, remove inner-dielectric-ayer on top, first area inner-dielectric-ayer and the second area.Then, on inner-dielectric-ayer, form one the 3rd polysilicon layer, and limit the 3rd polysilicon layer on the second area, and form a grid.At last, form a clearance wall, and,, finish separated grid structure for flash memory to form second source/drain region to the substrate implanted dopant of second area at the grid side.
Description of drawings
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 shows a kind of separated grid structure for flash memory of prior art;
Fig. 2 A to Fig. 2 F shows the manufacturing process profile of separated grid structure for flash memory according to a preferred embodiment of the invention;
Fig. 3 A to Fig. 3 F shows the manufacturing process profile of separated grid structure for flash memory according to a preferred embodiment of the invention.
Fig. 2 A to Fig. 2 F shows the manufacturing process profile of separated grid structure for flash memory according to a preferred embodiment of the invention.
Embodiment
Please refer to Fig. 2 A.At first, form a grid oxic horizon as tunnel oxide 21 on Semiconductor substrate 20, tunnel oxide 21 for example forms with thermal oxidation method, and THICKNESS CONTROL is below 100 dusts.Then, forming one first polysilicon layer 22 on tunnel oxide 21, for example carry out with Low Pressure Chemical Vapor Deposition, form a dielectric layer 23 on first polysilicon layer, 22 surfaces again, for example is oxide-nitride thing-oxide (ONO), and thickness is about 220 dusts.Afterwards, form a photoresist layer 24 on part dielectric layer 23 surfaces, the substrate that is covered by photoresist 24 is the first area 25 that forms flash memory, and the zone that is covered by photoresist 24 is the second area 26 that forms the MOS element.
Then, utilize photoetching and corrosion technology, remove not the dielectric layer 23 and first polysilicon layer 22 on the second area 26 that is covered by photoresist 24, the dielectric layer 23 on the etching second area and first polysilicon layer 22 successively, expose the tunnel oxide 21 of second area, for example carry out with dry ecthing method.Remove photoresist 24 again, then there are dielectric layer 23a, the first polysilicon layer 22a, tunnel oxide 21 to exist on the first area with substrate 20, and second area is behind etching process, only remaining tunnel oxide 21 and substrate 20, therefore expose the tunnel oxide 21 of second area, shown in Fig. 2 B.
Please refer to Fig. 2 C.Afterwards, dielectric layer 23a surface in the first area forms one second polysilicon layer 27 with tunnel oxide 21 surfaces that second area exposes, and form conductive capabilities than the better metal silicide layer 28 of polysilicon layer (Silicide), for example tungsten silicide on second polysilicon layer 27 surface.On metal silicide layer 28, form the mask layer 29 of etching protection again, for example silicon nitride.Then, on the mask layer 29 of first area and second area, form a photoresist layer 200,200a respectively, wherein, utilize 200 pairs of first area compositions of photoresist, to form one first separated grid and one second separated grid of flash memory, to the second area composition, form a gate regions of MOS element with photoresist 200a.
Please refer to Fig. 2 D again.Then, after limiting first separated grid and one second separated grid zone with photoresist, remove mask layer, tungsten silicide layer, second polysilicon layer, dielectric layer and second polysilicon layer of first area part, and form first separated grid 202 and second separated grid of being formed by mask layer 29a, tungsten silicide 28a, the second polysilicon layer 27a, dielectric layer 23b and the second polysilicon layer 22b 204.And first polysilicon layer is as the floating grid of separated grid, and second polysilicon layer is as its control gate.Limit the grid of second area simultaneously with photoresist, remove mask layer, tungsten silicide and second polysilicon layer of second area part, and form the grid of forming by mask layer 29b, tungsten silicide 28b and the second polysilicon layer 27b 206.
Then, form a clearance wall (spacer) 207 with grid 206 sides, deposition one silicon nitride layer on substrate for example, etch-back silicon nitride layer and forming again at first separated grid 202, second separated grid 204.Again Semiconductor substrate 20 is carried out the step that ion injects, then on the substrate of first area, form first source/drain region 208,208a, and form second source/drain region 208b on the substrate of second area.Wherein, first separated grid 202 of first area and second separated grid 204 have a common source polar region 208a.
Please refer to Fig. 2 E.On the grid of the separated grid of first area and second area, form an inner-dielectric-ayer 210, for example deposit with the CVD method, its height of deposition need cover first separated grid and second separated grid at least, again with chemical mechanical milling method planarization inner-dielectric-ayer 210 surfaces.Then, again through the rotten dielectric layer of carving step qualification first area of photoetching, remove the inner-dielectric-ayer of first area part, remaining dielectric layer 210a need cover part first separated grid 202 and second separated grid 204 at least, and covers the common source polar region 208a of first separated grid and second separated grid.
Afterwards, on dielectric layer, form one the 3rd polysilicon layer, to the 3rd polysilicon layer composition, remove the 3rd polysilicon layer on second area surface simultaneously, then the 3rd polysilicon layer 212 on surface, first area is as the selection grid of flash memory, shown in Fig. 2 F, and the 3rd polysilicon layer thickness is about the 2000-5000 dust.
Therefore, in the present embodiment, be with the floating grid of first polysilicon layer as the flash memory separated grid, with second polysilicon layer and tungsten silicide as the control gate of separated grid and as the MOS element gate, and with the 3rd polysilicon layer and tungsten silicide selection grid as separated grid.
Fig. 3 A to Fig. 3 F shows the manufacturing process profile of the separated grid structure for flash memory of another preferred embodiment according to the present invention.
Please refer to Fig. 3 A.Form a tunnel oxide 31, one first polysilicon layer 32, a dielectric layer 33, one second polysilicon layer 34, a tungsten silicide 35 and a mask layer 36 on substrate 30 successively, wherein dielectric layer 33 for example is oxide-nitride thing-oxide and silicon nitride with mask layer 36.Then, on the first area 38 of desire formation flash memory, form a photoresist 37, to limit separated grid.
Then, mask layer, silicon tungsten thing, second polysilicon layer, dielectric layer and first polysilicon layer that first area 38 is not covered by photoresist removed in etching, then the first area has mask layer 36a, silicon tungsten thing 35a, the second polysilicon layer 34a, dielectric layer 33a and the first polysilicon layer 32a, and first polysilicon layer is as the floating grid of separated grid, and second polysilicon layer is as its control gate.Remove simultaneously that desire forms mask layer, silicon tungsten thing, second polysilicon layer, dielectric layer and first polysilicon layer of MOS element second area 39 and the tunnel oxide 31 that exposes second area 39 surfaces, shown in Fig. 3 B.And form clearance walls 304 at first separated grid 300 and second separated grid 302, deposition one silicon nitride layer on substrate for example, etch-back silicon nitride layer and forming again.Again Semiconductor substrate 20 is carried out the step that ion injects, then form first source/drain region 306,306a on the substrate of first area, wherein, first separated grid 300 and second separated grid 302 of first area have one source pole district 306a jointly.
Please refer to Fig. 3 C.Afterwards, on the tunnel oxide 31 that exposes with second area on the separated grid of first area, form an inner-dielectric-ayer 308, for example deposit with the CVD method, its height of deposition need cover first separated grid and second separated grid at least, again with chemical mechanical milling method planarization inner-dielectric-ayer 308 surfaces.Then, on inner-dielectric-ayer 308 surfaces of first area, form a photoresist layer again, use the inner-dielectric-ayer 308 that limits the first area, remove the inner-dielectric-ayer of first area part, and the remaining dielectric layer 308a in first area need cover part first separated grid and second separated grid at least, and covers the common source polar region of first separated grid and second separated grid, removes the inner-dielectric-ayer of second area simultaneously, expose the tunnel oxide 31 of second area once more, shown in Fig. 3 D.
Please refer to Fig. 3 E.On the tunnel oxide 31 that exposes with second area on the inner-dielectric-ayer 308a, form one the 3rd polysilicon layer 312 again, and on the 3rd polysilicon layer, form a tungsten silicide 314, with the 3rd polysilicon layer 312 and the selection grid of tungsten silicide 314 as flash memory.Then, shown in Fig. 3 F, limit the 3rd polysilicon layer and the tungsten silicide of second area, to form the grid 316 of MOS element, it is made up of the 3rd polysilicon layer 312a and tungsten silicide 314a.Again grid 316 sides are formed clearance wall 318, and, form second source/drain region 320 the substrate implanted dopant of second area.
Therefore, in the present embodiment, with the floating grid of first polysilicon layer, with second polysilicon layer and tungsten silicide control gate, with the 3rd polysilicon layer and tungsten silicide selection grid as the mos gate utmost point and separated grid as separated grid as the flash memory separated grid.
The present invention mainly is by the deposition of an inner-dielectric-ayer and the carrying out of chemical mechanical milling method, and planarization is rugged separated grid surface originally, and then improves deposition and the etching quality of selecting grid.Therefore, the present invention be except that simplifying the manufacture craft, more can make to dwindle memory cell size and can carry out smoothly, and the usefulness high able to programme of taking into account separated grid simultaneously and being had, have the influence that high memory cell current can not cause that but over-erasure is relevant, and also dwindled memory-size.
Though the present invention discloses as above in conjunction with the preferred embodiments; but it is not in order to limit the present invention; those skilled in the art can make various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be defined by accompanying Claim.
Claims (24)
1. the manufacture method of a separated grid structure for flash memory, it provides a substrate, and this substrate comprises one first separated grid and one second separated grid at least, and this manufacture method comprises the following steps: at least
On this substrate, form an inner-dielectric-ayer, cover this first separated grid and this second separated grid;
Limit this inner-dielectric-ayer, make this inner-dielectric-ayer cover the partly common source between this first separated grid, this second separated grid of part and this first separated grid and this second separated grid at least, wherein, this inner-dielectric-ayer is all kept in each follow-up step; And
On this inner-dielectric-ayer, form a polysilicon layer, and limit this polysilicon layer, to finish this separated grid structure for flash memory.
2. manufacture method as claimed in claim 1 wherein, after forming this inner-dielectric-ayer, also comprises the step with this inner-dielectric-ayer of chemical mechanical milling method planarization.
3. manufacture method as claimed in claim 1, wherein, this polysilicon layer is as the selection grid of this flash memory.
4. the manufacture method of a separated grid structure for flash memory, it provides a substrate, and this substrate comprises a first area and a second area at least, and this manufacture method comprises the following steps: at least
A. on this substrate, form a tunnel oxide, one first polysilicon layer and a dielectric layer successively;
B. form a photoresist layer, cover this dielectric layer of this top, first area, remove this dielectric layer and this first polysilicon layer that are not covered, expose this tunnel oxide on this second area by photoresist;
C. on this substrate, form one second polysilicon layer and a mask layer successively;
D. limit this first area, remove this mask layer of part, this second polysilicon layer, this dielectric layer and this first polysilicon layer, form one first separated grid and one second separated grid, limit this second area simultaneously, remove this mask layer of part and this second polysilicon layer, form a grid;
E. the side at this first separated grid, this second separated grid and this grid forms a clearance wall;
F. to this substrate implanted dopant, form first source/drain region and second source/drain region in this first area and this second area respectively, wherein this first separated grid and this second separated grid have source area altogether;
G. form an inner-dielectric-ayer on this substrate, limit this inner-dielectric-ayer, remove this this inner-dielectric-ayer of top, first area, this inner-dielectric-ayer is in order to be filled in the space between this first separated grid and this second separated grid; And
H. on this substrate, form one the 3rd polysilicon layer, limit the 3rd polysilicon layer, remove the 3rd polysilicon layer on this second area, to finish this separated grid structure for flash memory.
5. manufacture method as claimed in claim 4 wherein, in this step c, also is included in the step that this second polysilicon layer surface forms a tungsten silicide.
6. manufacture method as claimed in claim 4 wherein, in this step g, forms the step that also comprises behind this inner-dielectric-ayer with this inner-dielectric-ayer of chemical mechanical milling method planarization.
7. manufacture method as claimed in claim 4, wherein, this dielectric layer material is oxide-nitride thing-oxide.
8. manufacture method as claimed in claim 4, wherein, this mask layer is a silicon nitride.
9. manufacture method as claimed in claim 4, wherein, this clearance wall is a silicon nitride.
10. manufacture method as claimed in claim 4, wherein, this grid structure of this second area comprises this second polysilicon layer and this mask layer.
11. manufacture method as claimed in claim 4, wherein, first polysilicon layer is as the floating grid of this first separated grid and this second separated grid.
12. manufacture method as claimed in claim 4, wherein, this second polysilicon layer is as the control gate of this flash memory.
13. manufacture method as claimed in claim 4, wherein, the 3rd polysilicon layer is as the selection grid of this flash memory.
14. the manufacture method of a separated grid structure for flash memory, it provides a substrate, and this substrate comprises a first area and a second area at least, and this manufacture method comprises the following steps: at least
A. on this substrate, form a tunnel oxide, one first polysilicon layer and a dielectric layer, one second polysilicon layer and a mask layer successively;
B. limit this first area, remove this this mask layer of first area part, this second polysilicon layer, this dielectric layer and this first polysilicon layer and remove this mask layer on this second area, this second polysilicon layer, this dielectric layer and this first polysilicon layer, on this first area, form one first separated grid and one second separated grid, and expose this tunnel oxide of this second area;
C. form a clearance wall at this first separated grid and this second separated grid side;
D. to this substrate implanted dopant of this first area, to form first source/drain region, wherein this first separated grid and this second separated grid have a common source;
E. on this substrate, form an inner-dielectric-ayer, limit this inner-dielectric-ayer, remove this inner-dielectric-ayer on this this inner-dielectric-ayer of top, first area and this second area;
F. on this inner-dielectric-ayer, form one the 3rd polysilicon layer, limit the 3rd polysilicon layer on this second area, form a grid;
G. form a clearance wall at this grid side; And
H. to this substrate implanted dopant of this second area, to form second source/drain region, to finish this separated grid structure for flash memory.
15. manufacture method as claimed in claim 14 wherein, in this step a, also is included in the step that this second polysilicon layer surface forms one first tungsten silicide.
16. manufacture method as claimed in claim 14 wherein, in this step e, forms the step that also comprises behind this inner-dielectric-ayer with this inner-dielectric-ayer of chemical mechanical milling method planarization.
17. manufacture method as claimed in claim 14 wherein, in this step g, also is included in the step that the 3rd polysilicon layer surface forms one second tungsten silicide.
18. manufacture method as claimed in claim 14, wherein, this dielectric layer material is oxide-nitride thing-oxide.
19. manufacture method as claimed in claim 14, wherein, this mask layer is a silicon nitride.
20. manufacture method as claimed in claim 14, wherein, this clearance wall is a silicon nitride.
21. manufacture method as claimed in claim 14, wherein, this grid structure of this second area is made up of the 3rd polysilicon layer.
22. manufacture method as claimed in claim 14, wherein, this first polysilicon layer is as the floating grid of this first separated grid and this second separated grid.
23. manufacture method as claimed in claim 14, wherein, this second polysilicon layer and this first tungsten silicide are as the control gate of this flash memory.
24. manufacture method as claimed in claim 14, wherein, the 3rd polysilicon layer and this second tungsten silicide are as the selection grid of this flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 98115228 CN1131559C (en) | 1998-06-24 | 1998-06-24 | Manufacture of the separated grid structure for flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 98115228 CN1131559C (en) | 1998-06-24 | 1998-06-24 | Manufacture of the separated grid structure for flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1239826A CN1239826A (en) | 1999-12-29 |
| CN1131559C true CN1131559C (en) | 2003-12-17 |
Family
ID=5224471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 98115228 Expired - Lifetime CN1131559C (en) | 1998-06-24 | 1998-06-24 | Manufacture of the separated grid structure for flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1131559C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456453C (en) * | 2005-09-27 | 2009-01-28 | 力晶半导体股份有限公司 | Production of flash memory |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100500448B1 (en) * | 2003-02-06 | 2005-07-14 | 삼성전자주식회사 | Method of fabricating a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit fabricated thereby |
| CN1309083C (en) * | 2003-08-28 | 2007-04-04 | 力晶半导体股份有限公司 | Separated grid flash memory unit and its mfg. method |
| KR100816733B1 (en) | 2006-06-29 | 2008-03-25 | 주식회사 하이닉스반도체 | Method for fabricating recess gate in semiconductor device |
| US8334560B2 (en) | 2009-09-02 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reverse disturb immune asymmetrical sidewall floating gate devices |
| CN103107076B (en) * | 2011-11-11 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of separate grid type flash memory and memory set |
| CN105355547B (en) * | 2014-08-21 | 2019-04-12 | 中芯国际集成电路制造(上海)有限公司 | The production method of the production method and memory device of grid |
| TWI590388B (en) * | 2016-04-12 | 2017-07-01 | 新唐科技股份有限公司 | Memory devices and the methods for foring the same |
| CN107910332A (en) * | 2017-11-09 | 2018-04-13 | 上海华力微电子有限公司 | A kind of gate connection structures of memory and forming method thereof |
-
1998
- 1998-06-24 CN CN 98115228 patent/CN1131559C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456453C (en) * | 2005-09-27 | 2009-01-28 | 力晶半导体股份有限公司 | Production of flash memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1239826A (en) | 1999-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100966265B1 (en) | Nand flash memory array with cut-off gate line and methods for operating and fabricating the same | |
| US6005270A (en) | Semiconductor nonvolatile memory device and method of production of same | |
| US5705415A (en) | Process for forming an electrically programmable read-only memory cell | |
| EP0676811B1 (en) | EEPROM cell with isolation transistor and methods for making and operating the same | |
| KR100474472B1 (en) | Integrated circuit and method of manufacturing thereof | |
| CN101521207B (en) | Integrated circuit | |
| CN1269218C (en) | Method for forming semiconductor memory array and the made memory arroy by same | |
| US7394125B1 (en) | Recessed channel with separated ONO memory device | |
| CN100479169C (en) | Method for forming at least part of bi-bit storage core array on semiconductor substrate | |
| CN1495905A (en) | Self-registered separated grid and non-flash memory and making method | |
| CN1905195A (en) | Flash memory device and method of manufacturing the same | |
| CN1131559C (en) | Manufacture of the separated grid structure for flash memory | |
| CN1310846A (en) | Electrically erasable nonvolatile memory | |
| CN1992235A (en) | Nor-type flash memory cell array and method for manufacturing the same | |
| CN100568508C (en) | Symmetrical and self aligned non-volatile memory architecture | |
| CN104900650A (en) | Split gate flash memory and manufacturing method thereof | |
| CN1992233A (en) | Flash memory device having vertical split gate structure and method for manufacturing the same | |
| CN112490248B (en) | Ferroelectric floating gate memory cell string and preparation method thereof | |
| CN1099705C (en) | Manufacture of flash memory unit | |
| US6211074B1 (en) | Methods and arrangements for reducing stress and preventing cracking in a silicide layer | |
| CN1127760C (en) | Method for fabricating nonvolatile memory device | |
| CN1096708C (en) | Manufacture of tunneling oxide unit for EPROM | |
| CN1136617C (en) | Nonvolatile memory with high coupling rate and its manufacture | |
| CN1218385C (en) | Method for mfg. imbedded storage | |
| CN100448009C (en) | Non-volatile memory and manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20031217 |
|
| CX01 | Expiry of patent term |