CN1127760C - Method for fabricating nonvolatile memory device - Google Patents
Method for fabricating nonvolatile memory device Download PDFInfo
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- CN1127760C CN1127760C CN98108027A CN98108027A CN1127760C CN 1127760 C CN1127760 C CN 1127760C CN 98108027 A CN98108027 A CN 98108027A CN 98108027 A CN98108027 A CN 98108027A CN 1127760 C CN1127760 C CN 1127760C
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
Abstract
A method for manufacturing a non-volatile semiconductor memory element is comprised by: forming a second conductive bit line under a first conductive substrate; forming an insulation film and a first conductive layer and a first conductive line; forming a gate insulation film on the substrate to form a tunnel insulation film; forming a second conductive film, and second conductive lines which is adopted by floating gate and program gate between the bit lines; forming a dielectric film on the surface of a second conductive line; a third conductive film and an insulation film, forming a word line and a floating gate; forming insulation side wall cushions on both sides of the insulation film and the word line and the dielectric film and the floating gate in the construction picture; using the cushion cover mould to construct the program tunnel insulation film, and forming a contact hole and a program line being connected to a program gate via the contact hole.
Description
Technical field
The present invention relates to a kind of method that is used for making non-volatile memory device, particularly relate to a kind of non-volatile memory device that is used for making a simple layer stack structure with program grid.
Background technology
The effective dimensions of these memories of the packaging density that is decided by non-volatile memory device such as flash Electrically Erasable Read Only Memory (flash-EEPROM) and EEPROM depends on the size of unit and the arrangement architecture of unit, in aspect of these memory cell, the minimum unit structure is a simple stepped construction.
As shown in Figure 1, a non-volatile memory device has a common stepped construction.One tunnel effect (tunneling) oxide layer 12 is arranged on a P type semiconductor substrate 11, a floating grid 13 is arranged on tunnel effect oxide layer 12, on this floating grid 13, be formed with a control gate 15.One dielectric layer 14 is arranged between control gate 15 and floating grid 13.Surface underneath in the Semiconductor substrate 11 of floating grid 13 both sides is formed with N type extrinsic region 16.
As shown in Figure 2, Fig. 2 shows a kind of array structure with memory cell of simple stacked non-volatile memory device, is constituting word line 17 each other on the direction of a preset distance on the Semiconductor substrate (not shown); Also on the direction of a preset distance, constituting metal bit line 18 each other perpendicular to word line 17.Every next but two word line 17 constitutes a public drain electrode line 20 on the direction identical with word line 17.Because per two unit need a hard contact, so the effective dimensions of memory cell becomes bigger.
In order to address such a problem, invented a kind of non-volatile memory device that does not need hard contact.
Fig. 3 one does not wherein need the array circuit figure of the non-volatile memory device of metal contact hole, and Fig. 4 is the formation of this non-volatile memory device of seeing along the I-I line of Fig. 3.
Wherein do not need in the conventional non-volatile memory device of metal contact hole one, source electrode and drain electrode extrinsic region are used as bit line.In other words, constituting on the direction of a preset distance somely each other, constituting word line 23 at a distance of a preset distance perpendicular to this extrinsic region place each other the dense doping of n type zone (calculating).At this moment, extrinsic region is to being isolated by separator 28.One extrinsic region is to being used as one source pole and a drain electrode and a n
+Bit line 29.
Floating grid 24 be placed in word line 23 and extrinsic region between.At this moment, the word line on floating grid 24 23 becomes control gate.Between control gate and floating grid 24, constitute a dielectric layer 26, and between floating grid 24 and Semiconductor substrate 21, constitute a grid oxic horizon 27.
At n
+The end of bit line 29 is mounted with a plurality of selection n
+The selection transistor 30 of bit line 29.The metal contact hole 31 that is connected to a plurality of selection transistors 30 makes selects transistor 30 to link to each other with the data line metal (not shown).
As mentioned above, even in not needing this non-volatile memory device of metal contact hole, even because the resistance of extrinsic region does not form the bit line of each unit, per Unit 32 or need a metal contact hole more than Unit 32.Therefore can dwindle effective cell size.
But, because do not need this conventional non-volatile memory device of metal contact hole to have a simple stepped construction therein, so be under identical bias state in two adjacent unit on the direction of word line.Therefore, can produce the program disturb that a non-selected cell is programmed or is wiped free of there.In order to solve this program disturb, bit line is separated each other with separated source between adjacent cells and drain electrode.Therefore, the raceway groove cutting unit with dissymmetrical structure of selecting grid is used as memory cell.
Fig. 5 shows a kind of source electrode therein by the array circuit figure of the nonvolatile semiconductor memory member that separates from drain electrode, and Fig. 6 shows the cutaway view in the structure of next nonvolatile memory cell of situation that does not have improved metal contact hole.
As shown in Figure 5, in not needing a non-volatile memory device of metal contact hole, because each cell source and drain electrode separate, so source electrode line and drain line are formed on each other on the direction of a preset distance 32 and 33, wherein source electrode line 32 is connected to n type dense doped source extrinsic region (not shown) and drain line 33 is connected to the dense doped-drain extrinsic region of n type (not shown).Word line 23 is formed on and source electrode and drain line 32 and 33 quadrature positions.
Every strip metal data wire 34 is positioned on the end and drain line 33 equidirectionals of drain line 33.Some selection transistors 30 are formed on the end of source electrode and drain line 32 and 33.Be connected to the metal contact hole 31 of selecting transistor 30 and be connected to selection transistor and data line metal 34.
Fig. 6 show utilize the raceway groove cutting unit do not having a non-volatile memory device of improved metal contact hole, floating grid 24 to be placed on the gate oxide level 27, and gate oxide level 27 places on the P type semiconductor substrate 21.On floating grid 24, form a control gate 25.Select grid 35 to be formed on the gate oxide level 27 and on control gate 25.Selecting between grid 35 and control gate 25 and the floating grid 24 and between control gate 25 and floating grid 24, to form a dielectric layer.A pair of n type source electrode and drain region 22 be formed on Semiconductor substrate 21 surfaces below.At this moment, in source electrode and the drain region 22 be formed on the straight line of a side of floating grid 24 and another be formed on the opposite side of floating grid 24 at interval a position.
The non-volatile memory device of this routine has some problems.At first, it provides a little effective cell size, because it has a simple stepped construction, is under identical bias condition at two adjacent cells on the word-line direction also, so produced the program disturb that non-selected cell is programmed or is wiped free of when programming.Secondly, though the source electrode of each unit and drain electrode therein is separated or used therein in the non-volatile memory device that does not have metal contact hole of the raceway groove separative element with a unsymmetric structure not that generating routine disturbs, because bit line or select the separation of grid to make the size of a unit cell increase.
Summary of the invention
Therefore, the present invention proposes a kind of method that is used for making a non-volatile memory device, this method has in fact avoided because the restriction of correlation technique and several problems that shortcoming is produced.
An object of the present invention is to provide a kind of method that is used for making a non-volatile memory device, this non-volatile memory device has a little effective cell size by eliminating program disturb.
Additional feature and advantage of the present invention will in explanation subsequently, be stated and from the explanation as can be known partial content be conspicuous, perhaps also can by practice of the present invention obtain the instruction.By realizing and obtain objects and advantages of the present invention in the specification of being write and claim and the pointed practical structures of accompanying drawing.
For the advantage that realizes these and other and according to purpose of the present invention, as summary and briefly description, the method that is used for making a non-volatile memory device comprises following step: in the surface underneath of a substrate of first conductivity type, at the bit line that forms second conductivity type each other on the direction of a preset distance; One after the other form a separator and one first conductive layer and remove this separator and first conductive layer subsequently selectively and make and be isolated from each other perpendicular to the bit line place to form first conductor wire; Form a gate isolation on this substrate and side by side on the surface of first conductor wire, forming a tunnel effect separator on this separator; On whole surface, form one second conductive layer, and remove second conductive layer, tunnel effect separator and first conductor wire selectively to be formed for floating grid between this bit line and second conductor wire of program grid; On second conductor wire, form a deielectric-coating; One after the other comprising formation the 3rd conductive layer and an insulating barrier on the whole surface of dielectric layer, removing insulating barrier, the 3rd conductive layer, dielectric layer and second conductor wire selectively between first conductor wire, to form word line and floating grid with vertical this bit line place; Both sides at insulating barrier, word line, dielectric layer and the floating grid of this composition form the insulative sidewall pad; Utilize this insulative sidewall pad as mask selectively to this program tunnel effect insulating barrier composition, to form contact hole, on the insulating barrier between the bit line, form the program line that is electrically connected to the program grid by this contact hole.
Be understood that the general description of front and following detailed description be the typical case and indicative be that desire provides further explanation to rights protection of the present invention.
Description of drawings
These and various other purpose, feature and advantage of the present invention will be understood after reading to have read the detailed description of doing with reference to accompanying drawing easily.
Fig. 1 is a kind of cutaway view of structure of the general nonvolatile memory cell with a simple layer stack structure;
Fig. 2 one has the circuit diagram of array of the general non-volatile memory device of simple layer stack structure;
Fig. 3 one does not have the array circuit figure of the conventional non-volatile memory device of metal contact hole;
Fig. 4 is the profile along the structure of the non-volatile memory device that does not have metal contact hole shown in the I-I line of Fig. 3;
Fig. 5 is that the source electrode of each unit therein is the array circuit figure of the non-volatile memory device that does not have metal contact hole that separates with drain electrode;
Fig. 6 is the cutaway view of structure of a nonvolatile memory cell that does not utilize the improved metal contact hole of raceway groove separative element;
Fig. 7 is the symbol according to a nonvolatile memory cell of the present invention;
Fig. 8 is the circuit diagram according to first array of non-volatile memory cell structure of the present invention;
Fig. 9 is the circuit diagram according to second array of non-volatile memory cell structure of the present invention;
Figure 10 is the Butut according to a non-volatile memory device of the present invention;
Figure 11 is the cutaway view along this non-volatile memory device shown in the I-I line of Figure 10;
Figure 12 is the cutaway view along this non-volatile memory device shown in the II-II line of Figure 10;
Figure 13 is the cutaway view along this non-volatile memory device shown in the III-III line of Figure 10;
Figure 14 is the cutaway view along this non-volatile memory device shown in the IV-IV line of Figure 10;
Figure 15 A-15D is according to most preferred embodiment of the present invention, is used for making the cutaway view of treatment step of the method for this non-volatile memory device along the explanation of the I-I line of Figure 10;
Figure 16 A-16D is according to most preferred embodiment of the present invention, is used for making the treatment step cutaway view of the method for this non-volatile memory device along the explanation of the II-II line of Figure 10.
Embodiment
Describe most preferred embodiment of the present invention now in detail, provided these examples in the accompanying drawings.
Fig. 7 shows the symbol of a non-volatile memory cells of the present invention, Fig. 8 is the circuit diagram of first array of non-volatile memory cell structure according to the present invention, Fig. 9 is to be Butut according to a non-volatile memory device of the present invention according to the circuit diagram of second array of non-volatile memory cell structure of the present invention and Figure 10.
As shown in Figure 7, a nonvolatile memory cell comprises a control gate 60, a floating grid 53, n
+Bit line 42 and program grid 49.At this moment, this n
+The function of bit line is as source electrode and drain electrode.Between source electrode and drain electrode, have monitor current to flow, and program current flow between floating grid 53 and program grid 49.In when programming, utilize tunnel effect and between program grid 49 and floating grid 53, form the tunnel effect diode, therefore carry out programming by the electric charge that is provided for floating grid 53.
Non-volatile memory device as shown in Figure 8, a plurality of word lines 51 are to be formed on the Semiconductor substrate (not shown) at a distance of the mode of a preset distance each other.A plurality of n
+Bit line 42 is vertically to be formed at a distance of mode and a plurality of word line 51 of a preset distance each other, to form accurate rectangle.A plurality of program lines 55 with n
+Bit line 42 identical directions are formed on this Semiconductor substrate.
Referring to Fig. 9, for the coupling of reduction program, program line 55 can be formed on a pair of adjacent n
+Between the bit line 42.In order from a plurality of nonvolatile memory cells 56, to select, respectively positive 8V and negative 8V are added to the control gate 60 of word line 51 and the program grid 49 of program line 55, to produce tunnel effect.In addition, respectively OV and positive voltage are added to program grid 49 and control gate 60, with selected cell.In addition, a positive voltage and a negative voltage are added to control gate 60 and program grid 49 respectively, and in initial stage programming, simultaneously bias voltage are added to source electrode and drain to connect this raceway groove so that the drain current circulation.Utilize a sense amplifier then, this drain current is monitored so that utilize tunnel effect to finish the change in charge of programming and monitoring floating grid 48 at this moment by these program grid 49.
As shown in figure 10, on a direction of a P type semiconductor substrate (not shown) to form a plurality of n at a distance of the mode of a preset distance each other
+Bit line 42.In this case, this n in a memory cell
+Bit line 42 is extrinsic region and source electrode and drain electrode.A plurality of word lines 51 are with each other at a distance of mode and this n of a preset distance
+Bit line 42 vertically is formed.Field oxide layer 44 is with each other at a distance of mode and this n of a preset distance
+Bit line 42 is formed perpendicularly.Program line 55 with each other at a distance of the mode of a preset distance with this n
+Be formed on the identical direction of bit line.
On the P type semiconductor substrate, at n
+Form the island floating grid 53 of a matrix type between the bit line 42 and between the field oxide 44.At this moment, form each word line 51 with cover with word line 51 equidirectionals on a plurality of floating grids 53 of forming.Each word line 51 is control gates 60 in a memory cell.On the direction identical, on this field oxide 44, form program grid 49 with corresponding program line 55.At this moment, each n
+Bit line 42, each floating grid 53, each word line 51 and each program line 55 are all isolated mutually.On this field oxide layer 44 between two unit, form program grid 49.Thereby do not influence the size of a unit.Between this floating grid 53, form program tunnel effect oxide layer 47, thereby can utilize the tunnel effect programming.
Figure 11 is the cutaway view along the structure of this non-volatile memory device shown in the I-I line of Figure 10, and Figure 12 is the cutaway view along the structure of this non-volatile memory device shown in the II-II line of Figure 10.Figure 13 is the cutaway view along the structure of this non-volatile memory device shown in the III-III line of Figure 10.Figure 14 is the cutaway view along the structure of this non-volatile memory device shown in the IV-IV line of Figure 10.
Shown in Figure 11 as along shown in the I-I line of Figure 10, this non-volatile memory device include with each other at a distance of the mode of a preset distance at the formed n of the surface underneath of a P type semiconductor substrate 41
+ Bit line 42; Including n
+A formed grid oxic horizon 46 on this Semiconductor substrate 41 of bit line 42; At this n
+The both sides of bit line 42 are formed a plurality of floating grids 53 on grid oxic horizon 46; Surperficial formed deielectric-coating 50 at floating grid 53; Including a formed word line 51 on the whole surface of deielectric-coating 50; Formed one second oxide layer 52 on this word line 51; With this above floating grid 53 on second oxide layer 52 formed a plurality of program lines 55.
As along among the Figure 12 shown in the II-II line of Figure 10, this non-volatile memory device includes with each other at a distance of mode formed a plurality of field oxides 44 on a P type semiconductor substrate 41 of a preset distance; At the both sides of this field oxide 44 formed grid oxic horizon 46 on this Semiconductor substrate; Formed program grid 49 on this field oxide 44; Formed program tunnel effect oxide layer 47 on this field oxide 44 and program grid 49 with program line contact hole; The formed floating grid 53 of part in this grid oxic horizon 46 and this program raceway groove oxide layer 47; Formed dielectric layer 50 on this floating grid 53; Formed second oxide layer 52 on this program tunnel effect layer 47 and word line 51 with program line contact hole; With the formed program line 55 that is electrically connected with program grid 49 by this program line contact hole on second oxide layer 52.
Shown in Figure 13 as along shown in the III-III line of Figure 10, this non-volatile memory device includes the firm n that is included in the grid oxic horizon 46 on the P type semiconductor substrate 41
+ Bit line 42; Comprising n
+Formed field oxide 44 in the Semiconductor substrate 41 of bit line 42; With formed word line 51 on the part of grid oxic horizon 46 and field oxide 44.
As along the Figure 14 shown in the IV-IV line of Figure 10, this non-volatile memory device is included in formed n in the P type semiconductor substrate 41
+ Bit line 42 and grid oxic horizon 46; Including n
+A formed field oxide 44 on the Semiconductor substrate 41 of bit line 42; At n
+Formed program grid 49 on this oxide layer of bit line 42 both sides; With formed each program line 55 on the core of each program grid 49.
Erase operation according to non-volatile memory device of the present invention will be discussed below.Erase operation is to carry out to semi-conductive substrate 41 or to program grid 49 by the grid oxic horizon 46 of a unit.Under the situation that semi-conductive substrate 41 is carried out, grid oxic horizon 46 is suitable for formation the thickness of the 9-11nm of tunnel effect.As for bias voltage, a negative voltage or a ground voltage are added to control gate 60 and a positive voltage is added to drain electrode.
Figure 15 A to 15D and Figure 16 A to 16D are the processing steps that is used for making a kind of method of this non-volatile memory device according to most preferred embodiment of the present invention respectively along the I-I line of Figure 10 and the explanation of II-II line.According to this method, before forming floating grid, form the program grid.Therefore, the feature of an embedding program grid technique is that these program grid are placed under this floating grid.
Beginning is referring to Figure 15 A and 16A, and deposit one deck first photoresist on P type semiconductor substrate 41 exposes subsequently selectively and development treatment is removed photoresist with the position at extrinsic region.Then, with the figure of first photoresist as a mask, with inject mix and the dense foreign ion of diffusion n type with shape n below this Semiconductor substrate 41
+Bit line.Then, remove remaining first photoresist layer.In order to prevent owing to n
+The horizontal proliferation of bit line 42 and cause that cell size increases is forming n
+Just define n before the bit line 42
+The position of bit line 42, and subsequently at this n
+The side of bit line 42 forms high-temperature low-pressure medium (HLD) sidewall pad and injects ion subsequently.
Afterwards, form one first oxide layer in succession, have one first polysilicon layer and one second photoresist film of ion doping by a CVD (chemical vapor deposition, chemical vapor deposition) technology.Then, second photoetching film selectively exposed and development treatment to keep the position above the field oxide.As a mask, first oxide layer and first polysilicon layer are corroded selectively to form the field oxide 44 and first polysilicon lines 45 with the second photoresist figure.Then, remove remaining second photoresist film.At this moment, this field oxide 44 has the shape of a line and at this field oxide 44 and n
+Zone between the bit line 42 is a channel region.
Referring to Figure 15 B and 16B, on the whole surface that comprises first polysilicon layer 45, carry out thermal oxidation so that the thermal oxidation on the surface by first polysilicon lines 45 generates a grid oxic horizon 46 and program tunnel effect oxide layer 47.In this case, form grid oxic horizon 46 to have the thickness of 9-10nm; Because the thickness of formed this program tunnel effect oxide layer 47 of characteristic of the high concentration of foreign ion and the first polycrystalline line 45 itself is thicker than grid oxic horizon 46 in this first polysilicon lines 45; And because n
+So the concentration height of the foreign ion of bit line 42 is at this n
+Grid oxic horizon 46 on the bit line 42 is thick, i.e. 70-300 dust (A).So, in this polysilicon layer of corrosion, can obtain enough corrosion barrier potentials in the technology below.
Then, on the whole surface that comprises grid oxic horizon 46 and program tunnel effect layer 47, one after the other form second polysilicon layer and the 3rd photoresist film, and subsequently the 3rd photoresist film exposed selectively and development treatment to remove at n
+The 3rd photoresist film on the bit line 42.As a mask, this second polysilicon layer is corroded selectively to form second polysilicon lines 48 with the figure of the 3rd photoetching film.Then, this program tunnel effect oxide layer 47 and first polysilicon lines 45 are corroded selectively to form a plurality of program grid grid 49 of a rectangular matrix shape.Subsequently, remove remaining the 3rd photoresist film.In this case, in forming this program grid 49, this field oxide 44 has also been corroded selectively to have a matrix shape rather than a wire shaped.In addition, this second polysilicon lines 48 has covered channel region.
Referring to Figure 15 C and 16C, on this second polysilicon lines 48, form a deielectric-coating 50, and one after the other form the 3rd polysilicon layer, second oxide layer 52 and the 4th photoresist film on the whole surface of this deielectric-coating 50 comprising subsequently.In this case, this deielectric-coating 50 is made by a kind of oxide or oxide nitride oxide (ONO), thus the leakage current of having eliminated in running to be produced.
The 4th photoresist film is carried out exposure and development treatment to remove the 4th top photoresist film of this field oxide 44.Make a mask with the image of the 4th photoresist film, corrode second oxide layer 52, the 3rd polysilicon layer, deielectric-coating 50 and second polysilicon lines 48 selectively.Remove remaining the 4th photoresist film.At this moment, perpendicular to n
+The 3rd polysilicon layer is corroded selectively forming word line 51 between field oxide 44 in bit line 42 places, and corrodes this second polysilicon layer 48 selectively with at n
+On this grid oxic horizon 46, form a plurality of floating grids 53 between bit line 42 and the field oxide 44.In this case, by oxidation first polysilicon layer, promptly the program grid 49, form floating grid 53 after the generator tunnel effect oxide layer 47.Therefore, floating grid 53 these program grid 49 of contact also cover the corner part of adjacent programs grid 49, thereby have increased coupling ratio and thereby improved the efficient of tunnel effect.In addition, because the surface of this program grid 49 is coarse, thereby improved the efficient of tunnel effect.Just, because the grain structure of this polysilicon makes the surface of program grid 49 have coarse surface.Therefore, if this polysilicon is oxidized, then the interface between polysilicon and the oxide layer is coarse, and the roughness on the surface of this oxide layer becomes level and smooth.For this reason, in coarse part, electric field is reinforced.When forming electrode on such polysilicon, the characteristic of tunnel(l)ing current is enhanced.
Referring to last Figure 15 D and 16D, form the 3rd oxide layer on the whole surface that comprises second oxide layer 52 and utilize deep etch to handle selectively subsequently that composition forms the 3rd oxidized sidewalls pad 54 with the both sides at second oxide layer 52, word line 51, dielectric layer 50 and floating grid 53.As a mask, and program grid 49 is as a corrosion restriction (etchstopper) with second oxide layer 52 and the 3rd oxidized sidewalls pad 54, and this program tunnel effect oxide layer 47 is corroded selectively to expose the part of this program grid 49.On the whole surface that includes second oxide layer 52 and the 3rd oxidized sidewalls pad 54, form program line 55.At this moment, at adjacent a pair of n
+Form each program line 55 between the bit line 42.
The method that the present invention is used for making a non-volatile memory device has some advantages.Nonvolatile memory cell with a simple layer stack structure is selected to be programmed or to be wiped free of by the preset voltage that is added to program grid and control gate, thereby does not need metal contact hole.Therefore, can provide a very little effective cell size and suppressed program disturb.In addition, because these program grid place under this floating grid,, thereby reduced operating voltage so the characteristic of program extends through floating grid by this program grid.
Obviously, those skilled in the art are without prejudice to spirit of the present invention with do not exceed under the prerequisite of scope of the present invention and can make various improvement and variation to the method that is used for making non-volatile memory device of the present invention.Therefore, the present invention has covered in the scope of the condition of equivalent of claim and they improvement and the variation to the present invention did.
Claims (10)
1. method that is used for making a non-volatile memory device comprises step:
In the surface underneath of a substrate of first conductivity type, at the bit line that on the direction of a preset distance, forms second conductivity type each other;
One after the other on this whole surface, form a separator and first conductive layer and removing this separator and first conductive layer selectively so that it is isolated from each other perpendicular to this bit line place subsequently, thereby form first conductor wire;
Form a gate isolation on this substrate and side by side on the surface of first conductor wire on this separator, forming a tunnel effect separator;
On whole surface, form one second conductive layer, and remove second conductive layer, tunnel effect separator and first conductor wire selectively to be formed for floating grid between this bit line and second conductor wire of program grid;
On second conductor wire, form a deielectric-coating;
One after the other comprising formation the 3rd conductive layer and an insulating barrier on the whole surface of deielectric-coating, removing insulating barrier, the 3rd conductive layer, dielectric layer and second conductor wire selectively between first conductor wire, to form word line and floating grid with vertical this bit line place;
Both sides at insulating barrier, word line, dielectric layer and the floating grid of this composition form the insulative sidewall pad;
Utilize this insulative sidewall pad as mask selectively to this program tunnel effect insulating barrier composition, to form contact hole; With
On the insulating barrier between the bit line, form the program line that is electrically connected to the program grid by this contact hole.
2. method as claimed in claim 1 wherein forms each program line between a pair of adjacent bit lines.
3. method as claimed in claim 1 is wherein by forming bit line in the substrate that n type foreign ion is injected into first conductivity type.
4. method as claimed in claim 1 wherein comes respectively substrate and the exposure of first conductor wire to be formed gate insulator and tunnel effect insulating barrier by carrying out thermal oxidation.
5. method as claimed in claim 1, wherein the thickness of this gate insulator generation is 9-11nm.
6. method as claimed in claim 1 wherein forms each bit line, limits the position of these bit lines, forms sidewall pad, implanting impurity ion then at its end.
7. method as claimed in claim 1 wherein utilizes chemical vapor deposition process to form this insulating barrier.
8. method as claimed in claim 1, wherein formation covers the floating grid of a corner part of adjacent programs grid.
9. method as claimed in claim 1 wherein forms the program grid with a rectangular shape.
10. method as claimed in claim 1, wherein this dielectric layer is manufactured by oxide nitride oxide.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970031838A KR100244278B1 (en) | 1997-07-09 | 1997-07-09 | Manufacturing method for non-volatile memory device |
| KR31838/1997 | 1997-07-09 | ||
| KR31838/97 | 1997-07-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1204870A CN1204870A (en) | 1999-01-13 |
| CN1127760C true CN1127760C (en) | 2003-11-12 |
Family
ID=19513923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98108027A Expired - Fee Related CN1127760C (en) | 1997-07-09 | 1998-04-28 | Method for fabricating nonvolatile memory device |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP2887128B2 (en) |
| KR (1) | KR100244278B1 (en) |
| CN (1) | CN1127760C (en) |
| DE (1) | DE19813457C2 (en) |
| TW (1) | TW344139B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100466979B1 (en) * | 1997-12-26 | 2005-04-06 | 삼성전자주식회사 | Semiconductor memory device and program verification method thereof |
| KR100317318B1 (en) * | 1998-04-23 | 2001-12-22 | 김영환 | Nonvolatile memory device and method for fabricating the same |
| JP4012341B2 (en) * | 1999-07-14 | 2007-11-21 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| JP4117998B2 (en) * | 2000-03-30 | 2008-07-16 | シャープ株式会社 | Nonvolatile semiconductor memory device, reading, writing and erasing methods thereof, and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0936257A (en) * | 1995-07-14 | 1997-02-07 | Matsushita Electron Corp | Semiconductor storage device and its manufacture |
| JP2734433B2 (en) * | 1995-10-31 | 1998-03-30 | 日本電気株式会社 | Manufacturing method of nonvolatile semiconductor memory device |
-
1997
- 1997-07-09 KR KR1019970031838A patent/KR100244278B1/en not_active IP Right Cessation
- 1997-10-15 TW TW086115104A patent/TW344139B/en not_active IP Right Cessation
-
1998
- 1998-02-16 JP JP10033086A patent/JP2887128B2/en not_active Expired - Fee Related
- 1998-03-26 DE DE19813457A patent/DE19813457C2/en not_active Expired - Fee Related
- 1998-04-28 CN CN98108027A patent/CN1127760C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1140783A (en) | 1999-02-12 |
| KR100244278B1 (en) | 2000-02-01 |
| JP2887128B2 (en) | 1999-04-26 |
| DE19813457A1 (en) | 1999-01-14 |
| DE19813457C2 (en) | 2001-09-27 |
| TW344139B (en) | 1998-11-01 |
| KR19990009425A (en) | 1999-02-05 |
| CN1204870A (en) | 1999-01-13 |
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