CN1309048C - Method for forming floating grid - Google Patents
Method for forming floating grid Download PDFInfo
- Publication number
- CN1309048C CN1309048C CNB2004100312438A CN200410031243A CN1309048C CN 1309048 C CN1309048 C CN 1309048C CN B2004100312438 A CNB2004100312438 A CN B2004100312438A CN 200410031243 A CN200410031243 A CN 200410031243A CN 1309048 C CN1309048 C CN 1309048C
- Authority
- CN
- China
- Prior art keywords
- floating grid
- formation method
- substrate
- layer
- lining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 230000002262 irrigation Effects 0.000 claims description 16
- 238000003973 irrigation Methods 0.000 claims description 16
- 239000000126 substance Substances 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 7
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 2
- 239000000460 chlorine Substances 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000008367 deionised water Substances 0.000 claims description 2
- 229910021641 deionized water Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 230000010415 tropism Effects 0.000 claims 2
- 230000005641 tunneling Effects 0.000 abstract description 3
- 230000001154 acute effect Effects 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 230000015654 memory Effects 0.000 description 20
- 230000008569 process Effects 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 229920002521 macromolecule Polymers 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 1
- 239000003637 basic solution Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Images
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a floating grid forming method. The method firstly provides a substrate, a patterned lining layer and a masking layer are formed on the substrate, and a ditch is formed in the substrate. A tunneling oxide layer is formed on the surface of the ditch, and conductor layers are filled in the ditch. Subsequently, an etching step is carried out, a first floating gate and a second floating gate are formed on the side wall of the ditch, and the top rim angles of the first floating gate and the second floating gate are acute angles.
Description
Technical field
The formation method of the relevant a kind of memory component of the present invention, and the formation method of relevant a kind of floating grid particularly.
Background technology
Flash memory component is owing to have and can repeatedly carry out the actions such as depositing in, read, erase of data, and the data that deposits in the advantage that also can not disappear after outage.Therefore, become PC and electronic equipment a kind of non-volatile memory device of extensively adopting.
Typical flash memory component is to make floating grid (Floating Gate) and control grid (Control Gate) (stack type grid structure) with doped polycrystalline silicon.And, be separated by with dielectric layer between grid between floating grid and the control grid, and be separated by with tunnel oxide (Tunnel Oxide) between floating grid and substrate.
When flash memory being write the operation of (Write) data, by applying bias voltage, so that electronics injects floating grid in control grid and source/drain regions.During data in reading flash memory, apply operating voltage on the control grid, this moment, the electriferous state of floating grid can influence the ON/OFF of its lower channel (Channel), and the ON/OFF of this raceway groove is a foundation with interpretation data value " 0 " or " 1 ".When flash memory when carrying out the erasing of data (Erase), the relative current potential of substrate, source area, drain region or control grid is improved, utilizing tunneling effect to make electronics pass tunnel oxide (Tunneling Oxide) and drain into (being Substrate Erase or Drain (Source) Side Erase) in substrate or the leakage (source) extremely, or pass dielectric layer between grid and drain in the control grid by floating grid.
Yet, during data in the flash memory of erasing,, therefore easily make floating grid discharge polyelectron and have a positive charge, this phenomenon be referred to as excessively to erase (Over-Erase) because the electron amount of discharging from floating grid is wayward.When this phenomenon of excessively erasing was too serious, the raceway groove that can make the floating grid below promptly presented the state that continues conducting, and causes the erroneous judgement of data when the control grid does not apply operating voltage.So in order to solve the problem that element is excessively erased, many flash memories can adopt the design of separated grid (Split Gate).Its architectural feature also has the selection grid (or being called the grid of erasing) that is positioned at above control grid and floating grid sidewall, the substrate except control grid and floating grid.Wherein, this selects to be separated by with dielectric layer between another layer grid between grid and control grid, floating grid and the substrate.So when the phenomenon of excessively erasing is too serious, that is floating grid below raceway groove selects the raceway groove of grid below still can keep closed condition when the control grid does not apply the state that promptly presents conducting under the operating voltage state.That is select closing of grid, and can make drain region and source area present non-conduction state, so can prevent the erroneous judgement of data.
Yet if the shape of the corner of floating grid both sides is sharp-pointed inadequately, when flash memory is carrying out data when erasing, the corner of floating grid both sides is difficult for producing big electric field, therefore can spend the time of length to carry out data and erase.So several can improve the method for the corner shape of floating grid existing proposition.Wherein a kind of mode is exposed in Application No. the 6th, 429, No. 075.Please refer to Fig. 1 and Fig. 2, wherein first insulating barrier 20 is disposed on the substrate 12, and floating grid 22 is disposed on first insulating barrier 20, and second insulating barrier 26 is disposed on the floating grid 22.And, under the technological temperatures of 800 to 900 degree Celsius, when carrying out thermal oxidation technology, the corner that can make floating grid 22 both sides among Fig. 1 because of thermal oxidation generate as shown in Figure 2 silicon oxide layer 27 and sharp-pointed corner 29.Yet, because the temperature of this thermal oxidation technology is still higher relatively, therefore, must the considerable process heat budget of cost.So the method is not a basic solution.In addition, based on considering of element integrated level, the mode that forms memory cell in irrigation canals and ditches will become following a kind of technology trend.Yet the thermal oxidation technology of being carried out in irrigation canals and ditches is more wayward.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of formation method of floating grid is being provided, and by forming the floating grid that the corner, top has sharp comer, makes follow-up formed flash memory cell carrying out data when erasing, and has faster speed.
The present invention proposes a kind of formation method of floating grid, the method is that substrate is provided earlier, this substrate comprises at least one component isolation structure, the active area that component isolation structure defined thus, be formed at the lining on the substrate of this active area, be formed at the mask layer on the lining, and irrigation canals and ditches, wherein these irrigation canals and ditches run through lining and mask layer is formed in the substrate.Afterwards, form tunnel oxide in the irrigation canals and ditches surface.Then, in irrigation canals and ditches, insert conductor layer.Then, carry out the isotropic etching step, remove the conductor layer of part, wherein the upper surface of the conductor layer that is kept is circular-arc sunk surface.Then, carry out the anisotropic etching step, and utilize the accessory substance that is generated in the anisotropic etching step to be mask, remove the conductor layer of part and the tunnel oxide of part, use the substrate of expose portion.Continue it, remove accessory substance, mask layer and lining, to form first floating grid and second floating grid in trench sidewall.Wherein, the corner, top of first floating grid and second floating grid and trench sidewall adjacency is a sharp comer.
First floating grid (or second floating grid) that has sharp comer owing to corner, top of the present invention forms by the etch process of secondary.Therefore need not carry out to reduce the heat budget of technology effectively under the thermal process situation such as hot boiler tube.And, when carrying out secondary etch process, be the accessory substance that produced with etch process as the autoregistration etching mask, and this autoregistration etching mask can be protected the profile of the corner, top of floating grid.
In addition, because the corner, top of first floating grid of the present invention (or second floating grid) is a sharp comer, therefore when carrying out data when erasing by the formed flash memory cell of subsequent technique, this sharp comer can produce higher electric field, makes electronics to discharge apace via this sharp comer.So required time of erase data is shorter, and also can reduce the required voltage of bestowing.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the generalized section of the partial structurtes of existing a kind of flash memory cell;
Fig. 2 is the generalized section of the flash memory cell of Fig. 1 through the partial structurtes of thermal process gained;
Fig. 3 is according to looking schematic diagram on the floating grid in a kind of flash memory cell of a preferred embodiment of the present invention;
Fig. 4 A to Fig. 4 D is the manufacturing process generalized section according to a kind of floating grid of a preferred embodiment of the present invention, and is by the generalized section of I to I ' among Fig. 3.
Description of reference numerals
12,200: substrate 20,26: insulating barrier
27: silicon oxide layer 29: corner
100: active area 102: component isolation structure
202: lining 204: mask layer
206: irrigation canals and ditches 208: tunnel oxide
210: conductor layer 212: upper surface
213: accessory substance 22,214a, 214b: floating grid
216: the corner, top
Embodiment
Fig. 3 is according to looking schematic diagram on the floating grid in a kind of flash memory cell of a preferred embodiment of the present invention.Fig. 4 A to Fig. 4 D is the manufacturing process profile that illustrates a kind of floating grid of the preferred embodiment of the present invention, and is by the generalized section of I to I ' among Fig. 3.
At first please provide substrate 200 simultaneously with reference to Fig. 3 and Fig. 4 A, this substrate 200 has formed monobasic spare isolation structure 102 at least, and this component isolation structure 102 is the strip layout, and defines active area 100.Wherein, substrate 200 for example is a silicon substrate.In addition, the formation method of component isolation structure 102 for example be the selective oxidation method (Local Oxidation, LOCOS) or the shallow trench isolation method (Shallow TrenchIsolation, STI).Then, form lining 202 in substrate 200 surfaces, this lining 202 for example is a silicon oxide layer, and its formation method for example is thermal oxidation method (Thermal Oxidation).Then, form mask layer 204 on lining 202, this mask layer 204 for example is a silicon nitride layer, and its formation method for example be chemical vapour deposition technique (Chemical Vapor Deposition, CVD).Then, patterned mask layer 204, lining 202 and substrate 200 are to form irrigation canals and ditches (Trench) 206 in the active area 100 of substrate 200.
Afterwards, please refer to Fig. 4 B, form tunnel oxide 208 in irrigation canals and ditches 206 surfaces.Wherein, the material of tunnel oxide 208 for example is a silica, and its formation method for example is a thermal oxidation method.Then, form one deck conductor layer 210 that fills up irrigation canals and ditches 206 on substrate 200, it for example is polysilicon layer or doped polysilicon layer, and the formation method of doped polysilicon layer for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carry out the ion implantation step, and form.Continue it, carry out the etch-back step, so that the surface of conductor layer 210 is lower than the surface of mask layer 204.Wherein, this etch-back step for example is to carry out dry etch process or chemical mechanical milling tech.Then, carry out primary etching step, remove the conductor layer 210 of part.The upper surface 212 of the conductor layer 210 that wherein, is remained is circular-arc sunk surface.This etching step comprises the isotropic etching step, and it for example is a wet etch step, and this etchant for example is the mixed solution (Ammonium Hydrogen Peroxide Mixture is called for short APM) that is made of ammoniacal liquor, hydrogen peroxide and deionized water.
Then, please refer to Fig. 4 C, carry out secondary etching step, and the accessory substance 213 that utilizes in the etching process to be generated is mask, remove the conductor layer 210 of part, to form floating grid 214a and floating grid 214b in irrigation canals and ditches 206 sidewalls (not adjacent sidewall) with component isolation structure 102.What deserves to be mentioned is that because this etching step is the plasma etch step of anisotropic etching, and the mist of use chlorine/hydrogen bromide/oxygen is as plasma etching gas.Therefore, when carrying out this plasma etching step, can produce macromolecule accessory substance 213 simultaneously, and this macromolecule accessory substance 213 can cover the conductor layer 210 and corner, top 216 of part.So macromolecule accessory substance 213 also can avoid the sharp-pointed external form of corner, top 216 to suffer damage (Damage) in this plasma etching step except the etching mask that can be used as this plasma etching step.And the ratio of the employed hydrogen bromide of this plasma etching step is higher, and the macromolecule accessory substance 213 that is generated is understood the more, and its coverage effect for corner, top 216 also can be better.
Continuing it, please refer to Fig. 4 D, remove macromolecule accessory substance 213, is the floating grid 214a and the floating grid 214b of sharp comer to obtain in abutting connection with the corner, top 216 of irrigation canals and ditches 206 sidewalls.Afterwards, more can carry out the related process of existing flash memory cell, forming source area (not illustrating), drain region (not illustrating), control grid (not illustrating) and the necessary member of selecting grid memory cell such as (not illustrating), and then finish the making of memory cell.About these technologies because for those skilled in the art can know by inference easily, therefore repeat no more in this.
In the above embodiment of the present invention, the floating grid that has sharp comer owing to corner, top of the present invention forms by the etch process of secondary.Therefore need not carry out to reduce the heat budget of technology effectively under the thermal process situation such as hot boiler tube.And when carrying out secondary etch process, as the autoregistration etching mask, and this autoregistration etching mask can be protected the profile of the corner, top of floating grid with accessory substance that etch process was produced.
In addition, because the corner, top of first floating grid of the present invention (or second floating grid) is a sharp comer, therefore when carrying out data when erasing by the formed flash memory cell of subsequent technique, this sharp comer can produce higher electric field, makes electronics to discharge apace via this sharp comer.So required time of erase data is shorter, and also can reduce the required voltage of bestowing.
Though the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention; should do a little change and retouching, so protection scope of the present invention is when looking appended being as the criterion that claim defined.
Claims (10)
1. the formation method of a floating grid comprises:
One substrate is provided, this substrate comprises at least one component isolation structure, by the active area that this component isolation structure defined, be formed at the lining on this substrate of this active area, be formed at the mask layer on this lining, and irrigation canals and ditches, wherein these irrigation canals and ditches run through this lining and this mask layer is formed in this substrate;
Form a tunnel oxide in this irrigation canals and ditches surface;
In these irrigation canals and ditches, insert a conductor layer;
Carry out first-class tropism's etching step, remove this conductor layer of part, wherein the upper surface of this conductor layer that is kept is a circular-arc sunk surface;
Carry out an anisotropic etching step, and utilize an accessory substance that is generated in this anisotropic etching step to be mask, remove this conductor layer of part and this tunnel oxide of part, use this substrate of expose portion; And
Remove this accessory substance, this mask layer and this lining, to form one first floating grid and one second floating grid in this trench sidewall, wherein the corner, top of this first floating grid and this second floating grid and this trench sidewall adjacency is a sharp comer.
2. the formation method of floating grid as claimed in claim 1, wherein these tropism's etching steps comprise a wet etch step.
3. the formation method of floating grid as claimed in claim 2, wherein the employed etchant of this wet etch step comprises a mixed solution that is made of ammoniacal liquor, hydrogen peroxide and deionized water.
4. the formation method of floating grid as claimed in claim 1, wherein this anisotropic etching step comprises a plasma etching step.
5. the formation method of floating grid as claimed in claim 4, wherein the employed gas of this plasma etching step comprises chlorine/hydrogen bromide/oxygen.
6. the formation method of floating grid as claimed in claim 1, wherein this circular-arc sunk surface is higher than this lining surface.
7. the formation method of floating grid as claimed in claim 1, wherein this substrate is a silicon substrate.
8. the formation method of floating grid as claimed in claim 1, wherein this conductor layer is a polysilicon layer.
9. the formation method of floating grid as claimed in claim 1, wherein this mask layer is a silicon nitride layer.
10. the formation method of floating grid as claimed in claim 1, wherein this lining is an one silica layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312438A CN1309048C (en) | 2004-03-26 | 2004-03-26 | Method for forming floating grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312438A CN1309048C (en) | 2004-03-26 | 2004-03-26 | Method for forming floating grid |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1674258A CN1674258A (en) | 2005-09-28 |
| CN1309048C true CN1309048C (en) | 2007-04-04 |
Family
ID=35046657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100312438A Expired - Fee Related CN1309048C (en) | 2004-03-26 | 2004-03-26 | Method for forming floating grid |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1309048C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593687B (en) * | 2008-05-30 | 2011-11-30 | 中芯国际集成电路制造(北京)有限公司 | Polysilicon grid, side wall, and semiconductor device and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001687A (en) * | 1999-04-01 | 1999-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for forming self-aligned source in flash cell using SiN spacer as hard mask |
| US6228713B1 (en) * | 1999-06-28 | 2001-05-08 | Chartered Semiconductor Manufacturing Ltd. | Self-aligned floating gate for memory application using shallow trench isolation |
| US6429075B2 (en) * | 1998-07-02 | 2002-08-06 | Silicon Storage Technology, Inc. | Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby |
| US6537882B1 (en) * | 1996-08-15 | 2003-03-25 | Nec Corporation | Method of fabricating a semiconductor device in which no side walls are formed adjacent the gates of the MOSFETs of the memory cell |
-
2004
- 2004-03-26 CN CNB2004100312438A patent/CN1309048C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6537882B1 (en) * | 1996-08-15 | 2003-03-25 | Nec Corporation | Method of fabricating a semiconductor device in which no side walls are formed adjacent the gates of the MOSFETs of the memory cell |
| US6429075B2 (en) * | 1998-07-02 | 2002-08-06 | Silicon Storage Technology, Inc. | Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby |
| US6001687A (en) * | 1999-04-01 | 1999-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for forming self-aligned source in flash cell using SiN spacer as hard mask |
| US6228713B1 (en) * | 1999-06-28 | 2001-05-08 | Chartered Semiconductor Manufacturing Ltd. | Self-aligned floating gate for memory application using shallow trench isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1674258A (en) | 2005-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100625142B1 (en) | Method of manufacturing a semiconductor device | |
| US5702965A (en) | Flash memory cell and method of making the same | |
| TW200408069A (en) | Method of manufacturing a flash memory cell | |
| US20060148177A1 (en) | Method for forming split gate flash nonvolatile memory devices | |
| CN1614768A (en) | Method of manufacturing split gate type nonvolatile memory device | |
| JP2005530357A (en) | Floating gate extended with conductive spacer | |
| US5756384A (en) | Method of fabricating an EPROM cell with a high coupling ratio | |
| CN104617048B (en) | Flash memory and forming method thereof | |
| US8106448B2 (en) | NAND flash memory device | |
| US7892959B2 (en) | Method of manufacturing flash memory device with reduced void generation | |
| CN1309048C (en) | Method for forming floating grid | |
| KR100800379B1 (en) | Method for manufacturing gate of non volatile memory device | |
| KR100733144B1 (en) | Non-volatile memory device and method of forming non-volatile memory device | |
| CN102054841A (en) | NAND gate flash memory and manufacturing method thereof | |
| CN1133215C (en) | Read-only memory and its manufacture | |
| CN100341138C (en) | Method for making flash memory | |
| CN1307710C (en) | Method for producing flash memory storing unit | |
| KR100390913B1 (en) | Process for forming gate of flash mamory device | |
| CN105762150A (en) | Flash memory and manufacturing method thereof | |
| KR100628245B1 (en) | Method for fabrication flash memory device | |
| KR100661232B1 (en) | Method for removing the ONO residue in flash device | |
| JP2002313968A (en) | Semiconductor device and its manufacturing method | |
| KR100798767B1 (en) | Method for manufacturing flash memory device | |
| KR100702778B1 (en) | Method for fabricating flash memory device | |
| KR100309813B1 (en) | A method of manufacturing a split gate type flash memory cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070404 Termination date: 20100326 |